1 /* Support for generating ACPI tables and passing them to Guests 2 * 3 * ARM virt ACPI generation 4 * 5 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> 6 * Copyright (C) 2006 Fabrice Bellard 7 * Copyright (C) 2013 Red Hat Inc 8 * 9 * Author: Michael S. Tsirkin <mst@redhat.com> 10 * 11 * Copyright (c) 2015 HUAWEI TECHNOLOGIES CO.,LTD. 12 * 13 * Author: Shannon Zhao <zhaoshenglong@huawei.com> 14 * 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of the GNU General Public License as published by 17 * the Free Software Foundation; either version 2 of the License, or 18 * (at your option) any later version. 19 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 25 * You should have received a copy of the GNU General Public License along 26 * with this program; if not, see <http://www.gnu.org/licenses/>. 27 */ 28 29 #include "qemu-common.h" 30 #include "hw/arm/virt-acpi-build.h" 31 #include "qemu/bitmap.h" 32 #include "trace.h" 33 #include "qom/cpu.h" 34 #include "target-arm/cpu.h" 35 #include "hw/acpi/acpi-defs.h" 36 #include "hw/acpi/acpi.h" 37 #include "hw/nvram/fw_cfg.h" 38 #include "hw/acpi/bios-linker-loader.h" 39 #include "hw/loader.h" 40 #include "hw/hw.h" 41 #include "hw/acpi/aml-build.h" 42 #include "hw/pci/pcie_host.h" 43 #include "hw/pci/pci.h" 44 45 #define ARM_SPI_BASE 32 46 47 typedef struct VirtAcpiCpuInfo { 48 DECLARE_BITMAP(found_cpus, VIRT_ACPI_CPU_ID_LIMIT); 49 } VirtAcpiCpuInfo; 50 51 static void virt_acpi_get_cpu_info(VirtAcpiCpuInfo *cpuinfo) 52 { 53 CPUState *cpu; 54 55 memset(cpuinfo->found_cpus, 0, sizeof cpuinfo->found_cpus); 56 CPU_FOREACH(cpu) { 57 set_bit(cpu->cpu_index, cpuinfo->found_cpus); 58 } 59 } 60 61 static void acpi_dsdt_add_cpus(Aml *scope, int smp_cpus) 62 { 63 uint16_t i; 64 65 for (i = 0; i < smp_cpus; i++) { 66 Aml *dev = aml_device("C%03x", i); 67 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0007"))); 68 aml_append(dev, aml_name_decl("_UID", aml_int(i))); 69 aml_append(scope, dev); 70 } 71 } 72 73 static void acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap, 74 int uart_irq) 75 { 76 Aml *dev = aml_device("COM0"); 77 aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0011"))); 78 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 79 80 Aml *crs = aml_resource_template(); 81 aml_append(crs, aml_memory32_fixed(uart_memmap->base, 82 uart_memmap->size, AML_READ_WRITE)); 83 aml_append(crs, 84 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 85 AML_EXCLUSIVE, uart_irq)); 86 aml_append(dev, aml_name_decl("_CRS", crs)); 87 aml_append(scope, dev); 88 } 89 90 static void acpi_dsdt_add_rtc(Aml *scope, const MemMapEntry *rtc_memmap, 91 int rtc_irq) 92 { 93 Aml *dev = aml_device("RTC0"); 94 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0013"))); 95 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 96 97 Aml *crs = aml_resource_template(); 98 aml_append(crs, aml_memory32_fixed(rtc_memmap->base, 99 rtc_memmap->size, AML_READ_WRITE)); 100 aml_append(crs, 101 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 102 AML_EXCLUSIVE, rtc_irq)); 103 aml_append(dev, aml_name_decl("_CRS", crs)); 104 aml_append(scope, dev); 105 } 106 107 static void acpi_dsdt_add_flash(Aml *scope, const MemMapEntry *flash_memmap) 108 { 109 Aml *dev, *crs; 110 hwaddr base = flash_memmap->base; 111 hwaddr size = flash_memmap->size; 112 113 dev = aml_device("FLS0"); 114 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015"))); 115 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 116 117 crs = aml_resource_template(); 118 aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE)); 119 aml_append(dev, aml_name_decl("_CRS", crs)); 120 aml_append(scope, dev); 121 122 dev = aml_device("FLS1"); 123 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015"))); 124 aml_append(dev, aml_name_decl("_UID", aml_int(1))); 125 crs = aml_resource_template(); 126 aml_append(crs, aml_memory32_fixed(base + size, size, AML_READ_WRITE)); 127 aml_append(dev, aml_name_decl("_CRS", crs)); 128 aml_append(scope, dev); 129 } 130 131 static void acpi_dsdt_add_virtio(Aml *scope, 132 const MemMapEntry *virtio_mmio_memmap, 133 int mmio_irq, int num) 134 { 135 hwaddr base = virtio_mmio_memmap->base; 136 hwaddr size = virtio_mmio_memmap->size; 137 int irq = mmio_irq; 138 int i; 139 140 for (i = 0; i < num; i++) { 141 Aml *dev = aml_device("VR%02u", i); 142 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005"))); 143 aml_append(dev, aml_name_decl("_UID", aml_int(i))); 144 145 Aml *crs = aml_resource_template(); 146 aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE)); 147 aml_append(crs, 148 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 149 AML_EXCLUSIVE, irq + i)); 150 aml_append(dev, aml_name_decl("_CRS", crs)); 151 aml_append(scope, dev); 152 base += size; 153 } 154 } 155 156 static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, int irq) 157 { 158 Aml *method, *crs, *ifctx, *UUID, *ifctx1, *elsectx, *buf; 159 int i, bus_no; 160 hwaddr base_mmio = memmap[VIRT_PCIE_MMIO].base; 161 hwaddr size_mmio = memmap[VIRT_PCIE_MMIO].size; 162 hwaddr base_pio = memmap[VIRT_PCIE_PIO].base; 163 hwaddr size_pio = memmap[VIRT_PCIE_PIO].size; 164 hwaddr base_ecam = memmap[VIRT_PCIE_ECAM].base; 165 hwaddr size_ecam = memmap[VIRT_PCIE_ECAM].size; 166 int nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN; 167 168 Aml *dev = aml_device("%s", "PCI0"); 169 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08"))); 170 aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03"))); 171 aml_append(dev, aml_name_decl("_SEG", aml_int(0))); 172 aml_append(dev, aml_name_decl("_BBN", aml_int(0))); 173 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 174 aml_append(dev, aml_name_decl("_UID", aml_string("PCI0"))); 175 aml_append(dev, aml_name_decl("_STR", aml_unicode("PCIe 0 Device"))); 176 177 /* Declare the PCI Routing Table. */ 178 Aml *rt_pkg = aml_package(nr_pcie_buses * PCI_NUM_PINS); 179 for (bus_no = 0; bus_no < nr_pcie_buses; bus_no++) { 180 for (i = 0; i < PCI_NUM_PINS; i++) { 181 int gsi = (i + bus_no) % PCI_NUM_PINS; 182 Aml *pkg = aml_package(4); 183 aml_append(pkg, aml_int((bus_no << 16) | 0xFFFF)); 184 aml_append(pkg, aml_int(i)); 185 aml_append(pkg, aml_name("GSI%d", gsi)); 186 aml_append(pkg, aml_int(0)); 187 aml_append(rt_pkg, pkg); 188 } 189 } 190 aml_append(dev, aml_name_decl("_PRT", rt_pkg)); 191 192 /* Create GSI link device */ 193 for (i = 0; i < PCI_NUM_PINS; i++) { 194 Aml *dev_gsi = aml_device("GSI%d", i); 195 aml_append(dev_gsi, aml_name_decl("_HID", aml_string("PNP0C0F"))); 196 aml_append(dev_gsi, aml_name_decl("_UID", aml_int(0))); 197 crs = aml_resource_template(); 198 aml_append(crs, 199 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 200 AML_EXCLUSIVE, irq + i)); 201 aml_append(dev_gsi, aml_name_decl("_PRS", crs)); 202 crs = aml_resource_template(); 203 aml_append(crs, 204 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 205 AML_EXCLUSIVE, irq + i)); 206 aml_append(dev_gsi, aml_name_decl("_CRS", crs)); 207 method = aml_method("_SRS", 1); 208 aml_append(dev_gsi, method); 209 aml_append(dev, dev_gsi); 210 } 211 212 method = aml_method("_CBA", 0); 213 aml_append(method, aml_return(aml_int(base_ecam))); 214 aml_append(dev, method); 215 216 method = aml_method("_CRS", 0); 217 Aml *rbuf = aml_resource_template(); 218 aml_append(rbuf, 219 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 220 0x0000, 0x0000, nr_pcie_buses - 1, 0x0000, 221 nr_pcie_buses)); 222 aml_append(rbuf, 223 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 224 AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, base_mmio, 225 base_mmio + size_mmio - 1, 0x0000, size_mmio)); 226 aml_append(rbuf, 227 aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 228 AML_ENTIRE_RANGE, 0x0000, 0x0000, size_pio - 1, base_pio, 229 size_pio)); 230 231 aml_append(method, aml_name_decl("RBUF", rbuf)); 232 aml_append(method, aml_return(rbuf)); 233 aml_append(dev, method); 234 235 /* Declare an _OSC (OS Control Handoff) method */ 236 aml_append(dev, aml_name_decl("SUPP", aml_int(0))); 237 aml_append(dev, aml_name_decl("CTRL", aml_int(0))); 238 method = aml_method("_OSC", 4); 239 aml_append(method, 240 aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1")); 241 242 /* PCI Firmware Specification 3.0 243 * 4.5.1. _OSC Interface for PCI Host Bridge Devices 244 * The _OSC interface for a PCI/PCI-X/PCI Express hierarchy is 245 * identified by the Universal Unique IDentifier (UUID) 246 * 33DB4D5B-1FF7-401C-9657-7441C03DD766 247 */ 248 UUID = aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766"); 249 ifctx = aml_if(aml_equal(aml_arg(0), UUID)); 250 aml_append(ifctx, 251 aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2")); 252 aml_append(ifctx, 253 aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3")); 254 aml_append(ifctx, aml_store(aml_name("CDW2"), aml_name("SUPP"))); 255 aml_append(ifctx, aml_store(aml_name("CDW3"), aml_name("CTRL"))); 256 aml_append(ifctx, aml_store(aml_and(aml_name("CTRL"), aml_int(0x1D)), 257 aml_name("CTRL"))); 258 259 ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(0x1)))); 260 aml_append(ifctx1, aml_store(aml_or(aml_name("CDW1"), aml_int(0x08)), 261 aml_name("CDW1"))); 262 aml_append(ifctx, ifctx1); 263 264 ifctx1 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), aml_name("CTRL")))); 265 aml_append(ifctx1, aml_store(aml_or(aml_name("CDW1"), aml_int(0x10)), 266 aml_name("CDW1"))); 267 aml_append(ifctx, ifctx1); 268 269 aml_append(ifctx, aml_store(aml_name("CTRL"), aml_name("CDW3"))); 270 aml_append(ifctx, aml_return(aml_arg(3))); 271 aml_append(method, ifctx); 272 273 elsectx = aml_else(); 274 aml_append(elsectx, aml_store(aml_or(aml_name("CDW1"), aml_int(4)), 275 aml_name("CDW1"))); 276 aml_append(elsectx, aml_return(aml_arg(3))); 277 aml_append(method, elsectx); 278 aml_append(dev, method); 279 280 method = aml_method("_DSM", 4); 281 282 /* PCI Firmware Specification 3.0 283 * 4.6.1. _DSM for PCI Express Slot Information 284 * The UUID in _DSM in this context is 285 * {E5C937D0-3553-4D7A-9117-EA4D19C3434D} 286 */ 287 UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D"); 288 ifctx = aml_if(aml_equal(aml_arg(0), UUID)); 289 ifctx1 = aml_if(aml_equal(aml_arg(2), aml_int(0))); 290 uint8_t byte_list[1] = {1}; 291 buf = aml_buffer(1, byte_list); 292 aml_append(ifctx1, aml_return(buf)); 293 aml_append(ifctx, ifctx1); 294 aml_append(method, ifctx); 295 296 byte_list[0] = 0; 297 buf = aml_buffer(1, byte_list); 298 aml_append(method, aml_return(buf)); 299 aml_append(dev, method); 300 301 Aml *dev_rp0 = aml_device("%s", "RP0"); 302 aml_append(dev_rp0, aml_name_decl("_ADR", aml_int(0))); 303 aml_append(dev, dev_rp0); 304 aml_append(scope, dev); 305 } 306 307 /* RSDP */ 308 static GArray * 309 build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt) 310 { 311 AcpiRsdpDescriptor *rsdp = acpi_data_push(rsdp_table, sizeof *rsdp); 312 313 bios_linker_loader_alloc(linker, ACPI_BUILD_RSDP_FILE, 16, 314 true /* fseg memory */); 315 316 memcpy(&rsdp->signature, "RSD PTR ", sizeof(rsdp->signature)); 317 memcpy(rsdp->oem_id, ACPI_BUILD_APPNAME6, sizeof(rsdp->oem_id)); 318 rsdp->length = cpu_to_le32(sizeof(*rsdp)); 319 rsdp->revision = 0x02; 320 321 /* Point to RSDT */ 322 rsdp->rsdt_physical_address = cpu_to_le32(rsdt); 323 /* Address to be filled by Guest linker */ 324 bios_linker_loader_add_pointer(linker, ACPI_BUILD_RSDP_FILE, 325 ACPI_BUILD_TABLE_FILE, 326 rsdp_table, &rsdp->rsdt_physical_address, 327 sizeof rsdp->rsdt_physical_address); 328 rsdp->checksum = 0; 329 /* Checksum to be filled by Guest linker */ 330 bios_linker_loader_add_checksum(linker, ACPI_BUILD_RSDP_FILE, 331 rsdp, rsdp, sizeof *rsdp, &rsdp->checksum); 332 333 return rsdp_table; 334 } 335 336 static void 337 build_mcfg(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info) 338 { 339 AcpiTableMcfg *mcfg; 340 const MemMapEntry *memmap = guest_info->memmap; 341 int len = sizeof(*mcfg) + sizeof(mcfg->allocation[0]); 342 343 mcfg = acpi_data_push(table_data, len); 344 mcfg->allocation[0].address = cpu_to_le64(memmap[VIRT_PCIE_ECAM].base); 345 346 /* Only a single allocation so no need to play with segments */ 347 mcfg->allocation[0].pci_segment = cpu_to_le16(0); 348 mcfg->allocation[0].start_bus_number = 0; 349 mcfg->allocation[0].end_bus_number = (memmap[VIRT_PCIE_ECAM].size 350 / PCIE_MMCFG_SIZE_MIN) - 1; 351 352 build_header(linker, table_data, (void *)mcfg, "MCFG", len, 5); 353 } 354 355 /* GTDT */ 356 static void 357 build_gtdt(GArray *table_data, GArray *linker) 358 { 359 int gtdt_start = table_data->len; 360 AcpiGenericTimerTable *gtdt; 361 362 gtdt = acpi_data_push(table_data, sizeof *gtdt); 363 /* The interrupt values are the same with the device tree when adding 16 */ 364 gtdt->secure_el1_interrupt = ARCH_TIMER_S_EL1_IRQ + 16; 365 gtdt->secure_el1_flags = ACPI_EDGE_SENSITIVE; 366 367 gtdt->non_secure_el1_interrupt = ARCH_TIMER_NS_EL1_IRQ + 16; 368 gtdt->non_secure_el1_flags = ACPI_EDGE_SENSITIVE; 369 370 gtdt->virtual_timer_interrupt = ARCH_TIMER_VIRT_IRQ + 16; 371 gtdt->virtual_timer_flags = ACPI_EDGE_SENSITIVE; 372 373 gtdt->non_secure_el2_interrupt = ARCH_TIMER_NS_EL2_IRQ + 16; 374 gtdt->non_secure_el2_flags = ACPI_EDGE_SENSITIVE; 375 376 build_header(linker, table_data, 377 (void *)(table_data->data + gtdt_start), "GTDT", 378 table_data->len - gtdt_start, 5); 379 } 380 381 /* MADT */ 382 static void 383 build_madt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info, 384 VirtAcpiCpuInfo *cpuinfo) 385 { 386 int madt_start = table_data->len; 387 const MemMapEntry *memmap = guest_info->memmap; 388 AcpiMultipleApicTable *madt; 389 AcpiMadtGenericDistributor *gicd; 390 int i; 391 392 madt = acpi_data_push(table_data, sizeof *madt); 393 394 for (i = 0; i < guest_info->smp_cpus; i++) { 395 AcpiMadtGenericInterrupt *gicc = acpi_data_push(table_data, 396 sizeof *gicc); 397 gicc->type = ACPI_APIC_GENERIC_INTERRUPT; 398 gicc->length = sizeof(*gicc); 399 gicc->base_address = memmap[VIRT_GIC_CPU].base; 400 gicc->cpu_interface_number = i; 401 gicc->arm_mpidr = i; 402 gicc->uid = i; 403 if (test_bit(i, cpuinfo->found_cpus)) { 404 gicc->flags = cpu_to_le32(ACPI_GICC_ENABLED); 405 } 406 } 407 408 gicd = acpi_data_push(table_data, sizeof *gicd); 409 gicd->type = ACPI_APIC_GENERIC_DISTRIBUTOR; 410 gicd->length = sizeof(*gicd); 411 gicd->base_address = memmap[VIRT_GIC_DIST].base; 412 413 build_header(linker, table_data, 414 (void *)(table_data->data + madt_start), "APIC", 415 table_data->len - madt_start, 5); 416 } 417 418 /* FADT */ 419 static void 420 build_fadt(GArray *table_data, GArray *linker, unsigned dsdt) 421 { 422 AcpiFadtDescriptorRev5_1 *fadt = acpi_data_push(table_data, sizeof(*fadt)); 423 424 /* Hardware Reduced = 1 and use PSCI 0.2+ and with HVC */ 425 fadt->flags = cpu_to_le32(1 << ACPI_FADT_F_HW_REDUCED_ACPI); 426 fadt->arm_boot_flags = cpu_to_le16((1 << ACPI_FADT_ARM_USE_PSCI_G_0_2) | 427 (1 << ACPI_FADT_ARM_PSCI_USE_HVC)); 428 429 /* ACPI v5.1 (fadt->revision.fadt->minor_revision) */ 430 fadt->minor_revision = 0x1; 431 432 fadt->dsdt = cpu_to_le32(dsdt); 433 /* DSDT address to be filled by Guest linker */ 434 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, 435 ACPI_BUILD_TABLE_FILE, 436 table_data, &fadt->dsdt, 437 sizeof fadt->dsdt); 438 439 build_header(linker, table_data, 440 (void *)fadt, "FACP", sizeof(*fadt), 5); 441 } 442 443 /* DSDT */ 444 static void 445 build_dsdt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info) 446 { 447 Aml *scope, *dsdt; 448 const MemMapEntry *memmap = guest_info->memmap; 449 const int *irqmap = guest_info->irqmap; 450 451 dsdt = init_aml_allocator(); 452 /* Reserve space for header */ 453 acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader)); 454 455 scope = aml_scope("\\_SB"); 456 acpi_dsdt_add_cpus(scope, guest_info->smp_cpus); 457 acpi_dsdt_add_uart(scope, &memmap[VIRT_UART], 458 (irqmap[VIRT_UART] + ARM_SPI_BASE)); 459 acpi_dsdt_add_rtc(scope, &memmap[VIRT_RTC], 460 (irqmap[VIRT_RTC] + ARM_SPI_BASE)); 461 acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]); 462 acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO], 463 (irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS); 464 acpi_dsdt_add_pci(scope, memmap, (irqmap[VIRT_PCIE] + ARM_SPI_BASE)); 465 466 aml_append(dsdt, scope); 467 468 /* copy AML table into ACPI tables blob and patch header there */ 469 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); 470 build_header(linker, table_data, 471 (void *)(table_data->data + table_data->len - dsdt->buf->len), 472 "DSDT", dsdt->buf->len, 5); 473 free_aml_allocator(); 474 } 475 476 typedef 477 struct AcpiBuildState { 478 /* Copy of table in RAM (for patching). */ 479 MemoryRegion *table_mr; 480 MemoryRegion *rsdp_mr; 481 MemoryRegion *linker_mr; 482 /* Is table patched? */ 483 bool patched; 484 VirtGuestInfo *guest_info; 485 } AcpiBuildState; 486 487 static 488 void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables) 489 { 490 GArray *table_offsets; 491 unsigned dsdt, rsdt; 492 VirtAcpiCpuInfo cpuinfo; 493 GArray *tables_blob = tables->table_data; 494 495 virt_acpi_get_cpu_info(&cpuinfo); 496 497 table_offsets = g_array_new(false, true /* clear */, 498 sizeof(uint32_t)); 499 500 bios_linker_loader_alloc(tables->linker, ACPI_BUILD_TABLE_FILE, 501 64, false /* high memory */); 502 503 /* 504 * The ACPI v5.1 tables for Hardware-reduced ACPI platform are: 505 * RSDP 506 * RSDT 507 * FADT 508 * GTDT 509 * MADT 510 * DSDT 511 */ 512 513 /* DSDT is pointed to by FADT */ 514 dsdt = tables_blob->len; 515 build_dsdt(tables_blob, tables->linker, guest_info); 516 517 /* FADT MADT GTDT pointed to by RSDT */ 518 acpi_add_table(table_offsets, tables_blob); 519 build_fadt(tables_blob, tables->linker, dsdt); 520 521 acpi_add_table(table_offsets, tables_blob); 522 build_madt(tables_blob, tables->linker, guest_info, &cpuinfo); 523 524 acpi_add_table(table_offsets, tables_blob); 525 build_gtdt(tables_blob, tables->linker); 526 527 acpi_add_table(table_offsets, tables_blob); 528 build_mcfg(tables_blob, tables->linker, guest_info); 529 530 /* RSDT is pointed to by RSDP */ 531 rsdt = tables_blob->len; 532 build_rsdt(tables_blob, tables->linker, table_offsets); 533 534 /* RSDP is in FSEG memory, so allocate it separately */ 535 build_rsdp(tables->rsdp, tables->linker, rsdt); 536 537 /* Cleanup memory that's no longer used. */ 538 g_array_free(table_offsets, true); 539 } 540 541 static void acpi_ram_update(MemoryRegion *mr, GArray *data) 542 { 543 uint32_t size = acpi_data_len(data); 544 545 /* Make sure RAM size is correct - in case it got changed 546 * e.g. by migration */ 547 memory_region_ram_resize(mr, size, &error_abort); 548 549 memcpy(memory_region_get_ram_ptr(mr), data->data, size); 550 memory_region_set_dirty(mr, 0, size); 551 } 552 553 static void virt_acpi_build_update(void *build_opaque, uint32_t offset) 554 { 555 AcpiBuildState *build_state = build_opaque; 556 AcpiBuildTables tables; 557 558 /* No state to update or already patched? Nothing to do. */ 559 if (!build_state || build_state->patched) { 560 return; 561 } 562 build_state->patched = true; 563 564 acpi_build_tables_init(&tables); 565 566 virt_acpi_build(build_state->guest_info, &tables); 567 568 acpi_ram_update(build_state->table_mr, tables.table_data); 569 acpi_ram_update(build_state->rsdp_mr, tables.rsdp); 570 acpi_ram_update(build_state->linker_mr, tables.linker); 571 572 573 acpi_build_tables_cleanup(&tables, true); 574 } 575 576 static void virt_acpi_build_reset(void *build_opaque) 577 { 578 AcpiBuildState *build_state = build_opaque; 579 build_state->patched = false; 580 } 581 582 static MemoryRegion *acpi_add_rom_blob(AcpiBuildState *build_state, 583 GArray *blob, const char *name, 584 uint64_t max_size) 585 { 586 return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1, 587 name, virt_acpi_build_update, build_state); 588 } 589 590 static const VMStateDescription vmstate_virt_acpi_build = { 591 .name = "virt_acpi_build", 592 .version_id = 1, 593 .minimum_version_id = 1, 594 .fields = (VMStateField[]) { 595 VMSTATE_BOOL(patched, AcpiBuildState), 596 VMSTATE_END_OF_LIST() 597 }, 598 }; 599 600 void virt_acpi_setup(VirtGuestInfo *guest_info) 601 { 602 AcpiBuildTables tables; 603 AcpiBuildState *build_state; 604 605 if (!guest_info->fw_cfg) { 606 trace_virt_acpi_setup(); 607 return; 608 } 609 610 if (!acpi_enabled) { 611 trace_virt_acpi_setup(); 612 return; 613 } 614 615 build_state = g_malloc0(sizeof *build_state); 616 build_state->guest_info = guest_info; 617 618 acpi_build_tables_init(&tables); 619 virt_acpi_build(build_state->guest_info, &tables); 620 621 /* Now expose it all to Guest */ 622 build_state->table_mr = acpi_add_rom_blob(build_state, tables.table_data, 623 ACPI_BUILD_TABLE_FILE, 624 ACPI_BUILD_TABLE_MAX_SIZE); 625 assert(build_state->table_mr != NULL); 626 627 build_state->linker_mr = 628 acpi_add_rom_blob(build_state, tables.linker, "etc/table-loader", 0); 629 630 fw_cfg_add_file(guest_info->fw_cfg, ACPI_BUILD_TPMLOG_FILE, 631 tables.tcpalog->data, acpi_data_len(tables.tcpalog)); 632 633 build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp, 634 ACPI_BUILD_RSDP_FILE, 0); 635 636 qemu_register_reset(virt_acpi_build_reset, build_state); 637 virt_acpi_build_reset(build_state); 638 vmstate_register(NULL, 0, &vmstate_virt_acpi_build, build_state); 639 640 /* Cleanup tables but don't free the memory: we track it 641 * in build_state. 642 */ 643 acpi_build_tables_cleanup(&tables, false); 644 } 645