1 /* 2 * ARM Versatile Express emulation. 3 * 4 * Copyright (c) 2010 - 2011 B Labs Ltd. 5 * Copyright (c) 2011 Linaro Limited 6 * Written by Bahadir Balban, Amit Mahajan, Peter Maydell 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, see <http://www.gnu.org/licenses/>. 19 * 20 * Contributions after 2012-01-13 are licensed under the terms of the 21 * GNU GPL, version 2 or (at your option) any later version. 22 */ 23 24 #include "qemu/osdep.h" 25 #include "qapi/error.h" 26 #include "qemu/datadir.h" 27 #include "cpu.h" 28 #include "hw/sysbus.h" 29 #include "hw/arm/boot.h" 30 #include "hw/arm/primecell.h" 31 #include "hw/net/lan9118.h" 32 #include "hw/i2c/i2c.h" 33 #include "net/net.h" 34 #include "sysemu/sysemu.h" 35 #include "hw/boards.h" 36 #include "hw/loader.h" 37 #include "hw/block/flash.h" 38 #include "sysemu/device_tree.h" 39 #include "qemu/error-report.h" 40 #include <libfdt.h> 41 #include "hw/char/pl011.h" 42 #include "hw/cpu/a9mpcore.h" 43 #include "hw/cpu/a15mpcore.h" 44 #include "hw/i2c/arm_sbcon_i2c.h" 45 #include "hw/sd/sd.h" 46 #include "qapi/qmp/qlist.h" 47 #include "qom/object.h" 48 #include "audio/audio.h" 49 #include "target/arm/cpu-qom.h" 50 51 #define VEXPRESS_BOARD_ID 0x8e0 52 #define VEXPRESS_FLASH_SIZE (64 * 1024 * 1024) 53 #define VEXPRESS_FLASH_SECT_SIZE (256 * 1024) 54 55 /* Number of virtio transports to create (0..8; limited by 56 * number of available IRQ lines). 57 */ 58 #define NUM_VIRTIO_TRANSPORTS 4 59 60 /* Address maps for peripherals: 61 * the Versatile Express motherboard has two possible maps, 62 * the "legacy" one (used for A9) and the "Cortex-A Series" 63 * map (used for newer cores). 64 * Individual daughterboards can also have different maps for 65 * their peripherals. 66 */ 67 68 enum { 69 VE_SYSREGS, 70 VE_SP810, 71 VE_SERIALPCI, 72 VE_PL041, 73 VE_MMCI, 74 VE_KMI0, 75 VE_KMI1, 76 VE_UART0, 77 VE_UART1, 78 VE_UART2, 79 VE_UART3, 80 VE_WDT, 81 VE_TIMER01, 82 VE_TIMER23, 83 VE_SERIALDVI, 84 VE_RTC, 85 VE_COMPACTFLASH, 86 VE_CLCD, 87 VE_NORFLASH0, 88 VE_NORFLASH1, 89 VE_NORFLASHALIAS, 90 VE_SRAM, 91 VE_VIDEORAM, 92 VE_ETHERNET, 93 VE_USB, 94 VE_DAPROM, 95 VE_VIRTIO, 96 }; 97 98 static hwaddr motherboard_legacy_map[] = { 99 [VE_NORFLASHALIAS] = 0, 100 /* CS7: 0x10000000 .. 0x10020000 */ 101 [VE_SYSREGS] = 0x10000000, 102 [VE_SP810] = 0x10001000, 103 [VE_SERIALPCI] = 0x10002000, 104 [VE_PL041] = 0x10004000, 105 [VE_MMCI] = 0x10005000, 106 [VE_KMI0] = 0x10006000, 107 [VE_KMI1] = 0x10007000, 108 [VE_UART0] = 0x10009000, 109 [VE_UART1] = 0x1000a000, 110 [VE_UART2] = 0x1000b000, 111 [VE_UART3] = 0x1000c000, 112 [VE_WDT] = 0x1000f000, 113 [VE_TIMER01] = 0x10011000, 114 [VE_TIMER23] = 0x10012000, 115 [VE_VIRTIO] = 0x10013000, 116 [VE_SERIALDVI] = 0x10016000, 117 [VE_RTC] = 0x10017000, 118 [VE_COMPACTFLASH] = 0x1001a000, 119 [VE_CLCD] = 0x1001f000, 120 /* CS0: 0x40000000 .. 0x44000000 */ 121 [VE_NORFLASH0] = 0x40000000, 122 /* CS1: 0x44000000 .. 0x48000000 */ 123 [VE_NORFLASH1] = 0x44000000, 124 /* CS2: 0x48000000 .. 0x4a000000 */ 125 [VE_SRAM] = 0x48000000, 126 /* CS3: 0x4c000000 .. 0x50000000 */ 127 [VE_VIDEORAM] = 0x4c000000, 128 [VE_ETHERNET] = 0x4e000000, 129 [VE_USB] = 0x4f000000, 130 }; 131 132 static hwaddr motherboard_aseries_map[] = { 133 [VE_NORFLASHALIAS] = 0, 134 /* CS0: 0x08000000 .. 0x0c000000 */ 135 [VE_NORFLASH0] = 0x08000000, 136 /* CS4: 0x0c000000 .. 0x10000000 */ 137 [VE_NORFLASH1] = 0x0c000000, 138 /* CS5: 0x10000000 .. 0x14000000 */ 139 /* CS1: 0x14000000 .. 0x18000000 */ 140 [VE_SRAM] = 0x14000000, 141 /* CS2: 0x18000000 .. 0x1c000000 */ 142 [VE_VIDEORAM] = 0x18000000, 143 [VE_ETHERNET] = 0x1a000000, 144 [VE_USB] = 0x1b000000, 145 /* CS3: 0x1c000000 .. 0x20000000 */ 146 [VE_DAPROM] = 0x1c000000, 147 [VE_SYSREGS] = 0x1c010000, 148 [VE_SP810] = 0x1c020000, 149 [VE_SERIALPCI] = 0x1c030000, 150 [VE_PL041] = 0x1c040000, 151 [VE_MMCI] = 0x1c050000, 152 [VE_KMI0] = 0x1c060000, 153 [VE_KMI1] = 0x1c070000, 154 [VE_UART0] = 0x1c090000, 155 [VE_UART1] = 0x1c0a0000, 156 [VE_UART2] = 0x1c0b0000, 157 [VE_UART3] = 0x1c0c0000, 158 [VE_WDT] = 0x1c0f0000, 159 [VE_TIMER01] = 0x1c110000, 160 [VE_TIMER23] = 0x1c120000, 161 [VE_VIRTIO] = 0x1c130000, 162 [VE_SERIALDVI] = 0x1c160000, 163 [VE_RTC] = 0x1c170000, 164 [VE_COMPACTFLASH] = 0x1c1a0000, 165 [VE_CLCD] = 0x1c1f0000, 166 }; 167 168 /* Structure defining the peculiarities of a specific daughterboard */ 169 170 typedef struct VEDBoardInfo VEDBoardInfo; 171 172 struct VexpressMachineClass { 173 MachineClass parent; 174 VEDBoardInfo *daughterboard; 175 }; 176 177 struct VexpressMachineState { 178 MachineState parent; 179 MemoryRegion vram; 180 MemoryRegion sram; 181 MemoryRegion flashalias; 182 MemoryRegion a15sram; 183 bool secure; 184 bool virt; 185 }; 186 187 #define TYPE_VEXPRESS_MACHINE "vexpress" 188 #define TYPE_VEXPRESS_A9_MACHINE MACHINE_TYPE_NAME("vexpress-a9") 189 #define TYPE_VEXPRESS_A15_MACHINE MACHINE_TYPE_NAME("vexpress-a15") 190 OBJECT_DECLARE_TYPE(VexpressMachineState, VexpressMachineClass, VEXPRESS_MACHINE) 191 192 typedef void DBoardInitFn(VexpressMachineState *machine, 193 ram_addr_t ram_size, 194 const char *cpu_type, 195 qemu_irq *pic); 196 197 struct VEDBoardInfo { 198 struct arm_boot_info bootinfo; 199 const hwaddr *motherboard_map; 200 hwaddr loader_start; 201 const hwaddr gic_cpu_if_addr; 202 uint32_t proc_id; 203 uint32_t num_voltage_sensors; 204 const uint32_t *voltages; 205 uint32_t num_clocks; 206 const uint32_t *clocks; 207 DBoardInitFn *init; 208 }; 209 210 static void init_cpus(MachineState *ms, const char *cpu_type, 211 const char *privdev, hwaddr periphbase, 212 qemu_irq *pic, bool secure, bool virt) 213 { 214 DeviceState *dev; 215 SysBusDevice *busdev; 216 int n; 217 unsigned int smp_cpus = ms->smp.cpus; 218 219 /* Create the actual CPUs */ 220 for (n = 0; n < smp_cpus; n++) { 221 Object *cpuobj = object_new(cpu_type); 222 223 if (!secure) { 224 object_property_set_bool(cpuobj, "has_el3", false, NULL); 225 } 226 if (!virt) { 227 if (object_property_find(cpuobj, "has_el2")) { 228 object_property_set_bool(cpuobj, "has_el2", false, NULL); 229 } 230 } 231 232 if (object_property_find(cpuobj, "reset-cbar")) { 233 object_property_set_int(cpuobj, "reset-cbar", periphbase, 234 &error_abort); 235 } 236 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); 237 } 238 239 /* Create the private peripheral devices (including the GIC); 240 * this must happen after the CPUs are created because a15mpcore_priv 241 * wires itself up to the CPU's generic_timer gpio out lines. 242 */ 243 dev = qdev_new(privdev); 244 qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); 245 busdev = SYS_BUS_DEVICE(dev); 246 sysbus_realize_and_unref(busdev, &error_fatal); 247 sysbus_mmio_map(busdev, 0, periphbase); 248 249 /* Interrupts [42:0] are from the motherboard; 250 * [47:43] are reserved; [63:48] are daughterboard 251 * peripherals. Note that some documentation numbers 252 * external interrupts starting from 32 (because there 253 * are internal interrupts 0..31). 254 */ 255 for (n = 0; n < 64; n++) { 256 pic[n] = qdev_get_gpio_in(dev, n); 257 } 258 259 /* Connect the CPUs to the GIC */ 260 for (n = 0; n < smp_cpus; n++) { 261 DeviceState *cpudev = DEVICE(qemu_get_cpu(n)); 262 263 sysbus_connect_irq(busdev, n, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 264 sysbus_connect_irq(busdev, n + smp_cpus, 265 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 266 sysbus_connect_irq(busdev, n + 2 * smp_cpus, 267 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 268 sysbus_connect_irq(busdev, n + 3 * smp_cpus, 269 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 270 } 271 } 272 273 static void a9_daughterboard_init(VexpressMachineState *vms, 274 ram_addr_t ram_size, 275 const char *cpu_type, 276 qemu_irq *pic) 277 { 278 MachineState *machine = MACHINE(vms); 279 MemoryRegion *sysmem = get_system_memory(); 280 281 if (ram_size > 0x40000000) { 282 /* 1GB is the maximum the address space permits */ 283 error_report("vexpress-a9: cannot model more than 1GB RAM"); 284 exit(1); 285 } 286 287 /* 288 * RAM is from 0x60000000 upwards. The bottom 64MB of the 289 * address space should in theory be remappable to various 290 * things including ROM or RAM; we always map the flash there. 291 */ 292 memory_region_add_subregion(sysmem, 0x60000000, machine->ram); 293 294 /* 0x1e000000 A9MPCore (SCU) private memory region */ 295 init_cpus(machine, cpu_type, TYPE_A9MPCORE_PRIV, 0x1e000000, pic, 296 vms->secure, vms->virt); 297 298 /* Daughterboard peripherals : 0x10020000 .. 0x20000000 */ 299 300 /* 0x10020000 PL111 CLCD (daughterboard) */ 301 sysbus_create_simple("pl111", 0x10020000, pic[44]); 302 303 /* 0x10060000 AXI RAM */ 304 /* 0x100e0000 PL341 Dynamic Memory Controller */ 305 /* 0x100e1000 PL354 Static Memory Controller */ 306 /* 0x100e2000 System Configuration Controller */ 307 308 sysbus_create_simple("sp804", 0x100e4000, pic[48]); 309 /* 0x100e5000 SP805 Watchdog module */ 310 /* 0x100e6000 BP147 TrustZone Protection Controller */ 311 /* 0x100e9000 PL301 'Fast' AXI matrix */ 312 /* 0x100ea000 PL301 'Slow' AXI matrix */ 313 /* 0x100ec000 TrustZone Address Space Controller */ 314 /* 0x10200000 CoreSight debug APB */ 315 /* 0x1e00a000 PL310 L2 Cache Controller */ 316 sysbus_create_varargs("l2x0", 0x1e00a000, NULL); 317 } 318 319 /* Voltage values for SYS_CFG_VOLT daughterboard registers; 320 * values are in microvolts. 321 */ 322 static const uint32_t a9_voltages[] = { 323 1000000, /* VD10 : 1.0V : SoC internal logic voltage */ 324 1000000, /* VD10_S2 : 1.0V : PL310, L2 cache, RAM, non-PL310 logic */ 325 1000000, /* VD10_S3 : 1.0V : Cortex-A9, cores, MPEs, SCU, PL310 logic */ 326 1800000, /* VCC1V8 : 1.8V : DDR2 SDRAM, test chip DDR2 I/O supply */ 327 900000, /* DDR2VTT : 0.9V : DDR2 SDRAM VTT termination voltage */ 328 3300000, /* VCC3V3 : 3.3V : local board supply for misc external logic */ 329 }; 330 331 /* Reset values for daughterboard oscillators (in Hz) */ 332 static const uint32_t a9_clocks[] = { 333 45000000, /* AMBA AXI ACLK: 45MHz */ 334 23750000, /* daughterboard CLCD clock: 23.75MHz */ 335 66670000, /* Test chip reference clock: 66.67MHz */ 336 }; 337 338 static VEDBoardInfo a9_daughterboard = { 339 .motherboard_map = motherboard_legacy_map, 340 .loader_start = 0x60000000, 341 .gic_cpu_if_addr = 0x1e000100, 342 .proc_id = 0x0c000191, 343 .num_voltage_sensors = ARRAY_SIZE(a9_voltages), 344 .voltages = a9_voltages, 345 .num_clocks = ARRAY_SIZE(a9_clocks), 346 .clocks = a9_clocks, 347 .init = a9_daughterboard_init, 348 }; 349 350 static void a15_daughterboard_init(VexpressMachineState *vms, 351 ram_addr_t ram_size, 352 const char *cpu_type, 353 qemu_irq *pic) 354 { 355 MachineState *machine = MACHINE(vms); 356 MemoryRegion *sysmem = get_system_memory(); 357 358 { 359 /* We have to use a separate 64 bit variable here to avoid the gcc 360 * "comparison is always false due to limited range of data type" 361 * warning if we are on a host where ram_addr_t is 32 bits. 362 */ 363 uint64_t rsz = ram_size; 364 if (rsz > (30ULL * 1024 * 1024 * 1024)) { 365 error_report("vexpress-a15: cannot model more than 30GB RAM"); 366 exit(1); 367 } 368 } 369 370 /* RAM is from 0x80000000 upwards; there is no low-memory alias for it. */ 371 memory_region_add_subregion(sysmem, 0x80000000, machine->ram); 372 373 /* 0x2c000000 A15MPCore private memory region (GIC) */ 374 init_cpus(machine, cpu_type, TYPE_A15MPCORE_PRIV, 375 0x2c000000, pic, vms->secure, vms->virt); 376 377 /* A15 daughterboard peripherals: */ 378 379 /* 0x20000000: CoreSight interfaces: not modelled */ 380 /* 0x2a000000: PL301 AXI interconnect: not modelled */ 381 /* 0x2a420000: SCC: not modelled */ 382 /* 0x2a430000: system counter: not modelled */ 383 /* 0x2b000000: HDLCD controller: not modelled */ 384 /* 0x2b060000: SP805 watchdog: not modelled */ 385 /* 0x2b0a0000: PL341 dynamic memory controller: not modelled */ 386 /* 0x2e000000: system SRAM */ 387 memory_region_init_ram(&vms->a15sram, NULL, "vexpress.a15sram", 0x10000, 388 &error_fatal); 389 memory_region_add_subregion(sysmem, 0x2e000000, &vms->a15sram); 390 391 /* 0x7ffb0000: DMA330 DMA controller: not modelled */ 392 /* 0x7ffd0000: PL354 static memory controller: not modelled */ 393 } 394 395 static const uint32_t a15_voltages[] = { 396 900000, /* Vcore: 0.9V : CPU core voltage */ 397 }; 398 399 static const uint32_t a15_clocks[] = { 400 60000000, /* OSCCLK0: 60MHz : CPU_CLK reference */ 401 0, /* OSCCLK1: reserved */ 402 0, /* OSCCLK2: reserved */ 403 0, /* OSCCLK3: reserved */ 404 40000000, /* OSCCLK4: 40MHz : external AXI master clock */ 405 23750000, /* OSCCLK5: 23.75MHz : HDLCD PLL reference */ 406 50000000, /* OSCCLK6: 50MHz : static memory controller clock */ 407 60000000, /* OSCCLK7: 60MHz : SYSCLK reference */ 408 40000000, /* OSCCLK8: 40MHz : DDR2 PLL reference */ 409 }; 410 411 static VEDBoardInfo a15_daughterboard = { 412 .motherboard_map = motherboard_aseries_map, 413 .loader_start = 0x80000000, 414 .gic_cpu_if_addr = 0x2c002000, 415 .proc_id = 0x14000237, 416 .num_voltage_sensors = ARRAY_SIZE(a15_voltages), 417 .voltages = a15_voltages, 418 .num_clocks = ARRAY_SIZE(a15_clocks), 419 .clocks = a15_clocks, 420 .init = a15_daughterboard_init, 421 }; 422 423 static int add_virtio_mmio_node(void *fdt, uint32_t acells, uint32_t scells, 424 hwaddr addr, hwaddr size, uint32_t intc, 425 int irq) 426 { 427 /* Add a virtio_mmio node to the device tree blob: 428 * virtio_mmio@ADDRESS { 429 * compatible = "virtio,mmio"; 430 * reg = <ADDRESS, SIZE>; 431 * interrupt-parent = <&intc>; 432 * interrupts = <0, irq, 1>; 433 * } 434 * (Note that the format of the interrupts property is dependent on the 435 * interrupt controller that interrupt-parent points to; these are for 436 * the ARM GIC and indicate an SPI interrupt, rising-edge-triggered.) 437 */ 438 int rc; 439 char *nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, addr); 440 441 rc = qemu_fdt_add_subnode(fdt, nodename); 442 rc |= qemu_fdt_setprop_string(fdt, nodename, 443 "compatible", "virtio,mmio"); 444 rc |= qemu_fdt_setprop_sized_cells(fdt, nodename, "reg", 445 acells, addr, scells, size); 446 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", intc); 447 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 0, irq, 1); 448 qemu_fdt_setprop(fdt, nodename, "dma-coherent", NULL, 0); 449 g_free(nodename); 450 if (rc) { 451 return -1; 452 } 453 return 0; 454 } 455 456 static uint32_t find_int_controller(void *fdt) 457 { 458 /* Find the FDT node corresponding to the interrupt controller 459 * for virtio-mmio devices. We do this by scanning the fdt for 460 * a node with the right compatibility, since we know there is 461 * only one GIC on a vexpress board. 462 * We return the phandle of the node, or 0 if none was found. 463 */ 464 const char *compat = "arm,cortex-a9-gic"; 465 int offset; 466 467 offset = fdt_node_offset_by_compatible(fdt, -1, compat); 468 if (offset >= 0) { 469 return fdt_get_phandle(fdt, offset); 470 } 471 return 0; 472 } 473 474 static void vexpress_modify_dtb(const struct arm_boot_info *info, void *fdt) 475 { 476 uint32_t acells, scells, intc; 477 const VEDBoardInfo *daughterboard = (const VEDBoardInfo *)info; 478 479 acells = qemu_fdt_getprop_cell(fdt, "/", "#address-cells", 480 NULL, &error_fatal); 481 scells = qemu_fdt_getprop_cell(fdt, "/", "#size-cells", 482 NULL, &error_fatal); 483 intc = find_int_controller(fdt); 484 if (!intc) { 485 /* Not fatal, we just won't provide virtio. This will 486 * happen with older device tree blobs. 487 */ 488 warn_report("couldn't find interrupt controller in " 489 "dtb; will not include virtio-mmio devices in the dtb"); 490 } else { 491 int i; 492 const hwaddr *map = daughterboard->motherboard_map; 493 494 /* We iterate backwards here because adding nodes 495 * to the dtb puts them in last-first. 496 */ 497 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) { 498 add_virtio_mmio_node(fdt, acells, scells, 499 map[VE_VIRTIO] + 0x200 * i, 500 0x200, intc, 40 + i); 501 } 502 } 503 } 504 505 506 /* Open code a private version of pflash registration since we 507 * need to set non-default device width for VExpress platform. 508 */ 509 static PFlashCFI01 *ve_pflash_cfi01_register(hwaddr base, const char *name, 510 DriveInfo *di) 511 { 512 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 513 514 if (di) { 515 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(di)); 516 } 517 518 qdev_prop_set_uint32(dev, "num-blocks", 519 VEXPRESS_FLASH_SIZE / VEXPRESS_FLASH_SECT_SIZE); 520 qdev_prop_set_uint64(dev, "sector-length", VEXPRESS_FLASH_SECT_SIZE); 521 qdev_prop_set_uint8(dev, "width", 4); 522 qdev_prop_set_uint8(dev, "device-width", 2); 523 qdev_prop_set_bit(dev, "big-endian", false); 524 qdev_prop_set_uint16(dev, "id0", 0x89); 525 qdev_prop_set_uint16(dev, "id1", 0x18); 526 qdev_prop_set_uint16(dev, "id2", 0x00); 527 qdev_prop_set_uint16(dev, "id3", 0x00); 528 qdev_prop_set_string(dev, "name", name); 529 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 530 531 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 532 return PFLASH_CFI01(dev); 533 } 534 535 static void vexpress_common_init(MachineState *machine) 536 { 537 VexpressMachineState *vms = VEXPRESS_MACHINE(machine); 538 VexpressMachineClass *vmc = VEXPRESS_MACHINE_GET_CLASS(machine); 539 VEDBoardInfo *daughterboard = vmc->daughterboard; 540 DeviceState *dev, *sysctl, *pl041; 541 qemu_irq pic[64]; 542 uint32_t sys_id; 543 DriveInfo *dinfo; 544 PFlashCFI01 *pflash0; 545 I2CBus *i2c; 546 ram_addr_t vram_size, sram_size; 547 MemoryRegion *sysmem = get_system_memory(); 548 const hwaddr *map = daughterboard->motherboard_map; 549 QList *db_voltage, *db_clock; 550 int i; 551 552 daughterboard->init(vms, machine->ram_size, machine->cpu_type, pic); 553 554 /* 555 * If a bios file was provided, attempt to map it into memory 556 */ 557 if (machine->firmware) { 558 char *fn; 559 int image_size; 560 561 if (drive_get(IF_PFLASH, 0, 0)) { 562 error_report("The contents of the first flash device may be " 563 "specified with -bios or with -drive if=pflash... " 564 "but you cannot use both options at once"); 565 exit(1); 566 } 567 fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, machine->firmware); 568 if (!fn) { 569 error_report("Could not find ROM image '%s'", machine->firmware); 570 exit(1); 571 } 572 image_size = load_image_targphys(fn, map[VE_NORFLASH0], 573 VEXPRESS_FLASH_SIZE); 574 g_free(fn); 575 if (image_size < 0) { 576 error_report("Could not load ROM image '%s'", machine->firmware); 577 exit(1); 578 } 579 } 580 581 /* Motherboard peripherals: the wiring is the same but the 582 * addresses vary between the legacy and A-Series memory maps. 583 */ 584 585 sys_id = 0x1190f500; 586 587 sysctl = qdev_new("realview_sysctl"); 588 qdev_prop_set_uint32(sysctl, "sys_id", sys_id); 589 qdev_prop_set_uint32(sysctl, "proc_id", daughterboard->proc_id); 590 591 db_voltage = qlist_new(); 592 for (i = 0; i < daughterboard->num_voltage_sensors; i++) { 593 qlist_append_int(db_voltage, daughterboard->voltages[i]); 594 } 595 qdev_prop_set_array(sysctl, "db-voltage", db_voltage); 596 597 db_clock = qlist_new(); 598 for (i = 0; i < daughterboard->num_clocks; i++) { 599 qlist_append_int(db_clock, daughterboard->clocks[i]); 600 } 601 qdev_prop_set_array(sysctl, "db-clock", db_clock); 602 603 sysbus_realize_and_unref(SYS_BUS_DEVICE(sysctl), &error_fatal); 604 sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, map[VE_SYSREGS]); 605 606 /* VE_SP810: not modelled */ 607 /* VE_SERIALPCI: not modelled */ 608 609 pl041 = qdev_new("pl041"); 610 qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512); 611 if (machine->audiodev) { 612 qdev_prop_set_string(pl041, "audiodev", machine->audiodev); 613 } 614 sysbus_realize_and_unref(SYS_BUS_DEVICE(pl041), &error_fatal); 615 sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, map[VE_PL041]); 616 sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[11]); 617 618 dev = sysbus_create_varargs("pl181", map[VE_MMCI], pic[9], pic[10], NULL); 619 /* Wire up MMC card detect and read-only signals */ 620 qdev_connect_gpio_out_named(dev, "card-read-only", 0, 621 qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT)); 622 qdev_connect_gpio_out_named(dev, "card-inserted", 0, 623 qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN)); 624 dinfo = drive_get(IF_SD, 0, 0); 625 if (dinfo) { 626 DeviceState *card; 627 628 card = qdev_new(TYPE_SD_CARD); 629 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo), 630 &error_fatal); 631 qdev_realize_and_unref(card, qdev_get_child_bus(dev, "sd-bus"), 632 &error_fatal); 633 } 634 635 sysbus_create_simple("pl050_keyboard", map[VE_KMI0], pic[12]); 636 sysbus_create_simple("pl050_mouse", map[VE_KMI1], pic[13]); 637 638 pl011_create(map[VE_UART0], pic[5], serial_hd(0)); 639 pl011_create(map[VE_UART1], pic[6], serial_hd(1)); 640 pl011_create(map[VE_UART2], pic[7], serial_hd(2)); 641 pl011_create(map[VE_UART3], pic[8], serial_hd(3)); 642 643 sysbus_create_simple("sp804", map[VE_TIMER01], pic[2]); 644 sysbus_create_simple("sp804", map[VE_TIMER23], pic[3]); 645 646 dev = sysbus_create_simple(TYPE_ARM_SBCON_I2C, map[VE_SERIALDVI], NULL); 647 i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c"); 648 i2c_slave_create_simple(i2c, "sii9022", 0x39); 649 650 sysbus_create_simple("pl031", map[VE_RTC], pic[4]); /* RTC */ 651 652 /* VE_COMPACTFLASH: not modelled */ 653 654 sysbus_create_simple("pl111", map[VE_CLCD], pic[14]); 655 656 dinfo = drive_get(IF_PFLASH, 0, 0); 657 pflash0 = ve_pflash_cfi01_register(map[VE_NORFLASH0], "vexpress.flash0", 658 dinfo); 659 660 if (map[VE_NORFLASHALIAS] != -1) { 661 /* Map flash 0 as an alias into low memory */ 662 MemoryRegion *flash0mem; 663 flash0mem = sysbus_mmio_get_region(SYS_BUS_DEVICE(pflash0), 0); 664 memory_region_init_alias(&vms->flashalias, NULL, "vexpress.flashalias", 665 flash0mem, 0, VEXPRESS_FLASH_SIZE); 666 memory_region_add_subregion(sysmem, map[VE_NORFLASHALIAS], &vms->flashalias); 667 } 668 669 dinfo = drive_get(IF_PFLASH, 0, 1); 670 ve_pflash_cfi01_register(map[VE_NORFLASH1], "vexpress.flash1", dinfo); 671 672 sram_size = 0x2000000; 673 memory_region_init_ram(&vms->sram, NULL, "vexpress.sram", sram_size, 674 &error_fatal); 675 memory_region_add_subregion(sysmem, map[VE_SRAM], &vms->sram); 676 677 vram_size = 0x800000; 678 memory_region_init_ram(&vms->vram, NULL, "vexpress.vram", vram_size, 679 &error_fatal); 680 memory_region_add_subregion(sysmem, map[VE_VIDEORAM], &vms->vram); 681 682 /* 0x4e000000 LAN9118 Ethernet */ 683 if (nd_table[0].used) { 684 lan9118_init(&nd_table[0], map[VE_ETHERNET], pic[15]); 685 } 686 687 /* VE_USB: not modelled */ 688 689 /* VE_DAPROM: not modelled */ 690 691 /* Create mmio transports, so the user can create virtio backends 692 * (which will be automatically plugged in to the transports). If 693 * no backend is created the transport will just sit harmlessly idle. 694 */ 695 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) { 696 sysbus_create_simple("virtio-mmio", map[VE_VIRTIO] + 0x200 * i, 697 pic[40 + i]); 698 } 699 700 daughterboard->bootinfo.ram_size = machine->ram_size; 701 daughterboard->bootinfo.board_id = VEXPRESS_BOARD_ID; 702 daughterboard->bootinfo.loader_start = daughterboard->loader_start; 703 daughterboard->bootinfo.smp_loader_start = map[VE_SRAM]; 704 daughterboard->bootinfo.smp_bootreg_addr = map[VE_SYSREGS] + 0x30; 705 daughterboard->bootinfo.gic_cpu_if_addr = daughterboard->gic_cpu_if_addr; 706 daughterboard->bootinfo.modify_dtb = vexpress_modify_dtb; 707 /* When booting Linux we should be in secure state if the CPU has one. */ 708 daughterboard->bootinfo.secure_boot = vms->secure; 709 arm_load_kernel(ARM_CPU(first_cpu), machine, &daughterboard->bootinfo); 710 } 711 712 static bool vexpress_get_secure(Object *obj, Error **errp) 713 { 714 VexpressMachineState *vms = VEXPRESS_MACHINE(obj); 715 716 return vms->secure; 717 } 718 719 static void vexpress_set_secure(Object *obj, bool value, Error **errp) 720 { 721 VexpressMachineState *vms = VEXPRESS_MACHINE(obj); 722 723 vms->secure = value; 724 } 725 726 static bool vexpress_get_virt(Object *obj, Error **errp) 727 { 728 VexpressMachineState *vms = VEXPRESS_MACHINE(obj); 729 730 return vms->virt; 731 } 732 733 static void vexpress_set_virt(Object *obj, bool value, Error **errp) 734 { 735 VexpressMachineState *vms = VEXPRESS_MACHINE(obj); 736 737 vms->virt = value; 738 } 739 740 static void vexpress_instance_init(Object *obj) 741 { 742 VexpressMachineState *vms = VEXPRESS_MACHINE(obj); 743 744 /* EL3 is enabled by default on vexpress */ 745 vms->secure = true; 746 } 747 748 static void vexpress_a15_instance_init(Object *obj) 749 { 750 VexpressMachineState *vms = VEXPRESS_MACHINE(obj); 751 752 /* 753 * For the vexpress-a15, EL2 is by default enabled if EL3 is, 754 * but can also be specifically set to on or off. 755 */ 756 vms->virt = true; 757 } 758 759 static void vexpress_a9_instance_init(Object *obj) 760 { 761 VexpressMachineState *vms = VEXPRESS_MACHINE(obj); 762 763 /* The A9 doesn't have the virt extensions */ 764 vms->virt = false; 765 } 766 767 static void vexpress_class_init(ObjectClass *oc, void *data) 768 { 769 MachineClass *mc = MACHINE_CLASS(oc); 770 771 mc->desc = "ARM Versatile Express"; 772 mc->init = vexpress_common_init; 773 mc->max_cpus = 4; 774 mc->ignore_memory_transaction_failures = true; 775 mc->default_ram_id = "vexpress.highmem"; 776 777 machine_add_audiodev_property(mc); 778 object_class_property_add_bool(oc, "secure", vexpress_get_secure, 779 vexpress_set_secure); 780 object_class_property_set_description(oc, "secure", 781 "Set on/off to enable/disable the ARM " 782 "Security Extensions (TrustZone)"); 783 } 784 785 static void vexpress_a9_class_init(ObjectClass *oc, void *data) 786 { 787 MachineClass *mc = MACHINE_CLASS(oc); 788 VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc); 789 790 mc->desc = "ARM Versatile Express for Cortex-A9"; 791 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9"); 792 793 vmc->daughterboard = &a9_daughterboard; 794 } 795 796 static void vexpress_a15_class_init(ObjectClass *oc, void *data) 797 { 798 MachineClass *mc = MACHINE_CLASS(oc); 799 VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc); 800 801 mc->desc = "ARM Versatile Express for Cortex-A15"; 802 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); 803 804 vmc->daughterboard = &a15_daughterboard; 805 806 object_class_property_add_bool(oc, "virtualization", vexpress_get_virt, 807 vexpress_set_virt); 808 object_class_property_set_description(oc, "virtualization", 809 "Set on/off to enable/disable the ARM " 810 "Virtualization Extensions " 811 "(defaults to same as 'secure')"); 812 813 } 814 815 static const TypeInfo vexpress_info = { 816 .name = TYPE_VEXPRESS_MACHINE, 817 .parent = TYPE_MACHINE, 818 .abstract = true, 819 .instance_size = sizeof(VexpressMachineState), 820 .instance_init = vexpress_instance_init, 821 .class_size = sizeof(VexpressMachineClass), 822 .class_init = vexpress_class_init, 823 }; 824 825 static const TypeInfo vexpress_a9_info = { 826 .name = TYPE_VEXPRESS_A9_MACHINE, 827 .parent = TYPE_VEXPRESS_MACHINE, 828 .class_init = vexpress_a9_class_init, 829 .instance_init = vexpress_a9_instance_init, 830 }; 831 832 static const TypeInfo vexpress_a15_info = { 833 .name = TYPE_VEXPRESS_A15_MACHINE, 834 .parent = TYPE_VEXPRESS_MACHINE, 835 .class_init = vexpress_a15_class_init, 836 .instance_init = vexpress_a15_instance_init, 837 }; 838 839 static void vexpress_machine_init(void) 840 { 841 type_register_static(&vexpress_info); 842 type_register_static(&vexpress_a9_info); 843 type_register_static(&vexpress_a15_info); 844 } 845 846 type_init(vexpress_machine_init); 847