1 /* 2 * ARM Versatile Express emulation. 3 * 4 * Copyright (c) 2010 - 2011 B Labs Ltd. 5 * Copyright (c) 2011 Linaro Limited 6 * Written by Bahadir Balban, Amit Mahajan, Peter Maydell 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, see <http://www.gnu.org/licenses/>. 19 * 20 * Contributions after 2012-01-13 are licensed under the terms of the 21 * GNU GPL, version 2 or (at your option) any later version. 22 */ 23 24 #include "qemu/osdep.h" 25 #include "qapi/error.h" 26 #include "qemu/datadir.h" 27 #include "hw/sysbus.h" 28 #include "hw/arm/boot.h" 29 #include "hw/arm/primecell.h" 30 #include "hw/net/lan9118.h" 31 #include "hw/i2c/i2c.h" 32 #include "net/net.h" 33 #include "sysemu/sysemu.h" 34 #include "hw/boards.h" 35 #include "hw/loader.h" 36 #include "hw/block/flash.h" 37 #include "sysemu/device_tree.h" 38 #include "qemu/error-report.h" 39 #include <libfdt.h> 40 #include "hw/char/pl011.h" 41 #include "hw/cpu/a9mpcore.h" 42 #include "hw/cpu/a15mpcore.h" 43 #include "hw/i2c/arm_sbcon_i2c.h" 44 #include "hw/sd/sd.h" 45 #include "qapi/qmp/qlist.h" 46 #include "qom/object.h" 47 #include "audio/audio.h" 48 #include "target/arm/cpu-qom.h" 49 50 #define VEXPRESS_BOARD_ID 0x8e0 51 #define VEXPRESS_FLASH_SIZE (64 * 1024 * 1024) 52 #define VEXPRESS_FLASH_SECT_SIZE (256 * 1024) 53 54 /* Number of virtio transports to create (0..8; limited by 55 * number of available IRQ lines). 56 */ 57 #define NUM_VIRTIO_TRANSPORTS 4 58 59 /* Address maps for peripherals: 60 * the Versatile Express motherboard has two possible maps, 61 * the "legacy" one (used for A9) and the "Cortex-A Series" 62 * map (used for newer cores). 63 * Individual daughterboards can also have different maps for 64 * their peripherals. 65 */ 66 67 enum { 68 VE_SYSREGS, 69 VE_SP810, 70 VE_SERIALPCI, 71 VE_PL041, 72 VE_MMCI, 73 VE_KMI0, 74 VE_KMI1, 75 VE_UART0, 76 VE_UART1, 77 VE_UART2, 78 VE_UART3, 79 VE_WDT, 80 VE_TIMER01, 81 VE_TIMER23, 82 VE_SERIALDVI, 83 VE_RTC, 84 VE_COMPACTFLASH, 85 VE_CLCD, 86 VE_NORFLASH0, 87 VE_NORFLASH1, 88 VE_NORFLASHALIAS, 89 VE_SRAM, 90 VE_VIDEORAM, 91 VE_ETHERNET, 92 VE_USB, 93 VE_DAPROM, 94 VE_VIRTIO, 95 }; 96 97 static hwaddr motherboard_legacy_map[] = { 98 [VE_NORFLASHALIAS] = 0, 99 /* CS7: 0x10000000 .. 0x10020000 */ 100 [VE_SYSREGS] = 0x10000000, 101 [VE_SP810] = 0x10001000, 102 [VE_SERIALPCI] = 0x10002000, 103 [VE_PL041] = 0x10004000, 104 [VE_MMCI] = 0x10005000, 105 [VE_KMI0] = 0x10006000, 106 [VE_KMI1] = 0x10007000, 107 [VE_UART0] = 0x10009000, 108 [VE_UART1] = 0x1000a000, 109 [VE_UART2] = 0x1000b000, 110 [VE_UART3] = 0x1000c000, 111 [VE_WDT] = 0x1000f000, 112 [VE_TIMER01] = 0x10011000, 113 [VE_TIMER23] = 0x10012000, 114 [VE_VIRTIO] = 0x10013000, 115 [VE_SERIALDVI] = 0x10016000, 116 [VE_RTC] = 0x10017000, 117 [VE_COMPACTFLASH] = 0x1001a000, 118 [VE_CLCD] = 0x1001f000, 119 /* CS0: 0x40000000 .. 0x44000000 */ 120 [VE_NORFLASH0] = 0x40000000, 121 /* CS1: 0x44000000 .. 0x48000000 */ 122 [VE_NORFLASH1] = 0x44000000, 123 /* CS2: 0x48000000 .. 0x4a000000 */ 124 [VE_SRAM] = 0x48000000, 125 /* CS3: 0x4c000000 .. 0x50000000 */ 126 [VE_VIDEORAM] = 0x4c000000, 127 [VE_ETHERNET] = 0x4e000000, 128 [VE_USB] = 0x4f000000, 129 }; 130 131 static hwaddr motherboard_aseries_map[] = { 132 [VE_NORFLASHALIAS] = 0, 133 /* CS0: 0x08000000 .. 0x0c000000 */ 134 [VE_NORFLASH0] = 0x08000000, 135 /* CS4: 0x0c000000 .. 0x10000000 */ 136 [VE_NORFLASH1] = 0x0c000000, 137 /* CS5: 0x10000000 .. 0x14000000 */ 138 /* CS1: 0x14000000 .. 0x18000000 */ 139 [VE_SRAM] = 0x14000000, 140 /* CS2: 0x18000000 .. 0x1c000000 */ 141 [VE_VIDEORAM] = 0x18000000, 142 [VE_ETHERNET] = 0x1a000000, 143 [VE_USB] = 0x1b000000, 144 /* CS3: 0x1c000000 .. 0x20000000 */ 145 [VE_DAPROM] = 0x1c000000, 146 [VE_SYSREGS] = 0x1c010000, 147 [VE_SP810] = 0x1c020000, 148 [VE_SERIALPCI] = 0x1c030000, 149 [VE_PL041] = 0x1c040000, 150 [VE_MMCI] = 0x1c050000, 151 [VE_KMI0] = 0x1c060000, 152 [VE_KMI1] = 0x1c070000, 153 [VE_UART0] = 0x1c090000, 154 [VE_UART1] = 0x1c0a0000, 155 [VE_UART2] = 0x1c0b0000, 156 [VE_UART3] = 0x1c0c0000, 157 [VE_WDT] = 0x1c0f0000, 158 [VE_TIMER01] = 0x1c110000, 159 [VE_TIMER23] = 0x1c120000, 160 [VE_VIRTIO] = 0x1c130000, 161 [VE_SERIALDVI] = 0x1c160000, 162 [VE_RTC] = 0x1c170000, 163 [VE_COMPACTFLASH] = 0x1c1a0000, 164 [VE_CLCD] = 0x1c1f0000, 165 }; 166 167 /* Structure defining the peculiarities of a specific daughterboard */ 168 169 typedef struct VEDBoardInfo VEDBoardInfo; 170 171 struct VexpressMachineClass { 172 MachineClass parent; 173 VEDBoardInfo *daughterboard; 174 }; 175 176 struct VexpressMachineState { 177 MachineState parent; 178 MemoryRegion vram; 179 MemoryRegion sram; 180 MemoryRegion flashalias; 181 MemoryRegion a15sram; 182 bool secure; 183 bool virt; 184 }; 185 186 #define TYPE_VEXPRESS_MACHINE "vexpress" 187 #define TYPE_VEXPRESS_A9_MACHINE MACHINE_TYPE_NAME("vexpress-a9") 188 #define TYPE_VEXPRESS_A15_MACHINE MACHINE_TYPE_NAME("vexpress-a15") 189 OBJECT_DECLARE_TYPE(VexpressMachineState, VexpressMachineClass, VEXPRESS_MACHINE) 190 191 typedef void DBoardInitFn(VexpressMachineState *machine, 192 ram_addr_t ram_size, 193 const char *cpu_type, 194 qemu_irq *pic); 195 196 struct VEDBoardInfo { 197 struct arm_boot_info bootinfo; 198 const hwaddr *motherboard_map; 199 hwaddr loader_start; 200 const hwaddr gic_cpu_if_addr; 201 uint32_t proc_id; 202 uint32_t num_voltage_sensors; 203 const uint32_t *voltages; 204 uint32_t num_clocks; 205 const uint32_t *clocks; 206 DBoardInitFn *init; 207 }; 208 209 static void init_cpus(MachineState *ms, const char *cpu_type, 210 const char *privdev, hwaddr periphbase, 211 qemu_irq *pic, bool secure, bool virt) 212 { 213 DeviceState *dev; 214 SysBusDevice *busdev; 215 int n; 216 unsigned int smp_cpus = ms->smp.cpus; 217 218 /* Create the actual CPUs */ 219 for (n = 0; n < smp_cpus; n++) { 220 Object *cpuobj = object_new(cpu_type); 221 222 if (!secure) { 223 object_property_set_bool(cpuobj, "has_el3", false, NULL); 224 } 225 if (!virt) { 226 if (object_property_find(cpuobj, "has_el2")) { 227 object_property_set_bool(cpuobj, "has_el2", false, NULL); 228 } 229 } 230 231 if (object_property_find(cpuobj, "reset-cbar")) { 232 object_property_set_int(cpuobj, "reset-cbar", periphbase, 233 &error_abort); 234 } 235 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); 236 } 237 238 /* Create the private peripheral devices (including the GIC); 239 * this must happen after the CPUs are created because a15mpcore_priv 240 * wires itself up to the CPU's generic_timer gpio out lines. 241 */ 242 dev = qdev_new(privdev); 243 qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); 244 busdev = SYS_BUS_DEVICE(dev); 245 sysbus_realize_and_unref(busdev, &error_fatal); 246 sysbus_mmio_map(busdev, 0, periphbase); 247 248 /* Interrupts [42:0] are from the motherboard; 249 * [47:43] are reserved; [63:48] are daughterboard 250 * peripherals. Note that some documentation numbers 251 * external interrupts starting from 32 (because there 252 * are internal interrupts 0..31). 253 */ 254 for (n = 0; n < 64; n++) { 255 pic[n] = qdev_get_gpio_in(dev, n); 256 } 257 258 /* Connect the CPUs to the GIC */ 259 for (n = 0; n < smp_cpus; n++) { 260 DeviceState *cpudev = DEVICE(qemu_get_cpu(n)); 261 262 sysbus_connect_irq(busdev, n, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 263 sysbus_connect_irq(busdev, n + smp_cpus, 264 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 265 sysbus_connect_irq(busdev, n + 2 * smp_cpus, 266 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 267 sysbus_connect_irq(busdev, n + 3 * smp_cpus, 268 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 269 } 270 } 271 272 static void a9_daughterboard_init(VexpressMachineState *vms, 273 ram_addr_t ram_size, 274 const char *cpu_type, 275 qemu_irq *pic) 276 { 277 MachineState *machine = MACHINE(vms); 278 MemoryRegion *sysmem = get_system_memory(); 279 280 if (ram_size > 0x40000000) { 281 /* 1GB is the maximum the address space permits */ 282 error_report("vexpress-a9: cannot model more than 1GB RAM"); 283 exit(1); 284 } 285 286 /* 287 * RAM is from 0x60000000 upwards. The bottom 64MB of the 288 * address space should in theory be remappable to various 289 * things including ROM or RAM; we always map the flash there. 290 */ 291 memory_region_add_subregion(sysmem, 0x60000000, machine->ram); 292 293 /* 0x1e000000 A9MPCore (SCU) private memory region */ 294 init_cpus(machine, cpu_type, TYPE_A9MPCORE_PRIV, 0x1e000000, pic, 295 vms->secure, vms->virt); 296 297 /* Daughterboard peripherals : 0x10020000 .. 0x20000000 */ 298 299 /* 0x10020000 PL111 CLCD (daughterboard) */ 300 sysbus_create_simple("pl111", 0x10020000, pic[44]); 301 302 /* 0x10060000 AXI RAM */ 303 /* 0x100e0000 PL341 Dynamic Memory Controller */ 304 /* 0x100e1000 PL354 Static Memory Controller */ 305 /* 0x100e2000 System Configuration Controller */ 306 307 sysbus_create_simple("sp804", 0x100e4000, pic[48]); 308 /* 0x100e5000 SP805 Watchdog module */ 309 /* 0x100e6000 BP147 TrustZone Protection Controller */ 310 /* 0x100e9000 PL301 'Fast' AXI matrix */ 311 /* 0x100ea000 PL301 'Slow' AXI matrix */ 312 /* 0x100ec000 TrustZone Address Space Controller */ 313 /* 0x10200000 CoreSight debug APB */ 314 /* 0x1e00a000 PL310 L2 Cache Controller */ 315 sysbus_create_varargs("l2x0", 0x1e00a000, NULL); 316 } 317 318 /* Voltage values for SYS_CFG_VOLT daughterboard registers; 319 * values are in microvolts. 320 */ 321 static const uint32_t a9_voltages[] = { 322 1000000, /* VD10 : 1.0V : SoC internal logic voltage */ 323 1000000, /* VD10_S2 : 1.0V : PL310, L2 cache, RAM, non-PL310 logic */ 324 1000000, /* VD10_S3 : 1.0V : Cortex-A9, cores, MPEs, SCU, PL310 logic */ 325 1800000, /* VCC1V8 : 1.8V : DDR2 SDRAM, test chip DDR2 I/O supply */ 326 900000, /* DDR2VTT : 0.9V : DDR2 SDRAM VTT termination voltage */ 327 3300000, /* VCC3V3 : 3.3V : local board supply for misc external logic */ 328 }; 329 330 /* Reset values for daughterboard oscillators (in Hz) */ 331 static const uint32_t a9_clocks[] = { 332 45000000, /* AMBA AXI ACLK: 45MHz */ 333 23750000, /* daughterboard CLCD clock: 23.75MHz */ 334 66670000, /* Test chip reference clock: 66.67MHz */ 335 }; 336 337 static VEDBoardInfo a9_daughterboard = { 338 .motherboard_map = motherboard_legacy_map, 339 .loader_start = 0x60000000, 340 .gic_cpu_if_addr = 0x1e000100, 341 .proc_id = 0x0c000191, 342 .num_voltage_sensors = ARRAY_SIZE(a9_voltages), 343 .voltages = a9_voltages, 344 .num_clocks = ARRAY_SIZE(a9_clocks), 345 .clocks = a9_clocks, 346 .init = a9_daughterboard_init, 347 }; 348 349 static void a15_daughterboard_init(VexpressMachineState *vms, 350 ram_addr_t ram_size, 351 const char *cpu_type, 352 qemu_irq *pic) 353 { 354 MachineState *machine = MACHINE(vms); 355 MemoryRegion *sysmem = get_system_memory(); 356 357 { 358 /* We have to use a separate 64 bit variable here to avoid the gcc 359 * "comparison is always false due to limited range of data type" 360 * warning if we are on a host where ram_addr_t is 32 bits. 361 */ 362 uint64_t rsz = ram_size; 363 if (rsz > (30ULL * 1024 * 1024 * 1024)) { 364 error_report("vexpress-a15: cannot model more than 30GB RAM"); 365 exit(1); 366 } 367 } 368 369 /* RAM is from 0x80000000 upwards; there is no low-memory alias for it. */ 370 memory_region_add_subregion(sysmem, 0x80000000, machine->ram); 371 372 /* 0x2c000000 A15MPCore private memory region (GIC) */ 373 init_cpus(machine, cpu_type, TYPE_A15MPCORE_PRIV, 374 0x2c000000, pic, vms->secure, vms->virt); 375 376 /* A15 daughterboard peripherals: */ 377 378 /* 0x20000000: CoreSight interfaces: not modelled */ 379 /* 0x2a000000: PL301 AXI interconnect: not modelled */ 380 /* 0x2a420000: SCC: not modelled */ 381 /* 0x2a430000: system counter: not modelled */ 382 /* 0x2b000000: HDLCD controller: not modelled */ 383 /* 0x2b060000: SP805 watchdog: not modelled */ 384 /* 0x2b0a0000: PL341 dynamic memory controller: not modelled */ 385 /* 0x2e000000: system SRAM */ 386 memory_region_init_ram(&vms->a15sram, NULL, "vexpress.a15sram", 0x10000, 387 &error_fatal); 388 memory_region_add_subregion(sysmem, 0x2e000000, &vms->a15sram); 389 390 /* 0x7ffb0000: DMA330 DMA controller: not modelled */ 391 /* 0x7ffd0000: PL354 static memory controller: not modelled */ 392 } 393 394 static const uint32_t a15_voltages[] = { 395 900000, /* Vcore: 0.9V : CPU core voltage */ 396 }; 397 398 static const uint32_t a15_clocks[] = { 399 60000000, /* OSCCLK0: 60MHz : CPU_CLK reference */ 400 0, /* OSCCLK1: reserved */ 401 0, /* OSCCLK2: reserved */ 402 0, /* OSCCLK3: reserved */ 403 40000000, /* OSCCLK4: 40MHz : external AXI master clock */ 404 23750000, /* OSCCLK5: 23.75MHz : HDLCD PLL reference */ 405 50000000, /* OSCCLK6: 50MHz : static memory controller clock */ 406 60000000, /* OSCCLK7: 60MHz : SYSCLK reference */ 407 40000000, /* OSCCLK8: 40MHz : DDR2 PLL reference */ 408 }; 409 410 static VEDBoardInfo a15_daughterboard = { 411 .motherboard_map = motherboard_aseries_map, 412 .loader_start = 0x80000000, 413 .gic_cpu_if_addr = 0x2c002000, 414 .proc_id = 0x14000237, 415 .num_voltage_sensors = ARRAY_SIZE(a15_voltages), 416 .voltages = a15_voltages, 417 .num_clocks = ARRAY_SIZE(a15_clocks), 418 .clocks = a15_clocks, 419 .init = a15_daughterboard_init, 420 }; 421 422 static int add_virtio_mmio_node(void *fdt, uint32_t acells, uint32_t scells, 423 hwaddr addr, hwaddr size, uint32_t intc, 424 int irq) 425 { 426 /* Add a virtio_mmio node to the device tree blob: 427 * virtio_mmio@ADDRESS { 428 * compatible = "virtio,mmio"; 429 * reg = <ADDRESS, SIZE>; 430 * interrupt-parent = <&intc>; 431 * interrupts = <0, irq, 1>; 432 * } 433 * (Note that the format of the interrupts property is dependent on the 434 * interrupt controller that interrupt-parent points to; these are for 435 * the ARM GIC and indicate an SPI interrupt, rising-edge-triggered.) 436 */ 437 int rc; 438 char *nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, addr); 439 440 rc = qemu_fdt_add_subnode(fdt, nodename); 441 rc |= qemu_fdt_setprop_string(fdt, nodename, 442 "compatible", "virtio,mmio"); 443 rc |= qemu_fdt_setprop_sized_cells(fdt, nodename, "reg", 444 acells, addr, scells, size); 445 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", intc); 446 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 0, irq, 1); 447 qemu_fdt_setprop(fdt, nodename, "dma-coherent", NULL, 0); 448 g_free(nodename); 449 if (rc) { 450 return -1; 451 } 452 return 0; 453 } 454 455 static uint32_t find_int_controller(void *fdt) 456 { 457 /* Find the FDT node corresponding to the interrupt controller 458 * for virtio-mmio devices. We do this by scanning the fdt for 459 * a node with the right compatibility, since we know there is 460 * only one GIC on a vexpress board. 461 * We return the phandle of the node, or 0 if none was found. 462 */ 463 const char *compat = "arm,cortex-a9-gic"; 464 int offset; 465 466 offset = fdt_node_offset_by_compatible(fdt, -1, compat); 467 if (offset >= 0) { 468 return fdt_get_phandle(fdt, offset); 469 } 470 return 0; 471 } 472 473 static void vexpress_modify_dtb(const struct arm_boot_info *info, void *fdt) 474 { 475 uint32_t acells, scells, intc; 476 const VEDBoardInfo *daughterboard = (const VEDBoardInfo *)info; 477 478 acells = qemu_fdt_getprop_cell(fdt, "/", "#address-cells", 479 NULL, &error_fatal); 480 scells = qemu_fdt_getprop_cell(fdt, "/", "#size-cells", 481 NULL, &error_fatal); 482 intc = find_int_controller(fdt); 483 if (!intc) { 484 /* Not fatal, we just won't provide virtio. This will 485 * happen with older device tree blobs. 486 */ 487 warn_report("couldn't find interrupt controller in " 488 "dtb; will not include virtio-mmio devices in the dtb"); 489 } else { 490 int i; 491 const hwaddr *map = daughterboard->motherboard_map; 492 493 /* We iterate backwards here because adding nodes 494 * to the dtb puts them in last-first. 495 */ 496 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) { 497 add_virtio_mmio_node(fdt, acells, scells, 498 map[VE_VIRTIO] + 0x200 * i, 499 0x200, intc, 40 + i); 500 } 501 } 502 } 503 504 505 /* Open code a private version of pflash registration since we 506 * need to set non-default device width for VExpress platform. 507 */ 508 static PFlashCFI01 *ve_pflash_cfi01_register(hwaddr base, const char *name, 509 DriveInfo *di) 510 { 511 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 512 513 if (di) { 514 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(di)); 515 } 516 517 qdev_prop_set_uint32(dev, "num-blocks", 518 VEXPRESS_FLASH_SIZE / VEXPRESS_FLASH_SECT_SIZE); 519 qdev_prop_set_uint64(dev, "sector-length", VEXPRESS_FLASH_SECT_SIZE); 520 qdev_prop_set_uint8(dev, "width", 4); 521 qdev_prop_set_uint8(dev, "device-width", 2); 522 qdev_prop_set_bit(dev, "big-endian", false); 523 qdev_prop_set_uint16(dev, "id0", 0x89); 524 qdev_prop_set_uint16(dev, "id1", 0x18); 525 qdev_prop_set_uint16(dev, "id2", 0x00); 526 qdev_prop_set_uint16(dev, "id3", 0x00); 527 qdev_prop_set_string(dev, "name", name); 528 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 529 530 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 531 return PFLASH_CFI01(dev); 532 } 533 534 static void vexpress_common_init(MachineState *machine) 535 { 536 VexpressMachineState *vms = VEXPRESS_MACHINE(machine); 537 VexpressMachineClass *vmc = VEXPRESS_MACHINE_GET_CLASS(machine); 538 VEDBoardInfo *daughterboard = vmc->daughterboard; 539 DeviceState *dev, *sysctl, *pl041; 540 qemu_irq pic[64]; 541 uint32_t sys_id; 542 DriveInfo *dinfo; 543 PFlashCFI01 *pflash0; 544 I2CBus *i2c; 545 ram_addr_t vram_size, sram_size; 546 MemoryRegion *sysmem = get_system_memory(); 547 const hwaddr *map = daughterboard->motherboard_map; 548 QList *db_voltage, *db_clock; 549 int i; 550 551 daughterboard->init(vms, machine->ram_size, machine->cpu_type, pic); 552 553 /* 554 * If a bios file was provided, attempt to map it into memory 555 */ 556 if (machine->firmware) { 557 char *fn; 558 int image_size; 559 560 if (drive_get(IF_PFLASH, 0, 0)) { 561 error_report("The contents of the first flash device may be " 562 "specified with -bios or with -drive if=pflash... " 563 "but you cannot use both options at once"); 564 exit(1); 565 } 566 fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, machine->firmware); 567 if (!fn) { 568 error_report("Could not find ROM image '%s'", machine->firmware); 569 exit(1); 570 } 571 image_size = load_image_targphys(fn, map[VE_NORFLASH0], 572 VEXPRESS_FLASH_SIZE); 573 g_free(fn); 574 if (image_size < 0) { 575 error_report("Could not load ROM image '%s'", machine->firmware); 576 exit(1); 577 } 578 } 579 580 /* Motherboard peripherals: the wiring is the same but the 581 * addresses vary between the legacy and A-Series memory maps. 582 */ 583 584 sys_id = 0x1190f500; 585 586 sysctl = qdev_new("realview_sysctl"); 587 qdev_prop_set_uint32(sysctl, "sys_id", sys_id); 588 qdev_prop_set_uint32(sysctl, "proc_id", daughterboard->proc_id); 589 590 db_voltage = qlist_new(); 591 for (i = 0; i < daughterboard->num_voltage_sensors; i++) { 592 qlist_append_int(db_voltage, daughterboard->voltages[i]); 593 } 594 qdev_prop_set_array(sysctl, "db-voltage", db_voltage); 595 596 db_clock = qlist_new(); 597 for (i = 0; i < daughterboard->num_clocks; i++) { 598 qlist_append_int(db_clock, daughterboard->clocks[i]); 599 } 600 qdev_prop_set_array(sysctl, "db-clock", db_clock); 601 602 sysbus_realize_and_unref(SYS_BUS_DEVICE(sysctl), &error_fatal); 603 sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, map[VE_SYSREGS]); 604 605 /* VE_SP810: not modelled */ 606 /* VE_SERIALPCI: not modelled */ 607 608 pl041 = qdev_new("pl041"); 609 qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512); 610 if (machine->audiodev) { 611 qdev_prop_set_string(pl041, "audiodev", machine->audiodev); 612 } 613 sysbus_realize_and_unref(SYS_BUS_DEVICE(pl041), &error_fatal); 614 sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, map[VE_PL041]); 615 sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[11]); 616 617 dev = sysbus_create_varargs("pl181", map[VE_MMCI], pic[9], pic[10], NULL); 618 /* Wire up MMC card detect and read-only signals */ 619 qdev_connect_gpio_out_named(dev, "card-read-only", 0, 620 qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT)); 621 qdev_connect_gpio_out_named(dev, "card-inserted", 0, 622 qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN)); 623 dinfo = drive_get(IF_SD, 0, 0); 624 if (dinfo) { 625 DeviceState *card; 626 627 card = qdev_new(TYPE_SD_CARD); 628 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo), 629 &error_fatal); 630 qdev_realize_and_unref(card, qdev_get_child_bus(dev, "sd-bus"), 631 &error_fatal); 632 } 633 634 sysbus_create_simple("pl050_keyboard", map[VE_KMI0], pic[12]); 635 sysbus_create_simple("pl050_mouse", map[VE_KMI1], pic[13]); 636 637 pl011_create(map[VE_UART0], pic[5], serial_hd(0)); 638 pl011_create(map[VE_UART1], pic[6], serial_hd(1)); 639 pl011_create(map[VE_UART2], pic[7], serial_hd(2)); 640 pl011_create(map[VE_UART3], pic[8], serial_hd(3)); 641 642 sysbus_create_simple("sp804", map[VE_TIMER01], pic[2]); 643 sysbus_create_simple("sp804", map[VE_TIMER23], pic[3]); 644 645 dev = sysbus_create_simple(TYPE_ARM_SBCON_I2C, map[VE_SERIALDVI], NULL); 646 i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c"); 647 i2c_slave_create_simple(i2c, "sii9022", 0x39); 648 649 sysbus_create_simple("pl031", map[VE_RTC], pic[4]); /* RTC */ 650 651 /* VE_COMPACTFLASH: not modelled */ 652 653 sysbus_create_simple("pl111", map[VE_CLCD], pic[14]); 654 655 dinfo = drive_get(IF_PFLASH, 0, 0); 656 pflash0 = ve_pflash_cfi01_register(map[VE_NORFLASH0], "vexpress.flash0", 657 dinfo); 658 659 if (map[VE_NORFLASHALIAS] != -1) { 660 /* Map flash 0 as an alias into low memory */ 661 MemoryRegion *flash0mem; 662 flash0mem = sysbus_mmio_get_region(SYS_BUS_DEVICE(pflash0), 0); 663 memory_region_init_alias(&vms->flashalias, NULL, "vexpress.flashalias", 664 flash0mem, 0, VEXPRESS_FLASH_SIZE); 665 memory_region_add_subregion(sysmem, map[VE_NORFLASHALIAS], &vms->flashalias); 666 } 667 668 dinfo = drive_get(IF_PFLASH, 0, 1); 669 ve_pflash_cfi01_register(map[VE_NORFLASH1], "vexpress.flash1", dinfo); 670 671 sram_size = 0x2000000; 672 memory_region_init_ram(&vms->sram, NULL, "vexpress.sram", sram_size, 673 &error_fatal); 674 memory_region_add_subregion(sysmem, map[VE_SRAM], &vms->sram); 675 676 vram_size = 0x800000; 677 memory_region_init_ram(&vms->vram, NULL, "vexpress.vram", vram_size, 678 &error_fatal); 679 memory_region_add_subregion(sysmem, map[VE_VIDEORAM], &vms->vram); 680 681 /* 0x4e000000 LAN9118 Ethernet */ 682 if (qemu_find_nic_info("lan9118", true, NULL)) { 683 lan9118_init(map[VE_ETHERNET], pic[15]); 684 } 685 686 /* VE_USB: not modelled */ 687 688 /* VE_DAPROM: not modelled */ 689 690 /* Create mmio transports, so the user can create virtio backends 691 * (which will be automatically plugged in to the transports). If 692 * no backend is created the transport will just sit harmlessly idle. 693 */ 694 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) { 695 sysbus_create_simple("virtio-mmio", map[VE_VIRTIO] + 0x200 * i, 696 pic[40 + i]); 697 } 698 699 daughterboard->bootinfo.ram_size = machine->ram_size; 700 daughterboard->bootinfo.board_id = VEXPRESS_BOARD_ID; 701 daughterboard->bootinfo.loader_start = daughterboard->loader_start; 702 daughterboard->bootinfo.smp_loader_start = map[VE_SRAM]; 703 daughterboard->bootinfo.smp_bootreg_addr = map[VE_SYSREGS] + 0x30; 704 daughterboard->bootinfo.gic_cpu_if_addr = daughterboard->gic_cpu_if_addr; 705 daughterboard->bootinfo.modify_dtb = vexpress_modify_dtb; 706 /* When booting Linux we should be in secure state if the CPU has one. */ 707 daughterboard->bootinfo.secure_boot = vms->secure; 708 arm_load_kernel(ARM_CPU(first_cpu), machine, &daughterboard->bootinfo); 709 } 710 711 static bool vexpress_get_secure(Object *obj, Error **errp) 712 { 713 VexpressMachineState *vms = VEXPRESS_MACHINE(obj); 714 715 return vms->secure; 716 } 717 718 static void vexpress_set_secure(Object *obj, bool value, Error **errp) 719 { 720 VexpressMachineState *vms = VEXPRESS_MACHINE(obj); 721 722 vms->secure = value; 723 } 724 725 static bool vexpress_get_virt(Object *obj, Error **errp) 726 { 727 VexpressMachineState *vms = VEXPRESS_MACHINE(obj); 728 729 return vms->virt; 730 } 731 732 static void vexpress_set_virt(Object *obj, bool value, Error **errp) 733 { 734 VexpressMachineState *vms = VEXPRESS_MACHINE(obj); 735 736 vms->virt = value; 737 } 738 739 static void vexpress_instance_init(Object *obj) 740 { 741 VexpressMachineState *vms = VEXPRESS_MACHINE(obj); 742 743 /* EL3 is enabled by default on vexpress */ 744 vms->secure = true; 745 } 746 747 static void vexpress_a15_instance_init(Object *obj) 748 { 749 VexpressMachineState *vms = VEXPRESS_MACHINE(obj); 750 751 /* 752 * For the vexpress-a15, EL2 is by default enabled if EL3 is, 753 * but can also be specifically set to on or off. 754 */ 755 vms->virt = true; 756 } 757 758 static void vexpress_a9_instance_init(Object *obj) 759 { 760 VexpressMachineState *vms = VEXPRESS_MACHINE(obj); 761 762 /* The A9 doesn't have the virt extensions */ 763 vms->virt = false; 764 } 765 766 static void vexpress_class_init(ObjectClass *oc, void *data) 767 { 768 MachineClass *mc = MACHINE_CLASS(oc); 769 770 mc->desc = "ARM Versatile Express"; 771 mc->init = vexpress_common_init; 772 mc->max_cpus = 4; 773 mc->ignore_memory_transaction_failures = true; 774 mc->default_ram_id = "vexpress.highmem"; 775 776 machine_add_audiodev_property(mc); 777 object_class_property_add_bool(oc, "secure", vexpress_get_secure, 778 vexpress_set_secure); 779 object_class_property_set_description(oc, "secure", 780 "Set on/off to enable/disable the ARM " 781 "Security Extensions (TrustZone)"); 782 } 783 784 static void vexpress_a9_class_init(ObjectClass *oc, void *data) 785 { 786 MachineClass *mc = MACHINE_CLASS(oc); 787 VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc); 788 789 mc->desc = "ARM Versatile Express for Cortex-A9"; 790 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9"); 791 792 vmc->daughterboard = &a9_daughterboard; 793 } 794 795 static void vexpress_a15_class_init(ObjectClass *oc, void *data) 796 { 797 MachineClass *mc = MACHINE_CLASS(oc); 798 VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc); 799 800 mc->desc = "ARM Versatile Express for Cortex-A15"; 801 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); 802 803 vmc->daughterboard = &a15_daughterboard; 804 805 object_class_property_add_bool(oc, "virtualization", vexpress_get_virt, 806 vexpress_set_virt); 807 object_class_property_set_description(oc, "virtualization", 808 "Set on/off to enable/disable the ARM " 809 "Virtualization Extensions " 810 "(defaults to same as 'secure')"); 811 812 } 813 814 static const TypeInfo vexpress_info = { 815 .name = TYPE_VEXPRESS_MACHINE, 816 .parent = TYPE_MACHINE, 817 .abstract = true, 818 .instance_size = sizeof(VexpressMachineState), 819 .instance_init = vexpress_instance_init, 820 .class_size = sizeof(VexpressMachineClass), 821 .class_init = vexpress_class_init, 822 }; 823 824 static const TypeInfo vexpress_a9_info = { 825 .name = TYPE_VEXPRESS_A9_MACHINE, 826 .parent = TYPE_VEXPRESS_MACHINE, 827 .class_init = vexpress_a9_class_init, 828 .instance_init = vexpress_a9_instance_init, 829 }; 830 831 static const TypeInfo vexpress_a15_info = { 832 .name = TYPE_VEXPRESS_A15_MACHINE, 833 .parent = TYPE_VEXPRESS_MACHINE, 834 .class_init = vexpress_a15_class_init, 835 .instance_init = vexpress_a15_instance_init, 836 }; 837 838 static void vexpress_machine_init(void) 839 { 840 type_register_static(&vexpress_info); 841 type_register_static(&vexpress_a9_info); 842 type_register_static(&vexpress_a15_info); 843 } 844 845 type_init(vexpress_machine_init); 846