1 /* 2 * ARM Versatile Express emulation. 3 * 4 * Copyright (c) 2010 - 2011 B Labs Ltd. 5 * Copyright (c) 2011 Linaro Limited 6 * Written by Bahadir Balban, Amit Mahajan, Peter Maydell 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, see <http://www.gnu.org/licenses/>. 19 * 20 * Contributions after 2012-01-13 are licensed under the terms of the 21 * GNU GPL, version 2 or (at your option) any later version. 22 */ 23 24 #include "hw/sysbus.h" 25 #include "hw/arm/arm.h" 26 #include "hw/arm/primecell.h" 27 #include "hw/devices.h" 28 #include "net/net.h" 29 #include "sysemu/sysemu.h" 30 #include "hw/boards.h" 31 #include "exec/address-spaces.h" 32 #include "sysemu/blockdev.h" 33 #include "hw/block/flash.h" 34 35 #define VEXPRESS_BOARD_ID 0x8e0 36 #define VEXPRESS_FLASH_SIZE (64 * 1024 * 1024) 37 #define VEXPRESS_FLASH_SECT_SIZE (256 * 1024) 38 39 static struct arm_boot_info vexpress_binfo; 40 41 /* Address maps for peripherals: 42 * the Versatile Express motherboard has two possible maps, 43 * the "legacy" one (used for A9) and the "Cortex-A Series" 44 * map (used for newer cores). 45 * Individual daughterboards can also have different maps for 46 * their peripherals. 47 */ 48 49 enum { 50 VE_SYSREGS, 51 VE_SP810, 52 VE_SERIALPCI, 53 VE_PL041, 54 VE_MMCI, 55 VE_KMI0, 56 VE_KMI1, 57 VE_UART0, 58 VE_UART1, 59 VE_UART2, 60 VE_UART3, 61 VE_WDT, 62 VE_TIMER01, 63 VE_TIMER23, 64 VE_SERIALDVI, 65 VE_RTC, 66 VE_COMPACTFLASH, 67 VE_CLCD, 68 VE_NORFLASH0, 69 VE_NORFLASH1, 70 VE_NORFLASHALIAS, 71 VE_SRAM, 72 VE_VIDEORAM, 73 VE_ETHERNET, 74 VE_USB, 75 VE_DAPROM, 76 }; 77 78 static hwaddr motherboard_legacy_map[] = { 79 /* CS7: 0x10000000 .. 0x10020000 */ 80 [VE_SYSREGS] = 0x10000000, 81 [VE_SP810] = 0x10001000, 82 [VE_SERIALPCI] = 0x10002000, 83 [VE_PL041] = 0x10004000, 84 [VE_MMCI] = 0x10005000, 85 [VE_KMI0] = 0x10006000, 86 [VE_KMI1] = 0x10007000, 87 [VE_UART0] = 0x10009000, 88 [VE_UART1] = 0x1000a000, 89 [VE_UART2] = 0x1000b000, 90 [VE_UART3] = 0x1000c000, 91 [VE_WDT] = 0x1000f000, 92 [VE_TIMER01] = 0x10011000, 93 [VE_TIMER23] = 0x10012000, 94 [VE_SERIALDVI] = 0x10016000, 95 [VE_RTC] = 0x10017000, 96 [VE_COMPACTFLASH] = 0x1001a000, 97 [VE_CLCD] = 0x1001f000, 98 /* CS0: 0x40000000 .. 0x44000000 */ 99 [VE_NORFLASH0] = 0x40000000, 100 /* CS1: 0x44000000 .. 0x48000000 */ 101 [VE_NORFLASH1] = 0x44000000, 102 /* CS2: 0x48000000 .. 0x4a000000 */ 103 [VE_SRAM] = 0x48000000, 104 /* CS3: 0x4c000000 .. 0x50000000 */ 105 [VE_VIDEORAM] = 0x4c000000, 106 [VE_ETHERNET] = 0x4e000000, 107 [VE_USB] = 0x4f000000, 108 [VE_NORFLASHALIAS] = -1, /* not present */ 109 }; 110 111 static hwaddr motherboard_aseries_map[] = { 112 [VE_NORFLASHALIAS] = 0, 113 /* CS0: 0x08000000 .. 0x0c000000 */ 114 [VE_NORFLASH0] = 0x08000000, 115 /* CS4: 0x0c000000 .. 0x10000000 */ 116 [VE_NORFLASH1] = 0x0c000000, 117 /* CS5: 0x10000000 .. 0x14000000 */ 118 /* CS1: 0x14000000 .. 0x18000000 */ 119 [VE_SRAM] = 0x14000000, 120 /* CS2: 0x18000000 .. 0x1c000000 */ 121 [VE_VIDEORAM] = 0x18000000, 122 [VE_ETHERNET] = 0x1a000000, 123 [VE_USB] = 0x1b000000, 124 /* CS3: 0x1c000000 .. 0x20000000 */ 125 [VE_DAPROM] = 0x1c000000, 126 [VE_SYSREGS] = 0x1c010000, 127 [VE_SP810] = 0x1c020000, 128 [VE_SERIALPCI] = 0x1c030000, 129 [VE_PL041] = 0x1c040000, 130 [VE_MMCI] = 0x1c050000, 131 [VE_KMI0] = 0x1c060000, 132 [VE_KMI1] = 0x1c070000, 133 [VE_UART0] = 0x1c090000, 134 [VE_UART1] = 0x1c0a0000, 135 [VE_UART2] = 0x1c0b0000, 136 [VE_UART3] = 0x1c0c0000, 137 [VE_WDT] = 0x1c0f0000, 138 [VE_TIMER01] = 0x1c110000, 139 [VE_TIMER23] = 0x1c120000, 140 [VE_SERIALDVI] = 0x1c160000, 141 [VE_RTC] = 0x1c170000, 142 [VE_COMPACTFLASH] = 0x1c1a0000, 143 [VE_CLCD] = 0x1c1f0000, 144 }; 145 146 /* Structure defining the peculiarities of a specific daughterboard */ 147 148 typedef struct VEDBoardInfo VEDBoardInfo; 149 150 typedef void DBoardInitFn(const VEDBoardInfo *daughterboard, 151 ram_addr_t ram_size, 152 const char *cpu_model, 153 qemu_irq *pic); 154 155 struct VEDBoardInfo { 156 const hwaddr *motherboard_map; 157 hwaddr loader_start; 158 const hwaddr gic_cpu_if_addr; 159 uint32_t proc_id; 160 uint32_t num_voltage_sensors; 161 const uint32_t *voltages; 162 uint32_t num_clocks; 163 const uint32_t *clocks; 164 DBoardInitFn *init; 165 }; 166 167 static void a9_daughterboard_init(const VEDBoardInfo *daughterboard, 168 ram_addr_t ram_size, 169 const char *cpu_model, 170 qemu_irq *pic) 171 { 172 MemoryRegion *sysmem = get_system_memory(); 173 MemoryRegion *ram = g_new(MemoryRegion, 1); 174 MemoryRegion *lowram = g_new(MemoryRegion, 1); 175 DeviceState *dev; 176 SysBusDevice *busdev; 177 qemu_irq *irqp; 178 int n; 179 qemu_irq cpu_irq[4]; 180 ram_addr_t low_ram_size; 181 182 if (!cpu_model) { 183 cpu_model = "cortex-a9"; 184 } 185 186 for (n = 0; n < smp_cpus; n++) { 187 ARMCPU *cpu = cpu_arm_init(cpu_model); 188 if (!cpu) { 189 fprintf(stderr, "Unable to find CPU definition\n"); 190 exit(1); 191 } 192 irqp = arm_pic_init_cpu(cpu); 193 cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ]; 194 } 195 196 if (ram_size > 0x40000000) { 197 /* 1GB is the maximum the address space permits */ 198 fprintf(stderr, "vexpress-a9: cannot model more than 1GB RAM\n"); 199 exit(1); 200 } 201 202 memory_region_init_ram(ram, NULL, "vexpress.highmem", ram_size); 203 vmstate_register_ram_global(ram); 204 low_ram_size = ram_size; 205 if (low_ram_size > 0x4000000) { 206 low_ram_size = 0x4000000; 207 } 208 /* RAM is from 0x60000000 upwards. The bottom 64MB of the 209 * address space should in theory be remappable to various 210 * things including ROM or RAM; we always map the RAM there. 211 */ 212 memory_region_init_alias(lowram, NULL, "vexpress.lowmem", ram, 0, low_ram_size); 213 memory_region_add_subregion(sysmem, 0x0, lowram); 214 memory_region_add_subregion(sysmem, 0x60000000, ram); 215 216 /* 0x1e000000 A9MPCore (SCU) private memory region */ 217 dev = qdev_create(NULL, "a9mpcore_priv"); 218 qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); 219 qdev_init_nofail(dev); 220 busdev = SYS_BUS_DEVICE(dev); 221 sysbus_mmio_map(busdev, 0, 0x1e000000); 222 for (n = 0; n < smp_cpus; n++) { 223 sysbus_connect_irq(busdev, n, cpu_irq[n]); 224 } 225 /* Interrupts [42:0] are from the motherboard; 226 * [47:43] are reserved; [63:48] are daughterboard 227 * peripherals. Note that some documentation numbers 228 * external interrupts starting from 32 (because the 229 * A9MP has internal interrupts 0..31). 230 */ 231 for (n = 0; n < 64; n++) { 232 pic[n] = qdev_get_gpio_in(dev, n); 233 } 234 235 /* Daughterboard peripherals : 0x10020000 .. 0x20000000 */ 236 237 /* 0x10020000 PL111 CLCD (daughterboard) */ 238 sysbus_create_simple("pl111", 0x10020000, pic[44]); 239 240 /* 0x10060000 AXI RAM */ 241 /* 0x100e0000 PL341 Dynamic Memory Controller */ 242 /* 0x100e1000 PL354 Static Memory Controller */ 243 /* 0x100e2000 System Configuration Controller */ 244 245 sysbus_create_simple("sp804", 0x100e4000, pic[48]); 246 /* 0x100e5000 SP805 Watchdog module */ 247 /* 0x100e6000 BP147 TrustZone Protection Controller */ 248 /* 0x100e9000 PL301 'Fast' AXI matrix */ 249 /* 0x100ea000 PL301 'Slow' AXI matrix */ 250 /* 0x100ec000 TrustZone Address Space Controller */ 251 /* 0x10200000 CoreSight debug APB */ 252 /* 0x1e00a000 PL310 L2 Cache Controller */ 253 sysbus_create_varargs("l2x0", 0x1e00a000, NULL); 254 } 255 256 /* Voltage values for SYS_CFG_VOLT daughterboard registers; 257 * values are in microvolts. 258 */ 259 static const uint32_t a9_voltages[] = { 260 1000000, /* VD10 : 1.0V : SoC internal logic voltage */ 261 1000000, /* VD10_S2 : 1.0V : PL310, L2 cache, RAM, non-PL310 logic */ 262 1000000, /* VD10_S3 : 1.0V : Cortex-A9, cores, MPEs, SCU, PL310 logic */ 263 1800000, /* VCC1V8 : 1.8V : DDR2 SDRAM, test chip DDR2 I/O supply */ 264 900000, /* DDR2VTT : 0.9V : DDR2 SDRAM VTT termination voltage */ 265 3300000, /* VCC3V3 : 3.3V : local board supply for misc external logic */ 266 }; 267 268 /* Reset values for daughterboard oscillators (in Hz) */ 269 static const uint32_t a9_clocks[] = { 270 45000000, /* AMBA AXI ACLK: 45MHz */ 271 23750000, /* daughterboard CLCD clock: 23.75MHz */ 272 66670000, /* Test chip reference clock: 66.67MHz */ 273 }; 274 275 static const VEDBoardInfo a9_daughterboard = { 276 .motherboard_map = motherboard_legacy_map, 277 .loader_start = 0x60000000, 278 .gic_cpu_if_addr = 0x1e000100, 279 .proc_id = 0x0c000191, 280 .num_voltage_sensors = ARRAY_SIZE(a9_voltages), 281 .voltages = a9_voltages, 282 .num_clocks = ARRAY_SIZE(a9_clocks), 283 .clocks = a9_clocks, 284 .init = a9_daughterboard_init, 285 }; 286 287 static void a15_daughterboard_init(const VEDBoardInfo *daughterboard, 288 ram_addr_t ram_size, 289 const char *cpu_model, 290 qemu_irq *pic) 291 { 292 int n; 293 MemoryRegion *sysmem = get_system_memory(); 294 MemoryRegion *ram = g_new(MemoryRegion, 1); 295 MemoryRegion *sram = g_new(MemoryRegion, 1); 296 qemu_irq cpu_irq[4]; 297 DeviceState *dev; 298 SysBusDevice *busdev; 299 300 if (!cpu_model) { 301 cpu_model = "cortex-a15"; 302 } 303 304 for (n = 0; n < smp_cpus; n++) { 305 ARMCPU *cpu; 306 qemu_irq *irqp; 307 308 cpu = cpu_arm_init(cpu_model); 309 if (!cpu) { 310 fprintf(stderr, "Unable to find CPU definition\n"); 311 exit(1); 312 } 313 irqp = arm_pic_init_cpu(cpu); 314 cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ]; 315 } 316 317 { 318 /* We have to use a separate 64 bit variable here to avoid the gcc 319 * "comparison is always false due to limited range of data type" 320 * warning if we are on a host where ram_addr_t is 32 bits. 321 */ 322 uint64_t rsz = ram_size; 323 if (rsz > (30ULL * 1024 * 1024 * 1024)) { 324 fprintf(stderr, "vexpress-a15: cannot model more than 30GB RAM\n"); 325 exit(1); 326 } 327 } 328 329 memory_region_init_ram(ram, NULL, "vexpress.highmem", ram_size); 330 vmstate_register_ram_global(ram); 331 /* RAM is from 0x80000000 upwards; there is no low-memory alias for it. */ 332 memory_region_add_subregion(sysmem, 0x80000000, ram); 333 334 /* 0x2c000000 A15MPCore private memory region (GIC) */ 335 dev = qdev_create(NULL, "a15mpcore_priv"); 336 qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); 337 qdev_init_nofail(dev); 338 busdev = SYS_BUS_DEVICE(dev); 339 sysbus_mmio_map(busdev, 0, 0x2c000000); 340 for (n = 0; n < smp_cpus; n++) { 341 sysbus_connect_irq(busdev, n, cpu_irq[n]); 342 } 343 /* Interrupts [42:0] are from the motherboard; 344 * [47:43] are reserved; [63:48] are daughterboard 345 * peripherals. Note that some documentation numbers 346 * external interrupts starting from 32 (because there 347 * are internal interrupts 0..31). 348 */ 349 for (n = 0; n < 64; n++) { 350 pic[n] = qdev_get_gpio_in(dev, n); 351 } 352 353 /* A15 daughterboard peripherals: */ 354 355 /* 0x20000000: CoreSight interfaces: not modelled */ 356 /* 0x2a000000: PL301 AXI interconnect: not modelled */ 357 /* 0x2a420000: SCC: not modelled */ 358 /* 0x2a430000: system counter: not modelled */ 359 /* 0x2b000000: HDLCD controller: not modelled */ 360 /* 0x2b060000: SP805 watchdog: not modelled */ 361 /* 0x2b0a0000: PL341 dynamic memory controller: not modelled */ 362 /* 0x2e000000: system SRAM */ 363 memory_region_init_ram(sram, NULL, "vexpress.a15sram", 0x10000); 364 vmstate_register_ram_global(sram); 365 memory_region_add_subregion(sysmem, 0x2e000000, sram); 366 367 /* 0x7ffb0000: DMA330 DMA controller: not modelled */ 368 /* 0x7ffd0000: PL354 static memory controller: not modelled */ 369 } 370 371 static const uint32_t a15_voltages[] = { 372 900000, /* Vcore: 0.9V : CPU core voltage */ 373 }; 374 375 static const uint32_t a15_clocks[] = { 376 60000000, /* OSCCLK0: 60MHz : CPU_CLK reference */ 377 0, /* OSCCLK1: reserved */ 378 0, /* OSCCLK2: reserved */ 379 0, /* OSCCLK3: reserved */ 380 40000000, /* OSCCLK4: 40MHz : external AXI master clock */ 381 23750000, /* OSCCLK5: 23.75MHz : HDLCD PLL reference */ 382 50000000, /* OSCCLK6: 50MHz : static memory controller clock */ 383 60000000, /* OSCCLK7: 60MHz : SYSCLK reference */ 384 40000000, /* OSCCLK8: 40MHz : DDR2 PLL reference */ 385 }; 386 387 static const VEDBoardInfo a15_daughterboard = { 388 .motherboard_map = motherboard_aseries_map, 389 .loader_start = 0x80000000, 390 .gic_cpu_if_addr = 0x2c002000, 391 .proc_id = 0x14000237, 392 .num_voltage_sensors = ARRAY_SIZE(a15_voltages), 393 .voltages = a15_voltages, 394 .num_clocks = ARRAY_SIZE(a15_clocks), 395 .clocks = a15_clocks, 396 .init = a15_daughterboard_init, 397 }; 398 399 static void vexpress_common_init(const VEDBoardInfo *daughterboard, 400 QEMUMachineInitArgs *args) 401 { 402 DeviceState *dev, *sysctl, *pl041; 403 qemu_irq pic[64]; 404 uint32_t sys_id; 405 DriveInfo *dinfo; 406 pflash_t *pflash0; 407 ram_addr_t vram_size, sram_size; 408 MemoryRegion *sysmem = get_system_memory(); 409 MemoryRegion *vram = g_new(MemoryRegion, 1); 410 MemoryRegion *sram = g_new(MemoryRegion, 1); 411 MemoryRegion *flashalias = g_new(MemoryRegion, 1); 412 MemoryRegion *flash0mem; 413 const hwaddr *map = daughterboard->motherboard_map; 414 int i; 415 416 daughterboard->init(daughterboard, args->ram_size, args->cpu_model, pic); 417 418 /* Motherboard peripherals: the wiring is the same but the 419 * addresses vary between the legacy and A-Series memory maps. 420 */ 421 422 sys_id = 0x1190f500; 423 424 sysctl = qdev_create(NULL, "realview_sysctl"); 425 qdev_prop_set_uint32(sysctl, "sys_id", sys_id); 426 qdev_prop_set_uint32(sysctl, "proc_id", daughterboard->proc_id); 427 qdev_prop_set_uint32(sysctl, "len-db-voltage", 428 daughterboard->num_voltage_sensors); 429 for (i = 0; i < daughterboard->num_voltage_sensors; i++) { 430 char *propname = g_strdup_printf("db-voltage[%d]", i); 431 qdev_prop_set_uint32(sysctl, propname, daughterboard->voltages[i]); 432 g_free(propname); 433 } 434 qdev_prop_set_uint32(sysctl, "len-db-clock", 435 daughterboard->num_clocks); 436 for (i = 0; i < daughterboard->num_clocks; i++) { 437 char *propname = g_strdup_printf("db-clock[%d]", i); 438 qdev_prop_set_uint32(sysctl, propname, daughterboard->clocks[i]); 439 g_free(propname); 440 } 441 qdev_init_nofail(sysctl); 442 sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, map[VE_SYSREGS]); 443 444 /* VE_SP810: not modelled */ 445 /* VE_SERIALPCI: not modelled */ 446 447 pl041 = qdev_create(NULL, "pl041"); 448 qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512); 449 qdev_init_nofail(pl041); 450 sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, map[VE_PL041]); 451 sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[11]); 452 453 dev = sysbus_create_varargs("pl181", map[VE_MMCI], pic[9], pic[10], NULL); 454 /* Wire up MMC card detect and read-only signals */ 455 qdev_connect_gpio_out(dev, 0, 456 qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT)); 457 qdev_connect_gpio_out(dev, 1, 458 qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN)); 459 460 sysbus_create_simple("pl050_keyboard", map[VE_KMI0], pic[12]); 461 sysbus_create_simple("pl050_mouse", map[VE_KMI1], pic[13]); 462 463 sysbus_create_simple("pl011", map[VE_UART0], pic[5]); 464 sysbus_create_simple("pl011", map[VE_UART1], pic[6]); 465 sysbus_create_simple("pl011", map[VE_UART2], pic[7]); 466 sysbus_create_simple("pl011", map[VE_UART3], pic[8]); 467 468 sysbus_create_simple("sp804", map[VE_TIMER01], pic[2]); 469 sysbus_create_simple("sp804", map[VE_TIMER23], pic[3]); 470 471 /* VE_SERIALDVI: not modelled */ 472 473 sysbus_create_simple("pl031", map[VE_RTC], pic[4]); /* RTC */ 474 475 /* VE_COMPACTFLASH: not modelled */ 476 477 sysbus_create_simple("pl111", map[VE_CLCD], pic[14]); 478 479 dinfo = drive_get_next(IF_PFLASH); 480 pflash0 = pflash_cfi01_register(map[VE_NORFLASH0], NULL, "vexpress.flash0", 481 VEXPRESS_FLASH_SIZE, dinfo ? dinfo->bdrv : NULL, 482 VEXPRESS_FLASH_SECT_SIZE, 483 VEXPRESS_FLASH_SIZE / VEXPRESS_FLASH_SECT_SIZE, 4, 484 0x00, 0x89, 0x00, 0x18, 0); 485 if (!pflash0) { 486 fprintf(stderr, "vexpress: error registering flash 0.\n"); 487 exit(1); 488 } 489 490 if (map[VE_NORFLASHALIAS] != -1) { 491 /* Map flash 0 as an alias into low memory */ 492 flash0mem = sysbus_mmio_get_region(SYS_BUS_DEVICE(pflash0), 0); 493 memory_region_init_alias(flashalias, NULL, "vexpress.flashalias", 494 flash0mem, 0, VEXPRESS_FLASH_SIZE); 495 memory_region_add_subregion(sysmem, map[VE_NORFLASHALIAS], flashalias); 496 } 497 498 dinfo = drive_get_next(IF_PFLASH); 499 if (!pflash_cfi01_register(map[VE_NORFLASH1], NULL, "vexpress.flash1", 500 VEXPRESS_FLASH_SIZE, dinfo ? dinfo->bdrv : NULL, 501 VEXPRESS_FLASH_SECT_SIZE, 502 VEXPRESS_FLASH_SIZE / VEXPRESS_FLASH_SECT_SIZE, 4, 503 0x00, 0x89, 0x00, 0x18, 0)) { 504 fprintf(stderr, "vexpress: error registering flash 1.\n"); 505 exit(1); 506 } 507 508 sram_size = 0x2000000; 509 memory_region_init_ram(sram, NULL, "vexpress.sram", sram_size); 510 vmstate_register_ram_global(sram); 511 memory_region_add_subregion(sysmem, map[VE_SRAM], sram); 512 513 vram_size = 0x800000; 514 memory_region_init_ram(vram, NULL, "vexpress.vram", vram_size); 515 vmstate_register_ram_global(vram); 516 memory_region_add_subregion(sysmem, map[VE_VIDEORAM], vram); 517 518 /* 0x4e000000 LAN9118 Ethernet */ 519 if (nd_table[0].used) { 520 lan9118_init(&nd_table[0], map[VE_ETHERNET], pic[15]); 521 } 522 523 /* VE_USB: not modelled */ 524 525 /* VE_DAPROM: not modelled */ 526 527 vexpress_binfo.ram_size = args->ram_size; 528 vexpress_binfo.kernel_filename = args->kernel_filename; 529 vexpress_binfo.kernel_cmdline = args->kernel_cmdline; 530 vexpress_binfo.initrd_filename = args->initrd_filename; 531 vexpress_binfo.nb_cpus = smp_cpus; 532 vexpress_binfo.board_id = VEXPRESS_BOARD_ID; 533 vexpress_binfo.loader_start = daughterboard->loader_start; 534 vexpress_binfo.smp_loader_start = map[VE_SRAM]; 535 vexpress_binfo.smp_bootreg_addr = map[VE_SYSREGS] + 0x30; 536 vexpress_binfo.gic_cpu_if_addr = daughterboard->gic_cpu_if_addr; 537 arm_load_kernel(ARM_CPU(first_cpu), &vexpress_binfo); 538 } 539 540 static void vexpress_a9_init(QEMUMachineInitArgs *args) 541 { 542 vexpress_common_init(&a9_daughterboard, args); 543 } 544 545 static void vexpress_a15_init(QEMUMachineInitArgs *args) 546 { 547 vexpress_common_init(&a15_daughterboard, args); 548 } 549 550 static QEMUMachine vexpress_a9_machine = { 551 .name = "vexpress-a9", 552 .desc = "ARM Versatile Express for Cortex-A9", 553 .init = vexpress_a9_init, 554 .block_default_type = IF_SCSI, 555 .max_cpus = 4, 556 DEFAULT_MACHINE_OPTIONS, 557 }; 558 559 static QEMUMachine vexpress_a15_machine = { 560 .name = "vexpress-a15", 561 .desc = "ARM Versatile Express for Cortex-A15", 562 .init = vexpress_a15_init, 563 .block_default_type = IF_SCSI, 564 .max_cpus = 4, 565 DEFAULT_MACHINE_OPTIONS, 566 }; 567 568 static void vexpress_machine_init(void) 569 { 570 qemu_register_machine(&vexpress_a9_machine); 571 qemu_register_machine(&vexpress_a15_machine); 572 } 573 574 machine_init(vexpress_machine_init); 575