1 /* 2 * ARM Versatile Express emulation. 3 * 4 * Copyright (c) 2010 - 2011 B Labs Ltd. 5 * Copyright (c) 2011 Linaro Limited 6 * Written by Bahadir Balban, Amit Mahajan, Peter Maydell 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, see <http://www.gnu.org/licenses/>. 19 * 20 * Contributions after 2012-01-13 are licensed under the terms of the 21 * GNU GPL, version 2 or (at your option) any later version. 22 */ 23 24 #include "qemu/osdep.h" 25 #include "qapi/error.h" 26 #include "qemu-common.h" 27 #include "cpu.h" 28 #include "hw/sysbus.h" 29 #include "hw/arm/arm.h" 30 #include "hw/arm/primecell.h" 31 #include "hw/devices.h" 32 #include "net/net.h" 33 #include "sysemu/sysemu.h" 34 #include "hw/boards.h" 35 #include "hw/loader.h" 36 #include "exec/address-spaces.h" 37 #include "sysemu/block-backend.h" 38 #include "hw/block/flash.h" 39 #include "sysemu/device_tree.h" 40 #include "qemu/error-report.h" 41 #include <libfdt.h> 42 #include "hw/char/pl011.h" 43 #include "hw/cpu/a9mpcore.h" 44 #include "hw/cpu/a15mpcore.h" 45 46 #define VEXPRESS_BOARD_ID 0x8e0 47 #define VEXPRESS_FLASH_SIZE (64 * 1024 * 1024) 48 #define VEXPRESS_FLASH_SECT_SIZE (256 * 1024) 49 50 /* Number of virtio transports to create (0..8; limited by 51 * number of available IRQ lines). 52 */ 53 #define NUM_VIRTIO_TRANSPORTS 4 54 55 /* Address maps for peripherals: 56 * the Versatile Express motherboard has two possible maps, 57 * the "legacy" one (used for A9) and the "Cortex-A Series" 58 * map (used for newer cores). 59 * Individual daughterboards can also have different maps for 60 * their peripherals. 61 */ 62 63 enum { 64 VE_SYSREGS, 65 VE_SP810, 66 VE_SERIALPCI, 67 VE_PL041, 68 VE_MMCI, 69 VE_KMI0, 70 VE_KMI1, 71 VE_UART0, 72 VE_UART1, 73 VE_UART2, 74 VE_UART3, 75 VE_WDT, 76 VE_TIMER01, 77 VE_TIMER23, 78 VE_SERIALDVI, 79 VE_RTC, 80 VE_COMPACTFLASH, 81 VE_CLCD, 82 VE_NORFLASH0, 83 VE_NORFLASH1, 84 VE_NORFLASHALIAS, 85 VE_SRAM, 86 VE_VIDEORAM, 87 VE_ETHERNET, 88 VE_USB, 89 VE_DAPROM, 90 VE_VIRTIO, 91 }; 92 93 static hwaddr motherboard_legacy_map[] = { 94 [VE_NORFLASHALIAS] = 0, 95 /* CS7: 0x10000000 .. 0x10020000 */ 96 [VE_SYSREGS] = 0x10000000, 97 [VE_SP810] = 0x10001000, 98 [VE_SERIALPCI] = 0x10002000, 99 [VE_PL041] = 0x10004000, 100 [VE_MMCI] = 0x10005000, 101 [VE_KMI0] = 0x10006000, 102 [VE_KMI1] = 0x10007000, 103 [VE_UART0] = 0x10009000, 104 [VE_UART1] = 0x1000a000, 105 [VE_UART2] = 0x1000b000, 106 [VE_UART3] = 0x1000c000, 107 [VE_WDT] = 0x1000f000, 108 [VE_TIMER01] = 0x10011000, 109 [VE_TIMER23] = 0x10012000, 110 [VE_VIRTIO] = 0x10013000, 111 [VE_SERIALDVI] = 0x10016000, 112 [VE_RTC] = 0x10017000, 113 [VE_COMPACTFLASH] = 0x1001a000, 114 [VE_CLCD] = 0x1001f000, 115 /* CS0: 0x40000000 .. 0x44000000 */ 116 [VE_NORFLASH0] = 0x40000000, 117 /* CS1: 0x44000000 .. 0x48000000 */ 118 [VE_NORFLASH1] = 0x44000000, 119 /* CS2: 0x48000000 .. 0x4a000000 */ 120 [VE_SRAM] = 0x48000000, 121 /* CS3: 0x4c000000 .. 0x50000000 */ 122 [VE_VIDEORAM] = 0x4c000000, 123 [VE_ETHERNET] = 0x4e000000, 124 [VE_USB] = 0x4f000000, 125 }; 126 127 static hwaddr motherboard_aseries_map[] = { 128 [VE_NORFLASHALIAS] = 0, 129 /* CS0: 0x08000000 .. 0x0c000000 */ 130 [VE_NORFLASH0] = 0x08000000, 131 /* CS4: 0x0c000000 .. 0x10000000 */ 132 [VE_NORFLASH1] = 0x0c000000, 133 /* CS5: 0x10000000 .. 0x14000000 */ 134 /* CS1: 0x14000000 .. 0x18000000 */ 135 [VE_SRAM] = 0x14000000, 136 /* CS2: 0x18000000 .. 0x1c000000 */ 137 [VE_VIDEORAM] = 0x18000000, 138 [VE_ETHERNET] = 0x1a000000, 139 [VE_USB] = 0x1b000000, 140 /* CS3: 0x1c000000 .. 0x20000000 */ 141 [VE_DAPROM] = 0x1c000000, 142 [VE_SYSREGS] = 0x1c010000, 143 [VE_SP810] = 0x1c020000, 144 [VE_SERIALPCI] = 0x1c030000, 145 [VE_PL041] = 0x1c040000, 146 [VE_MMCI] = 0x1c050000, 147 [VE_KMI0] = 0x1c060000, 148 [VE_KMI1] = 0x1c070000, 149 [VE_UART0] = 0x1c090000, 150 [VE_UART1] = 0x1c0a0000, 151 [VE_UART2] = 0x1c0b0000, 152 [VE_UART3] = 0x1c0c0000, 153 [VE_WDT] = 0x1c0f0000, 154 [VE_TIMER01] = 0x1c110000, 155 [VE_TIMER23] = 0x1c120000, 156 [VE_VIRTIO] = 0x1c130000, 157 [VE_SERIALDVI] = 0x1c160000, 158 [VE_RTC] = 0x1c170000, 159 [VE_COMPACTFLASH] = 0x1c1a0000, 160 [VE_CLCD] = 0x1c1f0000, 161 }; 162 163 /* Structure defining the peculiarities of a specific daughterboard */ 164 165 typedef struct VEDBoardInfo VEDBoardInfo; 166 167 typedef struct { 168 MachineClass parent; 169 VEDBoardInfo *daughterboard; 170 } VexpressMachineClass; 171 172 typedef struct { 173 MachineState parent; 174 bool secure; 175 } VexpressMachineState; 176 177 #define TYPE_VEXPRESS_MACHINE "vexpress" 178 #define TYPE_VEXPRESS_A9_MACHINE MACHINE_TYPE_NAME("vexpress-a9") 179 #define TYPE_VEXPRESS_A15_MACHINE MACHINE_TYPE_NAME("vexpress-a15") 180 #define VEXPRESS_MACHINE(obj) \ 181 OBJECT_CHECK(VexpressMachineState, (obj), TYPE_VEXPRESS_MACHINE) 182 #define VEXPRESS_MACHINE_GET_CLASS(obj) \ 183 OBJECT_GET_CLASS(VexpressMachineClass, obj, TYPE_VEXPRESS_MACHINE) 184 #define VEXPRESS_MACHINE_CLASS(klass) \ 185 OBJECT_CLASS_CHECK(VexpressMachineClass, klass, TYPE_VEXPRESS_MACHINE) 186 187 typedef void DBoardInitFn(const VexpressMachineState *machine, 188 ram_addr_t ram_size, 189 const char *cpu_model, 190 qemu_irq *pic); 191 192 struct VEDBoardInfo { 193 struct arm_boot_info bootinfo; 194 const hwaddr *motherboard_map; 195 hwaddr loader_start; 196 const hwaddr gic_cpu_if_addr; 197 uint32_t proc_id; 198 uint32_t num_voltage_sensors; 199 const uint32_t *voltages; 200 uint32_t num_clocks; 201 const uint32_t *clocks; 202 DBoardInitFn *init; 203 }; 204 205 static void init_cpus(const char *cpu_model, const char *privdev, 206 hwaddr periphbase, qemu_irq *pic, bool secure) 207 { 208 ObjectClass *cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model); 209 DeviceState *dev; 210 SysBusDevice *busdev; 211 int n; 212 213 if (!cpu_oc) { 214 fprintf(stderr, "Unable to find CPU definition\n"); 215 exit(1); 216 } 217 218 /* Create the actual CPUs */ 219 for (n = 0; n < smp_cpus; n++) { 220 Object *cpuobj = object_new(object_class_get_name(cpu_oc)); 221 222 if (!secure) { 223 object_property_set_bool(cpuobj, false, "has_el3", NULL); 224 } 225 226 if (object_property_find(cpuobj, "reset-cbar", NULL)) { 227 object_property_set_int(cpuobj, periphbase, 228 "reset-cbar", &error_abort); 229 } 230 object_property_set_bool(cpuobj, true, "realized", &error_fatal); 231 } 232 233 /* Create the private peripheral devices (including the GIC); 234 * this must happen after the CPUs are created because a15mpcore_priv 235 * wires itself up to the CPU's generic_timer gpio out lines. 236 */ 237 dev = qdev_create(NULL, privdev); 238 qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); 239 qdev_init_nofail(dev); 240 busdev = SYS_BUS_DEVICE(dev); 241 sysbus_mmio_map(busdev, 0, periphbase); 242 243 /* Interrupts [42:0] are from the motherboard; 244 * [47:43] are reserved; [63:48] are daughterboard 245 * peripherals. Note that some documentation numbers 246 * external interrupts starting from 32 (because there 247 * are internal interrupts 0..31). 248 */ 249 for (n = 0; n < 64; n++) { 250 pic[n] = qdev_get_gpio_in(dev, n); 251 } 252 253 /* Connect the CPUs to the GIC */ 254 for (n = 0; n < smp_cpus; n++) { 255 DeviceState *cpudev = DEVICE(qemu_get_cpu(n)); 256 257 sysbus_connect_irq(busdev, n, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 258 sysbus_connect_irq(busdev, n + smp_cpus, 259 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 260 } 261 } 262 263 static void a9_daughterboard_init(const VexpressMachineState *vms, 264 ram_addr_t ram_size, 265 const char *cpu_model, 266 qemu_irq *pic) 267 { 268 MemoryRegion *sysmem = get_system_memory(); 269 MemoryRegion *ram = g_new(MemoryRegion, 1); 270 MemoryRegion *lowram = g_new(MemoryRegion, 1); 271 ram_addr_t low_ram_size; 272 273 if (!cpu_model) { 274 cpu_model = "cortex-a9"; 275 } 276 277 if (ram_size > 0x40000000) { 278 /* 1GB is the maximum the address space permits */ 279 fprintf(stderr, "vexpress-a9: cannot model more than 1GB RAM\n"); 280 exit(1); 281 } 282 283 memory_region_allocate_system_memory(ram, NULL, "vexpress.highmem", 284 ram_size); 285 low_ram_size = ram_size; 286 if (low_ram_size > 0x4000000) { 287 low_ram_size = 0x4000000; 288 } 289 /* RAM is from 0x60000000 upwards. The bottom 64MB of the 290 * address space should in theory be remappable to various 291 * things including ROM or RAM; we always map the RAM there. 292 */ 293 memory_region_init_alias(lowram, NULL, "vexpress.lowmem", ram, 0, low_ram_size); 294 memory_region_add_subregion(sysmem, 0x0, lowram); 295 memory_region_add_subregion(sysmem, 0x60000000, ram); 296 297 /* 0x1e000000 A9MPCore (SCU) private memory region */ 298 init_cpus(cpu_model, TYPE_A9MPCORE_PRIV, 0x1e000000, pic, vms->secure); 299 300 /* Daughterboard peripherals : 0x10020000 .. 0x20000000 */ 301 302 /* 0x10020000 PL111 CLCD (daughterboard) */ 303 sysbus_create_simple("pl111", 0x10020000, pic[44]); 304 305 /* 0x10060000 AXI RAM */ 306 /* 0x100e0000 PL341 Dynamic Memory Controller */ 307 /* 0x100e1000 PL354 Static Memory Controller */ 308 /* 0x100e2000 System Configuration Controller */ 309 310 sysbus_create_simple("sp804", 0x100e4000, pic[48]); 311 /* 0x100e5000 SP805 Watchdog module */ 312 /* 0x100e6000 BP147 TrustZone Protection Controller */ 313 /* 0x100e9000 PL301 'Fast' AXI matrix */ 314 /* 0x100ea000 PL301 'Slow' AXI matrix */ 315 /* 0x100ec000 TrustZone Address Space Controller */ 316 /* 0x10200000 CoreSight debug APB */ 317 /* 0x1e00a000 PL310 L2 Cache Controller */ 318 sysbus_create_varargs("l2x0", 0x1e00a000, NULL); 319 } 320 321 /* Voltage values for SYS_CFG_VOLT daughterboard registers; 322 * values are in microvolts. 323 */ 324 static const uint32_t a9_voltages[] = { 325 1000000, /* VD10 : 1.0V : SoC internal logic voltage */ 326 1000000, /* VD10_S2 : 1.0V : PL310, L2 cache, RAM, non-PL310 logic */ 327 1000000, /* VD10_S3 : 1.0V : Cortex-A9, cores, MPEs, SCU, PL310 logic */ 328 1800000, /* VCC1V8 : 1.8V : DDR2 SDRAM, test chip DDR2 I/O supply */ 329 900000, /* DDR2VTT : 0.9V : DDR2 SDRAM VTT termination voltage */ 330 3300000, /* VCC3V3 : 3.3V : local board supply for misc external logic */ 331 }; 332 333 /* Reset values for daughterboard oscillators (in Hz) */ 334 static const uint32_t a9_clocks[] = { 335 45000000, /* AMBA AXI ACLK: 45MHz */ 336 23750000, /* daughterboard CLCD clock: 23.75MHz */ 337 66670000, /* Test chip reference clock: 66.67MHz */ 338 }; 339 340 static VEDBoardInfo a9_daughterboard = { 341 .motherboard_map = motherboard_legacy_map, 342 .loader_start = 0x60000000, 343 .gic_cpu_if_addr = 0x1e000100, 344 .proc_id = 0x0c000191, 345 .num_voltage_sensors = ARRAY_SIZE(a9_voltages), 346 .voltages = a9_voltages, 347 .num_clocks = ARRAY_SIZE(a9_clocks), 348 .clocks = a9_clocks, 349 .init = a9_daughterboard_init, 350 }; 351 352 static void a15_daughterboard_init(const VexpressMachineState *vms, 353 ram_addr_t ram_size, 354 const char *cpu_model, 355 qemu_irq *pic) 356 { 357 MemoryRegion *sysmem = get_system_memory(); 358 MemoryRegion *ram = g_new(MemoryRegion, 1); 359 MemoryRegion *sram = g_new(MemoryRegion, 1); 360 361 if (!cpu_model) { 362 cpu_model = "cortex-a15"; 363 } 364 365 { 366 /* We have to use a separate 64 bit variable here to avoid the gcc 367 * "comparison is always false due to limited range of data type" 368 * warning if we are on a host where ram_addr_t is 32 bits. 369 */ 370 uint64_t rsz = ram_size; 371 if (rsz > (30ULL * 1024 * 1024 * 1024)) { 372 fprintf(stderr, "vexpress-a15: cannot model more than 30GB RAM\n"); 373 exit(1); 374 } 375 } 376 377 memory_region_allocate_system_memory(ram, NULL, "vexpress.highmem", 378 ram_size); 379 /* RAM is from 0x80000000 upwards; there is no low-memory alias for it. */ 380 memory_region_add_subregion(sysmem, 0x80000000, ram); 381 382 /* 0x2c000000 A15MPCore private memory region (GIC) */ 383 init_cpus(cpu_model, TYPE_A15MPCORE_PRIV, 0x2c000000, pic, vms->secure); 384 385 /* A15 daughterboard peripherals: */ 386 387 /* 0x20000000: CoreSight interfaces: not modelled */ 388 /* 0x2a000000: PL301 AXI interconnect: not modelled */ 389 /* 0x2a420000: SCC: not modelled */ 390 /* 0x2a430000: system counter: not modelled */ 391 /* 0x2b000000: HDLCD controller: not modelled */ 392 /* 0x2b060000: SP805 watchdog: not modelled */ 393 /* 0x2b0a0000: PL341 dynamic memory controller: not modelled */ 394 /* 0x2e000000: system SRAM */ 395 memory_region_init_ram(sram, NULL, "vexpress.a15sram", 0x10000, 396 &error_fatal); 397 memory_region_add_subregion(sysmem, 0x2e000000, sram); 398 399 /* 0x7ffb0000: DMA330 DMA controller: not modelled */ 400 /* 0x7ffd0000: PL354 static memory controller: not modelled */ 401 } 402 403 static const uint32_t a15_voltages[] = { 404 900000, /* Vcore: 0.9V : CPU core voltage */ 405 }; 406 407 static const uint32_t a15_clocks[] = { 408 60000000, /* OSCCLK0: 60MHz : CPU_CLK reference */ 409 0, /* OSCCLK1: reserved */ 410 0, /* OSCCLK2: reserved */ 411 0, /* OSCCLK3: reserved */ 412 40000000, /* OSCCLK4: 40MHz : external AXI master clock */ 413 23750000, /* OSCCLK5: 23.75MHz : HDLCD PLL reference */ 414 50000000, /* OSCCLK6: 50MHz : static memory controller clock */ 415 60000000, /* OSCCLK7: 60MHz : SYSCLK reference */ 416 40000000, /* OSCCLK8: 40MHz : DDR2 PLL reference */ 417 }; 418 419 static VEDBoardInfo a15_daughterboard = { 420 .motherboard_map = motherboard_aseries_map, 421 .loader_start = 0x80000000, 422 .gic_cpu_if_addr = 0x2c002000, 423 .proc_id = 0x14000237, 424 .num_voltage_sensors = ARRAY_SIZE(a15_voltages), 425 .voltages = a15_voltages, 426 .num_clocks = ARRAY_SIZE(a15_clocks), 427 .clocks = a15_clocks, 428 .init = a15_daughterboard_init, 429 }; 430 431 static int add_virtio_mmio_node(void *fdt, uint32_t acells, uint32_t scells, 432 hwaddr addr, hwaddr size, uint32_t intc, 433 int irq) 434 { 435 /* Add a virtio_mmio node to the device tree blob: 436 * virtio_mmio@ADDRESS { 437 * compatible = "virtio,mmio"; 438 * reg = <ADDRESS, SIZE>; 439 * interrupt-parent = <&intc>; 440 * interrupts = <0, irq, 1>; 441 * } 442 * (Note that the format of the interrupts property is dependent on the 443 * interrupt controller that interrupt-parent points to; these are for 444 * the ARM GIC and indicate an SPI interrupt, rising-edge-triggered.) 445 */ 446 int rc; 447 char *nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, addr); 448 449 rc = qemu_fdt_add_subnode(fdt, nodename); 450 rc |= qemu_fdt_setprop_string(fdt, nodename, 451 "compatible", "virtio,mmio"); 452 rc |= qemu_fdt_setprop_sized_cells(fdt, nodename, "reg", 453 acells, addr, scells, size); 454 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", intc); 455 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 0, irq, 1); 456 qemu_fdt_setprop(fdt, nodename, "dma-coherent", NULL, 0); 457 g_free(nodename); 458 if (rc) { 459 return -1; 460 } 461 return 0; 462 } 463 464 static uint32_t find_int_controller(void *fdt) 465 { 466 /* Find the FDT node corresponding to the interrupt controller 467 * for virtio-mmio devices. We do this by scanning the fdt for 468 * a node with the right compatibility, since we know there is 469 * only one GIC on a vexpress board. 470 * We return the phandle of the node, or 0 if none was found. 471 */ 472 const char *compat = "arm,cortex-a9-gic"; 473 int offset; 474 475 offset = fdt_node_offset_by_compatible(fdt, -1, compat); 476 if (offset >= 0) { 477 return fdt_get_phandle(fdt, offset); 478 } 479 return 0; 480 } 481 482 static void vexpress_modify_dtb(const struct arm_boot_info *info, void *fdt) 483 { 484 uint32_t acells, scells, intc; 485 const VEDBoardInfo *daughterboard = (const VEDBoardInfo *)info; 486 487 acells = qemu_fdt_getprop_cell(fdt, "/", "#address-cells", 488 NULL, &error_fatal); 489 scells = qemu_fdt_getprop_cell(fdt, "/", "#size-cells", 490 NULL, &error_fatal); 491 intc = find_int_controller(fdt); 492 if (!intc) { 493 /* Not fatal, we just won't provide virtio. This will 494 * happen with older device tree blobs. 495 */ 496 fprintf(stderr, "QEMU: warning: couldn't find interrupt controller in " 497 "dtb; will not include virtio-mmio devices in the dtb.\n"); 498 } else { 499 int i; 500 const hwaddr *map = daughterboard->motherboard_map; 501 502 /* We iterate backwards here because adding nodes 503 * to the dtb puts them in last-first. 504 */ 505 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) { 506 add_virtio_mmio_node(fdt, acells, scells, 507 map[VE_VIRTIO] + 0x200 * i, 508 0x200, intc, 40 + i); 509 } 510 } 511 } 512 513 514 /* Open code a private version of pflash registration since we 515 * need to set non-default device width for VExpress platform. 516 */ 517 static pflash_t *ve_pflash_cfi01_register(hwaddr base, const char *name, 518 DriveInfo *di) 519 { 520 DeviceState *dev = qdev_create(NULL, "cfi.pflash01"); 521 522 if (di) { 523 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(di), 524 &error_abort); 525 } 526 527 qdev_prop_set_uint32(dev, "num-blocks", 528 VEXPRESS_FLASH_SIZE / VEXPRESS_FLASH_SECT_SIZE); 529 qdev_prop_set_uint64(dev, "sector-length", VEXPRESS_FLASH_SECT_SIZE); 530 qdev_prop_set_uint8(dev, "width", 4); 531 qdev_prop_set_uint8(dev, "device-width", 2); 532 qdev_prop_set_bit(dev, "big-endian", false); 533 qdev_prop_set_uint16(dev, "id0", 0x89); 534 qdev_prop_set_uint16(dev, "id1", 0x18); 535 qdev_prop_set_uint16(dev, "id2", 0x00); 536 qdev_prop_set_uint16(dev, "id3", 0x00); 537 qdev_prop_set_string(dev, "name", name); 538 qdev_init_nofail(dev); 539 540 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 541 return OBJECT_CHECK(pflash_t, (dev), "cfi.pflash01"); 542 } 543 544 static void vexpress_common_init(MachineState *machine) 545 { 546 VexpressMachineState *vms = VEXPRESS_MACHINE(machine); 547 VexpressMachineClass *vmc = VEXPRESS_MACHINE_GET_CLASS(machine); 548 VEDBoardInfo *daughterboard = vmc->daughterboard; 549 DeviceState *dev, *sysctl, *pl041; 550 qemu_irq pic[64]; 551 uint32_t sys_id; 552 DriveInfo *dinfo; 553 pflash_t *pflash0; 554 ram_addr_t vram_size, sram_size; 555 MemoryRegion *sysmem = get_system_memory(); 556 MemoryRegion *vram = g_new(MemoryRegion, 1); 557 MemoryRegion *sram = g_new(MemoryRegion, 1); 558 MemoryRegion *flashalias = g_new(MemoryRegion, 1); 559 MemoryRegion *flash0mem; 560 const hwaddr *map = daughterboard->motherboard_map; 561 int i; 562 563 daughterboard->init(vms, machine->ram_size, machine->cpu_model, pic); 564 565 /* 566 * If a bios file was provided, attempt to map it into memory 567 */ 568 if (bios_name) { 569 char *fn; 570 int image_size; 571 572 if (drive_get(IF_PFLASH, 0, 0)) { 573 error_report("The contents of the first flash device may be " 574 "specified with -bios or with -drive if=pflash... " 575 "but you cannot use both options at once"); 576 exit(1); 577 } 578 fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 579 if (!fn) { 580 error_report("Could not find ROM image '%s'", bios_name); 581 exit(1); 582 } 583 image_size = load_image_targphys(fn, map[VE_NORFLASH0], 584 VEXPRESS_FLASH_SIZE); 585 g_free(fn); 586 if (image_size < 0) { 587 error_report("Could not load ROM image '%s'", bios_name); 588 exit(1); 589 } 590 } 591 592 /* Motherboard peripherals: the wiring is the same but the 593 * addresses vary between the legacy and A-Series memory maps. 594 */ 595 596 sys_id = 0x1190f500; 597 598 sysctl = qdev_create(NULL, "realview_sysctl"); 599 qdev_prop_set_uint32(sysctl, "sys_id", sys_id); 600 qdev_prop_set_uint32(sysctl, "proc_id", daughterboard->proc_id); 601 qdev_prop_set_uint32(sysctl, "len-db-voltage", 602 daughterboard->num_voltage_sensors); 603 for (i = 0; i < daughterboard->num_voltage_sensors; i++) { 604 char *propname = g_strdup_printf("db-voltage[%d]", i); 605 qdev_prop_set_uint32(sysctl, propname, daughterboard->voltages[i]); 606 g_free(propname); 607 } 608 qdev_prop_set_uint32(sysctl, "len-db-clock", 609 daughterboard->num_clocks); 610 for (i = 0; i < daughterboard->num_clocks; i++) { 611 char *propname = g_strdup_printf("db-clock[%d]", i); 612 qdev_prop_set_uint32(sysctl, propname, daughterboard->clocks[i]); 613 g_free(propname); 614 } 615 qdev_init_nofail(sysctl); 616 sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, map[VE_SYSREGS]); 617 618 /* VE_SP810: not modelled */ 619 /* VE_SERIALPCI: not modelled */ 620 621 pl041 = qdev_create(NULL, "pl041"); 622 qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512); 623 qdev_init_nofail(pl041); 624 sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, map[VE_PL041]); 625 sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[11]); 626 627 dev = sysbus_create_varargs("pl181", map[VE_MMCI], pic[9], pic[10], NULL); 628 /* Wire up MMC card detect and read-only signals */ 629 qdev_connect_gpio_out(dev, 0, 630 qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT)); 631 qdev_connect_gpio_out(dev, 1, 632 qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN)); 633 634 sysbus_create_simple("pl050_keyboard", map[VE_KMI0], pic[12]); 635 sysbus_create_simple("pl050_mouse", map[VE_KMI1], pic[13]); 636 637 pl011_create(map[VE_UART0], pic[5], serial_hds[0]); 638 pl011_create(map[VE_UART1], pic[6], serial_hds[1]); 639 pl011_create(map[VE_UART2], pic[7], serial_hds[2]); 640 pl011_create(map[VE_UART3], pic[8], serial_hds[3]); 641 642 sysbus_create_simple("sp804", map[VE_TIMER01], pic[2]); 643 sysbus_create_simple("sp804", map[VE_TIMER23], pic[3]); 644 645 /* VE_SERIALDVI: not modelled */ 646 647 sysbus_create_simple("pl031", map[VE_RTC], pic[4]); /* RTC */ 648 649 /* VE_COMPACTFLASH: not modelled */ 650 651 sysbus_create_simple("pl111", map[VE_CLCD], pic[14]); 652 653 dinfo = drive_get_next(IF_PFLASH); 654 pflash0 = ve_pflash_cfi01_register(map[VE_NORFLASH0], "vexpress.flash0", 655 dinfo); 656 if (!pflash0) { 657 fprintf(stderr, "vexpress: error registering flash 0.\n"); 658 exit(1); 659 } 660 661 if (map[VE_NORFLASHALIAS] != -1) { 662 /* Map flash 0 as an alias into low memory */ 663 flash0mem = sysbus_mmio_get_region(SYS_BUS_DEVICE(pflash0), 0); 664 memory_region_init_alias(flashalias, NULL, "vexpress.flashalias", 665 flash0mem, 0, VEXPRESS_FLASH_SIZE); 666 memory_region_add_subregion(sysmem, map[VE_NORFLASHALIAS], flashalias); 667 } 668 669 dinfo = drive_get_next(IF_PFLASH); 670 if (!ve_pflash_cfi01_register(map[VE_NORFLASH1], "vexpress.flash1", 671 dinfo)) { 672 fprintf(stderr, "vexpress: error registering flash 1.\n"); 673 exit(1); 674 } 675 676 sram_size = 0x2000000; 677 memory_region_init_ram(sram, NULL, "vexpress.sram", sram_size, 678 &error_fatal); 679 memory_region_add_subregion(sysmem, map[VE_SRAM], sram); 680 681 vram_size = 0x800000; 682 memory_region_init_ram(vram, NULL, "vexpress.vram", vram_size, 683 &error_fatal); 684 memory_region_add_subregion(sysmem, map[VE_VIDEORAM], vram); 685 686 /* 0x4e000000 LAN9118 Ethernet */ 687 if (nd_table[0].used) { 688 lan9118_init(&nd_table[0], map[VE_ETHERNET], pic[15]); 689 } 690 691 /* VE_USB: not modelled */ 692 693 /* VE_DAPROM: not modelled */ 694 695 /* Create mmio transports, so the user can create virtio backends 696 * (which will be automatically plugged in to the transports). If 697 * no backend is created the transport will just sit harmlessly idle. 698 */ 699 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) { 700 sysbus_create_simple("virtio-mmio", map[VE_VIRTIO] + 0x200 * i, 701 pic[40 + i]); 702 } 703 704 daughterboard->bootinfo.ram_size = machine->ram_size; 705 daughterboard->bootinfo.kernel_filename = machine->kernel_filename; 706 daughterboard->bootinfo.kernel_cmdline = machine->kernel_cmdline; 707 daughterboard->bootinfo.initrd_filename = machine->initrd_filename; 708 daughterboard->bootinfo.nb_cpus = smp_cpus; 709 daughterboard->bootinfo.board_id = VEXPRESS_BOARD_ID; 710 daughterboard->bootinfo.loader_start = daughterboard->loader_start; 711 daughterboard->bootinfo.smp_loader_start = map[VE_SRAM]; 712 daughterboard->bootinfo.smp_bootreg_addr = map[VE_SYSREGS] + 0x30; 713 daughterboard->bootinfo.gic_cpu_if_addr = daughterboard->gic_cpu_if_addr; 714 daughterboard->bootinfo.modify_dtb = vexpress_modify_dtb; 715 /* Indicate that when booting Linux we should be in secure state */ 716 daughterboard->bootinfo.secure_boot = true; 717 arm_load_kernel(ARM_CPU(first_cpu), &daughterboard->bootinfo); 718 } 719 720 static bool vexpress_get_secure(Object *obj, Error **errp) 721 { 722 VexpressMachineState *vms = VEXPRESS_MACHINE(obj); 723 724 return vms->secure; 725 } 726 727 static void vexpress_set_secure(Object *obj, bool value, Error **errp) 728 { 729 VexpressMachineState *vms = VEXPRESS_MACHINE(obj); 730 731 vms->secure = value; 732 } 733 734 static void vexpress_instance_init(Object *obj) 735 { 736 VexpressMachineState *vms = VEXPRESS_MACHINE(obj); 737 738 /* EL3 is enabled by default on vexpress */ 739 vms->secure = true; 740 object_property_add_bool(obj, "secure", vexpress_get_secure, 741 vexpress_set_secure, NULL); 742 object_property_set_description(obj, "secure", 743 "Set on/off to enable/disable the ARM " 744 "Security Extensions (TrustZone)", 745 NULL); 746 } 747 748 static void vexpress_class_init(ObjectClass *oc, void *data) 749 { 750 MachineClass *mc = MACHINE_CLASS(oc); 751 752 mc->desc = "ARM Versatile Express"; 753 mc->init = vexpress_common_init; 754 mc->max_cpus = 4; 755 mc->ignore_memory_transaction_failures = true; 756 } 757 758 static void vexpress_a9_class_init(ObjectClass *oc, void *data) 759 { 760 MachineClass *mc = MACHINE_CLASS(oc); 761 VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc); 762 763 mc->desc = "ARM Versatile Express for Cortex-A9"; 764 765 vmc->daughterboard = &a9_daughterboard; 766 } 767 768 static void vexpress_a15_class_init(ObjectClass *oc, void *data) 769 { 770 MachineClass *mc = MACHINE_CLASS(oc); 771 VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc); 772 773 mc->desc = "ARM Versatile Express for Cortex-A15"; 774 775 vmc->daughterboard = &a15_daughterboard; 776 } 777 778 static const TypeInfo vexpress_info = { 779 .name = TYPE_VEXPRESS_MACHINE, 780 .parent = TYPE_MACHINE, 781 .abstract = true, 782 .instance_size = sizeof(VexpressMachineState), 783 .instance_init = vexpress_instance_init, 784 .class_size = sizeof(VexpressMachineClass), 785 .class_init = vexpress_class_init, 786 }; 787 788 static const TypeInfo vexpress_a9_info = { 789 .name = TYPE_VEXPRESS_A9_MACHINE, 790 .parent = TYPE_VEXPRESS_MACHINE, 791 .class_init = vexpress_a9_class_init, 792 }; 793 794 static const TypeInfo vexpress_a15_info = { 795 .name = TYPE_VEXPRESS_A15_MACHINE, 796 .parent = TYPE_VEXPRESS_MACHINE, 797 .class_init = vexpress_a15_class_init, 798 }; 799 800 static void vexpress_machine_init(void) 801 { 802 type_register_static(&vexpress_info); 803 type_register_static(&vexpress_a9_info); 804 type_register_static(&vexpress_a15_info); 805 } 806 807 type_init(vexpress_machine_init); 808