xref: /openbmc/qemu/hw/arm/vexpress.c (revision 8d7f2e76)
1 /*
2  * ARM Versatile Express emulation.
3  *
4  * Copyright (c) 2010 - 2011 B Labs Ltd.
5  * Copyright (c) 2011 Linaro Limited
6  * Written by Bahadir Balban, Amit Mahajan, Peter Maydell
7  *
8  *  This program is free software; you can redistribute it and/or modify
9  *  it under the terms of the GNU General Public License version 2 as
10  *  published by the Free Software Foundation.
11  *
12  *  This program is distributed in the hope that it will be useful,
13  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
14  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  *  GNU General Public License for more details.
16  *
17  *  You should have received a copy of the GNU General Public License along
18  *  with this program; if not, see <http://www.gnu.org/licenses/>.
19  *
20  *  Contributions after 2012-01-13 are licensed under the terms of the
21  *  GNU GPL, version 2 or (at your option) any later version.
22  */
23 
24 #include "qemu/osdep.h"
25 #include "qapi/error.h"
26 #include "qemu/datadir.h"
27 #include "cpu.h"
28 #include "hw/sysbus.h"
29 #include "hw/arm/boot.h"
30 #include "hw/arm/primecell.h"
31 #include "hw/net/lan9118.h"
32 #include "hw/i2c/i2c.h"
33 #include "net/net.h"
34 #include "sysemu/sysemu.h"
35 #include "hw/boards.h"
36 #include "hw/loader.h"
37 #include "hw/block/flash.h"
38 #include "sysemu/device_tree.h"
39 #include "qemu/error-report.h"
40 #include <libfdt.h>
41 #include "hw/char/pl011.h"
42 #include "hw/cpu/a9mpcore.h"
43 #include "hw/cpu/a15mpcore.h"
44 #include "hw/i2c/arm_sbcon_i2c.h"
45 #include "hw/sd/sd.h"
46 #include "qom/object.h"
47 #include "audio/audio.h"
48 
49 #define VEXPRESS_BOARD_ID 0x8e0
50 #define VEXPRESS_FLASH_SIZE (64 * 1024 * 1024)
51 #define VEXPRESS_FLASH_SECT_SIZE (256 * 1024)
52 
53 /* Number of virtio transports to create (0..8; limited by
54  * number of available IRQ lines).
55  */
56 #define NUM_VIRTIO_TRANSPORTS 4
57 
58 /* Address maps for peripherals:
59  * the Versatile Express motherboard has two possible maps,
60  * the "legacy" one (used for A9) and the "Cortex-A Series"
61  * map (used for newer cores).
62  * Individual daughterboards can also have different maps for
63  * their peripherals.
64  */
65 
66 enum {
67     VE_SYSREGS,
68     VE_SP810,
69     VE_SERIALPCI,
70     VE_PL041,
71     VE_MMCI,
72     VE_KMI0,
73     VE_KMI1,
74     VE_UART0,
75     VE_UART1,
76     VE_UART2,
77     VE_UART3,
78     VE_WDT,
79     VE_TIMER01,
80     VE_TIMER23,
81     VE_SERIALDVI,
82     VE_RTC,
83     VE_COMPACTFLASH,
84     VE_CLCD,
85     VE_NORFLASH0,
86     VE_NORFLASH1,
87     VE_NORFLASHALIAS,
88     VE_SRAM,
89     VE_VIDEORAM,
90     VE_ETHERNET,
91     VE_USB,
92     VE_DAPROM,
93     VE_VIRTIO,
94 };
95 
96 static hwaddr motherboard_legacy_map[] = {
97     [VE_NORFLASHALIAS] = 0,
98     /* CS7: 0x10000000 .. 0x10020000 */
99     [VE_SYSREGS] = 0x10000000,
100     [VE_SP810] = 0x10001000,
101     [VE_SERIALPCI] = 0x10002000,
102     [VE_PL041] = 0x10004000,
103     [VE_MMCI] = 0x10005000,
104     [VE_KMI0] = 0x10006000,
105     [VE_KMI1] = 0x10007000,
106     [VE_UART0] = 0x10009000,
107     [VE_UART1] = 0x1000a000,
108     [VE_UART2] = 0x1000b000,
109     [VE_UART3] = 0x1000c000,
110     [VE_WDT] = 0x1000f000,
111     [VE_TIMER01] = 0x10011000,
112     [VE_TIMER23] = 0x10012000,
113     [VE_VIRTIO] = 0x10013000,
114     [VE_SERIALDVI] = 0x10016000,
115     [VE_RTC] = 0x10017000,
116     [VE_COMPACTFLASH] = 0x1001a000,
117     [VE_CLCD] = 0x1001f000,
118     /* CS0: 0x40000000 .. 0x44000000 */
119     [VE_NORFLASH0] = 0x40000000,
120     /* CS1: 0x44000000 .. 0x48000000 */
121     [VE_NORFLASH1] = 0x44000000,
122     /* CS2: 0x48000000 .. 0x4a000000 */
123     [VE_SRAM] = 0x48000000,
124     /* CS3: 0x4c000000 .. 0x50000000 */
125     [VE_VIDEORAM] = 0x4c000000,
126     [VE_ETHERNET] = 0x4e000000,
127     [VE_USB] = 0x4f000000,
128 };
129 
130 static hwaddr motherboard_aseries_map[] = {
131     [VE_NORFLASHALIAS] = 0,
132     /* CS0: 0x08000000 .. 0x0c000000 */
133     [VE_NORFLASH0] = 0x08000000,
134     /* CS4: 0x0c000000 .. 0x10000000 */
135     [VE_NORFLASH1] = 0x0c000000,
136     /* CS5: 0x10000000 .. 0x14000000 */
137     /* CS1: 0x14000000 .. 0x18000000 */
138     [VE_SRAM] = 0x14000000,
139     /* CS2: 0x18000000 .. 0x1c000000 */
140     [VE_VIDEORAM] = 0x18000000,
141     [VE_ETHERNET] = 0x1a000000,
142     [VE_USB] = 0x1b000000,
143     /* CS3: 0x1c000000 .. 0x20000000 */
144     [VE_DAPROM] = 0x1c000000,
145     [VE_SYSREGS] = 0x1c010000,
146     [VE_SP810] = 0x1c020000,
147     [VE_SERIALPCI] = 0x1c030000,
148     [VE_PL041] = 0x1c040000,
149     [VE_MMCI] = 0x1c050000,
150     [VE_KMI0] = 0x1c060000,
151     [VE_KMI1] = 0x1c070000,
152     [VE_UART0] = 0x1c090000,
153     [VE_UART1] = 0x1c0a0000,
154     [VE_UART2] = 0x1c0b0000,
155     [VE_UART3] = 0x1c0c0000,
156     [VE_WDT] = 0x1c0f0000,
157     [VE_TIMER01] = 0x1c110000,
158     [VE_TIMER23] = 0x1c120000,
159     [VE_VIRTIO] = 0x1c130000,
160     [VE_SERIALDVI] = 0x1c160000,
161     [VE_RTC] = 0x1c170000,
162     [VE_COMPACTFLASH] = 0x1c1a0000,
163     [VE_CLCD] = 0x1c1f0000,
164 };
165 
166 /* Structure defining the peculiarities of a specific daughterboard */
167 
168 typedef struct VEDBoardInfo VEDBoardInfo;
169 
170 struct VexpressMachineClass {
171     MachineClass parent;
172     VEDBoardInfo *daughterboard;
173 };
174 
175 struct VexpressMachineState {
176     MachineState parent;
177     MemoryRegion vram;
178     MemoryRegion sram;
179     MemoryRegion flashalias;
180     MemoryRegion lowram;
181     MemoryRegion a15sram;
182     bool secure;
183     bool virt;
184 };
185 
186 #define TYPE_VEXPRESS_MACHINE   "vexpress"
187 #define TYPE_VEXPRESS_A9_MACHINE   MACHINE_TYPE_NAME("vexpress-a9")
188 #define TYPE_VEXPRESS_A15_MACHINE   MACHINE_TYPE_NAME("vexpress-a15")
189 OBJECT_DECLARE_TYPE(VexpressMachineState, VexpressMachineClass, VEXPRESS_MACHINE)
190 
191 typedef void DBoardInitFn(VexpressMachineState *machine,
192                           ram_addr_t ram_size,
193                           const char *cpu_type,
194                           qemu_irq *pic);
195 
196 struct VEDBoardInfo {
197     struct arm_boot_info bootinfo;
198     const hwaddr *motherboard_map;
199     hwaddr loader_start;
200     const hwaddr gic_cpu_if_addr;
201     uint32_t proc_id;
202     uint32_t num_voltage_sensors;
203     const uint32_t *voltages;
204     uint32_t num_clocks;
205     const uint32_t *clocks;
206     DBoardInitFn *init;
207 };
208 
209 static void init_cpus(MachineState *ms, const char *cpu_type,
210                       const char *privdev, hwaddr periphbase,
211                       qemu_irq *pic, bool secure, bool virt)
212 {
213     DeviceState *dev;
214     SysBusDevice *busdev;
215     int n;
216     unsigned int smp_cpus = ms->smp.cpus;
217 
218     /* Create the actual CPUs */
219     for (n = 0; n < smp_cpus; n++) {
220         Object *cpuobj = object_new(cpu_type);
221 
222         if (!secure) {
223             object_property_set_bool(cpuobj, "has_el3", false, NULL);
224         }
225         if (!virt) {
226             if (object_property_find(cpuobj, "has_el2")) {
227                 object_property_set_bool(cpuobj, "has_el2", false, NULL);
228             }
229         }
230 
231         if (object_property_find(cpuobj, "reset-cbar")) {
232             object_property_set_int(cpuobj, "reset-cbar", periphbase,
233                                     &error_abort);
234         }
235         qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
236     }
237 
238     /* Create the private peripheral devices (including the GIC);
239      * this must happen after the CPUs are created because a15mpcore_priv
240      * wires itself up to the CPU's generic_timer gpio out lines.
241      */
242     dev = qdev_new(privdev);
243     qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
244     busdev = SYS_BUS_DEVICE(dev);
245     sysbus_realize_and_unref(busdev, &error_fatal);
246     sysbus_mmio_map(busdev, 0, periphbase);
247 
248     /* Interrupts [42:0] are from the motherboard;
249      * [47:43] are reserved; [63:48] are daughterboard
250      * peripherals. Note that some documentation numbers
251      * external interrupts starting from 32 (because there
252      * are internal interrupts 0..31).
253      */
254     for (n = 0; n < 64; n++) {
255         pic[n] = qdev_get_gpio_in(dev, n);
256     }
257 
258     /* Connect the CPUs to the GIC */
259     for (n = 0; n < smp_cpus; n++) {
260         DeviceState *cpudev = DEVICE(qemu_get_cpu(n));
261 
262         sysbus_connect_irq(busdev, n, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
263         sysbus_connect_irq(busdev, n + smp_cpus,
264                            qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
265         sysbus_connect_irq(busdev, n + 2 * smp_cpus,
266                            qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
267         sysbus_connect_irq(busdev, n + 3 * smp_cpus,
268                            qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
269     }
270 }
271 
272 static void a9_daughterboard_init(VexpressMachineState *vms,
273                                   ram_addr_t ram_size,
274                                   const char *cpu_type,
275                                   qemu_irq *pic)
276 {
277     MachineState *machine = MACHINE(vms);
278     MemoryRegion *sysmem = get_system_memory();
279     ram_addr_t low_ram_size;
280 
281     if (ram_size > 0x40000000) {
282         /* 1GB is the maximum the address space permits */
283         error_report("vexpress-a9: cannot model more than 1GB RAM");
284         exit(1);
285     }
286 
287     low_ram_size = ram_size;
288     if (low_ram_size > 0x4000000) {
289         low_ram_size = 0x4000000;
290     }
291     /* RAM is from 0x60000000 upwards. The bottom 64MB of the
292      * address space should in theory be remappable to various
293      * things including ROM or RAM; we always map the RAM there.
294      */
295     memory_region_init_alias(&vms->lowram, NULL, "vexpress.lowmem",
296                              machine->ram, 0, low_ram_size);
297     memory_region_add_subregion(sysmem, 0x0, &vms->lowram);
298     memory_region_add_subregion(sysmem, 0x60000000, machine->ram);
299 
300     /* 0x1e000000 A9MPCore (SCU) private memory region */
301     init_cpus(machine, cpu_type, TYPE_A9MPCORE_PRIV, 0x1e000000, pic,
302               vms->secure, vms->virt);
303 
304     /* Daughterboard peripherals : 0x10020000 .. 0x20000000 */
305 
306     /* 0x10020000 PL111 CLCD (daughterboard) */
307     sysbus_create_simple("pl111", 0x10020000, pic[44]);
308 
309     /* 0x10060000 AXI RAM */
310     /* 0x100e0000 PL341 Dynamic Memory Controller */
311     /* 0x100e1000 PL354 Static Memory Controller */
312     /* 0x100e2000 System Configuration Controller */
313 
314     sysbus_create_simple("sp804", 0x100e4000, pic[48]);
315     /* 0x100e5000 SP805 Watchdog module */
316     /* 0x100e6000 BP147 TrustZone Protection Controller */
317     /* 0x100e9000 PL301 'Fast' AXI matrix */
318     /* 0x100ea000 PL301 'Slow' AXI matrix */
319     /* 0x100ec000 TrustZone Address Space Controller */
320     /* 0x10200000 CoreSight debug APB */
321     /* 0x1e00a000 PL310 L2 Cache Controller */
322     sysbus_create_varargs("l2x0", 0x1e00a000, NULL);
323 }
324 
325 /* Voltage values for SYS_CFG_VOLT daughterboard registers;
326  * values are in microvolts.
327  */
328 static const uint32_t a9_voltages[] = {
329     1000000, /* VD10 : 1.0V : SoC internal logic voltage */
330     1000000, /* VD10_S2 : 1.0V : PL310, L2 cache, RAM, non-PL310 logic */
331     1000000, /* VD10_S3 : 1.0V : Cortex-A9, cores, MPEs, SCU, PL310 logic */
332     1800000, /* VCC1V8 : 1.8V : DDR2 SDRAM, test chip DDR2 I/O supply */
333     900000, /* DDR2VTT : 0.9V : DDR2 SDRAM VTT termination voltage */
334     3300000, /* VCC3V3 : 3.3V : local board supply for misc external logic */
335 };
336 
337 /* Reset values for daughterboard oscillators (in Hz) */
338 static const uint32_t a9_clocks[] = {
339     45000000, /* AMBA AXI ACLK: 45MHz */
340     23750000, /* daughterboard CLCD clock: 23.75MHz */
341     66670000, /* Test chip reference clock: 66.67MHz */
342 };
343 
344 static VEDBoardInfo a9_daughterboard = {
345     .motherboard_map = motherboard_legacy_map,
346     .loader_start = 0x60000000,
347     .gic_cpu_if_addr = 0x1e000100,
348     .proc_id = 0x0c000191,
349     .num_voltage_sensors = ARRAY_SIZE(a9_voltages),
350     .voltages = a9_voltages,
351     .num_clocks = ARRAY_SIZE(a9_clocks),
352     .clocks = a9_clocks,
353     .init = a9_daughterboard_init,
354 };
355 
356 static void a15_daughterboard_init(VexpressMachineState *vms,
357                                    ram_addr_t ram_size,
358                                    const char *cpu_type,
359                                    qemu_irq *pic)
360 {
361     MachineState *machine = MACHINE(vms);
362     MemoryRegion *sysmem = get_system_memory();
363 
364     {
365         /* We have to use a separate 64 bit variable here to avoid the gcc
366          * "comparison is always false due to limited range of data type"
367          * warning if we are on a host where ram_addr_t is 32 bits.
368          */
369         uint64_t rsz = ram_size;
370         if (rsz > (30ULL * 1024 * 1024 * 1024)) {
371             error_report("vexpress-a15: cannot model more than 30GB RAM");
372             exit(1);
373         }
374     }
375 
376     /* RAM is from 0x80000000 upwards; there is no low-memory alias for it. */
377     memory_region_add_subregion(sysmem, 0x80000000, machine->ram);
378 
379     /* 0x2c000000 A15MPCore private memory region (GIC) */
380     init_cpus(machine, cpu_type, TYPE_A15MPCORE_PRIV,
381               0x2c000000, pic, vms->secure, vms->virt);
382 
383     /* A15 daughterboard peripherals: */
384 
385     /* 0x20000000: CoreSight interfaces: not modelled */
386     /* 0x2a000000: PL301 AXI interconnect: not modelled */
387     /* 0x2a420000: SCC: not modelled */
388     /* 0x2a430000: system counter: not modelled */
389     /* 0x2b000000: HDLCD controller: not modelled */
390     /* 0x2b060000: SP805 watchdog: not modelled */
391     /* 0x2b0a0000: PL341 dynamic memory controller: not modelled */
392     /* 0x2e000000: system SRAM */
393     memory_region_init_ram(&vms->a15sram, NULL, "vexpress.a15sram", 0x10000,
394                            &error_fatal);
395     memory_region_add_subregion(sysmem, 0x2e000000, &vms->a15sram);
396 
397     /* 0x7ffb0000: DMA330 DMA controller: not modelled */
398     /* 0x7ffd0000: PL354 static memory controller: not modelled */
399 }
400 
401 static const uint32_t a15_voltages[] = {
402     900000, /* Vcore: 0.9V : CPU core voltage */
403 };
404 
405 static const uint32_t a15_clocks[] = {
406     60000000, /* OSCCLK0: 60MHz : CPU_CLK reference */
407     0, /* OSCCLK1: reserved */
408     0, /* OSCCLK2: reserved */
409     0, /* OSCCLK3: reserved */
410     40000000, /* OSCCLK4: 40MHz : external AXI master clock */
411     23750000, /* OSCCLK5: 23.75MHz : HDLCD PLL reference */
412     50000000, /* OSCCLK6: 50MHz : static memory controller clock */
413     60000000, /* OSCCLK7: 60MHz : SYSCLK reference */
414     40000000, /* OSCCLK8: 40MHz : DDR2 PLL reference */
415 };
416 
417 static VEDBoardInfo a15_daughterboard = {
418     .motherboard_map = motherboard_aseries_map,
419     .loader_start = 0x80000000,
420     .gic_cpu_if_addr = 0x2c002000,
421     .proc_id = 0x14000237,
422     .num_voltage_sensors = ARRAY_SIZE(a15_voltages),
423     .voltages = a15_voltages,
424     .num_clocks = ARRAY_SIZE(a15_clocks),
425     .clocks = a15_clocks,
426     .init = a15_daughterboard_init,
427 };
428 
429 static int add_virtio_mmio_node(void *fdt, uint32_t acells, uint32_t scells,
430                                 hwaddr addr, hwaddr size, uint32_t intc,
431                                 int irq)
432 {
433     /* Add a virtio_mmio node to the device tree blob:
434      *   virtio_mmio@ADDRESS {
435      *       compatible = "virtio,mmio";
436      *       reg = <ADDRESS, SIZE>;
437      *       interrupt-parent = <&intc>;
438      *       interrupts = <0, irq, 1>;
439      *   }
440      * (Note that the format of the interrupts property is dependent on the
441      * interrupt controller that interrupt-parent points to; these are for
442      * the ARM GIC and indicate an SPI interrupt, rising-edge-triggered.)
443      */
444     int rc;
445     char *nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, addr);
446 
447     rc = qemu_fdt_add_subnode(fdt, nodename);
448     rc |= qemu_fdt_setprop_string(fdt, nodename,
449                                   "compatible", "virtio,mmio");
450     rc |= qemu_fdt_setprop_sized_cells(fdt, nodename, "reg",
451                                        acells, addr, scells, size);
452     qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", intc);
453     qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 0, irq, 1);
454     qemu_fdt_setprop(fdt, nodename, "dma-coherent", NULL, 0);
455     g_free(nodename);
456     if (rc) {
457         return -1;
458     }
459     return 0;
460 }
461 
462 static uint32_t find_int_controller(void *fdt)
463 {
464     /* Find the FDT node corresponding to the interrupt controller
465      * for virtio-mmio devices. We do this by scanning the fdt for
466      * a node with the right compatibility, since we know there is
467      * only one GIC on a vexpress board.
468      * We return the phandle of the node, or 0 if none was found.
469      */
470     const char *compat = "arm,cortex-a9-gic";
471     int offset;
472 
473     offset = fdt_node_offset_by_compatible(fdt, -1, compat);
474     if (offset >= 0) {
475         return fdt_get_phandle(fdt, offset);
476     }
477     return 0;
478 }
479 
480 static void vexpress_modify_dtb(const struct arm_boot_info *info, void *fdt)
481 {
482     uint32_t acells, scells, intc;
483     const VEDBoardInfo *daughterboard = (const VEDBoardInfo *)info;
484 
485     acells = qemu_fdt_getprop_cell(fdt, "/", "#address-cells",
486                                    NULL, &error_fatal);
487     scells = qemu_fdt_getprop_cell(fdt, "/", "#size-cells",
488                                    NULL, &error_fatal);
489     intc = find_int_controller(fdt);
490     if (!intc) {
491         /* Not fatal, we just won't provide virtio. This will
492          * happen with older device tree blobs.
493          */
494         warn_report("couldn't find interrupt controller in "
495                     "dtb; will not include virtio-mmio devices in the dtb");
496     } else {
497         int i;
498         const hwaddr *map = daughterboard->motherboard_map;
499 
500         /* We iterate backwards here because adding nodes
501          * to the dtb puts them in last-first.
502          */
503         for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) {
504             add_virtio_mmio_node(fdt, acells, scells,
505                                  map[VE_VIRTIO] + 0x200 * i,
506                                  0x200, intc, 40 + i);
507         }
508     }
509 }
510 
511 
512 /* Open code a private version of pflash registration since we
513  * need to set non-default device width for VExpress platform.
514  */
515 static PFlashCFI01 *ve_pflash_cfi01_register(hwaddr base, const char *name,
516                                              DriveInfo *di)
517 {
518     DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);
519 
520     if (di) {
521         qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(di));
522     }
523 
524     qdev_prop_set_uint32(dev, "num-blocks",
525                          VEXPRESS_FLASH_SIZE / VEXPRESS_FLASH_SECT_SIZE);
526     qdev_prop_set_uint64(dev, "sector-length", VEXPRESS_FLASH_SECT_SIZE);
527     qdev_prop_set_uint8(dev, "width", 4);
528     qdev_prop_set_uint8(dev, "device-width", 2);
529     qdev_prop_set_bit(dev, "big-endian", false);
530     qdev_prop_set_uint16(dev, "id0", 0x89);
531     qdev_prop_set_uint16(dev, "id1", 0x18);
532     qdev_prop_set_uint16(dev, "id2", 0x00);
533     qdev_prop_set_uint16(dev, "id3", 0x00);
534     qdev_prop_set_string(dev, "name", name);
535     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
536 
537     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
538     return PFLASH_CFI01(dev);
539 }
540 
541 static void vexpress_common_init(MachineState *machine)
542 {
543     VexpressMachineState *vms = VEXPRESS_MACHINE(machine);
544     VexpressMachineClass *vmc = VEXPRESS_MACHINE_GET_CLASS(machine);
545     VEDBoardInfo *daughterboard = vmc->daughterboard;
546     DeviceState *dev, *sysctl, *pl041;
547     qemu_irq pic[64];
548     uint32_t sys_id;
549     DriveInfo *dinfo;
550     PFlashCFI01 *pflash0;
551     I2CBus *i2c;
552     ram_addr_t vram_size, sram_size;
553     MemoryRegion *sysmem = get_system_memory();
554     const hwaddr *map = daughterboard->motherboard_map;
555     int i;
556 
557     daughterboard->init(vms, machine->ram_size, machine->cpu_type, pic);
558 
559     /*
560      * If a bios file was provided, attempt to map it into memory
561      */
562     if (machine->firmware) {
563         char *fn;
564         int image_size;
565 
566         if (drive_get(IF_PFLASH, 0, 0)) {
567             error_report("The contents of the first flash device may be "
568                          "specified with -bios or with -drive if=pflash... "
569                          "but you cannot use both options at once");
570             exit(1);
571         }
572         fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, machine->firmware);
573         if (!fn) {
574             error_report("Could not find ROM image '%s'", machine->firmware);
575             exit(1);
576         }
577         image_size = load_image_targphys(fn, map[VE_NORFLASH0],
578                                          VEXPRESS_FLASH_SIZE);
579         g_free(fn);
580         if (image_size < 0) {
581             error_report("Could not load ROM image '%s'", machine->firmware);
582             exit(1);
583         }
584     }
585 
586     /* Motherboard peripherals: the wiring is the same but the
587      * addresses vary between the legacy and A-Series memory maps.
588      */
589 
590     sys_id = 0x1190f500;
591 
592     sysctl = qdev_new("realview_sysctl");
593     qdev_prop_set_uint32(sysctl, "sys_id", sys_id);
594     qdev_prop_set_uint32(sysctl, "proc_id", daughterboard->proc_id);
595     qdev_prop_set_uint32(sysctl, "len-db-voltage",
596                          daughterboard->num_voltage_sensors);
597     for (i = 0; i < daughterboard->num_voltage_sensors; i++) {
598         char *propname = g_strdup_printf("db-voltage[%d]", i);
599         qdev_prop_set_uint32(sysctl, propname, daughterboard->voltages[i]);
600         g_free(propname);
601     }
602     qdev_prop_set_uint32(sysctl, "len-db-clock",
603                          daughterboard->num_clocks);
604     for (i = 0; i < daughterboard->num_clocks; i++) {
605         char *propname = g_strdup_printf("db-clock[%d]", i);
606         qdev_prop_set_uint32(sysctl, propname, daughterboard->clocks[i]);
607         g_free(propname);
608     }
609     sysbus_realize_and_unref(SYS_BUS_DEVICE(sysctl), &error_fatal);
610     sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, map[VE_SYSREGS]);
611 
612     /* VE_SP810: not modelled */
613     /* VE_SERIALPCI: not modelled */
614 
615     pl041 = qdev_new("pl041");
616     qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512);
617     if (machine->audiodev) {
618         qdev_prop_set_string(pl041, "audiodev", machine->audiodev);
619     }
620     sysbus_realize_and_unref(SYS_BUS_DEVICE(pl041), &error_fatal);
621     sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, map[VE_PL041]);
622     sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[11]);
623 
624     dev = sysbus_create_varargs("pl181", map[VE_MMCI], pic[9], pic[10], NULL);
625     /* Wire up MMC card detect and read-only signals */
626     qdev_connect_gpio_out_named(dev, "card-read-only", 0,
627                           qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT));
628     qdev_connect_gpio_out_named(dev, "card-inserted", 0,
629                           qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN));
630     dinfo = drive_get(IF_SD, 0, 0);
631     if (dinfo) {
632         DeviceState *card;
633 
634         card = qdev_new(TYPE_SD_CARD);
635         qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo),
636                                 &error_fatal);
637         qdev_realize_and_unref(card, qdev_get_child_bus(dev, "sd-bus"),
638                                &error_fatal);
639     }
640 
641     sysbus_create_simple("pl050_keyboard", map[VE_KMI0], pic[12]);
642     sysbus_create_simple("pl050_mouse", map[VE_KMI1], pic[13]);
643 
644     pl011_create(map[VE_UART0], pic[5], serial_hd(0));
645     pl011_create(map[VE_UART1], pic[6], serial_hd(1));
646     pl011_create(map[VE_UART2], pic[7], serial_hd(2));
647     pl011_create(map[VE_UART3], pic[8], serial_hd(3));
648 
649     sysbus_create_simple("sp804", map[VE_TIMER01], pic[2]);
650     sysbus_create_simple("sp804", map[VE_TIMER23], pic[3]);
651 
652     dev = sysbus_create_simple(TYPE_ARM_SBCON_I2C, map[VE_SERIALDVI], NULL);
653     i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
654     i2c_slave_create_simple(i2c, "sii9022", 0x39);
655 
656     sysbus_create_simple("pl031", map[VE_RTC], pic[4]); /* RTC */
657 
658     /* VE_COMPACTFLASH: not modelled */
659 
660     sysbus_create_simple("pl111", map[VE_CLCD], pic[14]);
661 
662     dinfo = drive_get(IF_PFLASH, 0, 0);
663     pflash0 = ve_pflash_cfi01_register(map[VE_NORFLASH0], "vexpress.flash0",
664                                        dinfo);
665 
666     if (map[VE_NORFLASHALIAS] != -1) {
667         /* Map flash 0 as an alias into low memory */
668         MemoryRegion *flash0mem;
669         flash0mem = sysbus_mmio_get_region(SYS_BUS_DEVICE(pflash0), 0);
670         memory_region_init_alias(&vms->flashalias, NULL, "vexpress.flashalias",
671                                  flash0mem, 0, VEXPRESS_FLASH_SIZE);
672         memory_region_add_subregion(sysmem, map[VE_NORFLASHALIAS], &vms->flashalias);
673     }
674 
675     dinfo = drive_get(IF_PFLASH, 0, 1);
676     ve_pflash_cfi01_register(map[VE_NORFLASH1], "vexpress.flash1", dinfo);
677 
678     sram_size = 0x2000000;
679     memory_region_init_ram(&vms->sram, NULL, "vexpress.sram", sram_size,
680                            &error_fatal);
681     memory_region_add_subregion(sysmem, map[VE_SRAM], &vms->sram);
682 
683     vram_size = 0x800000;
684     memory_region_init_ram(&vms->vram, NULL, "vexpress.vram", vram_size,
685                            &error_fatal);
686     memory_region_add_subregion(sysmem, map[VE_VIDEORAM], &vms->vram);
687 
688     /* 0x4e000000 LAN9118 Ethernet */
689     if (nd_table[0].used) {
690         lan9118_init(&nd_table[0], map[VE_ETHERNET], pic[15]);
691     }
692 
693     /* VE_USB: not modelled */
694 
695     /* VE_DAPROM: not modelled */
696 
697     /* Create mmio transports, so the user can create virtio backends
698      * (which will be automatically plugged in to the transports). If
699      * no backend is created the transport will just sit harmlessly idle.
700      */
701     for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) {
702         sysbus_create_simple("virtio-mmio", map[VE_VIRTIO] + 0x200 * i,
703                              pic[40 + i]);
704     }
705 
706     daughterboard->bootinfo.ram_size = machine->ram_size;
707     daughterboard->bootinfo.board_id = VEXPRESS_BOARD_ID;
708     daughterboard->bootinfo.loader_start = daughterboard->loader_start;
709     daughterboard->bootinfo.smp_loader_start = map[VE_SRAM];
710     daughterboard->bootinfo.smp_bootreg_addr = map[VE_SYSREGS] + 0x30;
711     daughterboard->bootinfo.gic_cpu_if_addr = daughterboard->gic_cpu_if_addr;
712     daughterboard->bootinfo.modify_dtb = vexpress_modify_dtb;
713     /* When booting Linux we should be in secure state if the CPU has one. */
714     daughterboard->bootinfo.secure_boot = vms->secure;
715     arm_load_kernel(ARM_CPU(first_cpu), machine, &daughterboard->bootinfo);
716 }
717 
718 static bool vexpress_get_secure(Object *obj, Error **errp)
719 {
720     VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
721 
722     return vms->secure;
723 }
724 
725 static void vexpress_set_secure(Object *obj, bool value, Error **errp)
726 {
727     VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
728 
729     vms->secure = value;
730 }
731 
732 static bool vexpress_get_virt(Object *obj, Error **errp)
733 {
734     VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
735 
736     return vms->virt;
737 }
738 
739 static void vexpress_set_virt(Object *obj, bool value, Error **errp)
740 {
741     VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
742 
743     vms->virt = value;
744 }
745 
746 static void vexpress_instance_init(Object *obj)
747 {
748     VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
749 
750     /* EL3 is enabled by default on vexpress */
751     vms->secure = true;
752 }
753 
754 static void vexpress_a15_instance_init(Object *obj)
755 {
756     VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
757 
758     /*
759      * For the vexpress-a15, EL2 is by default enabled if EL3 is,
760      * but can also be specifically set to on or off.
761      */
762     vms->virt = true;
763 }
764 
765 static void vexpress_a9_instance_init(Object *obj)
766 {
767     VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
768 
769     /* The A9 doesn't have the virt extensions */
770     vms->virt = false;
771 }
772 
773 static void vexpress_class_init(ObjectClass *oc, void *data)
774 {
775     MachineClass *mc = MACHINE_CLASS(oc);
776 
777     mc->desc = "ARM Versatile Express";
778     mc->init = vexpress_common_init;
779     mc->max_cpus = 4;
780     mc->ignore_memory_transaction_failures = true;
781     mc->default_ram_id = "vexpress.highmem";
782 
783     machine_add_audiodev_property(mc);
784     object_class_property_add_bool(oc, "secure", vexpress_get_secure,
785                                    vexpress_set_secure);
786     object_class_property_set_description(oc, "secure",
787                                           "Set on/off to enable/disable the ARM "
788                                           "Security Extensions (TrustZone)");
789 }
790 
791 static void vexpress_a9_class_init(ObjectClass *oc, void *data)
792 {
793     MachineClass *mc = MACHINE_CLASS(oc);
794     VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc);
795 
796     mc->desc = "ARM Versatile Express for Cortex-A9";
797     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9");
798 
799     vmc->daughterboard = &a9_daughterboard;
800 }
801 
802 static void vexpress_a15_class_init(ObjectClass *oc, void *data)
803 {
804     MachineClass *mc = MACHINE_CLASS(oc);
805     VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc);
806 
807     mc->desc = "ARM Versatile Express for Cortex-A15";
808     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
809 
810     vmc->daughterboard = &a15_daughterboard;
811 
812     object_class_property_add_bool(oc, "virtualization", vexpress_get_virt,
813                                    vexpress_set_virt);
814     object_class_property_set_description(oc, "virtualization",
815                                           "Set on/off to enable/disable the ARM "
816                                           "Virtualization Extensions "
817                                           "(defaults to same as 'secure')");
818 
819 }
820 
821 static const TypeInfo vexpress_info = {
822     .name = TYPE_VEXPRESS_MACHINE,
823     .parent = TYPE_MACHINE,
824     .abstract = true,
825     .instance_size = sizeof(VexpressMachineState),
826     .instance_init = vexpress_instance_init,
827     .class_size = sizeof(VexpressMachineClass),
828     .class_init = vexpress_class_init,
829 };
830 
831 static const TypeInfo vexpress_a9_info = {
832     .name = TYPE_VEXPRESS_A9_MACHINE,
833     .parent = TYPE_VEXPRESS_MACHINE,
834     .class_init = vexpress_a9_class_init,
835     .instance_init = vexpress_a9_instance_init,
836 };
837 
838 static const TypeInfo vexpress_a15_info = {
839     .name = TYPE_VEXPRESS_A15_MACHINE,
840     .parent = TYPE_VEXPRESS_MACHINE,
841     .class_init = vexpress_a15_class_init,
842     .instance_init = vexpress_a15_instance_init,
843 };
844 
845 static void vexpress_machine_init(void)
846 {
847     type_register_static(&vexpress_info);
848     type_register_static(&vexpress_a9_info);
849     type_register_static(&vexpress_a15_info);
850 }
851 
852 type_init(vexpress_machine_init);
853