1 /* 2 * ARM Versatile Platform/Application Baseboard System emulation. 3 * 4 * Copyright (c) 2005-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qapi/error.h" 12 #include "cpu.h" 13 #include "hw/sysbus.h" 14 #include "migration/vmstate.h" 15 #include "hw/arm/boot.h" 16 #include "hw/net/smc91c111.h" 17 #include "net/net.h" 18 #include "sysemu/sysemu.h" 19 #include "hw/pci/pci.h" 20 #include "hw/i2c/i2c.h" 21 #include "hw/i2c/arm_sbcon_i2c.h" 22 #include "hw/irq.h" 23 #include "hw/boards.h" 24 #include "exec/address-spaces.h" 25 #include "hw/block/flash.h" 26 #include "qemu/error-report.h" 27 #include "hw/char/pl011.h" 28 #include "hw/sd/sd.h" 29 #include "qom/object.h" 30 31 #define VERSATILE_FLASH_ADDR 0x34000000 32 #define VERSATILE_FLASH_SIZE (64 * 1024 * 1024) 33 #define VERSATILE_FLASH_SECT_SIZE (256 * 1024) 34 35 /* Primary interrupt controller. */ 36 37 #define TYPE_VERSATILE_PB_SIC "versatilepb_sic" 38 typedef struct vpb_sic_state vpb_sic_state; 39 DECLARE_INSTANCE_CHECKER(vpb_sic_state, VERSATILE_PB_SIC, 40 TYPE_VERSATILE_PB_SIC) 41 42 struct vpb_sic_state { 43 SysBusDevice parent_obj; 44 45 MemoryRegion iomem; 46 uint32_t level; 47 uint32_t mask; 48 uint32_t pic_enable; 49 qemu_irq parent[32]; 50 int irq; 51 }; 52 53 static const VMStateDescription vmstate_vpb_sic = { 54 .name = "versatilepb_sic", 55 .version_id = 1, 56 .minimum_version_id = 1, 57 .fields = (VMStateField[]) { 58 VMSTATE_UINT32(level, vpb_sic_state), 59 VMSTATE_UINT32(mask, vpb_sic_state), 60 VMSTATE_UINT32(pic_enable, vpb_sic_state), 61 VMSTATE_END_OF_LIST() 62 } 63 }; 64 65 static void vpb_sic_update(vpb_sic_state *s) 66 { 67 uint32_t flags; 68 69 flags = s->level & s->mask; 70 qemu_set_irq(s->parent[s->irq], flags != 0); 71 } 72 73 static void vpb_sic_update_pic(vpb_sic_state *s) 74 { 75 int i; 76 uint32_t mask; 77 78 for (i = 21; i <= 30; i++) { 79 mask = 1u << i; 80 if (!(s->pic_enable & mask)) 81 continue; 82 qemu_set_irq(s->parent[i], (s->level & mask) != 0); 83 } 84 } 85 86 static void vpb_sic_set_irq(void *opaque, int irq, int level) 87 { 88 vpb_sic_state *s = (vpb_sic_state *)opaque; 89 if (level) 90 s->level |= 1u << irq; 91 else 92 s->level &= ~(1u << irq); 93 if (s->pic_enable & (1u << irq)) 94 qemu_set_irq(s->parent[irq], level); 95 vpb_sic_update(s); 96 } 97 98 static uint64_t vpb_sic_read(void *opaque, hwaddr offset, 99 unsigned size) 100 { 101 vpb_sic_state *s = (vpb_sic_state *)opaque; 102 103 switch (offset >> 2) { 104 case 0: /* STATUS */ 105 return s->level & s->mask; 106 case 1: /* RAWSTAT */ 107 return s->level; 108 case 2: /* ENABLE */ 109 return s->mask; 110 case 4: /* SOFTINT */ 111 return s->level & 1; 112 case 8: /* PICENABLE */ 113 return s->pic_enable; 114 default: 115 printf ("vpb_sic_read: Bad register offset 0x%x\n", (int)offset); 116 return 0; 117 } 118 } 119 120 static void vpb_sic_write(void *opaque, hwaddr offset, 121 uint64_t value, unsigned size) 122 { 123 vpb_sic_state *s = (vpb_sic_state *)opaque; 124 125 switch (offset >> 2) { 126 case 2: /* ENSET */ 127 s->mask |= value; 128 break; 129 case 3: /* ENCLR */ 130 s->mask &= ~value; 131 break; 132 case 4: /* SOFTINTSET */ 133 if (value) 134 s->mask |= 1; 135 break; 136 case 5: /* SOFTINTCLR */ 137 if (value) 138 s->mask &= ~1u; 139 break; 140 case 8: /* PICENSET */ 141 s->pic_enable |= (value & 0x7fe00000); 142 vpb_sic_update_pic(s); 143 break; 144 case 9: /* PICENCLR */ 145 s->pic_enable &= ~value; 146 vpb_sic_update_pic(s); 147 break; 148 default: 149 printf ("vpb_sic_write: Bad register offset 0x%x\n", (int)offset); 150 return; 151 } 152 vpb_sic_update(s); 153 } 154 155 static const MemoryRegionOps vpb_sic_ops = { 156 .read = vpb_sic_read, 157 .write = vpb_sic_write, 158 .endianness = DEVICE_NATIVE_ENDIAN, 159 }; 160 161 static void vpb_sic_init(Object *obj) 162 { 163 DeviceState *dev = DEVICE(obj); 164 vpb_sic_state *s = VERSATILE_PB_SIC(obj); 165 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 166 int i; 167 168 qdev_init_gpio_in(dev, vpb_sic_set_irq, 32); 169 for (i = 0; i < 32; i++) { 170 sysbus_init_irq(sbd, &s->parent[i]); 171 } 172 s->irq = 31; 173 memory_region_init_io(&s->iomem, obj, &vpb_sic_ops, s, 174 "vpb-sic", 0x1000); 175 sysbus_init_mmio(sbd, &s->iomem); 176 } 177 178 /* Board init. */ 179 180 /* The AB and PB boards both use the same core, just with different 181 peripherals and expansion busses. For now we emulate a subset of the 182 PB peripherals and just change the board ID. */ 183 184 static struct arm_boot_info versatile_binfo; 185 186 static void versatile_init(MachineState *machine, int board_id) 187 { 188 Object *cpuobj; 189 ARMCPU *cpu; 190 MemoryRegion *sysmem = get_system_memory(); 191 qemu_irq pic[32]; 192 qemu_irq sic[32]; 193 DeviceState *dev, *sysctl; 194 SysBusDevice *busdev; 195 DeviceState *pl041; 196 PCIBus *pci_bus; 197 NICInfo *nd; 198 I2CBus *i2c; 199 int n; 200 int done_smc = 0; 201 DriveInfo *dinfo; 202 203 if (machine->ram_size > 0x10000000) { 204 /* Device starting at address 0x10000000, 205 * and memory cannot overlap with devices. 206 * Refuse to run rather than behaving very confusingly. 207 */ 208 error_report("versatilepb: memory size must not exceed 256MB"); 209 exit(1); 210 } 211 212 cpuobj = object_new(machine->cpu_type); 213 214 /* By default ARM1176 CPUs have EL3 enabled. This board does not 215 * currently support EL3 so the CPU EL3 property is disabled before 216 * realization. 217 */ 218 if (object_property_find(cpuobj, "has_el3", NULL)) { 219 object_property_set_bool(cpuobj, "has_el3", false, &error_fatal); 220 } 221 222 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); 223 224 cpu = ARM_CPU(cpuobj); 225 226 /* ??? RAM should repeat to fill physical memory space. */ 227 /* SDRAM at address zero. */ 228 memory_region_add_subregion(sysmem, 0, machine->ram); 229 230 sysctl = qdev_new("realview_sysctl"); 231 qdev_prop_set_uint32(sysctl, "sys_id", 0x41007004); 232 qdev_prop_set_uint32(sysctl, "proc_id", 0x02000000); 233 sysbus_realize_and_unref(SYS_BUS_DEVICE(sysctl), &error_fatal); 234 sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, 0x10000000); 235 236 dev = sysbus_create_varargs("pl190", 0x10140000, 237 qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ), 238 qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ), 239 NULL); 240 for (n = 0; n < 32; n++) { 241 pic[n] = qdev_get_gpio_in(dev, n); 242 } 243 dev = sysbus_create_simple(TYPE_VERSATILE_PB_SIC, 0x10003000, NULL); 244 for (n = 0; n < 32; n++) { 245 sysbus_connect_irq(SYS_BUS_DEVICE(dev), n, pic[n]); 246 sic[n] = qdev_get_gpio_in(dev, n); 247 } 248 249 sysbus_create_simple("pl050_keyboard", 0x10006000, sic[3]); 250 sysbus_create_simple("pl050_mouse", 0x10007000, sic[4]); 251 252 dev = qdev_new("versatile_pci"); 253 busdev = SYS_BUS_DEVICE(dev); 254 sysbus_realize_and_unref(busdev, &error_fatal); 255 sysbus_mmio_map(busdev, 0, 0x10001000); /* PCI controller regs */ 256 sysbus_mmio_map(busdev, 1, 0x41000000); /* PCI self-config */ 257 sysbus_mmio_map(busdev, 2, 0x42000000); /* PCI config */ 258 sysbus_mmio_map(busdev, 3, 0x43000000); /* PCI I/O */ 259 sysbus_mmio_map(busdev, 4, 0x44000000); /* PCI memory window 1 */ 260 sysbus_mmio_map(busdev, 5, 0x50000000); /* PCI memory window 2 */ 261 sysbus_mmio_map(busdev, 6, 0x60000000); /* PCI memory window 3 */ 262 sysbus_connect_irq(busdev, 0, sic[27]); 263 sysbus_connect_irq(busdev, 1, sic[28]); 264 sysbus_connect_irq(busdev, 2, sic[29]); 265 sysbus_connect_irq(busdev, 3, sic[30]); 266 pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci"); 267 268 for(n = 0; n < nb_nics; n++) { 269 nd = &nd_table[n]; 270 271 if (!done_smc && (!nd->model || strcmp(nd->model, "smc91c111") == 0)) { 272 smc91c111_init(nd, 0x10010000, sic[25]); 273 done_smc = 1; 274 } else { 275 pci_nic_init_nofail(nd, pci_bus, "rtl8139", NULL); 276 } 277 } 278 if (machine_usb(machine)) { 279 pci_create_simple(pci_bus, -1, "pci-ohci"); 280 } 281 n = drive_get_max_bus(IF_SCSI); 282 while (n >= 0) { 283 dev = DEVICE(pci_create_simple(pci_bus, -1, "lsi53c895a")); 284 lsi53c8xx_handle_legacy_cmdline(dev); 285 n--; 286 } 287 288 pl011_create(0x101f1000, pic[12], serial_hd(0)); 289 pl011_create(0x101f2000, pic[13], serial_hd(1)); 290 pl011_create(0x101f3000, pic[14], serial_hd(2)); 291 pl011_create(0x10009000, sic[6], serial_hd(3)); 292 293 dev = qdev_new("pl080"); 294 object_property_set_link(OBJECT(dev), "downstream", OBJECT(sysmem), 295 &error_fatal); 296 busdev = SYS_BUS_DEVICE(dev); 297 sysbus_realize_and_unref(busdev, &error_fatal); 298 sysbus_mmio_map(busdev, 0, 0x10130000); 299 sysbus_connect_irq(busdev, 0, pic[17]); 300 301 sysbus_create_simple("sp804", 0x101e2000, pic[4]); 302 sysbus_create_simple("sp804", 0x101e3000, pic[5]); 303 304 sysbus_create_simple("pl061", 0x101e4000, pic[6]); 305 sysbus_create_simple("pl061", 0x101e5000, pic[7]); 306 sysbus_create_simple("pl061", 0x101e6000, pic[8]); 307 sysbus_create_simple("pl061", 0x101e7000, pic[9]); 308 309 /* The versatile/PB actually has a modified Color LCD controller 310 that includes hardware cursor support from the PL111. */ 311 dev = sysbus_create_simple("pl110_versatile", 0x10120000, pic[16]); 312 /* Wire up the mux control signals from the SYS_CLCD register */ 313 qdev_connect_gpio_out(sysctl, 0, qdev_get_gpio_in(dev, 0)); 314 315 dev = sysbus_create_varargs("pl181", 0x10005000, sic[22], sic[1], NULL); 316 dinfo = drive_get_next(IF_SD); 317 if (dinfo) { 318 DeviceState *card; 319 320 card = qdev_new(TYPE_SD_CARD); 321 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo), 322 &error_fatal); 323 qdev_realize_and_unref(card, qdev_get_child_bus(dev, "sd-bus"), 324 &error_fatal); 325 } 326 327 dev = sysbus_create_varargs("pl181", 0x1000b000, sic[23], sic[2], NULL); 328 dinfo = drive_get_next(IF_SD); 329 if (dinfo) { 330 DeviceState *card; 331 332 card = qdev_new(TYPE_SD_CARD); 333 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo), 334 &error_fatal); 335 qdev_realize_and_unref(card, qdev_get_child_bus(dev, "sd-bus"), 336 &error_fatal); 337 } 338 339 /* Add PL031 Real Time Clock. */ 340 sysbus_create_simple("pl031", 0x101e8000, pic[10]); 341 342 dev = sysbus_create_simple(TYPE_VERSATILE_I2C, 0x10002000, NULL); 343 i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c"); 344 i2c_slave_create_simple(i2c, "ds1338", 0x68); 345 346 /* Add PL041 AACI Interface to the LM4549 codec */ 347 pl041 = qdev_new("pl041"); 348 qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512); 349 sysbus_realize_and_unref(SYS_BUS_DEVICE(pl041), &error_fatal); 350 sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, 0x10004000); 351 sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, sic[24]); 352 353 /* Memory map for Versatile/PB: */ 354 /* 0x10000000 System registers. */ 355 /* 0x10001000 PCI controller config registers. */ 356 /* 0x10002000 Serial bus interface. */ 357 /* 0x10003000 Secondary interrupt controller. */ 358 /* 0x10004000 AACI (audio). */ 359 /* 0x10005000 MMCI0. */ 360 /* 0x10006000 KMI0 (keyboard). */ 361 /* 0x10007000 KMI1 (mouse). */ 362 /* 0x10008000 Character LCD Interface. */ 363 /* 0x10009000 UART3. */ 364 /* 0x1000a000 Smart card 1. */ 365 /* 0x1000b000 MMCI1. */ 366 /* 0x10010000 Ethernet. */ 367 /* 0x10020000 USB. */ 368 /* 0x10100000 SSMC. */ 369 /* 0x10110000 MPMC. */ 370 /* 0x10120000 CLCD Controller. */ 371 /* 0x10130000 DMA Controller. */ 372 /* 0x10140000 Vectored interrupt controller. */ 373 /* 0x101d0000 AHB Monitor Interface. */ 374 /* 0x101e0000 System Controller. */ 375 /* 0x101e1000 Watchdog Interface. */ 376 /* 0x101e2000 Timer 0/1. */ 377 /* 0x101e3000 Timer 2/3. */ 378 /* 0x101e4000 GPIO port 0. */ 379 /* 0x101e5000 GPIO port 1. */ 380 /* 0x101e6000 GPIO port 2. */ 381 /* 0x101e7000 GPIO port 3. */ 382 /* 0x101e8000 RTC. */ 383 /* 0x101f0000 Smart card 0. */ 384 /* 0x101f1000 UART0. */ 385 /* 0x101f2000 UART1. */ 386 /* 0x101f3000 UART2. */ 387 /* 0x101f4000 SSPI. */ 388 /* 0x34000000 NOR Flash */ 389 390 dinfo = drive_get(IF_PFLASH, 0, 0); 391 if (!pflash_cfi01_register(VERSATILE_FLASH_ADDR, "versatile.flash", 392 VERSATILE_FLASH_SIZE, 393 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, 394 VERSATILE_FLASH_SECT_SIZE, 395 4, 0x0089, 0x0018, 0x0000, 0x0, 0)) { 396 fprintf(stderr, "qemu: Error registering flash memory.\n"); 397 } 398 399 versatile_binfo.ram_size = machine->ram_size; 400 versatile_binfo.board_id = board_id; 401 arm_load_kernel(cpu, machine, &versatile_binfo); 402 } 403 404 static void vpb_init(MachineState *machine) 405 { 406 versatile_init(machine, 0x183); 407 } 408 409 static void vab_init(MachineState *machine) 410 { 411 versatile_init(machine, 0x25e); 412 } 413 414 static void versatilepb_class_init(ObjectClass *oc, void *data) 415 { 416 MachineClass *mc = MACHINE_CLASS(oc); 417 418 mc->desc = "ARM Versatile/PB (ARM926EJ-S)"; 419 mc->init = vpb_init; 420 mc->block_default_type = IF_SCSI; 421 mc->ignore_memory_transaction_failures = true; 422 mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926"); 423 mc->default_ram_id = "versatile.ram"; 424 } 425 426 static const TypeInfo versatilepb_type = { 427 .name = MACHINE_TYPE_NAME("versatilepb"), 428 .parent = TYPE_MACHINE, 429 .class_init = versatilepb_class_init, 430 }; 431 432 static void versatileab_class_init(ObjectClass *oc, void *data) 433 { 434 MachineClass *mc = MACHINE_CLASS(oc); 435 436 mc->desc = "ARM Versatile/AB (ARM926EJ-S)"; 437 mc->init = vab_init; 438 mc->block_default_type = IF_SCSI; 439 mc->ignore_memory_transaction_failures = true; 440 mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926"); 441 mc->default_ram_id = "versatile.ram"; 442 } 443 444 static const TypeInfo versatileab_type = { 445 .name = MACHINE_TYPE_NAME("versatileab"), 446 .parent = TYPE_MACHINE, 447 .class_init = versatileab_class_init, 448 }; 449 450 static void versatile_machine_init(void) 451 { 452 type_register_static(&versatilepb_type); 453 type_register_static(&versatileab_type); 454 } 455 456 type_init(versatile_machine_init) 457 458 static void vpb_sic_class_init(ObjectClass *klass, void *data) 459 { 460 DeviceClass *dc = DEVICE_CLASS(klass); 461 462 dc->vmsd = &vmstate_vpb_sic; 463 } 464 465 static const TypeInfo vpb_sic_info = { 466 .name = TYPE_VERSATILE_PB_SIC, 467 .parent = TYPE_SYS_BUS_DEVICE, 468 .instance_size = sizeof(vpb_sic_state), 469 .instance_init = vpb_sic_init, 470 .class_init = vpb_sic_class_init, 471 }; 472 473 static void versatilepb_register_types(void) 474 { 475 type_register_static(&vpb_sic_info); 476 } 477 478 type_init(versatilepb_register_types) 479