1 /* 2 * ARM Versatile Platform/Application Baseboard System emulation. 3 * 4 * Copyright (c) 2005-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "hw/sysbus.h" 11 #include "hw/arm/arm.h" 12 #include "hw/devices.h" 13 #include "net/net.h" 14 #include "sysemu/sysemu.h" 15 #include "hw/pci/pci.h" 16 #include "hw/i2c/i2c.h" 17 #include "hw/boards.h" 18 #include "sysemu/block-backend.h" 19 #include "exec/address-spaces.h" 20 #include "hw/block/flash.h" 21 #include "qemu/error-report.h" 22 23 #define VERSATILE_FLASH_ADDR 0x34000000 24 #define VERSATILE_FLASH_SIZE (64 * 1024 * 1024) 25 #define VERSATILE_FLASH_SECT_SIZE (256 * 1024) 26 27 /* Primary interrupt controller. */ 28 29 #define TYPE_VERSATILE_PB_SIC "versatilepb_sic" 30 #define VERSATILE_PB_SIC(obj) \ 31 OBJECT_CHECK(vpb_sic_state, (obj), TYPE_VERSATILE_PB_SIC) 32 33 typedef struct vpb_sic_state { 34 SysBusDevice parent_obj; 35 36 MemoryRegion iomem; 37 uint32_t level; 38 uint32_t mask; 39 uint32_t pic_enable; 40 qemu_irq parent[32]; 41 int irq; 42 } vpb_sic_state; 43 44 static const VMStateDescription vmstate_vpb_sic = { 45 .name = "versatilepb_sic", 46 .version_id = 1, 47 .minimum_version_id = 1, 48 .fields = (VMStateField[]) { 49 VMSTATE_UINT32(level, vpb_sic_state), 50 VMSTATE_UINT32(mask, vpb_sic_state), 51 VMSTATE_UINT32(pic_enable, vpb_sic_state), 52 VMSTATE_END_OF_LIST() 53 } 54 }; 55 56 static void vpb_sic_update(vpb_sic_state *s) 57 { 58 uint32_t flags; 59 60 flags = s->level & s->mask; 61 qemu_set_irq(s->parent[s->irq], flags != 0); 62 } 63 64 static void vpb_sic_update_pic(vpb_sic_state *s) 65 { 66 int i; 67 uint32_t mask; 68 69 for (i = 21; i <= 30; i++) { 70 mask = 1u << i; 71 if (!(s->pic_enable & mask)) 72 continue; 73 qemu_set_irq(s->parent[i], (s->level & mask) != 0); 74 } 75 } 76 77 static void vpb_sic_set_irq(void *opaque, int irq, int level) 78 { 79 vpb_sic_state *s = (vpb_sic_state *)opaque; 80 if (level) 81 s->level |= 1u << irq; 82 else 83 s->level &= ~(1u << irq); 84 if (s->pic_enable & (1u << irq)) 85 qemu_set_irq(s->parent[irq], level); 86 vpb_sic_update(s); 87 } 88 89 static uint64_t vpb_sic_read(void *opaque, hwaddr offset, 90 unsigned size) 91 { 92 vpb_sic_state *s = (vpb_sic_state *)opaque; 93 94 switch (offset >> 2) { 95 case 0: /* STATUS */ 96 return s->level & s->mask; 97 case 1: /* RAWSTAT */ 98 return s->level; 99 case 2: /* ENABLE */ 100 return s->mask; 101 case 4: /* SOFTINT */ 102 return s->level & 1; 103 case 8: /* PICENABLE */ 104 return s->pic_enable; 105 default: 106 printf ("vpb_sic_read: Bad register offset 0x%x\n", (int)offset); 107 return 0; 108 } 109 } 110 111 static void vpb_sic_write(void *opaque, hwaddr offset, 112 uint64_t value, unsigned size) 113 { 114 vpb_sic_state *s = (vpb_sic_state *)opaque; 115 116 switch (offset >> 2) { 117 case 2: /* ENSET */ 118 s->mask |= value; 119 break; 120 case 3: /* ENCLR */ 121 s->mask &= ~value; 122 break; 123 case 4: /* SOFTINTSET */ 124 if (value) 125 s->mask |= 1; 126 break; 127 case 5: /* SOFTINTCLR */ 128 if (value) 129 s->mask &= ~1u; 130 break; 131 case 8: /* PICENSET */ 132 s->pic_enable |= (value & 0x7fe00000); 133 vpb_sic_update_pic(s); 134 break; 135 case 9: /* PICENCLR */ 136 s->pic_enable &= ~value; 137 vpb_sic_update_pic(s); 138 break; 139 default: 140 printf ("vpb_sic_write: Bad register offset 0x%x\n", (int)offset); 141 return; 142 } 143 vpb_sic_update(s); 144 } 145 146 static const MemoryRegionOps vpb_sic_ops = { 147 .read = vpb_sic_read, 148 .write = vpb_sic_write, 149 .endianness = DEVICE_NATIVE_ENDIAN, 150 }; 151 152 static int vpb_sic_init(SysBusDevice *sbd) 153 { 154 DeviceState *dev = DEVICE(sbd); 155 vpb_sic_state *s = VERSATILE_PB_SIC(dev); 156 int i; 157 158 qdev_init_gpio_in(dev, vpb_sic_set_irq, 32); 159 for (i = 0; i < 32; i++) { 160 sysbus_init_irq(sbd, &s->parent[i]); 161 } 162 s->irq = 31; 163 memory_region_init_io(&s->iomem, OBJECT(s), &vpb_sic_ops, s, 164 "vpb-sic", 0x1000); 165 sysbus_init_mmio(sbd, &s->iomem); 166 return 0; 167 } 168 169 /* Board init. */ 170 171 /* The AB and PB boards both use the same core, just with different 172 peripherals and expansion busses. For now we emulate a subset of the 173 PB peripherals and just change the board ID. */ 174 175 static struct arm_boot_info versatile_binfo; 176 177 static void versatile_init(MachineState *machine, int board_id) 178 { 179 ObjectClass *cpu_oc; 180 Object *cpuobj; 181 ARMCPU *cpu; 182 MemoryRegion *sysmem = get_system_memory(); 183 MemoryRegion *ram = g_new(MemoryRegion, 1); 184 qemu_irq pic[32]; 185 qemu_irq sic[32]; 186 DeviceState *dev, *sysctl; 187 SysBusDevice *busdev; 188 DeviceState *pl041; 189 PCIBus *pci_bus; 190 NICInfo *nd; 191 I2CBus *i2c; 192 int n; 193 int done_smc = 0; 194 DriveInfo *dinfo; 195 196 if (!machine->cpu_model) { 197 machine->cpu_model = "arm926"; 198 } 199 200 cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, machine->cpu_model); 201 if (!cpu_oc) { 202 fprintf(stderr, "Unable to find CPU definition\n"); 203 exit(1); 204 } 205 206 cpuobj = object_new(object_class_get_name(cpu_oc)); 207 208 /* By default ARM1176 CPUs have EL3 enabled. This board does not 209 * currently support EL3 so the CPU EL3 property is disabled before 210 * realization. 211 */ 212 if (object_property_find(cpuobj, "has_el3", NULL)) { 213 object_property_set_bool(cpuobj, false, "has_el3", &error_fatal); 214 } 215 216 object_property_set_bool(cpuobj, true, "realized", &error_fatal); 217 218 cpu = ARM_CPU(cpuobj); 219 220 memory_region_allocate_system_memory(ram, NULL, "versatile.ram", 221 machine->ram_size); 222 /* ??? RAM should repeat to fill physical memory space. */ 223 /* SDRAM at address zero. */ 224 memory_region_add_subregion(sysmem, 0, ram); 225 226 sysctl = qdev_create(NULL, "realview_sysctl"); 227 qdev_prop_set_uint32(sysctl, "sys_id", 0x41007004); 228 qdev_prop_set_uint32(sysctl, "proc_id", 0x02000000); 229 qdev_init_nofail(sysctl); 230 sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, 0x10000000); 231 232 dev = sysbus_create_varargs("pl190", 0x10140000, 233 qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ), 234 qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ), 235 NULL); 236 for (n = 0; n < 32; n++) { 237 pic[n] = qdev_get_gpio_in(dev, n); 238 } 239 dev = sysbus_create_simple(TYPE_VERSATILE_PB_SIC, 0x10003000, NULL); 240 for (n = 0; n < 32; n++) { 241 sysbus_connect_irq(SYS_BUS_DEVICE(dev), n, pic[n]); 242 sic[n] = qdev_get_gpio_in(dev, n); 243 } 244 245 sysbus_create_simple("pl050_keyboard", 0x10006000, sic[3]); 246 sysbus_create_simple("pl050_mouse", 0x10007000, sic[4]); 247 248 dev = qdev_create(NULL, "versatile_pci"); 249 busdev = SYS_BUS_DEVICE(dev); 250 qdev_init_nofail(dev); 251 sysbus_mmio_map(busdev, 0, 0x10001000); /* PCI controller regs */ 252 sysbus_mmio_map(busdev, 1, 0x41000000); /* PCI self-config */ 253 sysbus_mmio_map(busdev, 2, 0x42000000); /* PCI config */ 254 sysbus_mmio_map(busdev, 3, 0x43000000); /* PCI I/O */ 255 sysbus_mmio_map(busdev, 4, 0x44000000); /* PCI memory window 1 */ 256 sysbus_mmio_map(busdev, 5, 0x50000000); /* PCI memory window 2 */ 257 sysbus_mmio_map(busdev, 6, 0x60000000); /* PCI memory window 3 */ 258 sysbus_connect_irq(busdev, 0, sic[27]); 259 sysbus_connect_irq(busdev, 1, sic[28]); 260 sysbus_connect_irq(busdev, 2, sic[29]); 261 sysbus_connect_irq(busdev, 3, sic[30]); 262 pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci"); 263 264 for(n = 0; n < nb_nics; n++) { 265 nd = &nd_table[n]; 266 267 if (!done_smc && (!nd->model || strcmp(nd->model, "smc91c111") == 0)) { 268 smc91c111_init(nd, 0x10010000, sic[25]); 269 done_smc = 1; 270 } else { 271 pci_nic_init_nofail(nd, pci_bus, "rtl8139", NULL); 272 } 273 } 274 if (usb_enabled()) { 275 pci_create_simple(pci_bus, -1, "pci-ohci"); 276 } 277 n = drive_get_max_bus(IF_SCSI); 278 while (n >= 0) { 279 pci_create_simple(pci_bus, -1, "lsi53c895a"); 280 n--; 281 } 282 283 sysbus_create_simple("pl011", 0x101f1000, pic[12]); 284 sysbus_create_simple("pl011", 0x101f2000, pic[13]); 285 sysbus_create_simple("pl011", 0x101f3000, pic[14]); 286 sysbus_create_simple("pl011", 0x10009000, sic[6]); 287 288 sysbus_create_simple("pl080", 0x10130000, pic[17]); 289 sysbus_create_simple("sp804", 0x101e2000, pic[4]); 290 sysbus_create_simple("sp804", 0x101e3000, pic[5]); 291 292 sysbus_create_simple("pl061", 0x101e4000, pic[6]); 293 sysbus_create_simple("pl061", 0x101e5000, pic[7]); 294 sysbus_create_simple("pl061", 0x101e6000, pic[8]); 295 sysbus_create_simple("pl061", 0x101e7000, pic[9]); 296 297 /* The versatile/PB actually has a modified Color LCD controller 298 that includes hardware cursor support from the PL111. */ 299 dev = sysbus_create_simple("pl110_versatile", 0x10120000, pic[16]); 300 /* Wire up the mux control signals from the SYS_CLCD register */ 301 qdev_connect_gpio_out(sysctl, 0, qdev_get_gpio_in(dev, 0)); 302 303 sysbus_create_varargs("pl181", 0x10005000, sic[22], sic[1], NULL); 304 sysbus_create_varargs("pl181", 0x1000b000, sic[23], sic[2], NULL); 305 306 /* Add PL031 Real Time Clock. */ 307 sysbus_create_simple("pl031", 0x101e8000, pic[10]); 308 309 dev = sysbus_create_simple("versatile_i2c", 0x10002000, NULL); 310 i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c"); 311 i2c_create_slave(i2c, "ds1338", 0x68); 312 313 /* Add PL041 AACI Interface to the LM4549 codec */ 314 pl041 = qdev_create(NULL, "pl041"); 315 qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512); 316 qdev_init_nofail(pl041); 317 sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, 0x10004000); 318 sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, sic[24]); 319 320 /* Memory map for Versatile/PB: */ 321 /* 0x10000000 System registers. */ 322 /* 0x10001000 PCI controller config registers. */ 323 /* 0x10002000 Serial bus interface. */ 324 /* 0x10003000 Secondary interrupt controller. */ 325 /* 0x10004000 AACI (audio). */ 326 /* 0x10005000 MMCI0. */ 327 /* 0x10006000 KMI0 (keyboard). */ 328 /* 0x10007000 KMI1 (mouse). */ 329 /* 0x10008000 Character LCD Interface. */ 330 /* 0x10009000 UART3. */ 331 /* 0x1000a000 Smart card 1. */ 332 /* 0x1000b000 MMCI1. */ 333 /* 0x10010000 Ethernet. */ 334 /* 0x10020000 USB. */ 335 /* 0x10100000 SSMC. */ 336 /* 0x10110000 MPMC. */ 337 /* 0x10120000 CLCD Controller. */ 338 /* 0x10130000 DMA Controller. */ 339 /* 0x10140000 Vectored interrupt controller. */ 340 /* 0x101d0000 AHB Monitor Interface. */ 341 /* 0x101e0000 System Controller. */ 342 /* 0x101e1000 Watchdog Interface. */ 343 /* 0x101e2000 Timer 0/1. */ 344 /* 0x101e3000 Timer 2/3. */ 345 /* 0x101e4000 GPIO port 0. */ 346 /* 0x101e5000 GPIO port 1. */ 347 /* 0x101e6000 GPIO port 2. */ 348 /* 0x101e7000 GPIO port 3. */ 349 /* 0x101e8000 RTC. */ 350 /* 0x101f0000 Smart card 0. */ 351 /* 0x101f1000 UART0. */ 352 /* 0x101f2000 UART1. */ 353 /* 0x101f3000 UART2. */ 354 /* 0x101f4000 SSPI. */ 355 /* 0x34000000 NOR Flash */ 356 357 dinfo = drive_get(IF_PFLASH, 0, 0); 358 if (!pflash_cfi01_register(VERSATILE_FLASH_ADDR, NULL, "versatile.flash", 359 VERSATILE_FLASH_SIZE, 360 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, 361 VERSATILE_FLASH_SECT_SIZE, 362 VERSATILE_FLASH_SIZE / VERSATILE_FLASH_SECT_SIZE, 363 4, 0x0089, 0x0018, 0x0000, 0x0, 0)) { 364 fprintf(stderr, "qemu: Error registering flash memory.\n"); 365 } 366 367 versatile_binfo.ram_size = machine->ram_size; 368 versatile_binfo.kernel_filename = machine->kernel_filename; 369 versatile_binfo.kernel_cmdline = machine->kernel_cmdline; 370 versatile_binfo.initrd_filename = machine->initrd_filename; 371 versatile_binfo.board_id = board_id; 372 arm_load_kernel(cpu, &versatile_binfo); 373 } 374 375 static void vpb_init(MachineState *machine) 376 { 377 versatile_init(machine, 0x183); 378 } 379 380 static void vab_init(MachineState *machine) 381 { 382 versatile_init(machine, 0x25e); 383 } 384 385 static void versatilepb_class_init(ObjectClass *oc, void *data) 386 { 387 MachineClass *mc = MACHINE_CLASS(oc); 388 389 mc->desc = "ARM Versatile/PB (ARM926EJ-S)"; 390 mc->init = vpb_init; 391 mc->block_default_type = IF_SCSI; 392 } 393 394 static const TypeInfo versatilepb_type = { 395 .name = MACHINE_TYPE_NAME("versatilepb"), 396 .parent = TYPE_MACHINE, 397 .class_init = versatilepb_class_init, 398 }; 399 400 static void versatileab_class_init(ObjectClass *oc, void *data) 401 { 402 MachineClass *mc = MACHINE_CLASS(oc); 403 404 mc->desc = "ARM Versatile/AB (ARM926EJ-S)"; 405 mc->init = vab_init; 406 mc->block_default_type = IF_SCSI; 407 } 408 409 static const TypeInfo versatileab_type = { 410 .name = MACHINE_TYPE_NAME("versatileab"), 411 .parent = TYPE_MACHINE, 412 .class_init = versatileab_class_init, 413 }; 414 415 static void versatile_machine_init(void) 416 { 417 type_register_static(&versatilepb_type); 418 type_register_static(&versatileab_type); 419 } 420 421 machine_init(versatile_machine_init) 422 423 static void vpb_sic_class_init(ObjectClass *klass, void *data) 424 { 425 DeviceClass *dc = DEVICE_CLASS(klass); 426 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 427 428 k->init = vpb_sic_init; 429 dc->vmsd = &vmstate_vpb_sic; 430 } 431 432 static const TypeInfo vpb_sic_info = { 433 .name = TYPE_VERSATILE_PB_SIC, 434 .parent = TYPE_SYS_BUS_DEVICE, 435 .instance_size = sizeof(vpb_sic_state), 436 .class_init = vpb_sic_class_init, 437 }; 438 439 static void versatilepb_register_types(void) 440 { 441 type_register_static(&vpb_sic_info); 442 } 443 444 type_init(versatilepb_register_types) 445