1 /* 2 * ARM Versatile Platform/Application Baseboard System emulation. 3 * 4 * Copyright (c) 2005-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qapi/error.h" 12 #include "hw/sysbus.h" 13 #include "hw/arm/arm.h" 14 #include "hw/devices.h" 15 #include "net/net.h" 16 #include "sysemu/sysemu.h" 17 #include "hw/pci/pci.h" 18 #include "hw/i2c/i2c.h" 19 #include "hw/boards.h" 20 #include "sysemu/block-backend.h" 21 #include "exec/address-spaces.h" 22 #include "hw/block/flash.h" 23 #include "qemu/error-report.h" 24 25 #define VERSATILE_FLASH_ADDR 0x34000000 26 #define VERSATILE_FLASH_SIZE (64 * 1024 * 1024) 27 #define VERSATILE_FLASH_SECT_SIZE (256 * 1024) 28 29 /* Primary interrupt controller. */ 30 31 #define TYPE_VERSATILE_PB_SIC "versatilepb_sic" 32 #define VERSATILE_PB_SIC(obj) \ 33 OBJECT_CHECK(vpb_sic_state, (obj), TYPE_VERSATILE_PB_SIC) 34 35 typedef struct vpb_sic_state { 36 SysBusDevice parent_obj; 37 38 MemoryRegion iomem; 39 uint32_t level; 40 uint32_t mask; 41 uint32_t pic_enable; 42 qemu_irq parent[32]; 43 int irq; 44 } vpb_sic_state; 45 46 static const VMStateDescription vmstate_vpb_sic = { 47 .name = "versatilepb_sic", 48 .version_id = 1, 49 .minimum_version_id = 1, 50 .fields = (VMStateField[]) { 51 VMSTATE_UINT32(level, vpb_sic_state), 52 VMSTATE_UINT32(mask, vpb_sic_state), 53 VMSTATE_UINT32(pic_enable, vpb_sic_state), 54 VMSTATE_END_OF_LIST() 55 } 56 }; 57 58 static void vpb_sic_update(vpb_sic_state *s) 59 { 60 uint32_t flags; 61 62 flags = s->level & s->mask; 63 qemu_set_irq(s->parent[s->irq], flags != 0); 64 } 65 66 static void vpb_sic_update_pic(vpb_sic_state *s) 67 { 68 int i; 69 uint32_t mask; 70 71 for (i = 21; i <= 30; i++) { 72 mask = 1u << i; 73 if (!(s->pic_enable & mask)) 74 continue; 75 qemu_set_irq(s->parent[i], (s->level & mask) != 0); 76 } 77 } 78 79 static void vpb_sic_set_irq(void *opaque, int irq, int level) 80 { 81 vpb_sic_state *s = (vpb_sic_state *)opaque; 82 if (level) 83 s->level |= 1u << irq; 84 else 85 s->level &= ~(1u << irq); 86 if (s->pic_enable & (1u << irq)) 87 qemu_set_irq(s->parent[irq], level); 88 vpb_sic_update(s); 89 } 90 91 static uint64_t vpb_sic_read(void *opaque, hwaddr offset, 92 unsigned size) 93 { 94 vpb_sic_state *s = (vpb_sic_state *)opaque; 95 96 switch (offset >> 2) { 97 case 0: /* STATUS */ 98 return s->level & s->mask; 99 case 1: /* RAWSTAT */ 100 return s->level; 101 case 2: /* ENABLE */ 102 return s->mask; 103 case 4: /* SOFTINT */ 104 return s->level & 1; 105 case 8: /* PICENABLE */ 106 return s->pic_enable; 107 default: 108 printf ("vpb_sic_read: Bad register offset 0x%x\n", (int)offset); 109 return 0; 110 } 111 } 112 113 static void vpb_sic_write(void *opaque, hwaddr offset, 114 uint64_t value, unsigned size) 115 { 116 vpb_sic_state *s = (vpb_sic_state *)opaque; 117 118 switch (offset >> 2) { 119 case 2: /* ENSET */ 120 s->mask |= value; 121 break; 122 case 3: /* ENCLR */ 123 s->mask &= ~value; 124 break; 125 case 4: /* SOFTINTSET */ 126 if (value) 127 s->mask |= 1; 128 break; 129 case 5: /* SOFTINTCLR */ 130 if (value) 131 s->mask &= ~1u; 132 break; 133 case 8: /* PICENSET */ 134 s->pic_enable |= (value & 0x7fe00000); 135 vpb_sic_update_pic(s); 136 break; 137 case 9: /* PICENCLR */ 138 s->pic_enable &= ~value; 139 vpb_sic_update_pic(s); 140 break; 141 default: 142 printf ("vpb_sic_write: Bad register offset 0x%x\n", (int)offset); 143 return; 144 } 145 vpb_sic_update(s); 146 } 147 148 static const MemoryRegionOps vpb_sic_ops = { 149 .read = vpb_sic_read, 150 .write = vpb_sic_write, 151 .endianness = DEVICE_NATIVE_ENDIAN, 152 }; 153 154 static int vpb_sic_init(SysBusDevice *sbd) 155 { 156 DeviceState *dev = DEVICE(sbd); 157 vpb_sic_state *s = VERSATILE_PB_SIC(dev); 158 int i; 159 160 qdev_init_gpio_in(dev, vpb_sic_set_irq, 32); 161 for (i = 0; i < 32; i++) { 162 sysbus_init_irq(sbd, &s->parent[i]); 163 } 164 s->irq = 31; 165 memory_region_init_io(&s->iomem, OBJECT(s), &vpb_sic_ops, s, 166 "vpb-sic", 0x1000); 167 sysbus_init_mmio(sbd, &s->iomem); 168 return 0; 169 } 170 171 /* Board init. */ 172 173 /* The AB and PB boards both use the same core, just with different 174 peripherals and expansion busses. For now we emulate a subset of the 175 PB peripherals and just change the board ID. */ 176 177 static struct arm_boot_info versatile_binfo; 178 179 static void versatile_init(MachineState *machine, int board_id) 180 { 181 ObjectClass *cpu_oc; 182 Object *cpuobj; 183 ARMCPU *cpu; 184 MemoryRegion *sysmem = get_system_memory(); 185 MemoryRegion *ram = g_new(MemoryRegion, 1); 186 qemu_irq pic[32]; 187 qemu_irq sic[32]; 188 DeviceState *dev, *sysctl; 189 SysBusDevice *busdev; 190 DeviceState *pl041; 191 PCIBus *pci_bus; 192 NICInfo *nd; 193 I2CBus *i2c; 194 int n; 195 int done_smc = 0; 196 DriveInfo *dinfo; 197 198 if (!machine->cpu_model) { 199 machine->cpu_model = "arm926"; 200 } 201 202 cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, machine->cpu_model); 203 if (!cpu_oc) { 204 fprintf(stderr, "Unable to find CPU definition\n"); 205 exit(1); 206 } 207 208 cpuobj = object_new(object_class_get_name(cpu_oc)); 209 210 /* By default ARM1176 CPUs have EL3 enabled. This board does not 211 * currently support EL3 so the CPU EL3 property is disabled before 212 * realization. 213 */ 214 if (object_property_find(cpuobj, "has_el3", NULL)) { 215 object_property_set_bool(cpuobj, false, "has_el3", &error_fatal); 216 } 217 218 object_property_set_bool(cpuobj, true, "realized", &error_fatal); 219 220 cpu = ARM_CPU(cpuobj); 221 222 memory_region_allocate_system_memory(ram, NULL, "versatile.ram", 223 machine->ram_size); 224 /* ??? RAM should repeat to fill physical memory space. */ 225 /* SDRAM at address zero. */ 226 memory_region_add_subregion(sysmem, 0, ram); 227 228 sysctl = qdev_create(NULL, "realview_sysctl"); 229 qdev_prop_set_uint32(sysctl, "sys_id", 0x41007004); 230 qdev_prop_set_uint32(sysctl, "proc_id", 0x02000000); 231 qdev_init_nofail(sysctl); 232 sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, 0x10000000); 233 234 dev = sysbus_create_varargs("pl190", 0x10140000, 235 qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ), 236 qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ), 237 NULL); 238 for (n = 0; n < 32; n++) { 239 pic[n] = qdev_get_gpio_in(dev, n); 240 } 241 dev = sysbus_create_simple(TYPE_VERSATILE_PB_SIC, 0x10003000, NULL); 242 for (n = 0; n < 32; n++) { 243 sysbus_connect_irq(SYS_BUS_DEVICE(dev), n, pic[n]); 244 sic[n] = qdev_get_gpio_in(dev, n); 245 } 246 247 sysbus_create_simple("pl050_keyboard", 0x10006000, sic[3]); 248 sysbus_create_simple("pl050_mouse", 0x10007000, sic[4]); 249 250 dev = qdev_create(NULL, "versatile_pci"); 251 busdev = SYS_BUS_DEVICE(dev); 252 qdev_init_nofail(dev); 253 sysbus_mmio_map(busdev, 0, 0x10001000); /* PCI controller regs */ 254 sysbus_mmio_map(busdev, 1, 0x41000000); /* PCI self-config */ 255 sysbus_mmio_map(busdev, 2, 0x42000000); /* PCI config */ 256 sysbus_mmio_map(busdev, 3, 0x43000000); /* PCI I/O */ 257 sysbus_mmio_map(busdev, 4, 0x44000000); /* PCI memory window 1 */ 258 sysbus_mmio_map(busdev, 5, 0x50000000); /* PCI memory window 2 */ 259 sysbus_mmio_map(busdev, 6, 0x60000000); /* PCI memory window 3 */ 260 sysbus_connect_irq(busdev, 0, sic[27]); 261 sysbus_connect_irq(busdev, 1, sic[28]); 262 sysbus_connect_irq(busdev, 2, sic[29]); 263 sysbus_connect_irq(busdev, 3, sic[30]); 264 pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci"); 265 266 for(n = 0; n < nb_nics; n++) { 267 nd = &nd_table[n]; 268 269 if (!done_smc && (!nd->model || strcmp(nd->model, "smc91c111") == 0)) { 270 smc91c111_init(nd, 0x10010000, sic[25]); 271 done_smc = 1; 272 } else { 273 pci_nic_init_nofail(nd, pci_bus, "rtl8139", NULL); 274 } 275 } 276 if (usb_enabled()) { 277 pci_create_simple(pci_bus, -1, "pci-ohci"); 278 } 279 n = drive_get_max_bus(IF_SCSI); 280 while (n >= 0) { 281 pci_create_simple(pci_bus, -1, "lsi53c895a"); 282 n--; 283 } 284 285 sysbus_create_simple("pl011", 0x101f1000, pic[12]); 286 sysbus_create_simple("pl011", 0x101f2000, pic[13]); 287 sysbus_create_simple("pl011", 0x101f3000, pic[14]); 288 sysbus_create_simple("pl011", 0x10009000, sic[6]); 289 290 sysbus_create_simple("pl080", 0x10130000, pic[17]); 291 sysbus_create_simple("sp804", 0x101e2000, pic[4]); 292 sysbus_create_simple("sp804", 0x101e3000, pic[5]); 293 294 sysbus_create_simple("pl061", 0x101e4000, pic[6]); 295 sysbus_create_simple("pl061", 0x101e5000, pic[7]); 296 sysbus_create_simple("pl061", 0x101e6000, pic[8]); 297 sysbus_create_simple("pl061", 0x101e7000, pic[9]); 298 299 /* The versatile/PB actually has a modified Color LCD controller 300 that includes hardware cursor support from the PL111. */ 301 dev = sysbus_create_simple("pl110_versatile", 0x10120000, pic[16]); 302 /* Wire up the mux control signals from the SYS_CLCD register */ 303 qdev_connect_gpio_out(sysctl, 0, qdev_get_gpio_in(dev, 0)); 304 305 sysbus_create_varargs("pl181", 0x10005000, sic[22], sic[1], NULL); 306 sysbus_create_varargs("pl181", 0x1000b000, sic[23], sic[2], NULL); 307 308 /* Add PL031 Real Time Clock. */ 309 sysbus_create_simple("pl031", 0x101e8000, pic[10]); 310 311 dev = sysbus_create_simple("versatile_i2c", 0x10002000, NULL); 312 i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c"); 313 i2c_create_slave(i2c, "ds1338", 0x68); 314 315 /* Add PL041 AACI Interface to the LM4549 codec */ 316 pl041 = qdev_create(NULL, "pl041"); 317 qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512); 318 qdev_init_nofail(pl041); 319 sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, 0x10004000); 320 sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, sic[24]); 321 322 /* Memory map for Versatile/PB: */ 323 /* 0x10000000 System registers. */ 324 /* 0x10001000 PCI controller config registers. */ 325 /* 0x10002000 Serial bus interface. */ 326 /* 0x10003000 Secondary interrupt controller. */ 327 /* 0x10004000 AACI (audio). */ 328 /* 0x10005000 MMCI0. */ 329 /* 0x10006000 KMI0 (keyboard). */ 330 /* 0x10007000 KMI1 (mouse). */ 331 /* 0x10008000 Character LCD Interface. */ 332 /* 0x10009000 UART3. */ 333 /* 0x1000a000 Smart card 1. */ 334 /* 0x1000b000 MMCI1. */ 335 /* 0x10010000 Ethernet. */ 336 /* 0x10020000 USB. */ 337 /* 0x10100000 SSMC. */ 338 /* 0x10110000 MPMC. */ 339 /* 0x10120000 CLCD Controller. */ 340 /* 0x10130000 DMA Controller. */ 341 /* 0x10140000 Vectored interrupt controller. */ 342 /* 0x101d0000 AHB Monitor Interface. */ 343 /* 0x101e0000 System Controller. */ 344 /* 0x101e1000 Watchdog Interface. */ 345 /* 0x101e2000 Timer 0/1. */ 346 /* 0x101e3000 Timer 2/3. */ 347 /* 0x101e4000 GPIO port 0. */ 348 /* 0x101e5000 GPIO port 1. */ 349 /* 0x101e6000 GPIO port 2. */ 350 /* 0x101e7000 GPIO port 3. */ 351 /* 0x101e8000 RTC. */ 352 /* 0x101f0000 Smart card 0. */ 353 /* 0x101f1000 UART0. */ 354 /* 0x101f2000 UART1. */ 355 /* 0x101f3000 UART2. */ 356 /* 0x101f4000 SSPI. */ 357 /* 0x34000000 NOR Flash */ 358 359 dinfo = drive_get(IF_PFLASH, 0, 0); 360 if (!pflash_cfi01_register(VERSATILE_FLASH_ADDR, NULL, "versatile.flash", 361 VERSATILE_FLASH_SIZE, 362 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, 363 VERSATILE_FLASH_SECT_SIZE, 364 VERSATILE_FLASH_SIZE / VERSATILE_FLASH_SECT_SIZE, 365 4, 0x0089, 0x0018, 0x0000, 0x0, 0)) { 366 fprintf(stderr, "qemu: Error registering flash memory.\n"); 367 } 368 369 versatile_binfo.ram_size = machine->ram_size; 370 versatile_binfo.kernel_filename = machine->kernel_filename; 371 versatile_binfo.kernel_cmdline = machine->kernel_cmdline; 372 versatile_binfo.initrd_filename = machine->initrd_filename; 373 versatile_binfo.board_id = board_id; 374 arm_load_kernel(cpu, &versatile_binfo); 375 } 376 377 static void vpb_init(MachineState *machine) 378 { 379 versatile_init(machine, 0x183); 380 } 381 382 static void vab_init(MachineState *machine) 383 { 384 versatile_init(machine, 0x25e); 385 } 386 387 static void versatilepb_class_init(ObjectClass *oc, void *data) 388 { 389 MachineClass *mc = MACHINE_CLASS(oc); 390 391 mc->desc = "ARM Versatile/PB (ARM926EJ-S)"; 392 mc->init = vpb_init; 393 mc->block_default_type = IF_SCSI; 394 } 395 396 static const TypeInfo versatilepb_type = { 397 .name = MACHINE_TYPE_NAME("versatilepb"), 398 .parent = TYPE_MACHINE, 399 .class_init = versatilepb_class_init, 400 }; 401 402 static void versatileab_class_init(ObjectClass *oc, void *data) 403 { 404 MachineClass *mc = MACHINE_CLASS(oc); 405 406 mc->desc = "ARM Versatile/AB (ARM926EJ-S)"; 407 mc->init = vab_init; 408 mc->block_default_type = IF_SCSI; 409 } 410 411 static const TypeInfo versatileab_type = { 412 .name = MACHINE_TYPE_NAME("versatileab"), 413 .parent = TYPE_MACHINE, 414 .class_init = versatileab_class_init, 415 }; 416 417 static void versatile_machine_init(void) 418 { 419 type_register_static(&versatilepb_type); 420 type_register_static(&versatileab_type); 421 } 422 423 type_init(versatile_machine_init) 424 425 static void vpb_sic_class_init(ObjectClass *klass, void *data) 426 { 427 DeviceClass *dc = DEVICE_CLASS(klass); 428 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 429 430 k->init = vpb_sic_init; 431 dc->vmsd = &vmstate_vpb_sic; 432 } 433 434 static const TypeInfo vpb_sic_info = { 435 .name = TYPE_VERSATILE_PB_SIC, 436 .parent = TYPE_SYS_BUS_DEVICE, 437 .instance_size = sizeof(vpb_sic_state), 438 .class_init = vpb_sic_class_init, 439 }; 440 441 static void versatilepb_register_types(void) 442 { 443 type_register_static(&vpb_sic_info); 444 } 445 446 type_init(versatilepb_register_types) 447