1 /* 2 * StrongARM SA-1100/SA-1110 emulation 3 * 4 * Copyright (C) 2011 Dmitry Eremin-Solenikov 5 * 6 * Largely based on StrongARM emulation: 7 * Copyright (c) 2006 Openedhand Ltd. 8 * Written by Andrzej Zaborowski <balrog@zabor.org> 9 * 10 * UART code based on QEMU 16550A UART emulation 11 * Copyright (c) 2003-2004 Fabrice Bellard 12 * Copyright (c) 2008 Citrix Systems, Inc. 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License version 2 as 16 * published by the Free Software Foundation. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License along 24 * with this program; if not, see <http://www.gnu.org/licenses/>. 25 * 26 * Contributions after 2012-01-13 are licensed under the terms of the 27 * GNU GPL, version 2 or (at your option) any later version. 28 */ 29 #include "hw/sysbus.h" 30 #include "strongarm.h" 31 #include "qemu/error-report.h" 32 #include "hw/arm/arm.h" 33 #include "sysemu/char.h" 34 #include "sysemu/sysemu.h" 35 #include "hw/ssi.h" 36 37 //#define DEBUG 38 39 /* 40 TODO 41 - Implement cp15, c14 ? 42 - Implement cp15, c15 !!! (idle used in L) 43 - Implement idle mode handling/DIM 44 - Implement sleep mode/Wake sources 45 - Implement reset control 46 - Implement memory control regs 47 - PCMCIA handling 48 - Maybe support MBGNT/MBREQ 49 - DMA channels 50 - GPCLK 51 - IrDA 52 - MCP 53 - Enhance UART with modem signals 54 */ 55 56 #ifdef DEBUG 57 # define DPRINTF(format, ...) printf(format , ## __VA_ARGS__) 58 #else 59 # define DPRINTF(format, ...) do { } while (0) 60 #endif 61 62 static struct { 63 hwaddr io_base; 64 int irq; 65 } sa_serial[] = { 66 { 0x80010000, SA_PIC_UART1 }, 67 { 0x80030000, SA_PIC_UART2 }, 68 { 0x80050000, SA_PIC_UART3 }, 69 { 0, 0 } 70 }; 71 72 /* Interrupt Controller */ 73 typedef struct { 74 SysBusDevice busdev; 75 MemoryRegion iomem; 76 qemu_irq irq; 77 qemu_irq fiq; 78 79 uint32_t pending; 80 uint32_t enabled; 81 uint32_t is_fiq; 82 uint32_t int_idle; 83 } StrongARMPICState; 84 85 #define ICIP 0x00 86 #define ICMR 0x04 87 #define ICLR 0x08 88 #define ICFP 0x10 89 #define ICPR 0x20 90 #define ICCR 0x0c 91 92 #define SA_PIC_SRCS 32 93 94 95 static void strongarm_pic_update(void *opaque) 96 { 97 StrongARMPICState *s = opaque; 98 99 /* FIXME: reflect DIM */ 100 qemu_set_irq(s->fiq, s->pending & s->enabled & s->is_fiq); 101 qemu_set_irq(s->irq, s->pending & s->enabled & ~s->is_fiq); 102 } 103 104 static void strongarm_pic_set_irq(void *opaque, int irq, int level) 105 { 106 StrongARMPICState *s = opaque; 107 108 if (level) { 109 s->pending |= 1 << irq; 110 } else { 111 s->pending &= ~(1 << irq); 112 } 113 114 strongarm_pic_update(s); 115 } 116 117 static uint64_t strongarm_pic_mem_read(void *opaque, hwaddr offset, 118 unsigned size) 119 { 120 StrongARMPICState *s = opaque; 121 122 switch (offset) { 123 case ICIP: 124 return s->pending & ~s->is_fiq & s->enabled; 125 case ICMR: 126 return s->enabled; 127 case ICLR: 128 return s->is_fiq; 129 case ICCR: 130 return s->int_idle == 0; 131 case ICFP: 132 return s->pending & s->is_fiq & s->enabled; 133 case ICPR: 134 return s->pending; 135 default: 136 printf("%s: Bad register offset 0x" TARGET_FMT_plx "\n", 137 __func__, offset); 138 return 0; 139 } 140 } 141 142 static void strongarm_pic_mem_write(void *opaque, hwaddr offset, 143 uint64_t value, unsigned size) 144 { 145 StrongARMPICState *s = opaque; 146 147 switch (offset) { 148 case ICMR: 149 s->enabled = value; 150 break; 151 case ICLR: 152 s->is_fiq = value; 153 break; 154 case ICCR: 155 s->int_idle = (value & 1) ? 0 : ~0; 156 break; 157 default: 158 printf("%s: Bad register offset 0x" TARGET_FMT_plx "\n", 159 __func__, offset); 160 break; 161 } 162 strongarm_pic_update(s); 163 } 164 165 static const MemoryRegionOps strongarm_pic_ops = { 166 .read = strongarm_pic_mem_read, 167 .write = strongarm_pic_mem_write, 168 .endianness = DEVICE_NATIVE_ENDIAN, 169 }; 170 171 static int strongarm_pic_initfn(SysBusDevice *dev) 172 { 173 StrongARMPICState *s = FROM_SYSBUS(StrongARMPICState, dev); 174 175 qdev_init_gpio_in(&dev->qdev, strongarm_pic_set_irq, SA_PIC_SRCS); 176 memory_region_init_io(&s->iomem, &strongarm_pic_ops, s, "pic", 0x1000); 177 sysbus_init_mmio(dev, &s->iomem); 178 sysbus_init_irq(dev, &s->irq); 179 sysbus_init_irq(dev, &s->fiq); 180 181 return 0; 182 } 183 184 static int strongarm_pic_post_load(void *opaque, int version_id) 185 { 186 strongarm_pic_update(opaque); 187 return 0; 188 } 189 190 static VMStateDescription vmstate_strongarm_pic_regs = { 191 .name = "strongarm_pic", 192 .version_id = 0, 193 .minimum_version_id = 0, 194 .minimum_version_id_old = 0, 195 .post_load = strongarm_pic_post_load, 196 .fields = (VMStateField[]) { 197 VMSTATE_UINT32(pending, StrongARMPICState), 198 VMSTATE_UINT32(enabled, StrongARMPICState), 199 VMSTATE_UINT32(is_fiq, StrongARMPICState), 200 VMSTATE_UINT32(int_idle, StrongARMPICState), 201 VMSTATE_END_OF_LIST(), 202 }, 203 }; 204 205 static void strongarm_pic_class_init(ObjectClass *klass, void *data) 206 { 207 DeviceClass *dc = DEVICE_CLASS(klass); 208 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 209 210 k->init = strongarm_pic_initfn; 211 dc->desc = "StrongARM PIC"; 212 dc->vmsd = &vmstate_strongarm_pic_regs; 213 } 214 215 static const TypeInfo strongarm_pic_info = { 216 .name = "strongarm_pic", 217 .parent = TYPE_SYS_BUS_DEVICE, 218 .instance_size = sizeof(StrongARMPICState), 219 .class_init = strongarm_pic_class_init, 220 }; 221 222 /* Real-Time Clock */ 223 #define RTAR 0x00 /* RTC Alarm register */ 224 #define RCNR 0x04 /* RTC Counter register */ 225 #define RTTR 0x08 /* RTC Timer Trim register */ 226 #define RTSR 0x10 /* RTC Status register */ 227 228 #define RTSR_AL (1 << 0) /* RTC Alarm detected */ 229 #define RTSR_HZ (1 << 1) /* RTC 1Hz detected */ 230 #define RTSR_ALE (1 << 2) /* RTC Alarm enable */ 231 #define RTSR_HZE (1 << 3) /* RTC 1Hz enable */ 232 233 /* 16 LSB of RTTR are clockdiv for internal trim logic, 234 * trim delete isn't emulated, so 235 * f = 32 768 / (RTTR_trim + 1) */ 236 237 typedef struct { 238 SysBusDevice busdev; 239 MemoryRegion iomem; 240 uint32_t rttr; 241 uint32_t rtsr; 242 uint32_t rtar; 243 uint32_t last_rcnr; 244 int64_t last_hz; 245 QEMUTimer *rtc_alarm; 246 QEMUTimer *rtc_hz; 247 qemu_irq rtc_irq; 248 qemu_irq rtc_hz_irq; 249 } StrongARMRTCState; 250 251 static inline void strongarm_rtc_int_update(StrongARMRTCState *s) 252 { 253 qemu_set_irq(s->rtc_irq, s->rtsr & RTSR_AL); 254 qemu_set_irq(s->rtc_hz_irq, s->rtsr & RTSR_HZ); 255 } 256 257 static void strongarm_rtc_hzupdate(StrongARMRTCState *s) 258 { 259 int64_t rt = qemu_get_clock_ms(rtc_clock); 260 s->last_rcnr += ((rt - s->last_hz) << 15) / 261 (1000 * ((s->rttr & 0xffff) + 1)); 262 s->last_hz = rt; 263 } 264 265 static inline void strongarm_rtc_timer_update(StrongARMRTCState *s) 266 { 267 if ((s->rtsr & RTSR_HZE) && !(s->rtsr & RTSR_HZ)) { 268 qemu_mod_timer(s->rtc_hz, s->last_hz + 1000); 269 } else { 270 qemu_del_timer(s->rtc_hz); 271 } 272 273 if ((s->rtsr & RTSR_ALE) && !(s->rtsr & RTSR_AL)) { 274 qemu_mod_timer(s->rtc_alarm, s->last_hz + 275 (((s->rtar - s->last_rcnr) * 1000 * 276 ((s->rttr & 0xffff) + 1)) >> 15)); 277 } else { 278 qemu_del_timer(s->rtc_alarm); 279 } 280 } 281 282 static inline void strongarm_rtc_alarm_tick(void *opaque) 283 { 284 StrongARMRTCState *s = opaque; 285 s->rtsr |= RTSR_AL; 286 strongarm_rtc_timer_update(s); 287 strongarm_rtc_int_update(s); 288 } 289 290 static inline void strongarm_rtc_hz_tick(void *opaque) 291 { 292 StrongARMRTCState *s = opaque; 293 s->rtsr |= RTSR_HZ; 294 strongarm_rtc_timer_update(s); 295 strongarm_rtc_int_update(s); 296 } 297 298 static uint64_t strongarm_rtc_read(void *opaque, hwaddr addr, 299 unsigned size) 300 { 301 StrongARMRTCState *s = opaque; 302 303 switch (addr) { 304 case RTTR: 305 return s->rttr; 306 case RTSR: 307 return s->rtsr; 308 case RTAR: 309 return s->rtar; 310 case RCNR: 311 return s->last_rcnr + 312 ((qemu_get_clock_ms(rtc_clock) - s->last_hz) << 15) / 313 (1000 * ((s->rttr & 0xffff) + 1)); 314 default: 315 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr); 316 return 0; 317 } 318 } 319 320 static void strongarm_rtc_write(void *opaque, hwaddr addr, 321 uint64_t value, unsigned size) 322 { 323 StrongARMRTCState *s = opaque; 324 uint32_t old_rtsr; 325 326 switch (addr) { 327 case RTTR: 328 strongarm_rtc_hzupdate(s); 329 s->rttr = value; 330 strongarm_rtc_timer_update(s); 331 break; 332 333 case RTSR: 334 old_rtsr = s->rtsr; 335 s->rtsr = (value & (RTSR_ALE | RTSR_HZE)) | 336 (s->rtsr & ~(value & (RTSR_AL | RTSR_HZ))); 337 338 if (s->rtsr != old_rtsr) { 339 strongarm_rtc_timer_update(s); 340 } 341 342 strongarm_rtc_int_update(s); 343 break; 344 345 case RTAR: 346 s->rtar = value; 347 strongarm_rtc_timer_update(s); 348 break; 349 350 case RCNR: 351 strongarm_rtc_hzupdate(s); 352 s->last_rcnr = value; 353 strongarm_rtc_timer_update(s); 354 break; 355 356 default: 357 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr); 358 } 359 } 360 361 static const MemoryRegionOps strongarm_rtc_ops = { 362 .read = strongarm_rtc_read, 363 .write = strongarm_rtc_write, 364 .endianness = DEVICE_NATIVE_ENDIAN, 365 }; 366 367 static int strongarm_rtc_init(SysBusDevice *dev) 368 { 369 StrongARMRTCState *s = FROM_SYSBUS(StrongARMRTCState, dev); 370 struct tm tm; 371 372 s->rttr = 0x0; 373 s->rtsr = 0; 374 375 qemu_get_timedate(&tm, 0); 376 377 s->last_rcnr = (uint32_t) mktimegm(&tm); 378 s->last_hz = qemu_get_clock_ms(rtc_clock); 379 380 s->rtc_alarm = qemu_new_timer_ms(rtc_clock, strongarm_rtc_alarm_tick, s); 381 s->rtc_hz = qemu_new_timer_ms(rtc_clock, strongarm_rtc_hz_tick, s); 382 383 sysbus_init_irq(dev, &s->rtc_irq); 384 sysbus_init_irq(dev, &s->rtc_hz_irq); 385 386 memory_region_init_io(&s->iomem, &strongarm_rtc_ops, s, "rtc", 0x10000); 387 sysbus_init_mmio(dev, &s->iomem); 388 389 return 0; 390 } 391 392 static void strongarm_rtc_pre_save(void *opaque) 393 { 394 StrongARMRTCState *s = opaque; 395 396 strongarm_rtc_hzupdate(s); 397 } 398 399 static int strongarm_rtc_post_load(void *opaque, int version_id) 400 { 401 StrongARMRTCState *s = opaque; 402 403 strongarm_rtc_timer_update(s); 404 strongarm_rtc_int_update(s); 405 406 return 0; 407 } 408 409 static const VMStateDescription vmstate_strongarm_rtc_regs = { 410 .name = "strongarm-rtc", 411 .version_id = 0, 412 .minimum_version_id = 0, 413 .minimum_version_id_old = 0, 414 .pre_save = strongarm_rtc_pre_save, 415 .post_load = strongarm_rtc_post_load, 416 .fields = (VMStateField[]) { 417 VMSTATE_UINT32(rttr, StrongARMRTCState), 418 VMSTATE_UINT32(rtsr, StrongARMRTCState), 419 VMSTATE_UINT32(rtar, StrongARMRTCState), 420 VMSTATE_UINT32(last_rcnr, StrongARMRTCState), 421 VMSTATE_INT64(last_hz, StrongARMRTCState), 422 VMSTATE_END_OF_LIST(), 423 }, 424 }; 425 426 static void strongarm_rtc_sysbus_class_init(ObjectClass *klass, void *data) 427 { 428 DeviceClass *dc = DEVICE_CLASS(klass); 429 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 430 431 k->init = strongarm_rtc_init; 432 dc->desc = "StrongARM RTC Controller"; 433 dc->vmsd = &vmstate_strongarm_rtc_regs; 434 } 435 436 static const TypeInfo strongarm_rtc_sysbus_info = { 437 .name = "strongarm-rtc", 438 .parent = TYPE_SYS_BUS_DEVICE, 439 .instance_size = sizeof(StrongARMRTCState), 440 .class_init = strongarm_rtc_sysbus_class_init, 441 }; 442 443 /* GPIO */ 444 #define GPLR 0x00 445 #define GPDR 0x04 446 #define GPSR 0x08 447 #define GPCR 0x0c 448 #define GRER 0x10 449 #define GFER 0x14 450 #define GEDR 0x18 451 #define GAFR 0x1c 452 453 typedef struct StrongARMGPIOInfo StrongARMGPIOInfo; 454 struct StrongARMGPIOInfo { 455 SysBusDevice busdev; 456 MemoryRegion iomem; 457 qemu_irq handler[28]; 458 qemu_irq irqs[11]; 459 qemu_irq irqX; 460 461 uint32_t ilevel; 462 uint32_t olevel; 463 uint32_t dir; 464 uint32_t rising; 465 uint32_t falling; 466 uint32_t status; 467 uint32_t gpsr; 468 uint32_t gafr; 469 470 uint32_t prev_level; 471 }; 472 473 474 static void strongarm_gpio_irq_update(StrongARMGPIOInfo *s) 475 { 476 int i; 477 for (i = 0; i < 11; i++) { 478 qemu_set_irq(s->irqs[i], s->status & (1 << i)); 479 } 480 481 qemu_set_irq(s->irqX, (s->status & ~0x7ff)); 482 } 483 484 static void strongarm_gpio_set(void *opaque, int line, int level) 485 { 486 StrongARMGPIOInfo *s = opaque; 487 uint32_t mask; 488 489 mask = 1 << line; 490 491 if (level) { 492 s->status |= s->rising & mask & 493 ~s->ilevel & ~s->dir; 494 s->ilevel |= mask; 495 } else { 496 s->status |= s->falling & mask & 497 s->ilevel & ~s->dir; 498 s->ilevel &= ~mask; 499 } 500 501 if (s->status & mask) { 502 strongarm_gpio_irq_update(s); 503 } 504 } 505 506 static void strongarm_gpio_handler_update(StrongARMGPIOInfo *s) 507 { 508 uint32_t level, diff; 509 int bit; 510 511 level = s->olevel & s->dir; 512 513 for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) { 514 bit = ffs(diff) - 1; 515 qemu_set_irq(s->handler[bit], (level >> bit) & 1); 516 } 517 518 s->prev_level = level; 519 } 520 521 static uint64_t strongarm_gpio_read(void *opaque, hwaddr offset, 522 unsigned size) 523 { 524 StrongARMGPIOInfo *s = opaque; 525 526 switch (offset) { 527 case GPDR: /* GPIO Pin-Direction registers */ 528 return s->dir; 529 530 case GPSR: /* GPIO Pin-Output Set registers */ 531 DPRINTF("%s: Read from a write-only register 0x" TARGET_FMT_plx "\n", 532 __func__, offset); 533 return s->gpsr; /* Return last written value. */ 534 535 case GPCR: /* GPIO Pin-Output Clear registers */ 536 DPRINTF("%s: Read from a write-only register 0x" TARGET_FMT_plx "\n", 537 __func__, offset); 538 return 31337; /* Specified as unpredictable in the docs. */ 539 540 case GRER: /* GPIO Rising-Edge Detect Enable registers */ 541 return s->rising; 542 543 case GFER: /* GPIO Falling-Edge Detect Enable registers */ 544 return s->falling; 545 546 case GAFR: /* GPIO Alternate Function registers */ 547 return s->gafr; 548 549 case GPLR: /* GPIO Pin-Level registers */ 550 return (s->olevel & s->dir) | 551 (s->ilevel & ~s->dir); 552 553 case GEDR: /* GPIO Edge Detect Status registers */ 554 return s->status; 555 556 default: 557 printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset); 558 } 559 560 return 0; 561 } 562 563 static void strongarm_gpio_write(void *opaque, hwaddr offset, 564 uint64_t value, unsigned size) 565 { 566 StrongARMGPIOInfo *s = opaque; 567 568 switch (offset) { 569 case GPDR: /* GPIO Pin-Direction registers */ 570 s->dir = value; 571 strongarm_gpio_handler_update(s); 572 break; 573 574 case GPSR: /* GPIO Pin-Output Set registers */ 575 s->olevel |= value; 576 strongarm_gpio_handler_update(s); 577 s->gpsr = value; 578 break; 579 580 case GPCR: /* GPIO Pin-Output Clear registers */ 581 s->olevel &= ~value; 582 strongarm_gpio_handler_update(s); 583 break; 584 585 case GRER: /* GPIO Rising-Edge Detect Enable registers */ 586 s->rising = value; 587 break; 588 589 case GFER: /* GPIO Falling-Edge Detect Enable registers */ 590 s->falling = value; 591 break; 592 593 case GAFR: /* GPIO Alternate Function registers */ 594 s->gafr = value; 595 break; 596 597 case GEDR: /* GPIO Edge Detect Status registers */ 598 s->status &= ~value; 599 strongarm_gpio_irq_update(s); 600 break; 601 602 default: 603 printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset); 604 } 605 } 606 607 static const MemoryRegionOps strongarm_gpio_ops = { 608 .read = strongarm_gpio_read, 609 .write = strongarm_gpio_write, 610 .endianness = DEVICE_NATIVE_ENDIAN, 611 }; 612 613 static DeviceState *strongarm_gpio_init(hwaddr base, 614 DeviceState *pic) 615 { 616 DeviceState *dev; 617 int i; 618 619 dev = qdev_create(NULL, "strongarm-gpio"); 620 qdev_init_nofail(dev); 621 622 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 623 for (i = 0; i < 12; i++) 624 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 625 qdev_get_gpio_in(pic, SA_PIC_GPIO0_EDGE + i)); 626 627 return dev; 628 } 629 630 static int strongarm_gpio_initfn(SysBusDevice *dev) 631 { 632 StrongARMGPIOInfo *s; 633 int i; 634 635 s = FROM_SYSBUS(StrongARMGPIOInfo, dev); 636 637 qdev_init_gpio_in(&dev->qdev, strongarm_gpio_set, 28); 638 qdev_init_gpio_out(&dev->qdev, s->handler, 28); 639 640 memory_region_init_io(&s->iomem, &strongarm_gpio_ops, s, "gpio", 0x1000); 641 642 sysbus_init_mmio(dev, &s->iomem); 643 for (i = 0; i < 11; i++) { 644 sysbus_init_irq(dev, &s->irqs[i]); 645 } 646 sysbus_init_irq(dev, &s->irqX); 647 648 return 0; 649 } 650 651 static const VMStateDescription vmstate_strongarm_gpio_regs = { 652 .name = "strongarm-gpio", 653 .version_id = 0, 654 .minimum_version_id = 0, 655 .minimum_version_id_old = 0, 656 .fields = (VMStateField[]) { 657 VMSTATE_UINT32(ilevel, StrongARMGPIOInfo), 658 VMSTATE_UINT32(olevel, StrongARMGPIOInfo), 659 VMSTATE_UINT32(dir, StrongARMGPIOInfo), 660 VMSTATE_UINT32(rising, StrongARMGPIOInfo), 661 VMSTATE_UINT32(falling, StrongARMGPIOInfo), 662 VMSTATE_UINT32(status, StrongARMGPIOInfo), 663 VMSTATE_UINT32(gafr, StrongARMGPIOInfo), 664 VMSTATE_END_OF_LIST(), 665 }, 666 }; 667 668 static void strongarm_gpio_class_init(ObjectClass *klass, void *data) 669 { 670 DeviceClass *dc = DEVICE_CLASS(klass); 671 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 672 673 k->init = strongarm_gpio_initfn; 674 dc->desc = "StrongARM GPIO controller"; 675 } 676 677 static const TypeInfo strongarm_gpio_info = { 678 .name = "strongarm-gpio", 679 .parent = TYPE_SYS_BUS_DEVICE, 680 .instance_size = sizeof(StrongARMGPIOInfo), 681 .class_init = strongarm_gpio_class_init, 682 }; 683 684 /* Peripheral Pin Controller */ 685 #define PPDR 0x00 686 #define PPSR 0x04 687 #define PPAR 0x08 688 #define PSDR 0x0c 689 #define PPFR 0x10 690 691 typedef struct StrongARMPPCInfo StrongARMPPCInfo; 692 struct StrongARMPPCInfo { 693 SysBusDevice busdev; 694 MemoryRegion iomem; 695 qemu_irq handler[28]; 696 697 uint32_t ilevel; 698 uint32_t olevel; 699 uint32_t dir; 700 uint32_t ppar; 701 uint32_t psdr; 702 uint32_t ppfr; 703 704 uint32_t prev_level; 705 }; 706 707 static void strongarm_ppc_set(void *opaque, int line, int level) 708 { 709 StrongARMPPCInfo *s = opaque; 710 711 if (level) { 712 s->ilevel |= 1 << line; 713 } else { 714 s->ilevel &= ~(1 << line); 715 } 716 } 717 718 static void strongarm_ppc_handler_update(StrongARMPPCInfo *s) 719 { 720 uint32_t level, diff; 721 int bit; 722 723 level = s->olevel & s->dir; 724 725 for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) { 726 bit = ffs(diff) - 1; 727 qemu_set_irq(s->handler[bit], (level >> bit) & 1); 728 } 729 730 s->prev_level = level; 731 } 732 733 static uint64_t strongarm_ppc_read(void *opaque, hwaddr offset, 734 unsigned size) 735 { 736 StrongARMPPCInfo *s = opaque; 737 738 switch (offset) { 739 case PPDR: /* PPC Pin Direction registers */ 740 return s->dir | ~0x3fffff; 741 742 case PPSR: /* PPC Pin State registers */ 743 return (s->olevel & s->dir) | 744 (s->ilevel & ~s->dir) | 745 ~0x3fffff; 746 747 case PPAR: 748 return s->ppar | ~0x41000; 749 750 case PSDR: 751 return s->psdr; 752 753 case PPFR: 754 return s->ppfr | ~0x7f001; 755 756 default: 757 printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset); 758 } 759 760 return 0; 761 } 762 763 static void strongarm_ppc_write(void *opaque, hwaddr offset, 764 uint64_t value, unsigned size) 765 { 766 StrongARMPPCInfo *s = opaque; 767 768 switch (offset) { 769 case PPDR: /* PPC Pin Direction registers */ 770 s->dir = value & 0x3fffff; 771 strongarm_ppc_handler_update(s); 772 break; 773 774 case PPSR: /* PPC Pin State registers */ 775 s->olevel = value & s->dir & 0x3fffff; 776 strongarm_ppc_handler_update(s); 777 break; 778 779 case PPAR: 780 s->ppar = value & 0x41000; 781 break; 782 783 case PSDR: 784 s->psdr = value & 0x3fffff; 785 break; 786 787 case PPFR: 788 s->ppfr = value & 0x7f001; 789 break; 790 791 default: 792 printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset); 793 } 794 } 795 796 static const MemoryRegionOps strongarm_ppc_ops = { 797 .read = strongarm_ppc_read, 798 .write = strongarm_ppc_write, 799 .endianness = DEVICE_NATIVE_ENDIAN, 800 }; 801 802 static int strongarm_ppc_init(SysBusDevice *dev) 803 { 804 StrongARMPPCInfo *s; 805 806 s = FROM_SYSBUS(StrongARMPPCInfo, dev); 807 808 qdev_init_gpio_in(&dev->qdev, strongarm_ppc_set, 22); 809 qdev_init_gpio_out(&dev->qdev, s->handler, 22); 810 811 memory_region_init_io(&s->iomem, &strongarm_ppc_ops, s, "ppc", 0x1000); 812 813 sysbus_init_mmio(dev, &s->iomem); 814 815 return 0; 816 } 817 818 static const VMStateDescription vmstate_strongarm_ppc_regs = { 819 .name = "strongarm-ppc", 820 .version_id = 0, 821 .minimum_version_id = 0, 822 .minimum_version_id_old = 0, 823 .fields = (VMStateField[]) { 824 VMSTATE_UINT32(ilevel, StrongARMPPCInfo), 825 VMSTATE_UINT32(olevel, StrongARMPPCInfo), 826 VMSTATE_UINT32(dir, StrongARMPPCInfo), 827 VMSTATE_UINT32(ppar, StrongARMPPCInfo), 828 VMSTATE_UINT32(psdr, StrongARMPPCInfo), 829 VMSTATE_UINT32(ppfr, StrongARMPPCInfo), 830 VMSTATE_END_OF_LIST(), 831 }, 832 }; 833 834 static void strongarm_ppc_class_init(ObjectClass *klass, void *data) 835 { 836 DeviceClass *dc = DEVICE_CLASS(klass); 837 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 838 839 k->init = strongarm_ppc_init; 840 dc->desc = "StrongARM PPC controller"; 841 } 842 843 static const TypeInfo strongarm_ppc_info = { 844 .name = "strongarm-ppc", 845 .parent = TYPE_SYS_BUS_DEVICE, 846 .instance_size = sizeof(StrongARMPPCInfo), 847 .class_init = strongarm_ppc_class_init, 848 }; 849 850 /* UART Ports */ 851 #define UTCR0 0x00 852 #define UTCR1 0x04 853 #define UTCR2 0x08 854 #define UTCR3 0x0c 855 #define UTDR 0x14 856 #define UTSR0 0x1c 857 #define UTSR1 0x20 858 859 #define UTCR0_PE (1 << 0) /* Parity enable */ 860 #define UTCR0_OES (1 << 1) /* Even parity */ 861 #define UTCR0_SBS (1 << 2) /* 2 stop bits */ 862 #define UTCR0_DSS (1 << 3) /* 8-bit data */ 863 864 #define UTCR3_RXE (1 << 0) /* Rx enable */ 865 #define UTCR3_TXE (1 << 1) /* Tx enable */ 866 #define UTCR3_BRK (1 << 2) /* Force Break */ 867 #define UTCR3_RIE (1 << 3) /* Rx int enable */ 868 #define UTCR3_TIE (1 << 4) /* Tx int enable */ 869 #define UTCR3_LBM (1 << 5) /* Loopback */ 870 871 #define UTSR0_TFS (1 << 0) /* Tx FIFO nearly empty */ 872 #define UTSR0_RFS (1 << 1) /* Rx FIFO nearly full */ 873 #define UTSR0_RID (1 << 2) /* Receiver Idle */ 874 #define UTSR0_RBB (1 << 3) /* Receiver begin break */ 875 #define UTSR0_REB (1 << 4) /* Receiver end break */ 876 #define UTSR0_EIF (1 << 5) /* Error in FIFO */ 877 878 #define UTSR1_RNE (1 << 1) /* Receive FIFO not empty */ 879 #define UTSR1_TNF (1 << 2) /* Transmit FIFO not full */ 880 #define UTSR1_PRE (1 << 3) /* Parity error */ 881 #define UTSR1_FRE (1 << 4) /* Frame error */ 882 #define UTSR1_ROR (1 << 5) /* Receive Over Run */ 883 884 #define RX_FIFO_PRE (1 << 8) 885 #define RX_FIFO_FRE (1 << 9) 886 #define RX_FIFO_ROR (1 << 10) 887 888 typedef struct { 889 SysBusDevice busdev; 890 MemoryRegion iomem; 891 CharDriverState *chr; 892 qemu_irq irq; 893 894 uint8_t utcr0; 895 uint16_t brd; 896 uint8_t utcr3; 897 uint8_t utsr0; 898 uint8_t utsr1; 899 900 uint8_t tx_fifo[8]; 901 uint8_t tx_start; 902 uint8_t tx_len; 903 uint16_t rx_fifo[12]; /* value + error flags in high bits */ 904 uint8_t rx_start; 905 uint8_t rx_len; 906 907 uint64_t char_transmit_time; /* time to transmit a char in ticks*/ 908 bool wait_break_end; 909 QEMUTimer *rx_timeout_timer; 910 QEMUTimer *tx_timer; 911 } StrongARMUARTState; 912 913 static void strongarm_uart_update_status(StrongARMUARTState *s) 914 { 915 uint16_t utsr1 = 0; 916 917 if (s->tx_len != 8) { 918 utsr1 |= UTSR1_TNF; 919 } 920 921 if (s->rx_len != 0) { 922 uint16_t ent = s->rx_fifo[s->rx_start]; 923 924 utsr1 |= UTSR1_RNE; 925 if (ent & RX_FIFO_PRE) { 926 s->utsr1 |= UTSR1_PRE; 927 } 928 if (ent & RX_FIFO_FRE) { 929 s->utsr1 |= UTSR1_FRE; 930 } 931 if (ent & RX_FIFO_ROR) { 932 s->utsr1 |= UTSR1_ROR; 933 } 934 } 935 936 s->utsr1 = utsr1; 937 } 938 939 static void strongarm_uart_update_int_status(StrongARMUARTState *s) 940 { 941 uint16_t utsr0 = s->utsr0 & 942 (UTSR0_REB | UTSR0_RBB | UTSR0_RID); 943 int i; 944 945 if ((s->utcr3 & UTCR3_TXE) && 946 (s->utcr3 & UTCR3_TIE) && 947 s->tx_len <= 4) { 948 utsr0 |= UTSR0_TFS; 949 } 950 951 if ((s->utcr3 & UTCR3_RXE) && 952 (s->utcr3 & UTCR3_RIE) && 953 s->rx_len > 4) { 954 utsr0 |= UTSR0_RFS; 955 } 956 957 for (i = 0; i < s->rx_len && i < 4; i++) 958 if (s->rx_fifo[(s->rx_start + i) % 12] & ~0xff) { 959 utsr0 |= UTSR0_EIF; 960 break; 961 } 962 963 s->utsr0 = utsr0; 964 qemu_set_irq(s->irq, utsr0); 965 } 966 967 static void strongarm_uart_update_parameters(StrongARMUARTState *s) 968 { 969 int speed, parity, data_bits, stop_bits, frame_size; 970 QEMUSerialSetParams ssp; 971 972 /* Start bit. */ 973 frame_size = 1; 974 if (s->utcr0 & UTCR0_PE) { 975 /* Parity bit. */ 976 frame_size++; 977 if (s->utcr0 & UTCR0_OES) { 978 parity = 'E'; 979 } else { 980 parity = 'O'; 981 } 982 } else { 983 parity = 'N'; 984 } 985 if (s->utcr0 & UTCR0_SBS) { 986 stop_bits = 2; 987 } else { 988 stop_bits = 1; 989 } 990 991 data_bits = (s->utcr0 & UTCR0_DSS) ? 8 : 7; 992 frame_size += data_bits + stop_bits; 993 speed = 3686400 / 16 / (s->brd + 1); 994 ssp.speed = speed; 995 ssp.parity = parity; 996 ssp.data_bits = data_bits; 997 ssp.stop_bits = stop_bits; 998 s->char_transmit_time = (get_ticks_per_sec() / speed) * frame_size; 999 if (s->chr) { 1000 qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); 1001 } 1002 1003 DPRINTF(stderr, "%s speed=%d parity=%c data=%d stop=%d\n", s->chr->label, 1004 speed, parity, data_bits, stop_bits); 1005 } 1006 1007 static void strongarm_uart_rx_to(void *opaque) 1008 { 1009 StrongARMUARTState *s = opaque; 1010 1011 if (s->rx_len) { 1012 s->utsr0 |= UTSR0_RID; 1013 strongarm_uart_update_int_status(s); 1014 } 1015 } 1016 1017 static void strongarm_uart_rx_push(StrongARMUARTState *s, uint16_t c) 1018 { 1019 if ((s->utcr3 & UTCR3_RXE) == 0) { 1020 /* rx disabled */ 1021 return; 1022 } 1023 1024 if (s->wait_break_end) { 1025 s->utsr0 |= UTSR0_REB; 1026 s->wait_break_end = false; 1027 } 1028 1029 if (s->rx_len < 12) { 1030 s->rx_fifo[(s->rx_start + s->rx_len) % 12] = c; 1031 s->rx_len++; 1032 } else 1033 s->rx_fifo[(s->rx_start + 11) % 12] |= RX_FIFO_ROR; 1034 } 1035 1036 static int strongarm_uart_can_receive(void *opaque) 1037 { 1038 StrongARMUARTState *s = opaque; 1039 1040 if (s->rx_len == 12) { 1041 return 0; 1042 } 1043 /* It's best not to get more than 2/3 of RX FIFO, so advertise that much */ 1044 if (s->rx_len < 8) { 1045 return 8 - s->rx_len; 1046 } 1047 return 1; 1048 } 1049 1050 static void strongarm_uart_receive(void *opaque, const uint8_t *buf, int size) 1051 { 1052 StrongARMUARTState *s = opaque; 1053 int i; 1054 1055 for (i = 0; i < size; i++) { 1056 strongarm_uart_rx_push(s, buf[i]); 1057 } 1058 1059 /* call the timeout receive callback in 3 char transmit time */ 1060 qemu_mod_timer(s->rx_timeout_timer, 1061 qemu_get_clock_ns(vm_clock) + s->char_transmit_time * 3); 1062 1063 strongarm_uart_update_status(s); 1064 strongarm_uart_update_int_status(s); 1065 } 1066 1067 static void strongarm_uart_event(void *opaque, int event) 1068 { 1069 StrongARMUARTState *s = opaque; 1070 if (event == CHR_EVENT_BREAK) { 1071 s->utsr0 |= UTSR0_RBB; 1072 strongarm_uart_rx_push(s, RX_FIFO_FRE); 1073 s->wait_break_end = true; 1074 strongarm_uart_update_status(s); 1075 strongarm_uart_update_int_status(s); 1076 } 1077 } 1078 1079 static void strongarm_uart_tx(void *opaque) 1080 { 1081 StrongARMUARTState *s = opaque; 1082 uint64_t new_xmit_ts = qemu_get_clock_ns(vm_clock); 1083 1084 if (s->utcr3 & UTCR3_LBM) /* loopback */ { 1085 strongarm_uart_receive(s, &s->tx_fifo[s->tx_start], 1); 1086 } else if (s->chr) { 1087 qemu_chr_fe_write(s->chr, &s->tx_fifo[s->tx_start], 1); 1088 } 1089 1090 s->tx_start = (s->tx_start + 1) % 8; 1091 s->tx_len--; 1092 if (s->tx_len) { 1093 qemu_mod_timer(s->tx_timer, new_xmit_ts + s->char_transmit_time); 1094 } 1095 strongarm_uart_update_status(s); 1096 strongarm_uart_update_int_status(s); 1097 } 1098 1099 static uint64_t strongarm_uart_read(void *opaque, hwaddr addr, 1100 unsigned size) 1101 { 1102 StrongARMUARTState *s = opaque; 1103 uint16_t ret; 1104 1105 switch (addr) { 1106 case UTCR0: 1107 return s->utcr0; 1108 1109 case UTCR1: 1110 return s->brd >> 8; 1111 1112 case UTCR2: 1113 return s->brd & 0xff; 1114 1115 case UTCR3: 1116 return s->utcr3; 1117 1118 case UTDR: 1119 if (s->rx_len != 0) { 1120 ret = s->rx_fifo[s->rx_start]; 1121 s->rx_start = (s->rx_start + 1) % 12; 1122 s->rx_len--; 1123 strongarm_uart_update_status(s); 1124 strongarm_uart_update_int_status(s); 1125 return ret; 1126 } 1127 return 0; 1128 1129 case UTSR0: 1130 return s->utsr0; 1131 1132 case UTSR1: 1133 return s->utsr1; 1134 1135 default: 1136 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr); 1137 return 0; 1138 } 1139 } 1140 1141 static void strongarm_uart_write(void *opaque, hwaddr addr, 1142 uint64_t value, unsigned size) 1143 { 1144 StrongARMUARTState *s = opaque; 1145 1146 switch (addr) { 1147 case UTCR0: 1148 s->utcr0 = value & 0x7f; 1149 strongarm_uart_update_parameters(s); 1150 break; 1151 1152 case UTCR1: 1153 s->brd = (s->brd & 0xff) | ((value & 0xf) << 8); 1154 strongarm_uart_update_parameters(s); 1155 break; 1156 1157 case UTCR2: 1158 s->brd = (s->brd & 0xf00) | (value & 0xff); 1159 strongarm_uart_update_parameters(s); 1160 break; 1161 1162 case UTCR3: 1163 s->utcr3 = value & 0x3f; 1164 if ((s->utcr3 & UTCR3_RXE) == 0) { 1165 s->rx_len = 0; 1166 } 1167 if ((s->utcr3 & UTCR3_TXE) == 0) { 1168 s->tx_len = 0; 1169 } 1170 strongarm_uart_update_status(s); 1171 strongarm_uart_update_int_status(s); 1172 break; 1173 1174 case UTDR: 1175 if ((s->utcr3 & UTCR3_TXE) && s->tx_len != 8) { 1176 s->tx_fifo[(s->tx_start + s->tx_len) % 8] = value; 1177 s->tx_len++; 1178 strongarm_uart_update_status(s); 1179 strongarm_uart_update_int_status(s); 1180 if (s->tx_len == 1) { 1181 strongarm_uart_tx(s); 1182 } 1183 } 1184 break; 1185 1186 case UTSR0: 1187 s->utsr0 = s->utsr0 & ~(value & 1188 (UTSR0_REB | UTSR0_RBB | UTSR0_RID)); 1189 strongarm_uart_update_int_status(s); 1190 break; 1191 1192 default: 1193 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr); 1194 } 1195 } 1196 1197 static const MemoryRegionOps strongarm_uart_ops = { 1198 .read = strongarm_uart_read, 1199 .write = strongarm_uart_write, 1200 .endianness = DEVICE_NATIVE_ENDIAN, 1201 }; 1202 1203 static int strongarm_uart_init(SysBusDevice *dev) 1204 { 1205 StrongARMUARTState *s = FROM_SYSBUS(StrongARMUARTState, dev); 1206 1207 memory_region_init_io(&s->iomem, &strongarm_uart_ops, s, "uart", 0x10000); 1208 sysbus_init_mmio(dev, &s->iomem); 1209 sysbus_init_irq(dev, &s->irq); 1210 1211 s->rx_timeout_timer = qemu_new_timer_ns(vm_clock, strongarm_uart_rx_to, s); 1212 s->tx_timer = qemu_new_timer_ns(vm_clock, strongarm_uart_tx, s); 1213 1214 if (s->chr) { 1215 qemu_chr_add_handlers(s->chr, 1216 strongarm_uart_can_receive, 1217 strongarm_uart_receive, 1218 strongarm_uart_event, 1219 s); 1220 } 1221 1222 return 0; 1223 } 1224 1225 static void strongarm_uart_reset(DeviceState *dev) 1226 { 1227 StrongARMUARTState *s = DO_UPCAST(StrongARMUARTState, busdev.qdev, dev); 1228 1229 s->utcr0 = UTCR0_DSS; /* 8 data, no parity */ 1230 s->brd = 23; /* 9600 */ 1231 /* enable send & recv - this actually violates spec */ 1232 s->utcr3 = UTCR3_TXE | UTCR3_RXE; 1233 1234 s->rx_len = s->tx_len = 0; 1235 1236 strongarm_uart_update_parameters(s); 1237 strongarm_uart_update_status(s); 1238 strongarm_uart_update_int_status(s); 1239 } 1240 1241 static int strongarm_uart_post_load(void *opaque, int version_id) 1242 { 1243 StrongARMUARTState *s = opaque; 1244 1245 strongarm_uart_update_parameters(s); 1246 strongarm_uart_update_status(s); 1247 strongarm_uart_update_int_status(s); 1248 1249 /* tx and restart timer */ 1250 if (s->tx_len) { 1251 strongarm_uart_tx(s); 1252 } 1253 1254 /* restart rx timeout timer */ 1255 if (s->rx_len) { 1256 qemu_mod_timer(s->rx_timeout_timer, 1257 qemu_get_clock_ns(vm_clock) + s->char_transmit_time * 3); 1258 } 1259 1260 return 0; 1261 } 1262 1263 static const VMStateDescription vmstate_strongarm_uart_regs = { 1264 .name = "strongarm-uart", 1265 .version_id = 0, 1266 .minimum_version_id = 0, 1267 .minimum_version_id_old = 0, 1268 .post_load = strongarm_uart_post_load, 1269 .fields = (VMStateField[]) { 1270 VMSTATE_UINT8(utcr0, StrongARMUARTState), 1271 VMSTATE_UINT16(brd, StrongARMUARTState), 1272 VMSTATE_UINT8(utcr3, StrongARMUARTState), 1273 VMSTATE_UINT8(utsr0, StrongARMUARTState), 1274 VMSTATE_UINT8_ARRAY(tx_fifo, StrongARMUARTState, 8), 1275 VMSTATE_UINT8(tx_start, StrongARMUARTState), 1276 VMSTATE_UINT8(tx_len, StrongARMUARTState), 1277 VMSTATE_UINT16_ARRAY(rx_fifo, StrongARMUARTState, 12), 1278 VMSTATE_UINT8(rx_start, StrongARMUARTState), 1279 VMSTATE_UINT8(rx_len, StrongARMUARTState), 1280 VMSTATE_BOOL(wait_break_end, StrongARMUARTState), 1281 VMSTATE_END_OF_LIST(), 1282 }, 1283 }; 1284 1285 static Property strongarm_uart_properties[] = { 1286 DEFINE_PROP_CHR("chardev", StrongARMUARTState, chr), 1287 DEFINE_PROP_END_OF_LIST(), 1288 }; 1289 1290 static void strongarm_uart_class_init(ObjectClass *klass, void *data) 1291 { 1292 DeviceClass *dc = DEVICE_CLASS(klass); 1293 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 1294 1295 k->init = strongarm_uart_init; 1296 dc->desc = "StrongARM UART controller"; 1297 dc->reset = strongarm_uart_reset; 1298 dc->vmsd = &vmstate_strongarm_uart_regs; 1299 dc->props = strongarm_uart_properties; 1300 } 1301 1302 static const TypeInfo strongarm_uart_info = { 1303 .name = "strongarm-uart", 1304 .parent = TYPE_SYS_BUS_DEVICE, 1305 .instance_size = sizeof(StrongARMUARTState), 1306 .class_init = strongarm_uart_class_init, 1307 }; 1308 1309 /* Synchronous Serial Ports */ 1310 typedef struct { 1311 SysBusDevice busdev; 1312 MemoryRegion iomem; 1313 qemu_irq irq; 1314 SSIBus *bus; 1315 1316 uint16_t sscr[2]; 1317 uint16_t sssr; 1318 1319 uint16_t rx_fifo[8]; 1320 uint8_t rx_level; 1321 uint8_t rx_start; 1322 } StrongARMSSPState; 1323 1324 #define SSCR0 0x60 /* SSP Control register 0 */ 1325 #define SSCR1 0x64 /* SSP Control register 1 */ 1326 #define SSDR 0x6c /* SSP Data register */ 1327 #define SSSR 0x74 /* SSP Status register */ 1328 1329 /* Bitfields for above registers */ 1330 #define SSCR0_SPI(x) (((x) & 0x30) == 0x00) 1331 #define SSCR0_SSP(x) (((x) & 0x30) == 0x10) 1332 #define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20) 1333 #define SSCR0_PSP(x) (((x) & 0x30) == 0x30) 1334 #define SSCR0_SSE (1 << 7) 1335 #define SSCR0_DSS(x) (((x) & 0xf) + 1) 1336 #define SSCR1_RIE (1 << 0) 1337 #define SSCR1_TIE (1 << 1) 1338 #define SSCR1_LBM (1 << 2) 1339 #define SSSR_TNF (1 << 2) 1340 #define SSSR_RNE (1 << 3) 1341 #define SSSR_TFS (1 << 5) 1342 #define SSSR_RFS (1 << 6) 1343 #define SSSR_ROR (1 << 7) 1344 #define SSSR_RW 0x0080 1345 1346 static void strongarm_ssp_int_update(StrongARMSSPState *s) 1347 { 1348 int level = 0; 1349 1350 level |= (s->sssr & SSSR_ROR); 1351 level |= (s->sssr & SSSR_RFS) && (s->sscr[1] & SSCR1_RIE); 1352 level |= (s->sssr & SSSR_TFS) && (s->sscr[1] & SSCR1_TIE); 1353 qemu_set_irq(s->irq, level); 1354 } 1355 1356 static void strongarm_ssp_fifo_update(StrongARMSSPState *s) 1357 { 1358 s->sssr &= ~SSSR_TFS; 1359 s->sssr &= ~SSSR_TNF; 1360 if (s->sscr[0] & SSCR0_SSE) { 1361 if (s->rx_level >= 4) { 1362 s->sssr |= SSSR_RFS; 1363 } else { 1364 s->sssr &= ~SSSR_RFS; 1365 } 1366 if (s->rx_level) { 1367 s->sssr |= SSSR_RNE; 1368 } else { 1369 s->sssr &= ~SSSR_RNE; 1370 } 1371 /* TX FIFO is never filled, so it is always in underrun 1372 condition if SSP is enabled */ 1373 s->sssr |= SSSR_TFS; 1374 s->sssr |= SSSR_TNF; 1375 } 1376 1377 strongarm_ssp_int_update(s); 1378 } 1379 1380 static uint64_t strongarm_ssp_read(void *opaque, hwaddr addr, 1381 unsigned size) 1382 { 1383 StrongARMSSPState *s = opaque; 1384 uint32_t retval; 1385 1386 switch (addr) { 1387 case SSCR0: 1388 return s->sscr[0]; 1389 case SSCR1: 1390 return s->sscr[1]; 1391 case SSSR: 1392 return s->sssr; 1393 case SSDR: 1394 if (~s->sscr[0] & SSCR0_SSE) { 1395 return 0xffffffff; 1396 } 1397 if (s->rx_level < 1) { 1398 printf("%s: SSP Rx Underrun\n", __func__); 1399 return 0xffffffff; 1400 } 1401 s->rx_level--; 1402 retval = s->rx_fifo[s->rx_start++]; 1403 s->rx_start &= 0x7; 1404 strongarm_ssp_fifo_update(s); 1405 return retval; 1406 default: 1407 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr); 1408 break; 1409 } 1410 return 0; 1411 } 1412 1413 static void strongarm_ssp_write(void *opaque, hwaddr addr, 1414 uint64_t value, unsigned size) 1415 { 1416 StrongARMSSPState *s = opaque; 1417 1418 switch (addr) { 1419 case SSCR0: 1420 s->sscr[0] = value & 0xffbf; 1421 if ((s->sscr[0] & SSCR0_SSE) && SSCR0_DSS(value) < 4) { 1422 printf("%s: Wrong data size: %i bits\n", __func__, 1423 (int)SSCR0_DSS(value)); 1424 } 1425 if (!(value & SSCR0_SSE)) { 1426 s->sssr = 0; 1427 s->rx_level = 0; 1428 } 1429 strongarm_ssp_fifo_update(s); 1430 break; 1431 1432 case SSCR1: 1433 s->sscr[1] = value & 0x2f; 1434 if (value & SSCR1_LBM) { 1435 printf("%s: Attempt to use SSP LBM mode\n", __func__); 1436 } 1437 strongarm_ssp_fifo_update(s); 1438 break; 1439 1440 case SSSR: 1441 s->sssr &= ~(value & SSSR_RW); 1442 strongarm_ssp_int_update(s); 1443 break; 1444 1445 case SSDR: 1446 if (SSCR0_UWIRE(s->sscr[0])) { 1447 value &= 0xff; 1448 } else 1449 /* Note how 32bits overflow does no harm here */ 1450 value &= (1 << SSCR0_DSS(s->sscr[0])) - 1; 1451 1452 /* Data goes from here to the Tx FIFO and is shifted out from 1453 * there directly to the slave, no need to buffer it. 1454 */ 1455 if (s->sscr[0] & SSCR0_SSE) { 1456 uint32_t readval; 1457 if (s->sscr[1] & SSCR1_LBM) { 1458 readval = value; 1459 } else { 1460 readval = ssi_transfer(s->bus, value); 1461 } 1462 1463 if (s->rx_level < 0x08) { 1464 s->rx_fifo[(s->rx_start + s->rx_level++) & 0x7] = readval; 1465 } else { 1466 s->sssr |= SSSR_ROR; 1467 } 1468 } 1469 strongarm_ssp_fifo_update(s); 1470 break; 1471 1472 default: 1473 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr); 1474 break; 1475 } 1476 } 1477 1478 static const MemoryRegionOps strongarm_ssp_ops = { 1479 .read = strongarm_ssp_read, 1480 .write = strongarm_ssp_write, 1481 .endianness = DEVICE_NATIVE_ENDIAN, 1482 }; 1483 1484 static int strongarm_ssp_post_load(void *opaque, int version_id) 1485 { 1486 StrongARMSSPState *s = opaque; 1487 1488 strongarm_ssp_fifo_update(s); 1489 1490 return 0; 1491 } 1492 1493 static int strongarm_ssp_init(SysBusDevice *dev) 1494 { 1495 StrongARMSSPState *s = FROM_SYSBUS(StrongARMSSPState, dev); 1496 1497 sysbus_init_irq(dev, &s->irq); 1498 1499 memory_region_init_io(&s->iomem, &strongarm_ssp_ops, s, "ssp", 0x1000); 1500 sysbus_init_mmio(dev, &s->iomem); 1501 1502 s->bus = ssi_create_bus(&dev->qdev, "ssi"); 1503 return 0; 1504 } 1505 1506 static void strongarm_ssp_reset(DeviceState *dev) 1507 { 1508 StrongARMSSPState *s = DO_UPCAST(StrongARMSSPState, busdev.qdev, dev); 1509 s->sssr = 0x03; /* 3 bit data, SPI, disabled */ 1510 s->rx_start = 0; 1511 s->rx_level = 0; 1512 } 1513 1514 static const VMStateDescription vmstate_strongarm_ssp_regs = { 1515 .name = "strongarm-ssp", 1516 .version_id = 0, 1517 .minimum_version_id = 0, 1518 .minimum_version_id_old = 0, 1519 .post_load = strongarm_ssp_post_load, 1520 .fields = (VMStateField[]) { 1521 VMSTATE_UINT16_ARRAY(sscr, StrongARMSSPState, 2), 1522 VMSTATE_UINT16(sssr, StrongARMSSPState), 1523 VMSTATE_UINT16_ARRAY(rx_fifo, StrongARMSSPState, 8), 1524 VMSTATE_UINT8(rx_start, StrongARMSSPState), 1525 VMSTATE_UINT8(rx_level, StrongARMSSPState), 1526 VMSTATE_END_OF_LIST(), 1527 }, 1528 }; 1529 1530 static void strongarm_ssp_class_init(ObjectClass *klass, void *data) 1531 { 1532 DeviceClass *dc = DEVICE_CLASS(klass); 1533 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 1534 1535 k->init = strongarm_ssp_init; 1536 dc->desc = "StrongARM SSP controller"; 1537 dc->reset = strongarm_ssp_reset; 1538 dc->vmsd = &vmstate_strongarm_ssp_regs; 1539 } 1540 1541 static const TypeInfo strongarm_ssp_info = { 1542 .name = "strongarm-ssp", 1543 .parent = TYPE_SYS_BUS_DEVICE, 1544 .instance_size = sizeof(StrongARMSSPState), 1545 .class_init = strongarm_ssp_class_init, 1546 }; 1547 1548 /* Main CPU functions */ 1549 StrongARMState *sa1110_init(MemoryRegion *sysmem, 1550 unsigned int sdram_size, const char *rev) 1551 { 1552 StrongARMState *s; 1553 qemu_irq *pic; 1554 int i; 1555 1556 s = g_malloc0(sizeof(StrongARMState)); 1557 1558 if (!rev) { 1559 rev = "sa1110-b5"; 1560 } 1561 1562 if (strncmp(rev, "sa1110", 6)) { 1563 error_report("Machine requires a SA1110 processor."); 1564 exit(1); 1565 } 1566 1567 s->cpu = cpu_arm_init(rev); 1568 1569 if (!s->cpu) { 1570 error_report("Unable to find CPU definition"); 1571 exit(1); 1572 } 1573 1574 memory_region_init_ram(&s->sdram, "strongarm.sdram", sdram_size); 1575 vmstate_register_ram_global(&s->sdram); 1576 memory_region_add_subregion(sysmem, SA_SDCS0, &s->sdram); 1577 1578 pic = arm_pic_init_cpu(s->cpu); 1579 s->pic = sysbus_create_varargs("strongarm_pic", 0x90050000, 1580 pic[ARM_PIC_CPU_IRQ], pic[ARM_PIC_CPU_FIQ], NULL); 1581 1582 sysbus_create_varargs("pxa25x-timer", 0x90000000, 1583 qdev_get_gpio_in(s->pic, SA_PIC_OSTC0), 1584 qdev_get_gpio_in(s->pic, SA_PIC_OSTC1), 1585 qdev_get_gpio_in(s->pic, SA_PIC_OSTC2), 1586 qdev_get_gpio_in(s->pic, SA_PIC_OSTC3), 1587 NULL); 1588 1589 sysbus_create_simple("strongarm-rtc", 0x90010000, 1590 qdev_get_gpio_in(s->pic, SA_PIC_RTC_ALARM)); 1591 1592 s->gpio = strongarm_gpio_init(0x90040000, s->pic); 1593 1594 s->ppc = sysbus_create_varargs("strongarm-ppc", 0x90060000, NULL); 1595 1596 for (i = 0; sa_serial[i].io_base; i++) { 1597 DeviceState *dev = qdev_create(NULL, "strongarm-uart"); 1598 qdev_prop_set_chr(dev, "chardev", serial_hds[i]); 1599 qdev_init_nofail(dev); 1600 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 1601 sa_serial[i].io_base); 1602 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, 1603 qdev_get_gpio_in(s->pic, sa_serial[i].irq)); 1604 } 1605 1606 s->ssp = sysbus_create_varargs("strongarm-ssp", 0x80070000, 1607 qdev_get_gpio_in(s->pic, SA_PIC_SSP), NULL); 1608 s->ssp_bus = (SSIBus *)qdev_get_child_bus(s->ssp, "ssi"); 1609 1610 return s; 1611 } 1612 1613 static void strongarm_register_types(void) 1614 { 1615 type_register_static(&strongarm_pic_info); 1616 type_register_static(&strongarm_rtc_sysbus_info); 1617 type_register_static(&strongarm_gpio_info); 1618 type_register_static(&strongarm_ppc_info); 1619 type_register_static(&strongarm_uart_info); 1620 type_register_static(&strongarm_ssp_info); 1621 } 1622 1623 type_init(strongarm_register_types) 1624