1 /* 2 * StrongARM SA-1100/SA-1110 emulation 3 * 4 * Copyright (C) 2011 Dmitry Eremin-Solenikov 5 * 6 * Largely based on StrongARM emulation: 7 * Copyright (c) 2006 Openedhand Ltd. 8 * Written by Andrzej Zaborowski <balrog@zabor.org> 9 * 10 * UART code based on QEMU 16550A UART emulation 11 * Copyright (c) 2003-2004 Fabrice Bellard 12 * Copyright (c) 2008 Citrix Systems, Inc. 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License version 2 as 16 * published by the Free Software Foundation. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License along 24 * with this program; if not, see <http://www.gnu.org/licenses/>. 25 * 26 * Contributions after 2012-01-13 are licensed under the terms of the 27 * GNU GPL, version 2 or (at your option) any later version. 28 */ 29 30 #include "qemu/osdep.h" 31 #include "qemu-common.h" 32 #include "cpu.h" 33 #include "hw/boards.h" 34 #include "hw/irq.h" 35 #include "hw/sysbus.h" 36 #include "migration/vmstate.h" 37 #include "strongarm.h" 38 #include "qemu/error-report.h" 39 #include "hw/arm/boot.h" 40 #include "chardev/char-fe.h" 41 #include "chardev/char-serial.h" 42 #include "sysemu/sysemu.h" 43 #include "hw/ssi/ssi.h" 44 #include "qemu/cutils.h" 45 #include "qemu/log.h" 46 47 //#define DEBUG 48 49 /* 50 TODO 51 - Implement cp15, c14 ? 52 - Implement cp15, c15 !!! (idle used in L) 53 - Implement idle mode handling/DIM 54 - Implement sleep mode/Wake sources 55 - Implement reset control 56 - Implement memory control regs 57 - PCMCIA handling 58 - Maybe support MBGNT/MBREQ 59 - DMA channels 60 - GPCLK 61 - IrDA 62 - MCP 63 - Enhance UART with modem signals 64 */ 65 66 #ifdef DEBUG 67 # define DPRINTF(format, ...) printf(format , ## __VA_ARGS__) 68 #else 69 # define DPRINTF(format, ...) do { } while (0) 70 #endif 71 72 static struct { 73 hwaddr io_base; 74 int irq; 75 } sa_serial[] = { 76 { 0x80010000, SA_PIC_UART1 }, 77 { 0x80030000, SA_PIC_UART2 }, 78 { 0x80050000, SA_PIC_UART3 }, 79 { 0, 0 } 80 }; 81 82 /* Interrupt Controller */ 83 84 #define TYPE_STRONGARM_PIC "strongarm_pic" 85 #define STRONGARM_PIC(obj) \ 86 OBJECT_CHECK(StrongARMPICState, (obj), TYPE_STRONGARM_PIC) 87 88 typedef struct StrongARMPICState { 89 SysBusDevice parent_obj; 90 91 MemoryRegion iomem; 92 qemu_irq irq; 93 qemu_irq fiq; 94 95 uint32_t pending; 96 uint32_t enabled; 97 uint32_t is_fiq; 98 uint32_t int_idle; 99 } StrongARMPICState; 100 101 #define ICIP 0x00 102 #define ICMR 0x04 103 #define ICLR 0x08 104 #define ICFP 0x10 105 #define ICPR 0x20 106 #define ICCR 0x0c 107 108 #define SA_PIC_SRCS 32 109 110 111 static void strongarm_pic_update(void *opaque) 112 { 113 StrongARMPICState *s = opaque; 114 115 /* FIXME: reflect DIM */ 116 qemu_set_irq(s->fiq, s->pending & s->enabled & s->is_fiq); 117 qemu_set_irq(s->irq, s->pending & s->enabled & ~s->is_fiq); 118 } 119 120 static void strongarm_pic_set_irq(void *opaque, int irq, int level) 121 { 122 StrongARMPICState *s = opaque; 123 124 if (level) { 125 s->pending |= 1 << irq; 126 } else { 127 s->pending &= ~(1 << irq); 128 } 129 130 strongarm_pic_update(s); 131 } 132 133 static uint64_t strongarm_pic_mem_read(void *opaque, hwaddr offset, 134 unsigned size) 135 { 136 StrongARMPICState *s = opaque; 137 138 switch (offset) { 139 case ICIP: 140 return s->pending & ~s->is_fiq & s->enabled; 141 case ICMR: 142 return s->enabled; 143 case ICLR: 144 return s->is_fiq; 145 case ICCR: 146 return s->int_idle == 0; 147 case ICFP: 148 return s->pending & s->is_fiq & s->enabled; 149 case ICPR: 150 return s->pending; 151 default: 152 printf("%s: Bad register offset 0x" TARGET_FMT_plx "\n", 153 __func__, offset); 154 return 0; 155 } 156 } 157 158 static void strongarm_pic_mem_write(void *opaque, hwaddr offset, 159 uint64_t value, unsigned size) 160 { 161 StrongARMPICState *s = opaque; 162 163 switch (offset) { 164 case ICMR: 165 s->enabled = value; 166 break; 167 case ICLR: 168 s->is_fiq = value; 169 break; 170 case ICCR: 171 s->int_idle = (value & 1) ? 0 : ~0; 172 break; 173 default: 174 printf("%s: Bad register offset 0x" TARGET_FMT_plx "\n", 175 __func__, offset); 176 break; 177 } 178 strongarm_pic_update(s); 179 } 180 181 static const MemoryRegionOps strongarm_pic_ops = { 182 .read = strongarm_pic_mem_read, 183 .write = strongarm_pic_mem_write, 184 .endianness = DEVICE_NATIVE_ENDIAN, 185 }; 186 187 static void strongarm_pic_initfn(Object *obj) 188 { 189 DeviceState *dev = DEVICE(obj); 190 StrongARMPICState *s = STRONGARM_PIC(obj); 191 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 192 193 qdev_init_gpio_in(dev, strongarm_pic_set_irq, SA_PIC_SRCS); 194 memory_region_init_io(&s->iomem, obj, &strongarm_pic_ops, s, 195 "pic", 0x1000); 196 sysbus_init_mmio(sbd, &s->iomem); 197 sysbus_init_irq(sbd, &s->irq); 198 sysbus_init_irq(sbd, &s->fiq); 199 } 200 201 static int strongarm_pic_post_load(void *opaque, int version_id) 202 { 203 strongarm_pic_update(opaque); 204 return 0; 205 } 206 207 static VMStateDescription vmstate_strongarm_pic_regs = { 208 .name = "strongarm_pic", 209 .version_id = 0, 210 .minimum_version_id = 0, 211 .post_load = strongarm_pic_post_load, 212 .fields = (VMStateField[]) { 213 VMSTATE_UINT32(pending, StrongARMPICState), 214 VMSTATE_UINT32(enabled, StrongARMPICState), 215 VMSTATE_UINT32(is_fiq, StrongARMPICState), 216 VMSTATE_UINT32(int_idle, StrongARMPICState), 217 VMSTATE_END_OF_LIST(), 218 }, 219 }; 220 221 static void strongarm_pic_class_init(ObjectClass *klass, void *data) 222 { 223 DeviceClass *dc = DEVICE_CLASS(klass); 224 225 dc->desc = "StrongARM PIC"; 226 dc->vmsd = &vmstate_strongarm_pic_regs; 227 } 228 229 static const TypeInfo strongarm_pic_info = { 230 .name = TYPE_STRONGARM_PIC, 231 .parent = TYPE_SYS_BUS_DEVICE, 232 .instance_size = sizeof(StrongARMPICState), 233 .instance_init = strongarm_pic_initfn, 234 .class_init = strongarm_pic_class_init, 235 }; 236 237 /* Real-Time Clock */ 238 #define RTAR 0x00 /* RTC Alarm register */ 239 #define RCNR 0x04 /* RTC Counter register */ 240 #define RTTR 0x08 /* RTC Timer Trim register */ 241 #define RTSR 0x10 /* RTC Status register */ 242 243 #define RTSR_AL (1 << 0) /* RTC Alarm detected */ 244 #define RTSR_HZ (1 << 1) /* RTC 1Hz detected */ 245 #define RTSR_ALE (1 << 2) /* RTC Alarm enable */ 246 #define RTSR_HZE (1 << 3) /* RTC 1Hz enable */ 247 248 /* 16 LSB of RTTR are clockdiv for internal trim logic, 249 * trim delete isn't emulated, so 250 * f = 32 768 / (RTTR_trim + 1) */ 251 252 #define TYPE_STRONGARM_RTC "strongarm-rtc" 253 #define STRONGARM_RTC(obj) \ 254 OBJECT_CHECK(StrongARMRTCState, (obj), TYPE_STRONGARM_RTC) 255 256 typedef struct StrongARMRTCState { 257 SysBusDevice parent_obj; 258 259 MemoryRegion iomem; 260 uint32_t rttr; 261 uint32_t rtsr; 262 uint32_t rtar; 263 uint32_t last_rcnr; 264 int64_t last_hz; 265 QEMUTimer *rtc_alarm; 266 QEMUTimer *rtc_hz; 267 qemu_irq rtc_irq; 268 qemu_irq rtc_hz_irq; 269 } StrongARMRTCState; 270 271 static inline void strongarm_rtc_int_update(StrongARMRTCState *s) 272 { 273 qemu_set_irq(s->rtc_irq, s->rtsr & RTSR_AL); 274 qemu_set_irq(s->rtc_hz_irq, s->rtsr & RTSR_HZ); 275 } 276 277 static void strongarm_rtc_hzupdate(StrongARMRTCState *s) 278 { 279 int64_t rt = qemu_clock_get_ms(rtc_clock); 280 s->last_rcnr += ((rt - s->last_hz) << 15) / 281 (1000 * ((s->rttr & 0xffff) + 1)); 282 s->last_hz = rt; 283 } 284 285 static inline void strongarm_rtc_timer_update(StrongARMRTCState *s) 286 { 287 if ((s->rtsr & RTSR_HZE) && !(s->rtsr & RTSR_HZ)) { 288 timer_mod(s->rtc_hz, s->last_hz + 1000); 289 } else { 290 timer_del(s->rtc_hz); 291 } 292 293 if ((s->rtsr & RTSR_ALE) && !(s->rtsr & RTSR_AL)) { 294 timer_mod(s->rtc_alarm, s->last_hz + 295 (((s->rtar - s->last_rcnr) * 1000 * 296 ((s->rttr & 0xffff) + 1)) >> 15)); 297 } else { 298 timer_del(s->rtc_alarm); 299 } 300 } 301 302 static inline void strongarm_rtc_alarm_tick(void *opaque) 303 { 304 StrongARMRTCState *s = opaque; 305 s->rtsr |= RTSR_AL; 306 strongarm_rtc_timer_update(s); 307 strongarm_rtc_int_update(s); 308 } 309 310 static inline void strongarm_rtc_hz_tick(void *opaque) 311 { 312 StrongARMRTCState *s = opaque; 313 s->rtsr |= RTSR_HZ; 314 strongarm_rtc_timer_update(s); 315 strongarm_rtc_int_update(s); 316 } 317 318 static uint64_t strongarm_rtc_read(void *opaque, hwaddr addr, 319 unsigned size) 320 { 321 StrongARMRTCState *s = opaque; 322 323 switch (addr) { 324 case RTTR: 325 return s->rttr; 326 case RTSR: 327 return s->rtsr; 328 case RTAR: 329 return s->rtar; 330 case RCNR: 331 return s->last_rcnr + 332 ((qemu_clock_get_ms(rtc_clock) - s->last_hz) << 15) / 333 (1000 * ((s->rttr & 0xffff) + 1)); 334 default: 335 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr); 336 return 0; 337 } 338 } 339 340 static void strongarm_rtc_write(void *opaque, hwaddr addr, 341 uint64_t value, unsigned size) 342 { 343 StrongARMRTCState *s = opaque; 344 uint32_t old_rtsr; 345 346 switch (addr) { 347 case RTTR: 348 strongarm_rtc_hzupdate(s); 349 s->rttr = value; 350 strongarm_rtc_timer_update(s); 351 break; 352 353 case RTSR: 354 old_rtsr = s->rtsr; 355 s->rtsr = (value & (RTSR_ALE | RTSR_HZE)) | 356 (s->rtsr & ~(value & (RTSR_AL | RTSR_HZ))); 357 358 if (s->rtsr != old_rtsr) { 359 strongarm_rtc_timer_update(s); 360 } 361 362 strongarm_rtc_int_update(s); 363 break; 364 365 case RTAR: 366 s->rtar = value; 367 strongarm_rtc_timer_update(s); 368 break; 369 370 case RCNR: 371 strongarm_rtc_hzupdate(s); 372 s->last_rcnr = value; 373 strongarm_rtc_timer_update(s); 374 break; 375 376 default: 377 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr); 378 } 379 } 380 381 static const MemoryRegionOps strongarm_rtc_ops = { 382 .read = strongarm_rtc_read, 383 .write = strongarm_rtc_write, 384 .endianness = DEVICE_NATIVE_ENDIAN, 385 }; 386 387 static void strongarm_rtc_init(Object *obj) 388 { 389 StrongARMRTCState *s = STRONGARM_RTC(obj); 390 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 391 struct tm tm; 392 393 s->rttr = 0x0; 394 s->rtsr = 0; 395 396 qemu_get_timedate(&tm, 0); 397 398 s->last_rcnr = (uint32_t) mktimegm(&tm); 399 s->last_hz = qemu_clock_get_ms(rtc_clock); 400 401 s->rtc_alarm = timer_new_ms(rtc_clock, strongarm_rtc_alarm_tick, s); 402 s->rtc_hz = timer_new_ms(rtc_clock, strongarm_rtc_hz_tick, s); 403 404 sysbus_init_irq(dev, &s->rtc_irq); 405 sysbus_init_irq(dev, &s->rtc_hz_irq); 406 407 memory_region_init_io(&s->iomem, obj, &strongarm_rtc_ops, s, 408 "rtc", 0x10000); 409 sysbus_init_mmio(dev, &s->iomem); 410 } 411 412 static int strongarm_rtc_pre_save(void *opaque) 413 { 414 StrongARMRTCState *s = opaque; 415 416 strongarm_rtc_hzupdate(s); 417 418 return 0; 419 } 420 421 static int strongarm_rtc_post_load(void *opaque, int version_id) 422 { 423 StrongARMRTCState *s = opaque; 424 425 strongarm_rtc_timer_update(s); 426 strongarm_rtc_int_update(s); 427 428 return 0; 429 } 430 431 static const VMStateDescription vmstate_strongarm_rtc_regs = { 432 .name = "strongarm-rtc", 433 .version_id = 0, 434 .minimum_version_id = 0, 435 .pre_save = strongarm_rtc_pre_save, 436 .post_load = strongarm_rtc_post_load, 437 .fields = (VMStateField[]) { 438 VMSTATE_UINT32(rttr, StrongARMRTCState), 439 VMSTATE_UINT32(rtsr, StrongARMRTCState), 440 VMSTATE_UINT32(rtar, StrongARMRTCState), 441 VMSTATE_UINT32(last_rcnr, StrongARMRTCState), 442 VMSTATE_INT64(last_hz, StrongARMRTCState), 443 VMSTATE_END_OF_LIST(), 444 }, 445 }; 446 447 static void strongarm_rtc_sysbus_class_init(ObjectClass *klass, void *data) 448 { 449 DeviceClass *dc = DEVICE_CLASS(klass); 450 451 dc->desc = "StrongARM RTC Controller"; 452 dc->vmsd = &vmstate_strongarm_rtc_regs; 453 } 454 455 static const TypeInfo strongarm_rtc_sysbus_info = { 456 .name = TYPE_STRONGARM_RTC, 457 .parent = TYPE_SYS_BUS_DEVICE, 458 .instance_size = sizeof(StrongARMRTCState), 459 .instance_init = strongarm_rtc_init, 460 .class_init = strongarm_rtc_sysbus_class_init, 461 }; 462 463 /* GPIO */ 464 #define GPLR 0x00 465 #define GPDR 0x04 466 #define GPSR 0x08 467 #define GPCR 0x0c 468 #define GRER 0x10 469 #define GFER 0x14 470 #define GEDR 0x18 471 #define GAFR 0x1c 472 473 #define TYPE_STRONGARM_GPIO "strongarm-gpio" 474 #define STRONGARM_GPIO(obj) \ 475 OBJECT_CHECK(StrongARMGPIOInfo, (obj), TYPE_STRONGARM_GPIO) 476 477 typedef struct StrongARMGPIOInfo StrongARMGPIOInfo; 478 struct StrongARMGPIOInfo { 479 SysBusDevice busdev; 480 MemoryRegion iomem; 481 qemu_irq handler[28]; 482 qemu_irq irqs[11]; 483 qemu_irq irqX; 484 485 uint32_t ilevel; 486 uint32_t olevel; 487 uint32_t dir; 488 uint32_t rising; 489 uint32_t falling; 490 uint32_t status; 491 uint32_t gafr; 492 493 uint32_t prev_level; 494 }; 495 496 497 static void strongarm_gpio_irq_update(StrongARMGPIOInfo *s) 498 { 499 int i; 500 for (i = 0; i < 11; i++) { 501 qemu_set_irq(s->irqs[i], s->status & (1 << i)); 502 } 503 504 qemu_set_irq(s->irqX, (s->status & ~0x7ff)); 505 } 506 507 static void strongarm_gpio_set(void *opaque, int line, int level) 508 { 509 StrongARMGPIOInfo *s = opaque; 510 uint32_t mask; 511 512 mask = 1 << line; 513 514 if (level) { 515 s->status |= s->rising & mask & 516 ~s->ilevel & ~s->dir; 517 s->ilevel |= mask; 518 } else { 519 s->status |= s->falling & mask & 520 s->ilevel & ~s->dir; 521 s->ilevel &= ~mask; 522 } 523 524 if (s->status & mask) { 525 strongarm_gpio_irq_update(s); 526 } 527 } 528 529 static void strongarm_gpio_handler_update(StrongARMGPIOInfo *s) 530 { 531 uint32_t level, diff; 532 int bit; 533 534 level = s->olevel & s->dir; 535 536 for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) { 537 bit = ctz32(diff); 538 qemu_set_irq(s->handler[bit], (level >> bit) & 1); 539 } 540 541 s->prev_level = level; 542 } 543 544 static uint64_t strongarm_gpio_read(void *opaque, hwaddr offset, 545 unsigned size) 546 { 547 StrongARMGPIOInfo *s = opaque; 548 549 switch (offset) { 550 case GPDR: /* GPIO Pin-Direction registers */ 551 return s->dir; 552 553 case GPSR: /* GPIO Pin-Output Set registers */ 554 qemu_log_mask(LOG_GUEST_ERROR, 555 "strongarm GPIO: read from write only register GPSR\n"); 556 return 0; 557 558 case GPCR: /* GPIO Pin-Output Clear registers */ 559 qemu_log_mask(LOG_GUEST_ERROR, 560 "strongarm GPIO: read from write only register GPCR\n"); 561 return 0; 562 563 case GRER: /* GPIO Rising-Edge Detect Enable registers */ 564 return s->rising; 565 566 case GFER: /* GPIO Falling-Edge Detect Enable registers */ 567 return s->falling; 568 569 case GAFR: /* GPIO Alternate Function registers */ 570 return s->gafr; 571 572 case GPLR: /* GPIO Pin-Level registers */ 573 return (s->olevel & s->dir) | 574 (s->ilevel & ~s->dir); 575 576 case GEDR: /* GPIO Edge Detect Status registers */ 577 return s->status; 578 579 default: 580 printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset); 581 } 582 583 return 0; 584 } 585 586 static void strongarm_gpio_write(void *opaque, hwaddr offset, 587 uint64_t value, unsigned size) 588 { 589 StrongARMGPIOInfo *s = opaque; 590 591 switch (offset) { 592 case GPDR: /* GPIO Pin-Direction registers */ 593 s->dir = value & 0x0fffffff; 594 strongarm_gpio_handler_update(s); 595 break; 596 597 case GPSR: /* GPIO Pin-Output Set registers */ 598 s->olevel |= value & 0x0fffffff; 599 strongarm_gpio_handler_update(s); 600 break; 601 602 case GPCR: /* GPIO Pin-Output Clear registers */ 603 s->olevel &= ~value; 604 strongarm_gpio_handler_update(s); 605 break; 606 607 case GRER: /* GPIO Rising-Edge Detect Enable registers */ 608 s->rising = value; 609 break; 610 611 case GFER: /* GPIO Falling-Edge Detect Enable registers */ 612 s->falling = value; 613 break; 614 615 case GAFR: /* GPIO Alternate Function registers */ 616 s->gafr = value; 617 break; 618 619 case GEDR: /* GPIO Edge Detect Status registers */ 620 s->status &= ~value; 621 strongarm_gpio_irq_update(s); 622 break; 623 624 default: 625 printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset); 626 } 627 } 628 629 static const MemoryRegionOps strongarm_gpio_ops = { 630 .read = strongarm_gpio_read, 631 .write = strongarm_gpio_write, 632 .endianness = DEVICE_NATIVE_ENDIAN, 633 }; 634 635 static DeviceState *strongarm_gpio_init(hwaddr base, 636 DeviceState *pic) 637 { 638 DeviceState *dev; 639 int i; 640 641 dev = qdev_create(NULL, TYPE_STRONGARM_GPIO); 642 qdev_init_nofail(dev); 643 644 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 645 for (i = 0; i < 12; i++) 646 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 647 qdev_get_gpio_in(pic, SA_PIC_GPIO0_EDGE + i)); 648 649 return dev; 650 } 651 652 static void strongarm_gpio_initfn(Object *obj) 653 { 654 DeviceState *dev = DEVICE(obj); 655 StrongARMGPIOInfo *s = STRONGARM_GPIO(obj); 656 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 657 int i; 658 659 qdev_init_gpio_in(dev, strongarm_gpio_set, 28); 660 qdev_init_gpio_out(dev, s->handler, 28); 661 662 memory_region_init_io(&s->iomem, obj, &strongarm_gpio_ops, s, 663 "gpio", 0x1000); 664 665 sysbus_init_mmio(sbd, &s->iomem); 666 for (i = 0; i < 11; i++) { 667 sysbus_init_irq(sbd, &s->irqs[i]); 668 } 669 sysbus_init_irq(sbd, &s->irqX); 670 } 671 672 static const VMStateDescription vmstate_strongarm_gpio_regs = { 673 .name = "strongarm-gpio", 674 .version_id = 0, 675 .minimum_version_id = 0, 676 .fields = (VMStateField[]) { 677 VMSTATE_UINT32(ilevel, StrongARMGPIOInfo), 678 VMSTATE_UINT32(olevel, StrongARMGPIOInfo), 679 VMSTATE_UINT32(dir, StrongARMGPIOInfo), 680 VMSTATE_UINT32(rising, StrongARMGPIOInfo), 681 VMSTATE_UINT32(falling, StrongARMGPIOInfo), 682 VMSTATE_UINT32(status, StrongARMGPIOInfo), 683 VMSTATE_UINT32(gafr, StrongARMGPIOInfo), 684 VMSTATE_UINT32(prev_level, StrongARMGPIOInfo), 685 VMSTATE_END_OF_LIST(), 686 }, 687 }; 688 689 static void strongarm_gpio_class_init(ObjectClass *klass, void *data) 690 { 691 DeviceClass *dc = DEVICE_CLASS(klass); 692 693 dc->desc = "StrongARM GPIO controller"; 694 dc->vmsd = &vmstate_strongarm_gpio_regs; 695 } 696 697 static const TypeInfo strongarm_gpio_info = { 698 .name = TYPE_STRONGARM_GPIO, 699 .parent = TYPE_SYS_BUS_DEVICE, 700 .instance_size = sizeof(StrongARMGPIOInfo), 701 .instance_init = strongarm_gpio_initfn, 702 .class_init = strongarm_gpio_class_init, 703 }; 704 705 /* Peripheral Pin Controller */ 706 #define PPDR 0x00 707 #define PPSR 0x04 708 #define PPAR 0x08 709 #define PSDR 0x0c 710 #define PPFR 0x10 711 712 #define TYPE_STRONGARM_PPC "strongarm-ppc" 713 #define STRONGARM_PPC(obj) \ 714 OBJECT_CHECK(StrongARMPPCInfo, (obj), TYPE_STRONGARM_PPC) 715 716 typedef struct StrongARMPPCInfo StrongARMPPCInfo; 717 struct StrongARMPPCInfo { 718 SysBusDevice parent_obj; 719 720 MemoryRegion iomem; 721 qemu_irq handler[28]; 722 723 uint32_t ilevel; 724 uint32_t olevel; 725 uint32_t dir; 726 uint32_t ppar; 727 uint32_t psdr; 728 uint32_t ppfr; 729 730 uint32_t prev_level; 731 }; 732 733 static void strongarm_ppc_set(void *opaque, int line, int level) 734 { 735 StrongARMPPCInfo *s = opaque; 736 737 if (level) { 738 s->ilevel |= 1 << line; 739 } else { 740 s->ilevel &= ~(1 << line); 741 } 742 } 743 744 static void strongarm_ppc_handler_update(StrongARMPPCInfo *s) 745 { 746 uint32_t level, diff; 747 int bit; 748 749 level = s->olevel & s->dir; 750 751 for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) { 752 bit = ctz32(diff); 753 qemu_set_irq(s->handler[bit], (level >> bit) & 1); 754 } 755 756 s->prev_level = level; 757 } 758 759 static uint64_t strongarm_ppc_read(void *opaque, hwaddr offset, 760 unsigned size) 761 { 762 StrongARMPPCInfo *s = opaque; 763 764 switch (offset) { 765 case PPDR: /* PPC Pin Direction registers */ 766 return s->dir | ~0x3fffff; 767 768 case PPSR: /* PPC Pin State registers */ 769 return (s->olevel & s->dir) | 770 (s->ilevel & ~s->dir) | 771 ~0x3fffff; 772 773 case PPAR: 774 return s->ppar | ~0x41000; 775 776 case PSDR: 777 return s->psdr; 778 779 case PPFR: 780 return s->ppfr | ~0x7f001; 781 782 default: 783 printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset); 784 } 785 786 return 0; 787 } 788 789 static void strongarm_ppc_write(void *opaque, hwaddr offset, 790 uint64_t value, unsigned size) 791 { 792 StrongARMPPCInfo *s = opaque; 793 794 switch (offset) { 795 case PPDR: /* PPC Pin Direction registers */ 796 s->dir = value & 0x3fffff; 797 strongarm_ppc_handler_update(s); 798 break; 799 800 case PPSR: /* PPC Pin State registers */ 801 s->olevel = value & s->dir & 0x3fffff; 802 strongarm_ppc_handler_update(s); 803 break; 804 805 case PPAR: 806 s->ppar = value & 0x41000; 807 break; 808 809 case PSDR: 810 s->psdr = value & 0x3fffff; 811 break; 812 813 case PPFR: 814 s->ppfr = value & 0x7f001; 815 break; 816 817 default: 818 printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset); 819 } 820 } 821 822 static const MemoryRegionOps strongarm_ppc_ops = { 823 .read = strongarm_ppc_read, 824 .write = strongarm_ppc_write, 825 .endianness = DEVICE_NATIVE_ENDIAN, 826 }; 827 828 static void strongarm_ppc_init(Object *obj) 829 { 830 DeviceState *dev = DEVICE(obj); 831 StrongARMPPCInfo *s = STRONGARM_PPC(obj); 832 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 833 834 qdev_init_gpio_in(dev, strongarm_ppc_set, 22); 835 qdev_init_gpio_out(dev, s->handler, 22); 836 837 memory_region_init_io(&s->iomem, obj, &strongarm_ppc_ops, s, 838 "ppc", 0x1000); 839 840 sysbus_init_mmio(sbd, &s->iomem); 841 } 842 843 static const VMStateDescription vmstate_strongarm_ppc_regs = { 844 .name = "strongarm-ppc", 845 .version_id = 0, 846 .minimum_version_id = 0, 847 .fields = (VMStateField[]) { 848 VMSTATE_UINT32(ilevel, StrongARMPPCInfo), 849 VMSTATE_UINT32(olevel, StrongARMPPCInfo), 850 VMSTATE_UINT32(dir, StrongARMPPCInfo), 851 VMSTATE_UINT32(ppar, StrongARMPPCInfo), 852 VMSTATE_UINT32(psdr, StrongARMPPCInfo), 853 VMSTATE_UINT32(ppfr, StrongARMPPCInfo), 854 VMSTATE_UINT32(prev_level, StrongARMPPCInfo), 855 VMSTATE_END_OF_LIST(), 856 }, 857 }; 858 859 static void strongarm_ppc_class_init(ObjectClass *klass, void *data) 860 { 861 DeviceClass *dc = DEVICE_CLASS(klass); 862 863 dc->desc = "StrongARM PPC controller"; 864 dc->vmsd = &vmstate_strongarm_ppc_regs; 865 } 866 867 static const TypeInfo strongarm_ppc_info = { 868 .name = TYPE_STRONGARM_PPC, 869 .parent = TYPE_SYS_BUS_DEVICE, 870 .instance_size = sizeof(StrongARMPPCInfo), 871 .instance_init = strongarm_ppc_init, 872 .class_init = strongarm_ppc_class_init, 873 }; 874 875 /* UART Ports */ 876 #define UTCR0 0x00 877 #define UTCR1 0x04 878 #define UTCR2 0x08 879 #define UTCR3 0x0c 880 #define UTDR 0x14 881 #define UTSR0 0x1c 882 #define UTSR1 0x20 883 884 #define UTCR0_PE (1 << 0) /* Parity enable */ 885 #define UTCR0_OES (1 << 1) /* Even parity */ 886 #define UTCR0_SBS (1 << 2) /* 2 stop bits */ 887 #define UTCR0_DSS (1 << 3) /* 8-bit data */ 888 889 #define UTCR3_RXE (1 << 0) /* Rx enable */ 890 #define UTCR3_TXE (1 << 1) /* Tx enable */ 891 #define UTCR3_BRK (1 << 2) /* Force Break */ 892 #define UTCR3_RIE (1 << 3) /* Rx int enable */ 893 #define UTCR3_TIE (1 << 4) /* Tx int enable */ 894 #define UTCR3_LBM (1 << 5) /* Loopback */ 895 896 #define UTSR0_TFS (1 << 0) /* Tx FIFO nearly empty */ 897 #define UTSR0_RFS (1 << 1) /* Rx FIFO nearly full */ 898 #define UTSR0_RID (1 << 2) /* Receiver Idle */ 899 #define UTSR0_RBB (1 << 3) /* Receiver begin break */ 900 #define UTSR0_REB (1 << 4) /* Receiver end break */ 901 #define UTSR0_EIF (1 << 5) /* Error in FIFO */ 902 903 #define UTSR1_RNE (1 << 1) /* Receive FIFO not empty */ 904 #define UTSR1_TNF (1 << 2) /* Transmit FIFO not full */ 905 #define UTSR1_PRE (1 << 3) /* Parity error */ 906 #define UTSR1_FRE (1 << 4) /* Frame error */ 907 #define UTSR1_ROR (1 << 5) /* Receive Over Run */ 908 909 #define RX_FIFO_PRE (1 << 8) 910 #define RX_FIFO_FRE (1 << 9) 911 #define RX_FIFO_ROR (1 << 10) 912 913 #define TYPE_STRONGARM_UART "strongarm-uart" 914 #define STRONGARM_UART(obj) \ 915 OBJECT_CHECK(StrongARMUARTState, (obj), TYPE_STRONGARM_UART) 916 917 typedef struct StrongARMUARTState { 918 SysBusDevice parent_obj; 919 920 MemoryRegion iomem; 921 CharBackend chr; 922 qemu_irq irq; 923 924 uint8_t utcr0; 925 uint16_t brd; 926 uint8_t utcr3; 927 uint8_t utsr0; 928 uint8_t utsr1; 929 930 uint8_t tx_fifo[8]; 931 uint8_t tx_start; 932 uint8_t tx_len; 933 uint16_t rx_fifo[12]; /* value + error flags in high bits */ 934 uint8_t rx_start; 935 uint8_t rx_len; 936 937 uint64_t char_transmit_time; /* time to transmit a char in ticks*/ 938 bool wait_break_end; 939 QEMUTimer *rx_timeout_timer; 940 QEMUTimer *tx_timer; 941 } StrongARMUARTState; 942 943 static void strongarm_uart_update_status(StrongARMUARTState *s) 944 { 945 uint16_t utsr1 = 0; 946 947 if (s->tx_len != 8) { 948 utsr1 |= UTSR1_TNF; 949 } 950 951 if (s->rx_len != 0) { 952 uint16_t ent = s->rx_fifo[s->rx_start]; 953 954 utsr1 |= UTSR1_RNE; 955 if (ent & RX_FIFO_PRE) { 956 s->utsr1 |= UTSR1_PRE; 957 } 958 if (ent & RX_FIFO_FRE) { 959 s->utsr1 |= UTSR1_FRE; 960 } 961 if (ent & RX_FIFO_ROR) { 962 s->utsr1 |= UTSR1_ROR; 963 } 964 } 965 966 s->utsr1 = utsr1; 967 } 968 969 static void strongarm_uart_update_int_status(StrongARMUARTState *s) 970 { 971 uint16_t utsr0 = s->utsr0 & 972 (UTSR0_REB | UTSR0_RBB | UTSR0_RID); 973 int i; 974 975 if ((s->utcr3 & UTCR3_TXE) && 976 (s->utcr3 & UTCR3_TIE) && 977 s->tx_len <= 4) { 978 utsr0 |= UTSR0_TFS; 979 } 980 981 if ((s->utcr3 & UTCR3_RXE) && 982 (s->utcr3 & UTCR3_RIE) && 983 s->rx_len > 4) { 984 utsr0 |= UTSR0_RFS; 985 } 986 987 for (i = 0; i < s->rx_len && i < 4; i++) 988 if (s->rx_fifo[(s->rx_start + i) % 12] & ~0xff) { 989 utsr0 |= UTSR0_EIF; 990 break; 991 } 992 993 s->utsr0 = utsr0; 994 qemu_set_irq(s->irq, utsr0); 995 } 996 997 static void strongarm_uart_update_parameters(StrongARMUARTState *s) 998 { 999 int speed, parity, data_bits, stop_bits, frame_size; 1000 QEMUSerialSetParams ssp; 1001 1002 /* Start bit. */ 1003 frame_size = 1; 1004 if (s->utcr0 & UTCR0_PE) { 1005 /* Parity bit. */ 1006 frame_size++; 1007 if (s->utcr0 & UTCR0_OES) { 1008 parity = 'E'; 1009 } else { 1010 parity = 'O'; 1011 } 1012 } else { 1013 parity = 'N'; 1014 } 1015 if (s->utcr0 & UTCR0_SBS) { 1016 stop_bits = 2; 1017 } else { 1018 stop_bits = 1; 1019 } 1020 1021 data_bits = (s->utcr0 & UTCR0_DSS) ? 8 : 7; 1022 frame_size += data_bits + stop_bits; 1023 speed = 3686400 / 16 / (s->brd + 1); 1024 ssp.speed = speed; 1025 ssp.parity = parity; 1026 ssp.data_bits = data_bits; 1027 ssp.stop_bits = stop_bits; 1028 s->char_transmit_time = (NANOSECONDS_PER_SECOND / speed) * frame_size; 1029 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); 1030 1031 DPRINTF(stderr, "%s speed=%d parity=%c data=%d stop=%d\n", s->chr->label, 1032 speed, parity, data_bits, stop_bits); 1033 } 1034 1035 static void strongarm_uart_rx_to(void *opaque) 1036 { 1037 StrongARMUARTState *s = opaque; 1038 1039 if (s->rx_len) { 1040 s->utsr0 |= UTSR0_RID; 1041 strongarm_uart_update_int_status(s); 1042 } 1043 } 1044 1045 static void strongarm_uart_rx_push(StrongARMUARTState *s, uint16_t c) 1046 { 1047 if ((s->utcr3 & UTCR3_RXE) == 0) { 1048 /* rx disabled */ 1049 return; 1050 } 1051 1052 if (s->wait_break_end) { 1053 s->utsr0 |= UTSR0_REB; 1054 s->wait_break_end = false; 1055 } 1056 1057 if (s->rx_len < 12) { 1058 s->rx_fifo[(s->rx_start + s->rx_len) % 12] = c; 1059 s->rx_len++; 1060 } else 1061 s->rx_fifo[(s->rx_start + 11) % 12] |= RX_FIFO_ROR; 1062 } 1063 1064 static int strongarm_uart_can_receive(void *opaque) 1065 { 1066 StrongARMUARTState *s = opaque; 1067 1068 if (s->rx_len == 12) { 1069 return 0; 1070 } 1071 /* It's best not to get more than 2/3 of RX FIFO, so advertise that much */ 1072 if (s->rx_len < 8) { 1073 return 8 - s->rx_len; 1074 } 1075 return 1; 1076 } 1077 1078 static void strongarm_uart_receive(void *opaque, const uint8_t *buf, int size) 1079 { 1080 StrongARMUARTState *s = opaque; 1081 int i; 1082 1083 for (i = 0; i < size; i++) { 1084 strongarm_uart_rx_push(s, buf[i]); 1085 } 1086 1087 /* call the timeout receive callback in 3 char transmit time */ 1088 timer_mod(s->rx_timeout_timer, 1089 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 3); 1090 1091 strongarm_uart_update_status(s); 1092 strongarm_uart_update_int_status(s); 1093 } 1094 1095 static void strongarm_uart_event(void *opaque, int event) 1096 { 1097 StrongARMUARTState *s = opaque; 1098 if (event == CHR_EVENT_BREAK) { 1099 s->utsr0 |= UTSR0_RBB; 1100 strongarm_uart_rx_push(s, RX_FIFO_FRE); 1101 s->wait_break_end = true; 1102 strongarm_uart_update_status(s); 1103 strongarm_uart_update_int_status(s); 1104 } 1105 } 1106 1107 static void strongarm_uart_tx(void *opaque) 1108 { 1109 StrongARMUARTState *s = opaque; 1110 uint64_t new_xmit_ts = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 1111 1112 if (s->utcr3 & UTCR3_LBM) /* loopback */ { 1113 strongarm_uart_receive(s, &s->tx_fifo[s->tx_start], 1); 1114 } else if (qemu_chr_fe_backend_connected(&s->chr)) { 1115 /* XXX this blocks entire thread. Rewrite to use 1116 * qemu_chr_fe_write and background I/O callbacks */ 1117 qemu_chr_fe_write_all(&s->chr, &s->tx_fifo[s->tx_start], 1); 1118 } 1119 1120 s->tx_start = (s->tx_start + 1) % 8; 1121 s->tx_len--; 1122 if (s->tx_len) { 1123 timer_mod(s->tx_timer, new_xmit_ts + s->char_transmit_time); 1124 } 1125 strongarm_uart_update_status(s); 1126 strongarm_uart_update_int_status(s); 1127 } 1128 1129 static uint64_t strongarm_uart_read(void *opaque, hwaddr addr, 1130 unsigned size) 1131 { 1132 StrongARMUARTState *s = opaque; 1133 uint16_t ret; 1134 1135 switch (addr) { 1136 case UTCR0: 1137 return s->utcr0; 1138 1139 case UTCR1: 1140 return s->brd >> 8; 1141 1142 case UTCR2: 1143 return s->brd & 0xff; 1144 1145 case UTCR3: 1146 return s->utcr3; 1147 1148 case UTDR: 1149 if (s->rx_len != 0) { 1150 ret = s->rx_fifo[s->rx_start]; 1151 s->rx_start = (s->rx_start + 1) % 12; 1152 s->rx_len--; 1153 strongarm_uart_update_status(s); 1154 strongarm_uart_update_int_status(s); 1155 return ret; 1156 } 1157 return 0; 1158 1159 case UTSR0: 1160 return s->utsr0; 1161 1162 case UTSR1: 1163 return s->utsr1; 1164 1165 default: 1166 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr); 1167 return 0; 1168 } 1169 } 1170 1171 static void strongarm_uart_write(void *opaque, hwaddr addr, 1172 uint64_t value, unsigned size) 1173 { 1174 StrongARMUARTState *s = opaque; 1175 1176 switch (addr) { 1177 case UTCR0: 1178 s->utcr0 = value & 0x7f; 1179 strongarm_uart_update_parameters(s); 1180 break; 1181 1182 case UTCR1: 1183 s->brd = (s->brd & 0xff) | ((value & 0xf) << 8); 1184 strongarm_uart_update_parameters(s); 1185 break; 1186 1187 case UTCR2: 1188 s->brd = (s->brd & 0xf00) | (value & 0xff); 1189 strongarm_uart_update_parameters(s); 1190 break; 1191 1192 case UTCR3: 1193 s->utcr3 = value & 0x3f; 1194 if ((s->utcr3 & UTCR3_RXE) == 0) { 1195 s->rx_len = 0; 1196 } 1197 if ((s->utcr3 & UTCR3_TXE) == 0) { 1198 s->tx_len = 0; 1199 } 1200 strongarm_uart_update_status(s); 1201 strongarm_uart_update_int_status(s); 1202 break; 1203 1204 case UTDR: 1205 if ((s->utcr3 & UTCR3_TXE) && s->tx_len != 8) { 1206 s->tx_fifo[(s->tx_start + s->tx_len) % 8] = value; 1207 s->tx_len++; 1208 strongarm_uart_update_status(s); 1209 strongarm_uart_update_int_status(s); 1210 if (s->tx_len == 1) { 1211 strongarm_uart_tx(s); 1212 } 1213 } 1214 break; 1215 1216 case UTSR0: 1217 s->utsr0 = s->utsr0 & ~(value & 1218 (UTSR0_REB | UTSR0_RBB | UTSR0_RID)); 1219 strongarm_uart_update_int_status(s); 1220 break; 1221 1222 default: 1223 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr); 1224 } 1225 } 1226 1227 static const MemoryRegionOps strongarm_uart_ops = { 1228 .read = strongarm_uart_read, 1229 .write = strongarm_uart_write, 1230 .endianness = DEVICE_NATIVE_ENDIAN, 1231 }; 1232 1233 static void strongarm_uart_init(Object *obj) 1234 { 1235 StrongARMUARTState *s = STRONGARM_UART(obj); 1236 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 1237 1238 memory_region_init_io(&s->iomem, obj, &strongarm_uart_ops, s, 1239 "uart", 0x10000); 1240 sysbus_init_mmio(dev, &s->iomem); 1241 sysbus_init_irq(dev, &s->irq); 1242 1243 s->rx_timeout_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, strongarm_uart_rx_to, s); 1244 s->tx_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, strongarm_uart_tx, s); 1245 } 1246 1247 static void strongarm_uart_realize(DeviceState *dev, Error **errp) 1248 { 1249 StrongARMUARTState *s = STRONGARM_UART(dev); 1250 1251 qemu_chr_fe_set_handlers(&s->chr, 1252 strongarm_uart_can_receive, 1253 strongarm_uart_receive, 1254 strongarm_uart_event, 1255 NULL, s, NULL, true); 1256 } 1257 1258 static void strongarm_uart_reset(DeviceState *dev) 1259 { 1260 StrongARMUARTState *s = STRONGARM_UART(dev); 1261 1262 s->utcr0 = UTCR0_DSS; /* 8 data, no parity */ 1263 s->brd = 23; /* 9600 */ 1264 /* enable send & recv - this actually violates spec */ 1265 s->utcr3 = UTCR3_TXE | UTCR3_RXE; 1266 1267 s->rx_len = s->tx_len = 0; 1268 1269 strongarm_uart_update_parameters(s); 1270 strongarm_uart_update_status(s); 1271 strongarm_uart_update_int_status(s); 1272 } 1273 1274 static int strongarm_uart_post_load(void *opaque, int version_id) 1275 { 1276 StrongARMUARTState *s = opaque; 1277 1278 strongarm_uart_update_parameters(s); 1279 strongarm_uart_update_status(s); 1280 strongarm_uart_update_int_status(s); 1281 1282 /* tx and restart timer */ 1283 if (s->tx_len) { 1284 strongarm_uart_tx(s); 1285 } 1286 1287 /* restart rx timeout timer */ 1288 if (s->rx_len) { 1289 timer_mod(s->rx_timeout_timer, 1290 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 3); 1291 } 1292 1293 return 0; 1294 } 1295 1296 static const VMStateDescription vmstate_strongarm_uart_regs = { 1297 .name = "strongarm-uart", 1298 .version_id = 0, 1299 .minimum_version_id = 0, 1300 .post_load = strongarm_uart_post_load, 1301 .fields = (VMStateField[]) { 1302 VMSTATE_UINT8(utcr0, StrongARMUARTState), 1303 VMSTATE_UINT16(brd, StrongARMUARTState), 1304 VMSTATE_UINT8(utcr3, StrongARMUARTState), 1305 VMSTATE_UINT8(utsr0, StrongARMUARTState), 1306 VMSTATE_UINT8_ARRAY(tx_fifo, StrongARMUARTState, 8), 1307 VMSTATE_UINT8(tx_start, StrongARMUARTState), 1308 VMSTATE_UINT8(tx_len, StrongARMUARTState), 1309 VMSTATE_UINT16_ARRAY(rx_fifo, StrongARMUARTState, 12), 1310 VMSTATE_UINT8(rx_start, StrongARMUARTState), 1311 VMSTATE_UINT8(rx_len, StrongARMUARTState), 1312 VMSTATE_BOOL(wait_break_end, StrongARMUARTState), 1313 VMSTATE_END_OF_LIST(), 1314 }, 1315 }; 1316 1317 static Property strongarm_uart_properties[] = { 1318 DEFINE_PROP_CHR("chardev", StrongARMUARTState, chr), 1319 DEFINE_PROP_END_OF_LIST(), 1320 }; 1321 1322 static void strongarm_uart_class_init(ObjectClass *klass, void *data) 1323 { 1324 DeviceClass *dc = DEVICE_CLASS(klass); 1325 1326 dc->desc = "StrongARM UART controller"; 1327 dc->reset = strongarm_uart_reset; 1328 dc->vmsd = &vmstate_strongarm_uart_regs; 1329 dc->props = strongarm_uart_properties; 1330 dc->realize = strongarm_uart_realize; 1331 } 1332 1333 static const TypeInfo strongarm_uart_info = { 1334 .name = TYPE_STRONGARM_UART, 1335 .parent = TYPE_SYS_BUS_DEVICE, 1336 .instance_size = sizeof(StrongARMUARTState), 1337 .instance_init = strongarm_uart_init, 1338 .class_init = strongarm_uart_class_init, 1339 }; 1340 1341 /* Synchronous Serial Ports */ 1342 1343 #define TYPE_STRONGARM_SSP "strongarm-ssp" 1344 #define STRONGARM_SSP(obj) \ 1345 OBJECT_CHECK(StrongARMSSPState, (obj), TYPE_STRONGARM_SSP) 1346 1347 typedef struct StrongARMSSPState { 1348 SysBusDevice parent_obj; 1349 1350 MemoryRegion iomem; 1351 qemu_irq irq; 1352 SSIBus *bus; 1353 1354 uint16_t sscr[2]; 1355 uint16_t sssr; 1356 1357 uint16_t rx_fifo[8]; 1358 uint8_t rx_level; 1359 uint8_t rx_start; 1360 } StrongARMSSPState; 1361 1362 #define SSCR0 0x60 /* SSP Control register 0 */ 1363 #define SSCR1 0x64 /* SSP Control register 1 */ 1364 #define SSDR 0x6c /* SSP Data register */ 1365 #define SSSR 0x74 /* SSP Status register */ 1366 1367 /* Bitfields for above registers */ 1368 #define SSCR0_SPI(x) (((x) & 0x30) == 0x00) 1369 #define SSCR0_SSP(x) (((x) & 0x30) == 0x10) 1370 #define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20) 1371 #define SSCR0_PSP(x) (((x) & 0x30) == 0x30) 1372 #define SSCR0_SSE (1 << 7) 1373 #define SSCR0_DSS(x) (((x) & 0xf) + 1) 1374 #define SSCR1_RIE (1 << 0) 1375 #define SSCR1_TIE (1 << 1) 1376 #define SSCR1_LBM (1 << 2) 1377 #define SSSR_TNF (1 << 2) 1378 #define SSSR_RNE (1 << 3) 1379 #define SSSR_TFS (1 << 5) 1380 #define SSSR_RFS (1 << 6) 1381 #define SSSR_ROR (1 << 7) 1382 #define SSSR_RW 0x0080 1383 1384 static void strongarm_ssp_int_update(StrongARMSSPState *s) 1385 { 1386 int level = 0; 1387 1388 level |= (s->sssr & SSSR_ROR); 1389 level |= (s->sssr & SSSR_RFS) && (s->sscr[1] & SSCR1_RIE); 1390 level |= (s->sssr & SSSR_TFS) && (s->sscr[1] & SSCR1_TIE); 1391 qemu_set_irq(s->irq, level); 1392 } 1393 1394 static void strongarm_ssp_fifo_update(StrongARMSSPState *s) 1395 { 1396 s->sssr &= ~SSSR_TFS; 1397 s->sssr &= ~SSSR_TNF; 1398 if (s->sscr[0] & SSCR0_SSE) { 1399 if (s->rx_level >= 4) { 1400 s->sssr |= SSSR_RFS; 1401 } else { 1402 s->sssr &= ~SSSR_RFS; 1403 } 1404 if (s->rx_level) { 1405 s->sssr |= SSSR_RNE; 1406 } else { 1407 s->sssr &= ~SSSR_RNE; 1408 } 1409 /* TX FIFO is never filled, so it is always in underrun 1410 condition if SSP is enabled */ 1411 s->sssr |= SSSR_TFS; 1412 s->sssr |= SSSR_TNF; 1413 } 1414 1415 strongarm_ssp_int_update(s); 1416 } 1417 1418 static uint64_t strongarm_ssp_read(void *opaque, hwaddr addr, 1419 unsigned size) 1420 { 1421 StrongARMSSPState *s = opaque; 1422 uint32_t retval; 1423 1424 switch (addr) { 1425 case SSCR0: 1426 return s->sscr[0]; 1427 case SSCR1: 1428 return s->sscr[1]; 1429 case SSSR: 1430 return s->sssr; 1431 case SSDR: 1432 if (~s->sscr[0] & SSCR0_SSE) { 1433 return 0xffffffff; 1434 } 1435 if (s->rx_level < 1) { 1436 printf("%s: SSP Rx Underrun\n", __func__); 1437 return 0xffffffff; 1438 } 1439 s->rx_level--; 1440 retval = s->rx_fifo[s->rx_start++]; 1441 s->rx_start &= 0x7; 1442 strongarm_ssp_fifo_update(s); 1443 return retval; 1444 default: 1445 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr); 1446 break; 1447 } 1448 return 0; 1449 } 1450 1451 static void strongarm_ssp_write(void *opaque, hwaddr addr, 1452 uint64_t value, unsigned size) 1453 { 1454 StrongARMSSPState *s = opaque; 1455 1456 switch (addr) { 1457 case SSCR0: 1458 s->sscr[0] = value & 0xffbf; 1459 if ((s->sscr[0] & SSCR0_SSE) && SSCR0_DSS(value) < 4) { 1460 printf("%s: Wrong data size: %i bits\n", __func__, 1461 (int)SSCR0_DSS(value)); 1462 } 1463 if (!(value & SSCR0_SSE)) { 1464 s->sssr = 0; 1465 s->rx_level = 0; 1466 } 1467 strongarm_ssp_fifo_update(s); 1468 break; 1469 1470 case SSCR1: 1471 s->sscr[1] = value & 0x2f; 1472 if (value & SSCR1_LBM) { 1473 printf("%s: Attempt to use SSP LBM mode\n", __func__); 1474 } 1475 strongarm_ssp_fifo_update(s); 1476 break; 1477 1478 case SSSR: 1479 s->sssr &= ~(value & SSSR_RW); 1480 strongarm_ssp_int_update(s); 1481 break; 1482 1483 case SSDR: 1484 if (SSCR0_UWIRE(s->sscr[0])) { 1485 value &= 0xff; 1486 } else 1487 /* Note how 32bits overflow does no harm here */ 1488 value &= (1 << SSCR0_DSS(s->sscr[0])) - 1; 1489 1490 /* Data goes from here to the Tx FIFO and is shifted out from 1491 * there directly to the slave, no need to buffer it. 1492 */ 1493 if (s->sscr[0] & SSCR0_SSE) { 1494 uint32_t readval; 1495 if (s->sscr[1] & SSCR1_LBM) { 1496 readval = value; 1497 } else { 1498 readval = ssi_transfer(s->bus, value); 1499 } 1500 1501 if (s->rx_level < 0x08) { 1502 s->rx_fifo[(s->rx_start + s->rx_level++) & 0x7] = readval; 1503 } else { 1504 s->sssr |= SSSR_ROR; 1505 } 1506 } 1507 strongarm_ssp_fifo_update(s); 1508 break; 1509 1510 default: 1511 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr); 1512 break; 1513 } 1514 } 1515 1516 static const MemoryRegionOps strongarm_ssp_ops = { 1517 .read = strongarm_ssp_read, 1518 .write = strongarm_ssp_write, 1519 .endianness = DEVICE_NATIVE_ENDIAN, 1520 }; 1521 1522 static int strongarm_ssp_post_load(void *opaque, int version_id) 1523 { 1524 StrongARMSSPState *s = opaque; 1525 1526 strongarm_ssp_fifo_update(s); 1527 1528 return 0; 1529 } 1530 1531 static void strongarm_ssp_init(Object *obj) 1532 { 1533 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 1534 DeviceState *dev = DEVICE(sbd); 1535 StrongARMSSPState *s = STRONGARM_SSP(dev); 1536 1537 sysbus_init_irq(sbd, &s->irq); 1538 1539 memory_region_init_io(&s->iomem, obj, &strongarm_ssp_ops, s, 1540 "ssp", 0x1000); 1541 sysbus_init_mmio(sbd, &s->iomem); 1542 1543 s->bus = ssi_create_bus(dev, "ssi"); 1544 } 1545 1546 static void strongarm_ssp_reset(DeviceState *dev) 1547 { 1548 StrongARMSSPState *s = STRONGARM_SSP(dev); 1549 1550 s->sssr = 0x03; /* 3 bit data, SPI, disabled */ 1551 s->rx_start = 0; 1552 s->rx_level = 0; 1553 } 1554 1555 static const VMStateDescription vmstate_strongarm_ssp_regs = { 1556 .name = "strongarm-ssp", 1557 .version_id = 0, 1558 .minimum_version_id = 0, 1559 .post_load = strongarm_ssp_post_load, 1560 .fields = (VMStateField[]) { 1561 VMSTATE_UINT16_ARRAY(sscr, StrongARMSSPState, 2), 1562 VMSTATE_UINT16(sssr, StrongARMSSPState), 1563 VMSTATE_UINT16_ARRAY(rx_fifo, StrongARMSSPState, 8), 1564 VMSTATE_UINT8(rx_start, StrongARMSSPState), 1565 VMSTATE_UINT8(rx_level, StrongARMSSPState), 1566 VMSTATE_END_OF_LIST(), 1567 }, 1568 }; 1569 1570 static void strongarm_ssp_class_init(ObjectClass *klass, void *data) 1571 { 1572 DeviceClass *dc = DEVICE_CLASS(klass); 1573 1574 dc->desc = "StrongARM SSP controller"; 1575 dc->reset = strongarm_ssp_reset; 1576 dc->vmsd = &vmstate_strongarm_ssp_regs; 1577 } 1578 1579 static const TypeInfo strongarm_ssp_info = { 1580 .name = TYPE_STRONGARM_SSP, 1581 .parent = TYPE_SYS_BUS_DEVICE, 1582 .instance_size = sizeof(StrongARMSSPState), 1583 .instance_init = strongarm_ssp_init, 1584 .class_init = strongarm_ssp_class_init, 1585 }; 1586 1587 /* Main CPU functions */ 1588 StrongARMState *sa1110_init(MemoryRegion *sysmem, 1589 unsigned int sdram_size, const char *cpu_type) 1590 { 1591 StrongARMState *s; 1592 int i; 1593 1594 s = g_new0(StrongARMState, 1); 1595 1596 if (strncmp(cpu_type, "sa1110", 6)) { 1597 error_report("Machine requires a SA1110 processor."); 1598 exit(1); 1599 } 1600 1601 s->cpu = ARM_CPU(cpu_create(cpu_type)); 1602 1603 memory_region_allocate_system_memory(&s->sdram, NULL, "strongarm.sdram", 1604 sdram_size); 1605 memory_region_add_subregion(sysmem, SA_SDCS0, &s->sdram); 1606 1607 s->pic = sysbus_create_varargs("strongarm_pic", 0x90050000, 1608 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ), 1609 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_FIQ), 1610 NULL); 1611 1612 sysbus_create_varargs("pxa25x-timer", 0x90000000, 1613 qdev_get_gpio_in(s->pic, SA_PIC_OSTC0), 1614 qdev_get_gpio_in(s->pic, SA_PIC_OSTC1), 1615 qdev_get_gpio_in(s->pic, SA_PIC_OSTC2), 1616 qdev_get_gpio_in(s->pic, SA_PIC_OSTC3), 1617 NULL); 1618 1619 sysbus_create_simple(TYPE_STRONGARM_RTC, 0x90010000, 1620 qdev_get_gpio_in(s->pic, SA_PIC_RTC_ALARM)); 1621 1622 s->gpio = strongarm_gpio_init(0x90040000, s->pic); 1623 1624 s->ppc = sysbus_create_varargs(TYPE_STRONGARM_PPC, 0x90060000, NULL); 1625 1626 for (i = 0; sa_serial[i].io_base; i++) { 1627 DeviceState *dev = qdev_create(NULL, TYPE_STRONGARM_UART); 1628 qdev_prop_set_chr(dev, "chardev", serial_hd(i)); 1629 qdev_init_nofail(dev); 1630 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 1631 sa_serial[i].io_base); 1632 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, 1633 qdev_get_gpio_in(s->pic, sa_serial[i].irq)); 1634 } 1635 1636 s->ssp = sysbus_create_varargs(TYPE_STRONGARM_SSP, 0x80070000, 1637 qdev_get_gpio_in(s->pic, SA_PIC_SSP), NULL); 1638 s->ssp_bus = (SSIBus *)qdev_get_child_bus(s->ssp, "ssi"); 1639 1640 return s; 1641 } 1642 1643 static void strongarm_register_types(void) 1644 { 1645 type_register_static(&strongarm_pic_info); 1646 type_register_static(&strongarm_rtc_sysbus_info); 1647 type_register_static(&strongarm_gpio_info); 1648 type_register_static(&strongarm_ppc_info); 1649 type_register_static(&strongarm_uart_info); 1650 type_register_static(&strongarm_ssp_info); 1651 } 1652 1653 type_init(strongarm_register_types) 1654