1 /* 2 * StrongARM SA-1100/SA-1110 emulation 3 * 4 * Copyright (C) 2011 Dmitry Eremin-Solenikov 5 * 6 * Largely based on StrongARM emulation: 7 * Copyright (c) 2006 Openedhand Ltd. 8 * Written by Andrzej Zaborowski <balrog@zabor.org> 9 * 10 * UART code based on QEMU 16550A UART emulation 11 * Copyright (c) 2003-2004 Fabrice Bellard 12 * Copyright (c) 2008 Citrix Systems, Inc. 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License version 2 as 16 * published by the Free Software Foundation. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License along 24 * with this program; if not, see <http://www.gnu.org/licenses/>. 25 * 26 * Contributions after 2012-01-13 are licensed under the terms of the 27 * GNU GPL, version 2 or (at your option) any later version. 28 */ 29 30 #include "hw/boards.h" 31 #include "hw/sysbus.h" 32 #include "strongarm.h" 33 #include "qemu/error-report.h" 34 #include "hw/arm/arm.h" 35 #include "sysemu/char.h" 36 #include "sysemu/sysemu.h" 37 #include "hw/ssi.h" 38 39 //#define DEBUG 40 41 /* 42 TODO 43 - Implement cp15, c14 ? 44 - Implement cp15, c15 !!! (idle used in L) 45 - Implement idle mode handling/DIM 46 - Implement sleep mode/Wake sources 47 - Implement reset control 48 - Implement memory control regs 49 - PCMCIA handling 50 - Maybe support MBGNT/MBREQ 51 - DMA channels 52 - GPCLK 53 - IrDA 54 - MCP 55 - Enhance UART with modem signals 56 */ 57 58 #ifdef DEBUG 59 # define DPRINTF(format, ...) printf(format , ## __VA_ARGS__) 60 #else 61 # define DPRINTF(format, ...) do { } while (0) 62 #endif 63 64 static struct { 65 hwaddr io_base; 66 int irq; 67 } sa_serial[] = { 68 { 0x80010000, SA_PIC_UART1 }, 69 { 0x80030000, SA_PIC_UART2 }, 70 { 0x80050000, SA_PIC_UART3 }, 71 { 0, 0 } 72 }; 73 74 /* Interrupt Controller */ 75 76 #define TYPE_STRONGARM_PIC "strongarm_pic" 77 #define STRONGARM_PIC(obj) \ 78 OBJECT_CHECK(StrongARMPICState, (obj), TYPE_STRONGARM_PIC) 79 80 typedef struct StrongARMPICState { 81 SysBusDevice parent_obj; 82 83 MemoryRegion iomem; 84 qemu_irq irq; 85 qemu_irq fiq; 86 87 uint32_t pending; 88 uint32_t enabled; 89 uint32_t is_fiq; 90 uint32_t int_idle; 91 } StrongARMPICState; 92 93 #define ICIP 0x00 94 #define ICMR 0x04 95 #define ICLR 0x08 96 #define ICFP 0x10 97 #define ICPR 0x20 98 #define ICCR 0x0c 99 100 #define SA_PIC_SRCS 32 101 102 103 static void strongarm_pic_update(void *opaque) 104 { 105 StrongARMPICState *s = opaque; 106 107 /* FIXME: reflect DIM */ 108 qemu_set_irq(s->fiq, s->pending & s->enabled & s->is_fiq); 109 qemu_set_irq(s->irq, s->pending & s->enabled & ~s->is_fiq); 110 } 111 112 static void strongarm_pic_set_irq(void *opaque, int irq, int level) 113 { 114 StrongARMPICState *s = opaque; 115 116 if (level) { 117 s->pending |= 1 << irq; 118 } else { 119 s->pending &= ~(1 << irq); 120 } 121 122 strongarm_pic_update(s); 123 } 124 125 static uint64_t strongarm_pic_mem_read(void *opaque, hwaddr offset, 126 unsigned size) 127 { 128 StrongARMPICState *s = opaque; 129 130 switch (offset) { 131 case ICIP: 132 return s->pending & ~s->is_fiq & s->enabled; 133 case ICMR: 134 return s->enabled; 135 case ICLR: 136 return s->is_fiq; 137 case ICCR: 138 return s->int_idle == 0; 139 case ICFP: 140 return s->pending & s->is_fiq & s->enabled; 141 case ICPR: 142 return s->pending; 143 default: 144 printf("%s: Bad register offset 0x" TARGET_FMT_plx "\n", 145 __func__, offset); 146 return 0; 147 } 148 } 149 150 static void strongarm_pic_mem_write(void *opaque, hwaddr offset, 151 uint64_t value, unsigned size) 152 { 153 StrongARMPICState *s = opaque; 154 155 switch (offset) { 156 case ICMR: 157 s->enabled = value; 158 break; 159 case ICLR: 160 s->is_fiq = value; 161 break; 162 case ICCR: 163 s->int_idle = (value & 1) ? 0 : ~0; 164 break; 165 default: 166 printf("%s: Bad register offset 0x" TARGET_FMT_plx "\n", 167 __func__, offset); 168 break; 169 } 170 strongarm_pic_update(s); 171 } 172 173 static const MemoryRegionOps strongarm_pic_ops = { 174 .read = strongarm_pic_mem_read, 175 .write = strongarm_pic_mem_write, 176 .endianness = DEVICE_NATIVE_ENDIAN, 177 }; 178 179 static int strongarm_pic_initfn(SysBusDevice *sbd) 180 { 181 DeviceState *dev = DEVICE(sbd); 182 StrongARMPICState *s = STRONGARM_PIC(dev); 183 184 qdev_init_gpio_in(dev, strongarm_pic_set_irq, SA_PIC_SRCS); 185 memory_region_init_io(&s->iomem, OBJECT(s), &strongarm_pic_ops, s, 186 "pic", 0x1000); 187 sysbus_init_mmio(sbd, &s->iomem); 188 sysbus_init_irq(sbd, &s->irq); 189 sysbus_init_irq(sbd, &s->fiq); 190 191 return 0; 192 } 193 194 static int strongarm_pic_post_load(void *opaque, int version_id) 195 { 196 strongarm_pic_update(opaque); 197 return 0; 198 } 199 200 static VMStateDescription vmstate_strongarm_pic_regs = { 201 .name = "strongarm_pic", 202 .version_id = 0, 203 .minimum_version_id = 0, 204 .post_load = strongarm_pic_post_load, 205 .fields = (VMStateField[]) { 206 VMSTATE_UINT32(pending, StrongARMPICState), 207 VMSTATE_UINT32(enabled, StrongARMPICState), 208 VMSTATE_UINT32(is_fiq, StrongARMPICState), 209 VMSTATE_UINT32(int_idle, StrongARMPICState), 210 VMSTATE_END_OF_LIST(), 211 }, 212 }; 213 214 static void strongarm_pic_class_init(ObjectClass *klass, void *data) 215 { 216 DeviceClass *dc = DEVICE_CLASS(klass); 217 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 218 219 k->init = strongarm_pic_initfn; 220 dc->desc = "StrongARM PIC"; 221 dc->vmsd = &vmstate_strongarm_pic_regs; 222 } 223 224 static const TypeInfo strongarm_pic_info = { 225 .name = TYPE_STRONGARM_PIC, 226 .parent = TYPE_SYS_BUS_DEVICE, 227 .instance_size = sizeof(StrongARMPICState), 228 .class_init = strongarm_pic_class_init, 229 }; 230 231 /* Real-Time Clock */ 232 #define RTAR 0x00 /* RTC Alarm register */ 233 #define RCNR 0x04 /* RTC Counter register */ 234 #define RTTR 0x08 /* RTC Timer Trim register */ 235 #define RTSR 0x10 /* RTC Status register */ 236 237 #define RTSR_AL (1 << 0) /* RTC Alarm detected */ 238 #define RTSR_HZ (1 << 1) /* RTC 1Hz detected */ 239 #define RTSR_ALE (1 << 2) /* RTC Alarm enable */ 240 #define RTSR_HZE (1 << 3) /* RTC 1Hz enable */ 241 242 /* 16 LSB of RTTR are clockdiv for internal trim logic, 243 * trim delete isn't emulated, so 244 * f = 32 768 / (RTTR_trim + 1) */ 245 246 #define TYPE_STRONGARM_RTC "strongarm-rtc" 247 #define STRONGARM_RTC(obj) \ 248 OBJECT_CHECK(StrongARMRTCState, (obj), TYPE_STRONGARM_RTC) 249 250 typedef struct StrongARMRTCState { 251 SysBusDevice parent_obj; 252 253 MemoryRegion iomem; 254 uint32_t rttr; 255 uint32_t rtsr; 256 uint32_t rtar; 257 uint32_t last_rcnr; 258 int64_t last_hz; 259 QEMUTimer *rtc_alarm; 260 QEMUTimer *rtc_hz; 261 qemu_irq rtc_irq; 262 qemu_irq rtc_hz_irq; 263 } StrongARMRTCState; 264 265 static inline void strongarm_rtc_int_update(StrongARMRTCState *s) 266 { 267 qemu_set_irq(s->rtc_irq, s->rtsr & RTSR_AL); 268 qemu_set_irq(s->rtc_hz_irq, s->rtsr & RTSR_HZ); 269 } 270 271 static void strongarm_rtc_hzupdate(StrongARMRTCState *s) 272 { 273 int64_t rt = qemu_clock_get_ms(rtc_clock); 274 s->last_rcnr += ((rt - s->last_hz) << 15) / 275 (1000 * ((s->rttr & 0xffff) + 1)); 276 s->last_hz = rt; 277 } 278 279 static inline void strongarm_rtc_timer_update(StrongARMRTCState *s) 280 { 281 if ((s->rtsr & RTSR_HZE) && !(s->rtsr & RTSR_HZ)) { 282 timer_mod(s->rtc_hz, s->last_hz + 1000); 283 } else { 284 timer_del(s->rtc_hz); 285 } 286 287 if ((s->rtsr & RTSR_ALE) && !(s->rtsr & RTSR_AL)) { 288 timer_mod(s->rtc_alarm, s->last_hz + 289 (((s->rtar - s->last_rcnr) * 1000 * 290 ((s->rttr & 0xffff) + 1)) >> 15)); 291 } else { 292 timer_del(s->rtc_alarm); 293 } 294 } 295 296 static inline void strongarm_rtc_alarm_tick(void *opaque) 297 { 298 StrongARMRTCState *s = opaque; 299 s->rtsr |= RTSR_AL; 300 strongarm_rtc_timer_update(s); 301 strongarm_rtc_int_update(s); 302 } 303 304 static inline void strongarm_rtc_hz_tick(void *opaque) 305 { 306 StrongARMRTCState *s = opaque; 307 s->rtsr |= RTSR_HZ; 308 strongarm_rtc_timer_update(s); 309 strongarm_rtc_int_update(s); 310 } 311 312 static uint64_t strongarm_rtc_read(void *opaque, hwaddr addr, 313 unsigned size) 314 { 315 StrongARMRTCState *s = opaque; 316 317 switch (addr) { 318 case RTTR: 319 return s->rttr; 320 case RTSR: 321 return s->rtsr; 322 case RTAR: 323 return s->rtar; 324 case RCNR: 325 return s->last_rcnr + 326 ((qemu_clock_get_ms(rtc_clock) - s->last_hz) << 15) / 327 (1000 * ((s->rttr & 0xffff) + 1)); 328 default: 329 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr); 330 return 0; 331 } 332 } 333 334 static void strongarm_rtc_write(void *opaque, hwaddr addr, 335 uint64_t value, unsigned size) 336 { 337 StrongARMRTCState *s = opaque; 338 uint32_t old_rtsr; 339 340 switch (addr) { 341 case RTTR: 342 strongarm_rtc_hzupdate(s); 343 s->rttr = value; 344 strongarm_rtc_timer_update(s); 345 break; 346 347 case RTSR: 348 old_rtsr = s->rtsr; 349 s->rtsr = (value & (RTSR_ALE | RTSR_HZE)) | 350 (s->rtsr & ~(value & (RTSR_AL | RTSR_HZ))); 351 352 if (s->rtsr != old_rtsr) { 353 strongarm_rtc_timer_update(s); 354 } 355 356 strongarm_rtc_int_update(s); 357 break; 358 359 case RTAR: 360 s->rtar = value; 361 strongarm_rtc_timer_update(s); 362 break; 363 364 case RCNR: 365 strongarm_rtc_hzupdate(s); 366 s->last_rcnr = value; 367 strongarm_rtc_timer_update(s); 368 break; 369 370 default: 371 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr); 372 } 373 } 374 375 static const MemoryRegionOps strongarm_rtc_ops = { 376 .read = strongarm_rtc_read, 377 .write = strongarm_rtc_write, 378 .endianness = DEVICE_NATIVE_ENDIAN, 379 }; 380 381 static int strongarm_rtc_init(SysBusDevice *dev) 382 { 383 StrongARMRTCState *s = STRONGARM_RTC(dev); 384 struct tm tm; 385 386 s->rttr = 0x0; 387 s->rtsr = 0; 388 389 qemu_get_timedate(&tm, 0); 390 391 s->last_rcnr = (uint32_t) mktimegm(&tm); 392 s->last_hz = qemu_clock_get_ms(rtc_clock); 393 394 s->rtc_alarm = timer_new_ms(rtc_clock, strongarm_rtc_alarm_tick, s); 395 s->rtc_hz = timer_new_ms(rtc_clock, strongarm_rtc_hz_tick, s); 396 397 sysbus_init_irq(dev, &s->rtc_irq); 398 sysbus_init_irq(dev, &s->rtc_hz_irq); 399 400 memory_region_init_io(&s->iomem, OBJECT(s), &strongarm_rtc_ops, s, 401 "rtc", 0x10000); 402 sysbus_init_mmio(dev, &s->iomem); 403 404 return 0; 405 } 406 407 static void strongarm_rtc_pre_save(void *opaque) 408 { 409 StrongARMRTCState *s = opaque; 410 411 strongarm_rtc_hzupdate(s); 412 } 413 414 static int strongarm_rtc_post_load(void *opaque, int version_id) 415 { 416 StrongARMRTCState *s = opaque; 417 418 strongarm_rtc_timer_update(s); 419 strongarm_rtc_int_update(s); 420 421 return 0; 422 } 423 424 static const VMStateDescription vmstate_strongarm_rtc_regs = { 425 .name = "strongarm-rtc", 426 .version_id = 0, 427 .minimum_version_id = 0, 428 .pre_save = strongarm_rtc_pre_save, 429 .post_load = strongarm_rtc_post_load, 430 .fields = (VMStateField[]) { 431 VMSTATE_UINT32(rttr, StrongARMRTCState), 432 VMSTATE_UINT32(rtsr, StrongARMRTCState), 433 VMSTATE_UINT32(rtar, StrongARMRTCState), 434 VMSTATE_UINT32(last_rcnr, StrongARMRTCState), 435 VMSTATE_INT64(last_hz, StrongARMRTCState), 436 VMSTATE_END_OF_LIST(), 437 }, 438 }; 439 440 static void strongarm_rtc_sysbus_class_init(ObjectClass *klass, void *data) 441 { 442 DeviceClass *dc = DEVICE_CLASS(klass); 443 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 444 445 k->init = strongarm_rtc_init; 446 dc->desc = "StrongARM RTC Controller"; 447 dc->vmsd = &vmstate_strongarm_rtc_regs; 448 } 449 450 static const TypeInfo strongarm_rtc_sysbus_info = { 451 .name = TYPE_STRONGARM_RTC, 452 .parent = TYPE_SYS_BUS_DEVICE, 453 .instance_size = sizeof(StrongARMRTCState), 454 .class_init = strongarm_rtc_sysbus_class_init, 455 }; 456 457 /* GPIO */ 458 #define GPLR 0x00 459 #define GPDR 0x04 460 #define GPSR 0x08 461 #define GPCR 0x0c 462 #define GRER 0x10 463 #define GFER 0x14 464 #define GEDR 0x18 465 #define GAFR 0x1c 466 467 #define TYPE_STRONGARM_GPIO "strongarm-gpio" 468 #define STRONGARM_GPIO(obj) \ 469 OBJECT_CHECK(StrongARMGPIOInfo, (obj), TYPE_STRONGARM_GPIO) 470 471 typedef struct StrongARMGPIOInfo StrongARMGPIOInfo; 472 struct StrongARMGPIOInfo { 473 SysBusDevice busdev; 474 MemoryRegion iomem; 475 qemu_irq handler[28]; 476 qemu_irq irqs[11]; 477 qemu_irq irqX; 478 479 uint32_t ilevel; 480 uint32_t olevel; 481 uint32_t dir; 482 uint32_t rising; 483 uint32_t falling; 484 uint32_t status; 485 uint32_t gafr; 486 487 uint32_t prev_level; 488 }; 489 490 491 static void strongarm_gpio_irq_update(StrongARMGPIOInfo *s) 492 { 493 int i; 494 for (i = 0; i < 11; i++) { 495 qemu_set_irq(s->irqs[i], s->status & (1 << i)); 496 } 497 498 qemu_set_irq(s->irqX, (s->status & ~0x7ff)); 499 } 500 501 static void strongarm_gpio_set(void *opaque, int line, int level) 502 { 503 StrongARMGPIOInfo *s = opaque; 504 uint32_t mask; 505 506 mask = 1 << line; 507 508 if (level) { 509 s->status |= s->rising & mask & 510 ~s->ilevel & ~s->dir; 511 s->ilevel |= mask; 512 } else { 513 s->status |= s->falling & mask & 514 s->ilevel & ~s->dir; 515 s->ilevel &= ~mask; 516 } 517 518 if (s->status & mask) { 519 strongarm_gpio_irq_update(s); 520 } 521 } 522 523 static void strongarm_gpio_handler_update(StrongARMGPIOInfo *s) 524 { 525 uint32_t level, diff; 526 int bit; 527 528 level = s->olevel & s->dir; 529 530 for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) { 531 bit = ctz32(diff); 532 qemu_set_irq(s->handler[bit], (level >> bit) & 1); 533 } 534 535 s->prev_level = level; 536 } 537 538 static uint64_t strongarm_gpio_read(void *opaque, hwaddr offset, 539 unsigned size) 540 { 541 StrongARMGPIOInfo *s = opaque; 542 543 switch (offset) { 544 case GPDR: /* GPIO Pin-Direction registers */ 545 return s->dir; 546 547 case GPSR: /* GPIO Pin-Output Set registers */ 548 qemu_log_mask(LOG_GUEST_ERROR, 549 "strongarm GPIO: read from write only register GPSR\n"); 550 return 0; 551 552 case GPCR: /* GPIO Pin-Output Clear registers */ 553 qemu_log_mask(LOG_GUEST_ERROR, 554 "strongarm GPIO: read from write only register GPCR\n"); 555 return 0; 556 557 case GRER: /* GPIO Rising-Edge Detect Enable registers */ 558 return s->rising; 559 560 case GFER: /* GPIO Falling-Edge Detect Enable registers */ 561 return s->falling; 562 563 case GAFR: /* GPIO Alternate Function registers */ 564 return s->gafr; 565 566 case GPLR: /* GPIO Pin-Level registers */ 567 return (s->olevel & s->dir) | 568 (s->ilevel & ~s->dir); 569 570 case GEDR: /* GPIO Edge Detect Status registers */ 571 return s->status; 572 573 default: 574 printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset); 575 } 576 577 return 0; 578 } 579 580 static void strongarm_gpio_write(void *opaque, hwaddr offset, 581 uint64_t value, unsigned size) 582 { 583 StrongARMGPIOInfo *s = opaque; 584 585 switch (offset) { 586 case GPDR: /* GPIO Pin-Direction registers */ 587 s->dir = value; 588 strongarm_gpio_handler_update(s); 589 break; 590 591 case GPSR: /* GPIO Pin-Output Set registers */ 592 s->olevel |= value; 593 strongarm_gpio_handler_update(s); 594 break; 595 596 case GPCR: /* GPIO Pin-Output Clear registers */ 597 s->olevel &= ~value; 598 strongarm_gpio_handler_update(s); 599 break; 600 601 case GRER: /* GPIO Rising-Edge Detect Enable registers */ 602 s->rising = value; 603 break; 604 605 case GFER: /* GPIO Falling-Edge Detect Enable registers */ 606 s->falling = value; 607 break; 608 609 case GAFR: /* GPIO Alternate Function registers */ 610 s->gafr = value; 611 break; 612 613 case GEDR: /* GPIO Edge Detect Status registers */ 614 s->status &= ~value; 615 strongarm_gpio_irq_update(s); 616 break; 617 618 default: 619 printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset); 620 } 621 } 622 623 static const MemoryRegionOps strongarm_gpio_ops = { 624 .read = strongarm_gpio_read, 625 .write = strongarm_gpio_write, 626 .endianness = DEVICE_NATIVE_ENDIAN, 627 }; 628 629 static DeviceState *strongarm_gpio_init(hwaddr base, 630 DeviceState *pic) 631 { 632 DeviceState *dev; 633 int i; 634 635 dev = qdev_create(NULL, TYPE_STRONGARM_GPIO); 636 qdev_init_nofail(dev); 637 638 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 639 for (i = 0; i < 12; i++) 640 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 641 qdev_get_gpio_in(pic, SA_PIC_GPIO0_EDGE + i)); 642 643 return dev; 644 } 645 646 static int strongarm_gpio_initfn(SysBusDevice *sbd) 647 { 648 DeviceState *dev = DEVICE(sbd); 649 StrongARMGPIOInfo *s = STRONGARM_GPIO(dev); 650 int i; 651 652 qdev_init_gpio_in(dev, strongarm_gpio_set, 28); 653 qdev_init_gpio_out(dev, s->handler, 28); 654 655 memory_region_init_io(&s->iomem, OBJECT(s), &strongarm_gpio_ops, s, 656 "gpio", 0x1000); 657 658 sysbus_init_mmio(sbd, &s->iomem); 659 for (i = 0; i < 11; i++) { 660 sysbus_init_irq(sbd, &s->irqs[i]); 661 } 662 sysbus_init_irq(sbd, &s->irqX); 663 664 return 0; 665 } 666 667 static const VMStateDescription vmstate_strongarm_gpio_regs = { 668 .name = "strongarm-gpio", 669 .version_id = 0, 670 .minimum_version_id = 0, 671 .fields = (VMStateField[]) { 672 VMSTATE_UINT32(ilevel, StrongARMGPIOInfo), 673 VMSTATE_UINT32(olevel, StrongARMGPIOInfo), 674 VMSTATE_UINT32(dir, StrongARMGPIOInfo), 675 VMSTATE_UINT32(rising, StrongARMGPIOInfo), 676 VMSTATE_UINT32(falling, StrongARMGPIOInfo), 677 VMSTATE_UINT32(status, StrongARMGPIOInfo), 678 VMSTATE_UINT32(gafr, StrongARMGPIOInfo), 679 VMSTATE_UINT32(prev_level, StrongARMGPIOInfo), 680 VMSTATE_END_OF_LIST(), 681 }, 682 }; 683 684 static void strongarm_gpio_class_init(ObjectClass *klass, void *data) 685 { 686 DeviceClass *dc = DEVICE_CLASS(klass); 687 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 688 689 k->init = strongarm_gpio_initfn; 690 dc->desc = "StrongARM GPIO controller"; 691 dc->vmsd = &vmstate_strongarm_gpio_regs; 692 } 693 694 static const TypeInfo strongarm_gpio_info = { 695 .name = TYPE_STRONGARM_GPIO, 696 .parent = TYPE_SYS_BUS_DEVICE, 697 .instance_size = sizeof(StrongARMGPIOInfo), 698 .class_init = strongarm_gpio_class_init, 699 }; 700 701 /* Peripheral Pin Controller */ 702 #define PPDR 0x00 703 #define PPSR 0x04 704 #define PPAR 0x08 705 #define PSDR 0x0c 706 #define PPFR 0x10 707 708 #define TYPE_STRONGARM_PPC "strongarm-ppc" 709 #define STRONGARM_PPC(obj) \ 710 OBJECT_CHECK(StrongARMPPCInfo, (obj), TYPE_STRONGARM_PPC) 711 712 typedef struct StrongARMPPCInfo StrongARMPPCInfo; 713 struct StrongARMPPCInfo { 714 SysBusDevice parent_obj; 715 716 MemoryRegion iomem; 717 qemu_irq handler[28]; 718 719 uint32_t ilevel; 720 uint32_t olevel; 721 uint32_t dir; 722 uint32_t ppar; 723 uint32_t psdr; 724 uint32_t ppfr; 725 726 uint32_t prev_level; 727 }; 728 729 static void strongarm_ppc_set(void *opaque, int line, int level) 730 { 731 StrongARMPPCInfo *s = opaque; 732 733 if (level) { 734 s->ilevel |= 1 << line; 735 } else { 736 s->ilevel &= ~(1 << line); 737 } 738 } 739 740 static void strongarm_ppc_handler_update(StrongARMPPCInfo *s) 741 { 742 uint32_t level, diff; 743 int bit; 744 745 level = s->olevel & s->dir; 746 747 for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) { 748 bit = ctz32(diff); 749 qemu_set_irq(s->handler[bit], (level >> bit) & 1); 750 } 751 752 s->prev_level = level; 753 } 754 755 static uint64_t strongarm_ppc_read(void *opaque, hwaddr offset, 756 unsigned size) 757 { 758 StrongARMPPCInfo *s = opaque; 759 760 switch (offset) { 761 case PPDR: /* PPC Pin Direction registers */ 762 return s->dir | ~0x3fffff; 763 764 case PPSR: /* PPC Pin State registers */ 765 return (s->olevel & s->dir) | 766 (s->ilevel & ~s->dir) | 767 ~0x3fffff; 768 769 case PPAR: 770 return s->ppar | ~0x41000; 771 772 case PSDR: 773 return s->psdr; 774 775 case PPFR: 776 return s->ppfr | ~0x7f001; 777 778 default: 779 printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset); 780 } 781 782 return 0; 783 } 784 785 static void strongarm_ppc_write(void *opaque, hwaddr offset, 786 uint64_t value, unsigned size) 787 { 788 StrongARMPPCInfo *s = opaque; 789 790 switch (offset) { 791 case PPDR: /* PPC Pin Direction registers */ 792 s->dir = value & 0x3fffff; 793 strongarm_ppc_handler_update(s); 794 break; 795 796 case PPSR: /* PPC Pin State registers */ 797 s->olevel = value & s->dir & 0x3fffff; 798 strongarm_ppc_handler_update(s); 799 break; 800 801 case PPAR: 802 s->ppar = value & 0x41000; 803 break; 804 805 case PSDR: 806 s->psdr = value & 0x3fffff; 807 break; 808 809 case PPFR: 810 s->ppfr = value & 0x7f001; 811 break; 812 813 default: 814 printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset); 815 } 816 } 817 818 static const MemoryRegionOps strongarm_ppc_ops = { 819 .read = strongarm_ppc_read, 820 .write = strongarm_ppc_write, 821 .endianness = DEVICE_NATIVE_ENDIAN, 822 }; 823 824 static int strongarm_ppc_init(SysBusDevice *sbd) 825 { 826 DeviceState *dev = DEVICE(sbd); 827 StrongARMPPCInfo *s = STRONGARM_PPC(dev); 828 829 qdev_init_gpio_in(dev, strongarm_ppc_set, 22); 830 qdev_init_gpio_out(dev, s->handler, 22); 831 832 memory_region_init_io(&s->iomem, OBJECT(s), &strongarm_ppc_ops, s, 833 "ppc", 0x1000); 834 835 sysbus_init_mmio(sbd, &s->iomem); 836 837 return 0; 838 } 839 840 static const VMStateDescription vmstate_strongarm_ppc_regs = { 841 .name = "strongarm-ppc", 842 .version_id = 0, 843 .minimum_version_id = 0, 844 .fields = (VMStateField[]) { 845 VMSTATE_UINT32(ilevel, StrongARMPPCInfo), 846 VMSTATE_UINT32(olevel, StrongARMPPCInfo), 847 VMSTATE_UINT32(dir, StrongARMPPCInfo), 848 VMSTATE_UINT32(ppar, StrongARMPPCInfo), 849 VMSTATE_UINT32(psdr, StrongARMPPCInfo), 850 VMSTATE_UINT32(ppfr, StrongARMPPCInfo), 851 VMSTATE_UINT32(prev_level, StrongARMPPCInfo), 852 VMSTATE_END_OF_LIST(), 853 }, 854 }; 855 856 static void strongarm_ppc_class_init(ObjectClass *klass, void *data) 857 { 858 DeviceClass *dc = DEVICE_CLASS(klass); 859 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 860 861 k->init = strongarm_ppc_init; 862 dc->desc = "StrongARM PPC controller"; 863 dc->vmsd = &vmstate_strongarm_ppc_regs; 864 } 865 866 static const TypeInfo strongarm_ppc_info = { 867 .name = TYPE_STRONGARM_PPC, 868 .parent = TYPE_SYS_BUS_DEVICE, 869 .instance_size = sizeof(StrongARMPPCInfo), 870 .class_init = strongarm_ppc_class_init, 871 }; 872 873 /* UART Ports */ 874 #define UTCR0 0x00 875 #define UTCR1 0x04 876 #define UTCR2 0x08 877 #define UTCR3 0x0c 878 #define UTDR 0x14 879 #define UTSR0 0x1c 880 #define UTSR1 0x20 881 882 #define UTCR0_PE (1 << 0) /* Parity enable */ 883 #define UTCR0_OES (1 << 1) /* Even parity */ 884 #define UTCR0_SBS (1 << 2) /* 2 stop bits */ 885 #define UTCR0_DSS (1 << 3) /* 8-bit data */ 886 887 #define UTCR3_RXE (1 << 0) /* Rx enable */ 888 #define UTCR3_TXE (1 << 1) /* Tx enable */ 889 #define UTCR3_BRK (1 << 2) /* Force Break */ 890 #define UTCR3_RIE (1 << 3) /* Rx int enable */ 891 #define UTCR3_TIE (1 << 4) /* Tx int enable */ 892 #define UTCR3_LBM (1 << 5) /* Loopback */ 893 894 #define UTSR0_TFS (1 << 0) /* Tx FIFO nearly empty */ 895 #define UTSR0_RFS (1 << 1) /* Rx FIFO nearly full */ 896 #define UTSR0_RID (1 << 2) /* Receiver Idle */ 897 #define UTSR0_RBB (1 << 3) /* Receiver begin break */ 898 #define UTSR0_REB (1 << 4) /* Receiver end break */ 899 #define UTSR0_EIF (1 << 5) /* Error in FIFO */ 900 901 #define UTSR1_RNE (1 << 1) /* Receive FIFO not empty */ 902 #define UTSR1_TNF (1 << 2) /* Transmit FIFO not full */ 903 #define UTSR1_PRE (1 << 3) /* Parity error */ 904 #define UTSR1_FRE (1 << 4) /* Frame error */ 905 #define UTSR1_ROR (1 << 5) /* Receive Over Run */ 906 907 #define RX_FIFO_PRE (1 << 8) 908 #define RX_FIFO_FRE (1 << 9) 909 #define RX_FIFO_ROR (1 << 10) 910 911 #define TYPE_STRONGARM_UART "strongarm-uart" 912 #define STRONGARM_UART(obj) \ 913 OBJECT_CHECK(StrongARMUARTState, (obj), TYPE_STRONGARM_UART) 914 915 typedef struct StrongARMUARTState { 916 SysBusDevice parent_obj; 917 918 MemoryRegion iomem; 919 CharDriverState *chr; 920 qemu_irq irq; 921 922 uint8_t utcr0; 923 uint16_t brd; 924 uint8_t utcr3; 925 uint8_t utsr0; 926 uint8_t utsr1; 927 928 uint8_t tx_fifo[8]; 929 uint8_t tx_start; 930 uint8_t tx_len; 931 uint16_t rx_fifo[12]; /* value + error flags in high bits */ 932 uint8_t rx_start; 933 uint8_t rx_len; 934 935 uint64_t char_transmit_time; /* time to transmit a char in ticks*/ 936 bool wait_break_end; 937 QEMUTimer *rx_timeout_timer; 938 QEMUTimer *tx_timer; 939 } StrongARMUARTState; 940 941 static void strongarm_uart_update_status(StrongARMUARTState *s) 942 { 943 uint16_t utsr1 = 0; 944 945 if (s->tx_len != 8) { 946 utsr1 |= UTSR1_TNF; 947 } 948 949 if (s->rx_len != 0) { 950 uint16_t ent = s->rx_fifo[s->rx_start]; 951 952 utsr1 |= UTSR1_RNE; 953 if (ent & RX_FIFO_PRE) { 954 s->utsr1 |= UTSR1_PRE; 955 } 956 if (ent & RX_FIFO_FRE) { 957 s->utsr1 |= UTSR1_FRE; 958 } 959 if (ent & RX_FIFO_ROR) { 960 s->utsr1 |= UTSR1_ROR; 961 } 962 } 963 964 s->utsr1 = utsr1; 965 } 966 967 static void strongarm_uart_update_int_status(StrongARMUARTState *s) 968 { 969 uint16_t utsr0 = s->utsr0 & 970 (UTSR0_REB | UTSR0_RBB | UTSR0_RID); 971 int i; 972 973 if ((s->utcr3 & UTCR3_TXE) && 974 (s->utcr3 & UTCR3_TIE) && 975 s->tx_len <= 4) { 976 utsr0 |= UTSR0_TFS; 977 } 978 979 if ((s->utcr3 & UTCR3_RXE) && 980 (s->utcr3 & UTCR3_RIE) && 981 s->rx_len > 4) { 982 utsr0 |= UTSR0_RFS; 983 } 984 985 for (i = 0; i < s->rx_len && i < 4; i++) 986 if (s->rx_fifo[(s->rx_start + i) % 12] & ~0xff) { 987 utsr0 |= UTSR0_EIF; 988 break; 989 } 990 991 s->utsr0 = utsr0; 992 qemu_set_irq(s->irq, utsr0); 993 } 994 995 static void strongarm_uart_update_parameters(StrongARMUARTState *s) 996 { 997 int speed, parity, data_bits, stop_bits, frame_size; 998 QEMUSerialSetParams ssp; 999 1000 /* Start bit. */ 1001 frame_size = 1; 1002 if (s->utcr0 & UTCR0_PE) { 1003 /* Parity bit. */ 1004 frame_size++; 1005 if (s->utcr0 & UTCR0_OES) { 1006 parity = 'E'; 1007 } else { 1008 parity = 'O'; 1009 } 1010 } else { 1011 parity = 'N'; 1012 } 1013 if (s->utcr0 & UTCR0_SBS) { 1014 stop_bits = 2; 1015 } else { 1016 stop_bits = 1; 1017 } 1018 1019 data_bits = (s->utcr0 & UTCR0_DSS) ? 8 : 7; 1020 frame_size += data_bits + stop_bits; 1021 speed = 3686400 / 16 / (s->brd + 1); 1022 ssp.speed = speed; 1023 ssp.parity = parity; 1024 ssp.data_bits = data_bits; 1025 ssp.stop_bits = stop_bits; 1026 s->char_transmit_time = (get_ticks_per_sec() / speed) * frame_size; 1027 if (s->chr) { 1028 qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); 1029 } 1030 1031 DPRINTF(stderr, "%s speed=%d parity=%c data=%d stop=%d\n", s->chr->label, 1032 speed, parity, data_bits, stop_bits); 1033 } 1034 1035 static void strongarm_uart_rx_to(void *opaque) 1036 { 1037 StrongARMUARTState *s = opaque; 1038 1039 if (s->rx_len) { 1040 s->utsr0 |= UTSR0_RID; 1041 strongarm_uart_update_int_status(s); 1042 } 1043 } 1044 1045 static void strongarm_uart_rx_push(StrongARMUARTState *s, uint16_t c) 1046 { 1047 if ((s->utcr3 & UTCR3_RXE) == 0) { 1048 /* rx disabled */ 1049 return; 1050 } 1051 1052 if (s->wait_break_end) { 1053 s->utsr0 |= UTSR0_REB; 1054 s->wait_break_end = false; 1055 } 1056 1057 if (s->rx_len < 12) { 1058 s->rx_fifo[(s->rx_start + s->rx_len) % 12] = c; 1059 s->rx_len++; 1060 } else 1061 s->rx_fifo[(s->rx_start + 11) % 12] |= RX_FIFO_ROR; 1062 } 1063 1064 static int strongarm_uart_can_receive(void *opaque) 1065 { 1066 StrongARMUARTState *s = opaque; 1067 1068 if (s->rx_len == 12) { 1069 return 0; 1070 } 1071 /* It's best not to get more than 2/3 of RX FIFO, so advertise that much */ 1072 if (s->rx_len < 8) { 1073 return 8 - s->rx_len; 1074 } 1075 return 1; 1076 } 1077 1078 static void strongarm_uart_receive(void *opaque, const uint8_t *buf, int size) 1079 { 1080 StrongARMUARTState *s = opaque; 1081 int i; 1082 1083 for (i = 0; i < size; i++) { 1084 strongarm_uart_rx_push(s, buf[i]); 1085 } 1086 1087 /* call the timeout receive callback in 3 char transmit time */ 1088 timer_mod(s->rx_timeout_timer, 1089 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 3); 1090 1091 strongarm_uart_update_status(s); 1092 strongarm_uart_update_int_status(s); 1093 } 1094 1095 static void strongarm_uart_event(void *opaque, int event) 1096 { 1097 StrongARMUARTState *s = opaque; 1098 if (event == CHR_EVENT_BREAK) { 1099 s->utsr0 |= UTSR0_RBB; 1100 strongarm_uart_rx_push(s, RX_FIFO_FRE); 1101 s->wait_break_end = true; 1102 strongarm_uart_update_status(s); 1103 strongarm_uart_update_int_status(s); 1104 } 1105 } 1106 1107 static void strongarm_uart_tx(void *opaque) 1108 { 1109 StrongARMUARTState *s = opaque; 1110 uint64_t new_xmit_ts = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 1111 1112 if (s->utcr3 & UTCR3_LBM) /* loopback */ { 1113 strongarm_uart_receive(s, &s->tx_fifo[s->tx_start], 1); 1114 } else if (s->chr) { 1115 qemu_chr_fe_write(s->chr, &s->tx_fifo[s->tx_start], 1); 1116 } 1117 1118 s->tx_start = (s->tx_start + 1) % 8; 1119 s->tx_len--; 1120 if (s->tx_len) { 1121 timer_mod(s->tx_timer, new_xmit_ts + s->char_transmit_time); 1122 } 1123 strongarm_uart_update_status(s); 1124 strongarm_uart_update_int_status(s); 1125 } 1126 1127 static uint64_t strongarm_uart_read(void *opaque, hwaddr addr, 1128 unsigned size) 1129 { 1130 StrongARMUARTState *s = opaque; 1131 uint16_t ret; 1132 1133 switch (addr) { 1134 case UTCR0: 1135 return s->utcr0; 1136 1137 case UTCR1: 1138 return s->brd >> 8; 1139 1140 case UTCR2: 1141 return s->brd & 0xff; 1142 1143 case UTCR3: 1144 return s->utcr3; 1145 1146 case UTDR: 1147 if (s->rx_len != 0) { 1148 ret = s->rx_fifo[s->rx_start]; 1149 s->rx_start = (s->rx_start + 1) % 12; 1150 s->rx_len--; 1151 strongarm_uart_update_status(s); 1152 strongarm_uart_update_int_status(s); 1153 return ret; 1154 } 1155 return 0; 1156 1157 case UTSR0: 1158 return s->utsr0; 1159 1160 case UTSR1: 1161 return s->utsr1; 1162 1163 default: 1164 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr); 1165 return 0; 1166 } 1167 } 1168 1169 static void strongarm_uart_write(void *opaque, hwaddr addr, 1170 uint64_t value, unsigned size) 1171 { 1172 StrongARMUARTState *s = opaque; 1173 1174 switch (addr) { 1175 case UTCR0: 1176 s->utcr0 = value & 0x7f; 1177 strongarm_uart_update_parameters(s); 1178 break; 1179 1180 case UTCR1: 1181 s->brd = (s->brd & 0xff) | ((value & 0xf) << 8); 1182 strongarm_uart_update_parameters(s); 1183 break; 1184 1185 case UTCR2: 1186 s->brd = (s->brd & 0xf00) | (value & 0xff); 1187 strongarm_uart_update_parameters(s); 1188 break; 1189 1190 case UTCR3: 1191 s->utcr3 = value & 0x3f; 1192 if ((s->utcr3 & UTCR3_RXE) == 0) { 1193 s->rx_len = 0; 1194 } 1195 if ((s->utcr3 & UTCR3_TXE) == 0) { 1196 s->tx_len = 0; 1197 } 1198 strongarm_uart_update_status(s); 1199 strongarm_uart_update_int_status(s); 1200 break; 1201 1202 case UTDR: 1203 if ((s->utcr3 & UTCR3_TXE) && s->tx_len != 8) { 1204 s->tx_fifo[(s->tx_start + s->tx_len) % 8] = value; 1205 s->tx_len++; 1206 strongarm_uart_update_status(s); 1207 strongarm_uart_update_int_status(s); 1208 if (s->tx_len == 1) { 1209 strongarm_uart_tx(s); 1210 } 1211 } 1212 break; 1213 1214 case UTSR0: 1215 s->utsr0 = s->utsr0 & ~(value & 1216 (UTSR0_REB | UTSR0_RBB | UTSR0_RID)); 1217 strongarm_uart_update_int_status(s); 1218 break; 1219 1220 default: 1221 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr); 1222 } 1223 } 1224 1225 static const MemoryRegionOps strongarm_uart_ops = { 1226 .read = strongarm_uart_read, 1227 .write = strongarm_uart_write, 1228 .endianness = DEVICE_NATIVE_ENDIAN, 1229 }; 1230 1231 static int strongarm_uart_init(SysBusDevice *dev) 1232 { 1233 StrongARMUARTState *s = STRONGARM_UART(dev); 1234 1235 memory_region_init_io(&s->iomem, OBJECT(s), &strongarm_uart_ops, s, 1236 "uart", 0x10000); 1237 sysbus_init_mmio(dev, &s->iomem); 1238 sysbus_init_irq(dev, &s->irq); 1239 1240 s->rx_timeout_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, strongarm_uart_rx_to, s); 1241 s->tx_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, strongarm_uart_tx, s); 1242 1243 if (s->chr) { 1244 qemu_chr_add_handlers(s->chr, 1245 strongarm_uart_can_receive, 1246 strongarm_uart_receive, 1247 strongarm_uart_event, 1248 s); 1249 } 1250 1251 return 0; 1252 } 1253 1254 static void strongarm_uart_reset(DeviceState *dev) 1255 { 1256 StrongARMUARTState *s = STRONGARM_UART(dev); 1257 1258 s->utcr0 = UTCR0_DSS; /* 8 data, no parity */ 1259 s->brd = 23; /* 9600 */ 1260 /* enable send & recv - this actually violates spec */ 1261 s->utcr3 = UTCR3_TXE | UTCR3_RXE; 1262 1263 s->rx_len = s->tx_len = 0; 1264 1265 strongarm_uart_update_parameters(s); 1266 strongarm_uart_update_status(s); 1267 strongarm_uart_update_int_status(s); 1268 } 1269 1270 static int strongarm_uart_post_load(void *opaque, int version_id) 1271 { 1272 StrongARMUARTState *s = opaque; 1273 1274 strongarm_uart_update_parameters(s); 1275 strongarm_uart_update_status(s); 1276 strongarm_uart_update_int_status(s); 1277 1278 /* tx and restart timer */ 1279 if (s->tx_len) { 1280 strongarm_uart_tx(s); 1281 } 1282 1283 /* restart rx timeout timer */ 1284 if (s->rx_len) { 1285 timer_mod(s->rx_timeout_timer, 1286 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 3); 1287 } 1288 1289 return 0; 1290 } 1291 1292 static const VMStateDescription vmstate_strongarm_uart_regs = { 1293 .name = "strongarm-uart", 1294 .version_id = 0, 1295 .minimum_version_id = 0, 1296 .post_load = strongarm_uart_post_load, 1297 .fields = (VMStateField[]) { 1298 VMSTATE_UINT8(utcr0, StrongARMUARTState), 1299 VMSTATE_UINT16(brd, StrongARMUARTState), 1300 VMSTATE_UINT8(utcr3, StrongARMUARTState), 1301 VMSTATE_UINT8(utsr0, StrongARMUARTState), 1302 VMSTATE_UINT8_ARRAY(tx_fifo, StrongARMUARTState, 8), 1303 VMSTATE_UINT8(tx_start, StrongARMUARTState), 1304 VMSTATE_UINT8(tx_len, StrongARMUARTState), 1305 VMSTATE_UINT16_ARRAY(rx_fifo, StrongARMUARTState, 12), 1306 VMSTATE_UINT8(rx_start, StrongARMUARTState), 1307 VMSTATE_UINT8(rx_len, StrongARMUARTState), 1308 VMSTATE_BOOL(wait_break_end, StrongARMUARTState), 1309 VMSTATE_END_OF_LIST(), 1310 }, 1311 }; 1312 1313 static Property strongarm_uart_properties[] = { 1314 DEFINE_PROP_CHR("chardev", StrongARMUARTState, chr), 1315 DEFINE_PROP_END_OF_LIST(), 1316 }; 1317 1318 static void strongarm_uart_class_init(ObjectClass *klass, void *data) 1319 { 1320 DeviceClass *dc = DEVICE_CLASS(klass); 1321 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 1322 1323 k->init = strongarm_uart_init; 1324 dc->desc = "StrongARM UART controller"; 1325 dc->reset = strongarm_uart_reset; 1326 dc->vmsd = &vmstate_strongarm_uart_regs; 1327 dc->props = strongarm_uart_properties; 1328 } 1329 1330 static const TypeInfo strongarm_uart_info = { 1331 .name = TYPE_STRONGARM_UART, 1332 .parent = TYPE_SYS_BUS_DEVICE, 1333 .instance_size = sizeof(StrongARMUARTState), 1334 .class_init = strongarm_uart_class_init, 1335 }; 1336 1337 /* Synchronous Serial Ports */ 1338 1339 #define TYPE_STRONGARM_SSP "strongarm-ssp" 1340 #define STRONGARM_SSP(obj) \ 1341 OBJECT_CHECK(StrongARMSSPState, (obj), TYPE_STRONGARM_SSP) 1342 1343 typedef struct StrongARMSSPState { 1344 SysBusDevice parent_obj; 1345 1346 MemoryRegion iomem; 1347 qemu_irq irq; 1348 SSIBus *bus; 1349 1350 uint16_t sscr[2]; 1351 uint16_t sssr; 1352 1353 uint16_t rx_fifo[8]; 1354 uint8_t rx_level; 1355 uint8_t rx_start; 1356 } StrongARMSSPState; 1357 1358 #define SSCR0 0x60 /* SSP Control register 0 */ 1359 #define SSCR1 0x64 /* SSP Control register 1 */ 1360 #define SSDR 0x6c /* SSP Data register */ 1361 #define SSSR 0x74 /* SSP Status register */ 1362 1363 /* Bitfields for above registers */ 1364 #define SSCR0_SPI(x) (((x) & 0x30) == 0x00) 1365 #define SSCR0_SSP(x) (((x) & 0x30) == 0x10) 1366 #define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20) 1367 #define SSCR0_PSP(x) (((x) & 0x30) == 0x30) 1368 #define SSCR0_SSE (1 << 7) 1369 #define SSCR0_DSS(x) (((x) & 0xf) + 1) 1370 #define SSCR1_RIE (1 << 0) 1371 #define SSCR1_TIE (1 << 1) 1372 #define SSCR1_LBM (1 << 2) 1373 #define SSSR_TNF (1 << 2) 1374 #define SSSR_RNE (1 << 3) 1375 #define SSSR_TFS (1 << 5) 1376 #define SSSR_RFS (1 << 6) 1377 #define SSSR_ROR (1 << 7) 1378 #define SSSR_RW 0x0080 1379 1380 static void strongarm_ssp_int_update(StrongARMSSPState *s) 1381 { 1382 int level = 0; 1383 1384 level |= (s->sssr & SSSR_ROR); 1385 level |= (s->sssr & SSSR_RFS) && (s->sscr[1] & SSCR1_RIE); 1386 level |= (s->sssr & SSSR_TFS) && (s->sscr[1] & SSCR1_TIE); 1387 qemu_set_irq(s->irq, level); 1388 } 1389 1390 static void strongarm_ssp_fifo_update(StrongARMSSPState *s) 1391 { 1392 s->sssr &= ~SSSR_TFS; 1393 s->sssr &= ~SSSR_TNF; 1394 if (s->sscr[0] & SSCR0_SSE) { 1395 if (s->rx_level >= 4) { 1396 s->sssr |= SSSR_RFS; 1397 } else { 1398 s->sssr &= ~SSSR_RFS; 1399 } 1400 if (s->rx_level) { 1401 s->sssr |= SSSR_RNE; 1402 } else { 1403 s->sssr &= ~SSSR_RNE; 1404 } 1405 /* TX FIFO is never filled, so it is always in underrun 1406 condition if SSP is enabled */ 1407 s->sssr |= SSSR_TFS; 1408 s->sssr |= SSSR_TNF; 1409 } 1410 1411 strongarm_ssp_int_update(s); 1412 } 1413 1414 static uint64_t strongarm_ssp_read(void *opaque, hwaddr addr, 1415 unsigned size) 1416 { 1417 StrongARMSSPState *s = opaque; 1418 uint32_t retval; 1419 1420 switch (addr) { 1421 case SSCR0: 1422 return s->sscr[0]; 1423 case SSCR1: 1424 return s->sscr[1]; 1425 case SSSR: 1426 return s->sssr; 1427 case SSDR: 1428 if (~s->sscr[0] & SSCR0_SSE) { 1429 return 0xffffffff; 1430 } 1431 if (s->rx_level < 1) { 1432 printf("%s: SSP Rx Underrun\n", __func__); 1433 return 0xffffffff; 1434 } 1435 s->rx_level--; 1436 retval = s->rx_fifo[s->rx_start++]; 1437 s->rx_start &= 0x7; 1438 strongarm_ssp_fifo_update(s); 1439 return retval; 1440 default: 1441 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr); 1442 break; 1443 } 1444 return 0; 1445 } 1446 1447 static void strongarm_ssp_write(void *opaque, hwaddr addr, 1448 uint64_t value, unsigned size) 1449 { 1450 StrongARMSSPState *s = opaque; 1451 1452 switch (addr) { 1453 case SSCR0: 1454 s->sscr[0] = value & 0xffbf; 1455 if ((s->sscr[0] & SSCR0_SSE) && SSCR0_DSS(value) < 4) { 1456 printf("%s: Wrong data size: %i bits\n", __func__, 1457 (int)SSCR0_DSS(value)); 1458 } 1459 if (!(value & SSCR0_SSE)) { 1460 s->sssr = 0; 1461 s->rx_level = 0; 1462 } 1463 strongarm_ssp_fifo_update(s); 1464 break; 1465 1466 case SSCR1: 1467 s->sscr[1] = value & 0x2f; 1468 if (value & SSCR1_LBM) { 1469 printf("%s: Attempt to use SSP LBM mode\n", __func__); 1470 } 1471 strongarm_ssp_fifo_update(s); 1472 break; 1473 1474 case SSSR: 1475 s->sssr &= ~(value & SSSR_RW); 1476 strongarm_ssp_int_update(s); 1477 break; 1478 1479 case SSDR: 1480 if (SSCR0_UWIRE(s->sscr[0])) { 1481 value &= 0xff; 1482 } else 1483 /* Note how 32bits overflow does no harm here */ 1484 value &= (1 << SSCR0_DSS(s->sscr[0])) - 1; 1485 1486 /* Data goes from here to the Tx FIFO and is shifted out from 1487 * there directly to the slave, no need to buffer it. 1488 */ 1489 if (s->sscr[0] & SSCR0_SSE) { 1490 uint32_t readval; 1491 if (s->sscr[1] & SSCR1_LBM) { 1492 readval = value; 1493 } else { 1494 readval = ssi_transfer(s->bus, value); 1495 } 1496 1497 if (s->rx_level < 0x08) { 1498 s->rx_fifo[(s->rx_start + s->rx_level++) & 0x7] = readval; 1499 } else { 1500 s->sssr |= SSSR_ROR; 1501 } 1502 } 1503 strongarm_ssp_fifo_update(s); 1504 break; 1505 1506 default: 1507 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr); 1508 break; 1509 } 1510 } 1511 1512 static const MemoryRegionOps strongarm_ssp_ops = { 1513 .read = strongarm_ssp_read, 1514 .write = strongarm_ssp_write, 1515 .endianness = DEVICE_NATIVE_ENDIAN, 1516 }; 1517 1518 static int strongarm_ssp_post_load(void *opaque, int version_id) 1519 { 1520 StrongARMSSPState *s = opaque; 1521 1522 strongarm_ssp_fifo_update(s); 1523 1524 return 0; 1525 } 1526 1527 static int strongarm_ssp_init(SysBusDevice *sbd) 1528 { 1529 DeviceState *dev = DEVICE(sbd); 1530 StrongARMSSPState *s = STRONGARM_SSP(dev); 1531 1532 sysbus_init_irq(sbd, &s->irq); 1533 1534 memory_region_init_io(&s->iomem, OBJECT(s), &strongarm_ssp_ops, s, 1535 "ssp", 0x1000); 1536 sysbus_init_mmio(sbd, &s->iomem); 1537 1538 s->bus = ssi_create_bus(dev, "ssi"); 1539 return 0; 1540 } 1541 1542 static void strongarm_ssp_reset(DeviceState *dev) 1543 { 1544 StrongARMSSPState *s = STRONGARM_SSP(dev); 1545 1546 s->sssr = 0x03; /* 3 bit data, SPI, disabled */ 1547 s->rx_start = 0; 1548 s->rx_level = 0; 1549 } 1550 1551 static const VMStateDescription vmstate_strongarm_ssp_regs = { 1552 .name = "strongarm-ssp", 1553 .version_id = 0, 1554 .minimum_version_id = 0, 1555 .post_load = strongarm_ssp_post_load, 1556 .fields = (VMStateField[]) { 1557 VMSTATE_UINT16_ARRAY(sscr, StrongARMSSPState, 2), 1558 VMSTATE_UINT16(sssr, StrongARMSSPState), 1559 VMSTATE_UINT16_ARRAY(rx_fifo, StrongARMSSPState, 8), 1560 VMSTATE_UINT8(rx_start, StrongARMSSPState), 1561 VMSTATE_UINT8(rx_level, StrongARMSSPState), 1562 VMSTATE_END_OF_LIST(), 1563 }, 1564 }; 1565 1566 static void strongarm_ssp_class_init(ObjectClass *klass, void *data) 1567 { 1568 DeviceClass *dc = DEVICE_CLASS(klass); 1569 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 1570 1571 k->init = strongarm_ssp_init; 1572 dc->desc = "StrongARM SSP controller"; 1573 dc->reset = strongarm_ssp_reset; 1574 dc->vmsd = &vmstate_strongarm_ssp_regs; 1575 } 1576 1577 static const TypeInfo strongarm_ssp_info = { 1578 .name = TYPE_STRONGARM_SSP, 1579 .parent = TYPE_SYS_BUS_DEVICE, 1580 .instance_size = sizeof(StrongARMSSPState), 1581 .class_init = strongarm_ssp_class_init, 1582 }; 1583 1584 /* Main CPU functions */ 1585 StrongARMState *sa1110_init(MemoryRegion *sysmem, 1586 unsigned int sdram_size, const char *rev) 1587 { 1588 StrongARMState *s; 1589 int i; 1590 1591 s = g_new0(StrongARMState, 1); 1592 1593 if (!rev) { 1594 rev = "sa1110-b5"; 1595 } 1596 1597 if (strncmp(rev, "sa1110", 6)) { 1598 error_report("Machine requires a SA1110 processor."); 1599 exit(1); 1600 } 1601 1602 s->cpu = cpu_arm_init(rev); 1603 1604 if (!s->cpu) { 1605 error_report("Unable to find CPU definition"); 1606 exit(1); 1607 } 1608 1609 memory_region_allocate_system_memory(&s->sdram, NULL, "strongarm.sdram", 1610 sdram_size); 1611 memory_region_add_subregion(sysmem, SA_SDCS0, &s->sdram); 1612 1613 s->pic = sysbus_create_varargs("strongarm_pic", 0x90050000, 1614 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ), 1615 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_FIQ), 1616 NULL); 1617 1618 sysbus_create_varargs("pxa25x-timer", 0x90000000, 1619 qdev_get_gpio_in(s->pic, SA_PIC_OSTC0), 1620 qdev_get_gpio_in(s->pic, SA_PIC_OSTC1), 1621 qdev_get_gpio_in(s->pic, SA_PIC_OSTC2), 1622 qdev_get_gpio_in(s->pic, SA_PIC_OSTC3), 1623 NULL); 1624 1625 sysbus_create_simple(TYPE_STRONGARM_RTC, 0x90010000, 1626 qdev_get_gpio_in(s->pic, SA_PIC_RTC_ALARM)); 1627 1628 s->gpio = strongarm_gpio_init(0x90040000, s->pic); 1629 1630 s->ppc = sysbus_create_varargs(TYPE_STRONGARM_PPC, 0x90060000, NULL); 1631 1632 for (i = 0; sa_serial[i].io_base; i++) { 1633 DeviceState *dev = qdev_create(NULL, TYPE_STRONGARM_UART); 1634 qdev_prop_set_chr(dev, "chardev", serial_hds[i]); 1635 qdev_init_nofail(dev); 1636 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 1637 sa_serial[i].io_base); 1638 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, 1639 qdev_get_gpio_in(s->pic, sa_serial[i].irq)); 1640 } 1641 1642 s->ssp = sysbus_create_varargs(TYPE_STRONGARM_SSP, 0x80070000, 1643 qdev_get_gpio_in(s->pic, SA_PIC_SSP), NULL); 1644 s->ssp_bus = (SSIBus *)qdev_get_child_bus(s->ssp, "ssi"); 1645 1646 return s; 1647 } 1648 1649 static void strongarm_register_types(void) 1650 { 1651 type_register_static(&strongarm_pic_info); 1652 type_register_static(&strongarm_rtc_sysbus_info); 1653 type_register_static(&strongarm_gpio_info); 1654 type_register_static(&strongarm_ppc_info); 1655 type_register_static(&strongarm_uart_info); 1656 type_register_static(&strongarm_ssp_info); 1657 } 1658 1659 type_init(strongarm_register_types) 1660