1 /* 2 * StrongARM SA-1100/SA-1110 emulation 3 * 4 * Copyright (C) 2011 Dmitry Eremin-Solenikov 5 * 6 * Largely based on StrongARM emulation: 7 * Copyright (c) 2006 Openedhand Ltd. 8 * Written by Andrzej Zaborowski <balrog@zabor.org> 9 * 10 * UART code based on QEMU 16550A UART emulation 11 * Copyright (c) 2003-2004 Fabrice Bellard 12 * Copyright (c) 2008 Citrix Systems, Inc. 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License version 2 as 16 * published by the Free Software Foundation. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License along 24 * with this program; if not, see <http://www.gnu.org/licenses/>. 25 * 26 * Contributions after 2012-01-13 are licensed under the terms of the 27 * GNU GPL, version 2 or (at your option) any later version. 28 */ 29 30 #include "qemu/osdep.h" 31 #include "cpu.h" 32 #include "hw/irq.h" 33 #include "hw/qdev-properties.h" 34 #include "hw/qdev-properties-system.h" 35 #include "hw/sysbus.h" 36 #include "migration/vmstate.h" 37 #include "strongarm.h" 38 #include "qemu/error-report.h" 39 #include "hw/arm/boot.h" 40 #include "chardev/char-fe.h" 41 #include "chardev/char-serial.h" 42 #include "sysemu/sysemu.h" 43 #include "sysemu/rtc.h" 44 #include "hw/ssi/ssi.h" 45 #include "qapi/error.h" 46 #include "qemu/cutils.h" 47 #include "qemu/log.h" 48 #include "qom/object.h" 49 50 //#define DEBUG 51 52 /* 53 TODO 54 - Implement cp15, c14 ? 55 - Implement cp15, c15 !!! (idle used in L) 56 - Implement idle mode handling/DIM 57 - Implement sleep mode/Wake sources 58 - Implement reset control 59 - Implement memory control regs 60 - PCMCIA handling 61 - Maybe support MBGNT/MBREQ 62 - DMA channels 63 - GPCLK 64 - IrDA 65 - MCP 66 - Enhance UART with modem signals 67 */ 68 69 #ifdef DEBUG 70 # define DPRINTF(format, ...) printf(format , ## __VA_ARGS__) 71 #else 72 # define DPRINTF(format, ...) do { } while (0) 73 #endif 74 75 static struct { 76 hwaddr io_base; 77 int irq; 78 } sa_serial[] = { 79 { 0x80010000, SA_PIC_UART1 }, 80 { 0x80030000, SA_PIC_UART2 }, 81 { 0x80050000, SA_PIC_UART3 }, 82 { 0, 0 } 83 }; 84 85 /* Interrupt Controller */ 86 87 #define TYPE_STRONGARM_PIC "strongarm_pic" 88 OBJECT_DECLARE_SIMPLE_TYPE(StrongARMPICState, STRONGARM_PIC) 89 90 struct StrongARMPICState { 91 SysBusDevice parent_obj; 92 93 MemoryRegion iomem; 94 qemu_irq irq; 95 qemu_irq fiq; 96 97 uint32_t pending; 98 uint32_t enabled; 99 uint32_t is_fiq; 100 uint32_t int_idle; 101 }; 102 103 #define ICIP 0x00 104 #define ICMR 0x04 105 #define ICLR 0x08 106 #define ICFP 0x10 107 #define ICPR 0x20 108 #define ICCR 0x0c 109 110 #define SA_PIC_SRCS 32 111 112 113 static void strongarm_pic_update(void *opaque) 114 { 115 StrongARMPICState *s = opaque; 116 117 /* FIXME: reflect DIM */ 118 qemu_set_irq(s->fiq, s->pending & s->enabled & s->is_fiq); 119 qemu_set_irq(s->irq, s->pending & s->enabled & ~s->is_fiq); 120 } 121 122 static void strongarm_pic_set_irq(void *opaque, int irq, int level) 123 { 124 StrongARMPICState *s = opaque; 125 126 if (level) { 127 s->pending |= 1 << irq; 128 } else { 129 s->pending &= ~(1 << irq); 130 } 131 132 strongarm_pic_update(s); 133 } 134 135 static uint64_t strongarm_pic_mem_read(void *opaque, hwaddr offset, 136 unsigned size) 137 { 138 StrongARMPICState *s = opaque; 139 140 switch (offset) { 141 case ICIP: 142 return s->pending & ~s->is_fiq & s->enabled; 143 case ICMR: 144 return s->enabled; 145 case ICLR: 146 return s->is_fiq; 147 case ICCR: 148 return s->int_idle == 0; 149 case ICFP: 150 return s->pending & s->is_fiq & s->enabled; 151 case ICPR: 152 return s->pending; 153 default: 154 printf("%s: Bad register offset 0x" HWADDR_FMT_plx "\n", 155 __func__, offset); 156 return 0; 157 } 158 } 159 160 static void strongarm_pic_mem_write(void *opaque, hwaddr offset, 161 uint64_t value, unsigned size) 162 { 163 StrongARMPICState *s = opaque; 164 165 switch (offset) { 166 case ICMR: 167 s->enabled = value; 168 break; 169 case ICLR: 170 s->is_fiq = value; 171 break; 172 case ICCR: 173 s->int_idle = (value & 1) ? 0 : ~0; 174 break; 175 default: 176 printf("%s: Bad register offset 0x" HWADDR_FMT_plx "\n", 177 __func__, offset); 178 break; 179 } 180 strongarm_pic_update(s); 181 } 182 183 static const MemoryRegionOps strongarm_pic_ops = { 184 .read = strongarm_pic_mem_read, 185 .write = strongarm_pic_mem_write, 186 .endianness = DEVICE_NATIVE_ENDIAN, 187 }; 188 189 static void strongarm_pic_initfn(Object *obj) 190 { 191 DeviceState *dev = DEVICE(obj); 192 StrongARMPICState *s = STRONGARM_PIC(obj); 193 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 194 195 qdev_init_gpio_in(dev, strongarm_pic_set_irq, SA_PIC_SRCS); 196 memory_region_init_io(&s->iomem, obj, &strongarm_pic_ops, s, 197 "pic", 0x1000); 198 sysbus_init_mmio(sbd, &s->iomem); 199 sysbus_init_irq(sbd, &s->irq); 200 sysbus_init_irq(sbd, &s->fiq); 201 } 202 203 static int strongarm_pic_post_load(void *opaque, int version_id) 204 { 205 strongarm_pic_update(opaque); 206 return 0; 207 } 208 209 static const VMStateDescription vmstate_strongarm_pic_regs = { 210 .name = "strongarm_pic", 211 .version_id = 0, 212 .minimum_version_id = 0, 213 .post_load = strongarm_pic_post_load, 214 .fields = (VMStateField[]) { 215 VMSTATE_UINT32(pending, StrongARMPICState), 216 VMSTATE_UINT32(enabled, StrongARMPICState), 217 VMSTATE_UINT32(is_fiq, StrongARMPICState), 218 VMSTATE_UINT32(int_idle, StrongARMPICState), 219 VMSTATE_END_OF_LIST(), 220 }, 221 }; 222 223 static void strongarm_pic_class_init(ObjectClass *klass, void *data) 224 { 225 DeviceClass *dc = DEVICE_CLASS(klass); 226 227 dc->desc = "StrongARM PIC"; 228 dc->vmsd = &vmstate_strongarm_pic_regs; 229 } 230 231 static const TypeInfo strongarm_pic_info = { 232 .name = TYPE_STRONGARM_PIC, 233 .parent = TYPE_SYS_BUS_DEVICE, 234 .instance_size = sizeof(StrongARMPICState), 235 .instance_init = strongarm_pic_initfn, 236 .class_init = strongarm_pic_class_init, 237 }; 238 239 /* Real-Time Clock */ 240 #define RTAR 0x00 /* RTC Alarm register */ 241 #define RCNR 0x04 /* RTC Counter register */ 242 #define RTTR 0x08 /* RTC Timer Trim register */ 243 #define RTSR 0x10 /* RTC Status register */ 244 245 #define RTSR_AL (1 << 0) /* RTC Alarm detected */ 246 #define RTSR_HZ (1 << 1) /* RTC 1Hz detected */ 247 #define RTSR_ALE (1 << 2) /* RTC Alarm enable */ 248 #define RTSR_HZE (1 << 3) /* RTC 1Hz enable */ 249 250 /* 16 LSB of RTTR are clockdiv for internal trim logic, 251 * trim delete isn't emulated, so 252 * f = 32 768 / (RTTR_trim + 1) */ 253 254 #define TYPE_STRONGARM_RTC "strongarm-rtc" 255 OBJECT_DECLARE_SIMPLE_TYPE(StrongARMRTCState, STRONGARM_RTC) 256 257 struct StrongARMRTCState { 258 SysBusDevice parent_obj; 259 260 MemoryRegion iomem; 261 uint32_t rttr; 262 uint32_t rtsr; 263 uint32_t rtar; 264 uint32_t last_rcnr; 265 int64_t last_hz; 266 QEMUTimer *rtc_alarm; 267 QEMUTimer *rtc_hz; 268 qemu_irq rtc_irq; 269 qemu_irq rtc_hz_irq; 270 }; 271 272 static inline void strongarm_rtc_int_update(StrongARMRTCState *s) 273 { 274 qemu_set_irq(s->rtc_irq, s->rtsr & RTSR_AL); 275 qemu_set_irq(s->rtc_hz_irq, s->rtsr & RTSR_HZ); 276 } 277 278 static void strongarm_rtc_hzupdate(StrongARMRTCState *s) 279 { 280 int64_t rt = qemu_clock_get_ms(rtc_clock); 281 s->last_rcnr += ((rt - s->last_hz) << 15) / 282 (1000 * ((s->rttr & 0xffff) + 1)); 283 s->last_hz = rt; 284 } 285 286 static inline void strongarm_rtc_timer_update(StrongARMRTCState *s) 287 { 288 if ((s->rtsr & RTSR_HZE) && !(s->rtsr & RTSR_HZ)) { 289 timer_mod(s->rtc_hz, s->last_hz + 1000); 290 } else { 291 timer_del(s->rtc_hz); 292 } 293 294 if ((s->rtsr & RTSR_ALE) && !(s->rtsr & RTSR_AL)) { 295 timer_mod(s->rtc_alarm, s->last_hz + 296 (((s->rtar - s->last_rcnr) * 1000 * 297 ((s->rttr & 0xffff) + 1)) >> 15)); 298 } else { 299 timer_del(s->rtc_alarm); 300 } 301 } 302 303 static inline void strongarm_rtc_alarm_tick(void *opaque) 304 { 305 StrongARMRTCState *s = opaque; 306 s->rtsr |= RTSR_AL; 307 strongarm_rtc_timer_update(s); 308 strongarm_rtc_int_update(s); 309 } 310 311 static inline void strongarm_rtc_hz_tick(void *opaque) 312 { 313 StrongARMRTCState *s = opaque; 314 s->rtsr |= RTSR_HZ; 315 strongarm_rtc_timer_update(s); 316 strongarm_rtc_int_update(s); 317 } 318 319 static uint64_t strongarm_rtc_read(void *opaque, hwaddr addr, 320 unsigned size) 321 { 322 StrongARMRTCState *s = opaque; 323 324 switch (addr) { 325 case RTTR: 326 return s->rttr; 327 case RTSR: 328 return s->rtsr; 329 case RTAR: 330 return s->rtar; 331 case RCNR: 332 return s->last_rcnr + 333 ((qemu_clock_get_ms(rtc_clock) - s->last_hz) << 15) / 334 (1000 * ((s->rttr & 0xffff) + 1)); 335 default: 336 printf("%s: Bad register 0x" HWADDR_FMT_plx "\n", __func__, addr); 337 return 0; 338 } 339 } 340 341 static void strongarm_rtc_write(void *opaque, hwaddr addr, 342 uint64_t value, unsigned size) 343 { 344 StrongARMRTCState *s = opaque; 345 uint32_t old_rtsr; 346 347 switch (addr) { 348 case RTTR: 349 strongarm_rtc_hzupdate(s); 350 s->rttr = value; 351 strongarm_rtc_timer_update(s); 352 break; 353 354 case RTSR: 355 old_rtsr = s->rtsr; 356 s->rtsr = (value & (RTSR_ALE | RTSR_HZE)) | 357 (s->rtsr & ~(value & (RTSR_AL | RTSR_HZ))); 358 359 if (s->rtsr != old_rtsr) { 360 strongarm_rtc_timer_update(s); 361 } 362 363 strongarm_rtc_int_update(s); 364 break; 365 366 case RTAR: 367 s->rtar = value; 368 strongarm_rtc_timer_update(s); 369 break; 370 371 case RCNR: 372 strongarm_rtc_hzupdate(s); 373 s->last_rcnr = value; 374 strongarm_rtc_timer_update(s); 375 break; 376 377 default: 378 printf("%s: Bad register 0x" HWADDR_FMT_plx "\n", __func__, addr); 379 } 380 } 381 382 static const MemoryRegionOps strongarm_rtc_ops = { 383 .read = strongarm_rtc_read, 384 .write = strongarm_rtc_write, 385 .endianness = DEVICE_NATIVE_ENDIAN, 386 }; 387 388 static void strongarm_rtc_init(Object *obj) 389 { 390 StrongARMRTCState *s = STRONGARM_RTC(obj); 391 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 392 struct tm tm; 393 394 s->rttr = 0x0; 395 s->rtsr = 0; 396 397 qemu_get_timedate(&tm, 0); 398 399 s->last_rcnr = (uint32_t) mktimegm(&tm); 400 s->last_hz = qemu_clock_get_ms(rtc_clock); 401 402 sysbus_init_irq(dev, &s->rtc_irq); 403 sysbus_init_irq(dev, &s->rtc_hz_irq); 404 405 memory_region_init_io(&s->iomem, obj, &strongarm_rtc_ops, s, 406 "rtc", 0x10000); 407 sysbus_init_mmio(dev, &s->iomem); 408 } 409 410 static void strongarm_rtc_realize(DeviceState *dev, Error **errp) 411 { 412 StrongARMRTCState *s = STRONGARM_RTC(dev); 413 s->rtc_alarm = timer_new_ms(rtc_clock, strongarm_rtc_alarm_tick, s); 414 s->rtc_hz = timer_new_ms(rtc_clock, strongarm_rtc_hz_tick, s); 415 } 416 417 static int strongarm_rtc_pre_save(void *opaque) 418 { 419 StrongARMRTCState *s = opaque; 420 421 strongarm_rtc_hzupdate(s); 422 423 return 0; 424 } 425 426 static int strongarm_rtc_post_load(void *opaque, int version_id) 427 { 428 StrongARMRTCState *s = opaque; 429 430 strongarm_rtc_timer_update(s); 431 strongarm_rtc_int_update(s); 432 433 return 0; 434 } 435 436 static const VMStateDescription vmstate_strongarm_rtc_regs = { 437 .name = "strongarm-rtc", 438 .version_id = 0, 439 .minimum_version_id = 0, 440 .pre_save = strongarm_rtc_pre_save, 441 .post_load = strongarm_rtc_post_load, 442 .fields = (VMStateField[]) { 443 VMSTATE_UINT32(rttr, StrongARMRTCState), 444 VMSTATE_UINT32(rtsr, StrongARMRTCState), 445 VMSTATE_UINT32(rtar, StrongARMRTCState), 446 VMSTATE_UINT32(last_rcnr, StrongARMRTCState), 447 VMSTATE_INT64(last_hz, StrongARMRTCState), 448 VMSTATE_END_OF_LIST(), 449 }, 450 }; 451 452 static void strongarm_rtc_sysbus_class_init(ObjectClass *klass, void *data) 453 { 454 DeviceClass *dc = DEVICE_CLASS(klass); 455 456 dc->desc = "StrongARM RTC Controller"; 457 dc->vmsd = &vmstate_strongarm_rtc_regs; 458 dc->realize = strongarm_rtc_realize; 459 } 460 461 static const TypeInfo strongarm_rtc_sysbus_info = { 462 .name = TYPE_STRONGARM_RTC, 463 .parent = TYPE_SYS_BUS_DEVICE, 464 .instance_size = sizeof(StrongARMRTCState), 465 .instance_init = strongarm_rtc_init, 466 .class_init = strongarm_rtc_sysbus_class_init, 467 }; 468 469 /* GPIO */ 470 #define GPLR 0x00 471 #define GPDR 0x04 472 #define GPSR 0x08 473 #define GPCR 0x0c 474 #define GRER 0x10 475 #define GFER 0x14 476 #define GEDR 0x18 477 #define GAFR 0x1c 478 479 #define TYPE_STRONGARM_GPIO "strongarm-gpio" 480 OBJECT_DECLARE_SIMPLE_TYPE(StrongARMGPIOInfo, STRONGARM_GPIO) 481 482 struct StrongARMGPIOInfo { 483 SysBusDevice busdev; 484 MemoryRegion iomem; 485 qemu_irq handler[28]; 486 qemu_irq irqs[11]; 487 qemu_irq irqX; 488 489 uint32_t ilevel; 490 uint32_t olevel; 491 uint32_t dir; 492 uint32_t rising; 493 uint32_t falling; 494 uint32_t status; 495 uint32_t gafr; 496 497 uint32_t prev_level; 498 }; 499 500 501 static void strongarm_gpio_irq_update(StrongARMGPIOInfo *s) 502 { 503 int i; 504 for (i = 0; i < 11; i++) { 505 qemu_set_irq(s->irqs[i], s->status & (1 << i)); 506 } 507 508 qemu_set_irq(s->irqX, (s->status & ~0x7ff)); 509 } 510 511 static void strongarm_gpio_set(void *opaque, int line, int level) 512 { 513 StrongARMGPIOInfo *s = opaque; 514 uint32_t mask; 515 516 mask = 1 << line; 517 518 if (level) { 519 s->status |= s->rising & mask & 520 ~s->ilevel & ~s->dir; 521 s->ilevel |= mask; 522 } else { 523 s->status |= s->falling & mask & 524 s->ilevel & ~s->dir; 525 s->ilevel &= ~mask; 526 } 527 528 if (s->status & mask) { 529 strongarm_gpio_irq_update(s); 530 } 531 } 532 533 static void strongarm_gpio_handler_update(StrongARMGPIOInfo *s) 534 { 535 uint32_t level, diff; 536 int bit; 537 538 level = s->olevel & s->dir; 539 540 for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) { 541 bit = ctz32(diff); 542 qemu_set_irq(s->handler[bit], (level >> bit) & 1); 543 } 544 545 s->prev_level = level; 546 } 547 548 static uint64_t strongarm_gpio_read(void *opaque, hwaddr offset, 549 unsigned size) 550 { 551 StrongARMGPIOInfo *s = opaque; 552 553 switch (offset) { 554 case GPDR: /* GPIO Pin-Direction registers */ 555 return s->dir; 556 557 case GPSR: /* GPIO Pin-Output Set registers */ 558 qemu_log_mask(LOG_GUEST_ERROR, 559 "strongarm GPIO: read from write only register GPSR\n"); 560 return 0; 561 562 case GPCR: /* GPIO Pin-Output Clear registers */ 563 qemu_log_mask(LOG_GUEST_ERROR, 564 "strongarm GPIO: read from write only register GPCR\n"); 565 return 0; 566 567 case GRER: /* GPIO Rising-Edge Detect Enable registers */ 568 return s->rising; 569 570 case GFER: /* GPIO Falling-Edge Detect Enable registers */ 571 return s->falling; 572 573 case GAFR: /* GPIO Alternate Function registers */ 574 return s->gafr; 575 576 case GPLR: /* GPIO Pin-Level registers */ 577 return (s->olevel & s->dir) | 578 (s->ilevel & ~s->dir); 579 580 case GEDR: /* GPIO Edge Detect Status registers */ 581 return s->status; 582 583 default: 584 printf("%s: Bad offset 0x" HWADDR_FMT_plx "\n", __func__, offset); 585 } 586 587 return 0; 588 } 589 590 static void strongarm_gpio_write(void *opaque, hwaddr offset, 591 uint64_t value, unsigned size) 592 { 593 StrongARMGPIOInfo *s = opaque; 594 595 switch (offset) { 596 case GPDR: /* GPIO Pin-Direction registers */ 597 s->dir = value & 0x0fffffff; 598 strongarm_gpio_handler_update(s); 599 break; 600 601 case GPSR: /* GPIO Pin-Output Set registers */ 602 s->olevel |= value & 0x0fffffff; 603 strongarm_gpio_handler_update(s); 604 break; 605 606 case GPCR: /* GPIO Pin-Output Clear registers */ 607 s->olevel &= ~value; 608 strongarm_gpio_handler_update(s); 609 break; 610 611 case GRER: /* GPIO Rising-Edge Detect Enable registers */ 612 s->rising = value; 613 break; 614 615 case GFER: /* GPIO Falling-Edge Detect Enable registers */ 616 s->falling = value; 617 break; 618 619 case GAFR: /* GPIO Alternate Function registers */ 620 s->gafr = value; 621 break; 622 623 case GEDR: /* GPIO Edge Detect Status registers */ 624 s->status &= ~value; 625 strongarm_gpio_irq_update(s); 626 break; 627 628 default: 629 printf("%s: Bad offset 0x" HWADDR_FMT_plx "\n", __func__, offset); 630 } 631 } 632 633 static const MemoryRegionOps strongarm_gpio_ops = { 634 .read = strongarm_gpio_read, 635 .write = strongarm_gpio_write, 636 .endianness = DEVICE_NATIVE_ENDIAN, 637 }; 638 639 static DeviceState *strongarm_gpio_init(hwaddr base, 640 DeviceState *pic) 641 { 642 DeviceState *dev; 643 int i; 644 645 dev = qdev_new(TYPE_STRONGARM_GPIO); 646 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 647 648 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 649 for (i = 0; i < 12; i++) 650 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 651 qdev_get_gpio_in(pic, SA_PIC_GPIO0_EDGE + i)); 652 653 return dev; 654 } 655 656 static void strongarm_gpio_initfn(Object *obj) 657 { 658 DeviceState *dev = DEVICE(obj); 659 StrongARMGPIOInfo *s = STRONGARM_GPIO(obj); 660 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 661 int i; 662 663 qdev_init_gpio_in(dev, strongarm_gpio_set, 28); 664 qdev_init_gpio_out(dev, s->handler, 28); 665 666 memory_region_init_io(&s->iomem, obj, &strongarm_gpio_ops, s, 667 "gpio", 0x1000); 668 669 sysbus_init_mmio(sbd, &s->iomem); 670 for (i = 0; i < 11; i++) { 671 sysbus_init_irq(sbd, &s->irqs[i]); 672 } 673 sysbus_init_irq(sbd, &s->irqX); 674 } 675 676 static const VMStateDescription vmstate_strongarm_gpio_regs = { 677 .name = "strongarm-gpio", 678 .version_id = 0, 679 .minimum_version_id = 0, 680 .fields = (VMStateField[]) { 681 VMSTATE_UINT32(ilevel, StrongARMGPIOInfo), 682 VMSTATE_UINT32(olevel, StrongARMGPIOInfo), 683 VMSTATE_UINT32(dir, StrongARMGPIOInfo), 684 VMSTATE_UINT32(rising, StrongARMGPIOInfo), 685 VMSTATE_UINT32(falling, StrongARMGPIOInfo), 686 VMSTATE_UINT32(status, StrongARMGPIOInfo), 687 VMSTATE_UINT32(gafr, StrongARMGPIOInfo), 688 VMSTATE_UINT32(prev_level, StrongARMGPIOInfo), 689 VMSTATE_END_OF_LIST(), 690 }, 691 }; 692 693 static void strongarm_gpio_class_init(ObjectClass *klass, void *data) 694 { 695 DeviceClass *dc = DEVICE_CLASS(klass); 696 697 dc->desc = "StrongARM GPIO controller"; 698 dc->vmsd = &vmstate_strongarm_gpio_regs; 699 } 700 701 static const TypeInfo strongarm_gpio_info = { 702 .name = TYPE_STRONGARM_GPIO, 703 .parent = TYPE_SYS_BUS_DEVICE, 704 .instance_size = sizeof(StrongARMGPIOInfo), 705 .instance_init = strongarm_gpio_initfn, 706 .class_init = strongarm_gpio_class_init, 707 }; 708 709 /* Peripheral Pin Controller */ 710 #define PPDR 0x00 711 #define PPSR 0x04 712 #define PPAR 0x08 713 #define PSDR 0x0c 714 #define PPFR 0x10 715 716 #define TYPE_STRONGARM_PPC "strongarm-ppc" 717 OBJECT_DECLARE_SIMPLE_TYPE(StrongARMPPCInfo, STRONGARM_PPC) 718 719 struct StrongARMPPCInfo { 720 SysBusDevice parent_obj; 721 722 MemoryRegion iomem; 723 qemu_irq handler[28]; 724 725 uint32_t ilevel; 726 uint32_t olevel; 727 uint32_t dir; 728 uint32_t ppar; 729 uint32_t psdr; 730 uint32_t ppfr; 731 732 uint32_t prev_level; 733 }; 734 735 static void strongarm_ppc_set(void *opaque, int line, int level) 736 { 737 StrongARMPPCInfo *s = opaque; 738 739 if (level) { 740 s->ilevel |= 1 << line; 741 } else { 742 s->ilevel &= ~(1 << line); 743 } 744 } 745 746 static void strongarm_ppc_handler_update(StrongARMPPCInfo *s) 747 { 748 uint32_t level, diff; 749 int bit; 750 751 level = s->olevel & s->dir; 752 753 for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) { 754 bit = ctz32(diff); 755 qemu_set_irq(s->handler[bit], (level >> bit) & 1); 756 } 757 758 s->prev_level = level; 759 } 760 761 static uint64_t strongarm_ppc_read(void *opaque, hwaddr offset, 762 unsigned size) 763 { 764 StrongARMPPCInfo *s = opaque; 765 766 switch (offset) { 767 case PPDR: /* PPC Pin Direction registers */ 768 return s->dir | ~0x3fffff; 769 770 case PPSR: /* PPC Pin State registers */ 771 return (s->olevel & s->dir) | 772 (s->ilevel & ~s->dir) | 773 ~0x3fffff; 774 775 case PPAR: 776 return s->ppar | ~0x41000; 777 778 case PSDR: 779 return s->psdr; 780 781 case PPFR: 782 return s->ppfr | ~0x7f001; 783 784 default: 785 printf("%s: Bad offset 0x" HWADDR_FMT_plx "\n", __func__, offset); 786 } 787 788 return 0; 789 } 790 791 static void strongarm_ppc_write(void *opaque, hwaddr offset, 792 uint64_t value, unsigned size) 793 { 794 StrongARMPPCInfo *s = opaque; 795 796 switch (offset) { 797 case PPDR: /* PPC Pin Direction registers */ 798 s->dir = value & 0x3fffff; 799 strongarm_ppc_handler_update(s); 800 break; 801 802 case PPSR: /* PPC Pin State registers */ 803 s->olevel = value & s->dir & 0x3fffff; 804 strongarm_ppc_handler_update(s); 805 break; 806 807 case PPAR: 808 s->ppar = value & 0x41000; 809 break; 810 811 case PSDR: 812 s->psdr = value & 0x3fffff; 813 break; 814 815 case PPFR: 816 s->ppfr = value & 0x7f001; 817 break; 818 819 default: 820 printf("%s: Bad offset 0x" HWADDR_FMT_plx "\n", __func__, offset); 821 } 822 } 823 824 static const MemoryRegionOps strongarm_ppc_ops = { 825 .read = strongarm_ppc_read, 826 .write = strongarm_ppc_write, 827 .endianness = DEVICE_NATIVE_ENDIAN, 828 }; 829 830 static void strongarm_ppc_init(Object *obj) 831 { 832 DeviceState *dev = DEVICE(obj); 833 StrongARMPPCInfo *s = STRONGARM_PPC(obj); 834 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 835 836 qdev_init_gpio_in(dev, strongarm_ppc_set, 22); 837 qdev_init_gpio_out(dev, s->handler, 22); 838 839 memory_region_init_io(&s->iomem, obj, &strongarm_ppc_ops, s, 840 "ppc", 0x1000); 841 842 sysbus_init_mmio(sbd, &s->iomem); 843 } 844 845 static const VMStateDescription vmstate_strongarm_ppc_regs = { 846 .name = "strongarm-ppc", 847 .version_id = 0, 848 .minimum_version_id = 0, 849 .fields = (VMStateField[]) { 850 VMSTATE_UINT32(ilevel, StrongARMPPCInfo), 851 VMSTATE_UINT32(olevel, StrongARMPPCInfo), 852 VMSTATE_UINT32(dir, StrongARMPPCInfo), 853 VMSTATE_UINT32(ppar, StrongARMPPCInfo), 854 VMSTATE_UINT32(psdr, StrongARMPPCInfo), 855 VMSTATE_UINT32(ppfr, StrongARMPPCInfo), 856 VMSTATE_UINT32(prev_level, StrongARMPPCInfo), 857 VMSTATE_END_OF_LIST(), 858 }, 859 }; 860 861 static void strongarm_ppc_class_init(ObjectClass *klass, void *data) 862 { 863 DeviceClass *dc = DEVICE_CLASS(klass); 864 865 dc->desc = "StrongARM PPC controller"; 866 dc->vmsd = &vmstate_strongarm_ppc_regs; 867 } 868 869 static const TypeInfo strongarm_ppc_info = { 870 .name = TYPE_STRONGARM_PPC, 871 .parent = TYPE_SYS_BUS_DEVICE, 872 .instance_size = sizeof(StrongARMPPCInfo), 873 .instance_init = strongarm_ppc_init, 874 .class_init = strongarm_ppc_class_init, 875 }; 876 877 /* UART Ports */ 878 #define UTCR0 0x00 879 #define UTCR1 0x04 880 #define UTCR2 0x08 881 #define UTCR3 0x0c 882 #define UTDR 0x14 883 #define UTSR0 0x1c 884 #define UTSR1 0x20 885 886 #define UTCR0_PE (1 << 0) /* Parity enable */ 887 #define UTCR0_OES (1 << 1) /* Even parity */ 888 #define UTCR0_SBS (1 << 2) /* 2 stop bits */ 889 #define UTCR0_DSS (1 << 3) /* 8-bit data */ 890 891 #define UTCR3_RXE (1 << 0) /* Rx enable */ 892 #define UTCR3_TXE (1 << 1) /* Tx enable */ 893 #define UTCR3_BRK (1 << 2) /* Force Break */ 894 #define UTCR3_RIE (1 << 3) /* Rx int enable */ 895 #define UTCR3_TIE (1 << 4) /* Tx int enable */ 896 #define UTCR3_LBM (1 << 5) /* Loopback */ 897 898 #define UTSR0_TFS (1 << 0) /* Tx FIFO nearly empty */ 899 #define UTSR0_RFS (1 << 1) /* Rx FIFO nearly full */ 900 #define UTSR0_RID (1 << 2) /* Receiver Idle */ 901 #define UTSR0_RBB (1 << 3) /* Receiver begin break */ 902 #define UTSR0_REB (1 << 4) /* Receiver end break */ 903 #define UTSR0_EIF (1 << 5) /* Error in FIFO */ 904 905 #define UTSR1_RNE (1 << 1) /* Receive FIFO not empty */ 906 #define UTSR1_TNF (1 << 2) /* Transmit FIFO not full */ 907 #define UTSR1_PRE (1 << 3) /* Parity error */ 908 #define UTSR1_FRE (1 << 4) /* Frame error */ 909 #define UTSR1_ROR (1 << 5) /* Receive Over Run */ 910 911 #define RX_FIFO_PRE (1 << 8) 912 #define RX_FIFO_FRE (1 << 9) 913 #define RX_FIFO_ROR (1 << 10) 914 915 #define TYPE_STRONGARM_UART "strongarm-uart" 916 OBJECT_DECLARE_SIMPLE_TYPE(StrongARMUARTState, STRONGARM_UART) 917 918 struct StrongARMUARTState { 919 SysBusDevice parent_obj; 920 921 MemoryRegion iomem; 922 CharBackend chr; 923 qemu_irq irq; 924 925 uint8_t utcr0; 926 uint16_t brd; 927 uint8_t utcr3; 928 uint8_t utsr0; 929 uint8_t utsr1; 930 931 uint8_t tx_fifo[8]; 932 uint8_t tx_start; 933 uint8_t tx_len; 934 uint16_t rx_fifo[12]; /* value + error flags in high bits */ 935 uint8_t rx_start; 936 uint8_t rx_len; 937 938 uint64_t char_transmit_time; /* time to transmit a char in nanoseconds */ 939 bool wait_break_end; 940 QEMUTimer *rx_timeout_timer; 941 QEMUTimer *tx_timer; 942 }; 943 944 static void strongarm_uart_update_status(StrongARMUARTState *s) 945 { 946 uint16_t utsr1 = 0; 947 948 if (s->tx_len != 8) { 949 utsr1 |= UTSR1_TNF; 950 } 951 952 if (s->rx_len != 0) { 953 uint16_t ent = s->rx_fifo[s->rx_start]; 954 955 utsr1 |= UTSR1_RNE; 956 if (ent & RX_FIFO_PRE) { 957 s->utsr1 |= UTSR1_PRE; 958 } 959 if (ent & RX_FIFO_FRE) { 960 s->utsr1 |= UTSR1_FRE; 961 } 962 if (ent & RX_FIFO_ROR) { 963 s->utsr1 |= UTSR1_ROR; 964 } 965 } 966 967 s->utsr1 = utsr1; 968 } 969 970 static void strongarm_uart_update_int_status(StrongARMUARTState *s) 971 { 972 uint16_t utsr0 = s->utsr0 & 973 (UTSR0_REB | UTSR0_RBB | UTSR0_RID); 974 int i; 975 976 if ((s->utcr3 & UTCR3_TXE) && 977 (s->utcr3 & UTCR3_TIE) && 978 s->tx_len <= 4) { 979 utsr0 |= UTSR0_TFS; 980 } 981 982 if ((s->utcr3 & UTCR3_RXE) && 983 (s->utcr3 & UTCR3_RIE) && 984 s->rx_len > 4) { 985 utsr0 |= UTSR0_RFS; 986 } 987 988 for (i = 0; i < s->rx_len && i < 4; i++) 989 if (s->rx_fifo[(s->rx_start + i) % 12] & ~0xff) { 990 utsr0 |= UTSR0_EIF; 991 break; 992 } 993 994 s->utsr0 = utsr0; 995 qemu_set_irq(s->irq, utsr0); 996 } 997 998 static void strongarm_uart_update_parameters(StrongARMUARTState *s) 999 { 1000 int speed, parity, data_bits, stop_bits, frame_size; 1001 QEMUSerialSetParams ssp; 1002 1003 /* Start bit. */ 1004 frame_size = 1; 1005 if (s->utcr0 & UTCR0_PE) { 1006 /* Parity bit. */ 1007 frame_size++; 1008 if (s->utcr0 & UTCR0_OES) { 1009 parity = 'E'; 1010 } else { 1011 parity = 'O'; 1012 } 1013 } else { 1014 parity = 'N'; 1015 } 1016 if (s->utcr0 & UTCR0_SBS) { 1017 stop_bits = 2; 1018 } else { 1019 stop_bits = 1; 1020 } 1021 1022 data_bits = (s->utcr0 & UTCR0_DSS) ? 8 : 7; 1023 frame_size += data_bits + stop_bits; 1024 speed = 3686400 / 16 / (s->brd + 1); 1025 ssp.speed = speed; 1026 ssp.parity = parity; 1027 ssp.data_bits = data_bits; 1028 ssp.stop_bits = stop_bits; 1029 s->char_transmit_time = (NANOSECONDS_PER_SECOND / speed) * frame_size; 1030 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); 1031 1032 DPRINTF(stderr, "%s speed=%d parity=%c data=%d stop=%d\n", s->chr->label, 1033 speed, parity, data_bits, stop_bits); 1034 } 1035 1036 static void strongarm_uart_rx_to(void *opaque) 1037 { 1038 StrongARMUARTState *s = opaque; 1039 1040 if (s->rx_len) { 1041 s->utsr0 |= UTSR0_RID; 1042 strongarm_uart_update_int_status(s); 1043 } 1044 } 1045 1046 static void strongarm_uart_rx_push(StrongARMUARTState *s, uint16_t c) 1047 { 1048 if ((s->utcr3 & UTCR3_RXE) == 0) { 1049 /* rx disabled */ 1050 return; 1051 } 1052 1053 if (s->wait_break_end) { 1054 s->utsr0 |= UTSR0_REB; 1055 s->wait_break_end = false; 1056 } 1057 1058 if (s->rx_len < 12) { 1059 s->rx_fifo[(s->rx_start + s->rx_len) % 12] = c; 1060 s->rx_len++; 1061 } else 1062 s->rx_fifo[(s->rx_start + 11) % 12] |= RX_FIFO_ROR; 1063 } 1064 1065 static int strongarm_uart_can_receive(void *opaque) 1066 { 1067 StrongARMUARTState *s = opaque; 1068 1069 if (s->rx_len == 12) { 1070 return 0; 1071 } 1072 /* It's best not to get more than 2/3 of RX FIFO, so advertise that much */ 1073 if (s->rx_len < 8) { 1074 return 8 - s->rx_len; 1075 } 1076 return 1; 1077 } 1078 1079 static void strongarm_uart_receive(void *opaque, const uint8_t *buf, int size) 1080 { 1081 StrongARMUARTState *s = opaque; 1082 int i; 1083 1084 for (i = 0; i < size; i++) { 1085 strongarm_uart_rx_push(s, buf[i]); 1086 } 1087 1088 /* call the timeout receive callback in 3 char transmit time */ 1089 timer_mod(s->rx_timeout_timer, 1090 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 3); 1091 1092 strongarm_uart_update_status(s); 1093 strongarm_uart_update_int_status(s); 1094 } 1095 1096 static void strongarm_uart_event(void *opaque, QEMUChrEvent event) 1097 { 1098 StrongARMUARTState *s = opaque; 1099 if (event == CHR_EVENT_BREAK) { 1100 s->utsr0 |= UTSR0_RBB; 1101 strongarm_uart_rx_push(s, RX_FIFO_FRE); 1102 s->wait_break_end = true; 1103 strongarm_uart_update_status(s); 1104 strongarm_uart_update_int_status(s); 1105 } 1106 } 1107 1108 static void strongarm_uart_tx(void *opaque) 1109 { 1110 StrongARMUARTState *s = opaque; 1111 uint64_t new_xmit_ts = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 1112 1113 if (s->utcr3 & UTCR3_LBM) /* loopback */ { 1114 strongarm_uart_receive(s, &s->tx_fifo[s->tx_start], 1); 1115 } else if (qemu_chr_fe_backend_connected(&s->chr)) { 1116 /* XXX this blocks entire thread. Rewrite to use 1117 * qemu_chr_fe_write and background I/O callbacks */ 1118 qemu_chr_fe_write_all(&s->chr, &s->tx_fifo[s->tx_start], 1); 1119 } 1120 1121 s->tx_start = (s->tx_start + 1) % 8; 1122 s->tx_len--; 1123 if (s->tx_len) { 1124 timer_mod(s->tx_timer, new_xmit_ts + s->char_transmit_time); 1125 } 1126 strongarm_uart_update_status(s); 1127 strongarm_uart_update_int_status(s); 1128 } 1129 1130 static uint64_t strongarm_uart_read(void *opaque, hwaddr addr, 1131 unsigned size) 1132 { 1133 StrongARMUARTState *s = opaque; 1134 uint16_t ret; 1135 1136 switch (addr) { 1137 case UTCR0: 1138 return s->utcr0; 1139 1140 case UTCR1: 1141 return s->brd >> 8; 1142 1143 case UTCR2: 1144 return s->brd & 0xff; 1145 1146 case UTCR3: 1147 return s->utcr3; 1148 1149 case UTDR: 1150 if (s->rx_len != 0) { 1151 ret = s->rx_fifo[s->rx_start]; 1152 s->rx_start = (s->rx_start + 1) % 12; 1153 s->rx_len--; 1154 strongarm_uart_update_status(s); 1155 strongarm_uart_update_int_status(s); 1156 return ret; 1157 } 1158 return 0; 1159 1160 case UTSR0: 1161 return s->utsr0; 1162 1163 case UTSR1: 1164 return s->utsr1; 1165 1166 default: 1167 printf("%s: Bad register 0x" HWADDR_FMT_plx "\n", __func__, addr); 1168 return 0; 1169 } 1170 } 1171 1172 static void strongarm_uart_write(void *opaque, hwaddr addr, 1173 uint64_t value, unsigned size) 1174 { 1175 StrongARMUARTState *s = opaque; 1176 1177 switch (addr) { 1178 case UTCR0: 1179 s->utcr0 = value & 0x7f; 1180 strongarm_uart_update_parameters(s); 1181 break; 1182 1183 case UTCR1: 1184 s->brd = (s->brd & 0xff) | ((value & 0xf) << 8); 1185 strongarm_uart_update_parameters(s); 1186 break; 1187 1188 case UTCR2: 1189 s->brd = (s->brd & 0xf00) | (value & 0xff); 1190 strongarm_uart_update_parameters(s); 1191 break; 1192 1193 case UTCR3: 1194 s->utcr3 = value & 0x3f; 1195 if ((s->utcr3 & UTCR3_RXE) == 0) { 1196 s->rx_len = 0; 1197 } 1198 if ((s->utcr3 & UTCR3_TXE) == 0) { 1199 s->tx_len = 0; 1200 } 1201 strongarm_uart_update_status(s); 1202 strongarm_uart_update_int_status(s); 1203 break; 1204 1205 case UTDR: 1206 if ((s->utcr3 & UTCR3_TXE) && s->tx_len != 8) { 1207 s->tx_fifo[(s->tx_start + s->tx_len) % 8] = value; 1208 s->tx_len++; 1209 strongarm_uart_update_status(s); 1210 strongarm_uart_update_int_status(s); 1211 if (s->tx_len == 1) { 1212 strongarm_uart_tx(s); 1213 } 1214 } 1215 break; 1216 1217 case UTSR0: 1218 s->utsr0 = s->utsr0 & ~(value & 1219 (UTSR0_REB | UTSR0_RBB | UTSR0_RID)); 1220 strongarm_uart_update_int_status(s); 1221 break; 1222 1223 default: 1224 printf("%s: Bad register 0x" HWADDR_FMT_plx "\n", __func__, addr); 1225 } 1226 } 1227 1228 static const MemoryRegionOps strongarm_uart_ops = { 1229 .read = strongarm_uart_read, 1230 .write = strongarm_uart_write, 1231 .endianness = DEVICE_NATIVE_ENDIAN, 1232 }; 1233 1234 static void strongarm_uart_init(Object *obj) 1235 { 1236 StrongARMUARTState *s = STRONGARM_UART(obj); 1237 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 1238 1239 memory_region_init_io(&s->iomem, obj, &strongarm_uart_ops, s, 1240 "uart", 0x10000); 1241 sysbus_init_mmio(dev, &s->iomem); 1242 sysbus_init_irq(dev, &s->irq); 1243 } 1244 1245 static void strongarm_uart_realize(DeviceState *dev, Error **errp) 1246 { 1247 StrongARMUARTState *s = STRONGARM_UART(dev); 1248 1249 s->rx_timeout_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 1250 strongarm_uart_rx_to, 1251 s); 1252 s->tx_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, strongarm_uart_tx, s); 1253 qemu_chr_fe_set_handlers(&s->chr, 1254 strongarm_uart_can_receive, 1255 strongarm_uart_receive, 1256 strongarm_uart_event, 1257 NULL, s, NULL, true); 1258 } 1259 1260 static void strongarm_uart_reset(DeviceState *dev) 1261 { 1262 StrongARMUARTState *s = STRONGARM_UART(dev); 1263 1264 s->utcr0 = UTCR0_DSS; /* 8 data, no parity */ 1265 s->brd = 23; /* 9600 */ 1266 /* enable send & recv - this actually violates spec */ 1267 s->utcr3 = UTCR3_TXE | UTCR3_RXE; 1268 1269 s->rx_len = s->tx_len = 0; 1270 1271 strongarm_uart_update_parameters(s); 1272 strongarm_uart_update_status(s); 1273 strongarm_uart_update_int_status(s); 1274 } 1275 1276 static int strongarm_uart_post_load(void *opaque, int version_id) 1277 { 1278 StrongARMUARTState *s = opaque; 1279 1280 strongarm_uart_update_parameters(s); 1281 strongarm_uart_update_status(s); 1282 strongarm_uart_update_int_status(s); 1283 1284 /* tx and restart timer */ 1285 if (s->tx_len) { 1286 strongarm_uart_tx(s); 1287 } 1288 1289 /* restart rx timeout timer */ 1290 if (s->rx_len) { 1291 timer_mod(s->rx_timeout_timer, 1292 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 3); 1293 } 1294 1295 return 0; 1296 } 1297 1298 static const VMStateDescription vmstate_strongarm_uart_regs = { 1299 .name = "strongarm-uart", 1300 .version_id = 0, 1301 .minimum_version_id = 0, 1302 .post_load = strongarm_uart_post_load, 1303 .fields = (VMStateField[]) { 1304 VMSTATE_UINT8(utcr0, StrongARMUARTState), 1305 VMSTATE_UINT16(brd, StrongARMUARTState), 1306 VMSTATE_UINT8(utcr3, StrongARMUARTState), 1307 VMSTATE_UINT8(utsr0, StrongARMUARTState), 1308 VMSTATE_UINT8_ARRAY(tx_fifo, StrongARMUARTState, 8), 1309 VMSTATE_UINT8(tx_start, StrongARMUARTState), 1310 VMSTATE_UINT8(tx_len, StrongARMUARTState), 1311 VMSTATE_UINT16_ARRAY(rx_fifo, StrongARMUARTState, 12), 1312 VMSTATE_UINT8(rx_start, StrongARMUARTState), 1313 VMSTATE_UINT8(rx_len, StrongARMUARTState), 1314 VMSTATE_BOOL(wait_break_end, StrongARMUARTState), 1315 VMSTATE_END_OF_LIST(), 1316 }, 1317 }; 1318 1319 static Property strongarm_uart_properties[] = { 1320 DEFINE_PROP_CHR("chardev", StrongARMUARTState, chr), 1321 DEFINE_PROP_END_OF_LIST(), 1322 }; 1323 1324 static void strongarm_uart_class_init(ObjectClass *klass, void *data) 1325 { 1326 DeviceClass *dc = DEVICE_CLASS(klass); 1327 1328 dc->desc = "StrongARM UART controller"; 1329 dc->reset = strongarm_uart_reset; 1330 dc->vmsd = &vmstate_strongarm_uart_regs; 1331 device_class_set_props(dc, strongarm_uart_properties); 1332 dc->realize = strongarm_uart_realize; 1333 } 1334 1335 static const TypeInfo strongarm_uart_info = { 1336 .name = TYPE_STRONGARM_UART, 1337 .parent = TYPE_SYS_BUS_DEVICE, 1338 .instance_size = sizeof(StrongARMUARTState), 1339 .instance_init = strongarm_uart_init, 1340 .class_init = strongarm_uart_class_init, 1341 }; 1342 1343 /* Synchronous Serial Ports */ 1344 1345 #define TYPE_STRONGARM_SSP "strongarm-ssp" 1346 OBJECT_DECLARE_SIMPLE_TYPE(StrongARMSSPState, STRONGARM_SSP) 1347 1348 struct StrongARMSSPState { 1349 SysBusDevice parent_obj; 1350 1351 MemoryRegion iomem; 1352 qemu_irq irq; 1353 SSIBus *bus; 1354 1355 uint16_t sscr[2]; 1356 uint16_t sssr; 1357 1358 uint16_t rx_fifo[8]; 1359 uint8_t rx_level; 1360 uint8_t rx_start; 1361 }; 1362 1363 #define SSCR0 0x60 /* SSP Control register 0 */ 1364 #define SSCR1 0x64 /* SSP Control register 1 */ 1365 #define SSDR 0x6c /* SSP Data register */ 1366 #define SSSR 0x74 /* SSP Status register */ 1367 1368 /* Bitfields for above registers */ 1369 #define SSCR0_SPI(x) (((x) & 0x30) == 0x00) 1370 #define SSCR0_SSP(x) (((x) & 0x30) == 0x10) 1371 #define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20) 1372 #define SSCR0_PSP(x) (((x) & 0x30) == 0x30) 1373 #define SSCR0_SSE (1 << 7) 1374 #define SSCR0_DSS(x) (((x) & 0xf) + 1) 1375 #define SSCR1_RIE (1 << 0) 1376 #define SSCR1_TIE (1 << 1) 1377 #define SSCR1_LBM (1 << 2) 1378 #define SSSR_TNF (1 << 2) 1379 #define SSSR_RNE (1 << 3) 1380 #define SSSR_TFS (1 << 5) 1381 #define SSSR_RFS (1 << 6) 1382 #define SSSR_ROR (1 << 7) 1383 #define SSSR_RW 0x0080 1384 1385 static void strongarm_ssp_int_update(StrongARMSSPState *s) 1386 { 1387 int level = 0; 1388 1389 level |= (s->sssr & SSSR_ROR); 1390 level |= (s->sssr & SSSR_RFS) && (s->sscr[1] & SSCR1_RIE); 1391 level |= (s->sssr & SSSR_TFS) && (s->sscr[1] & SSCR1_TIE); 1392 qemu_set_irq(s->irq, level); 1393 } 1394 1395 static void strongarm_ssp_fifo_update(StrongARMSSPState *s) 1396 { 1397 s->sssr &= ~SSSR_TFS; 1398 s->sssr &= ~SSSR_TNF; 1399 if (s->sscr[0] & SSCR0_SSE) { 1400 if (s->rx_level >= 4) { 1401 s->sssr |= SSSR_RFS; 1402 } else { 1403 s->sssr &= ~SSSR_RFS; 1404 } 1405 if (s->rx_level) { 1406 s->sssr |= SSSR_RNE; 1407 } else { 1408 s->sssr &= ~SSSR_RNE; 1409 } 1410 /* TX FIFO is never filled, so it is always in underrun 1411 condition if SSP is enabled */ 1412 s->sssr |= SSSR_TFS; 1413 s->sssr |= SSSR_TNF; 1414 } 1415 1416 strongarm_ssp_int_update(s); 1417 } 1418 1419 static uint64_t strongarm_ssp_read(void *opaque, hwaddr addr, 1420 unsigned size) 1421 { 1422 StrongARMSSPState *s = opaque; 1423 uint32_t retval; 1424 1425 switch (addr) { 1426 case SSCR0: 1427 return s->sscr[0]; 1428 case SSCR1: 1429 return s->sscr[1]; 1430 case SSSR: 1431 return s->sssr; 1432 case SSDR: 1433 if (~s->sscr[0] & SSCR0_SSE) { 1434 return 0xffffffff; 1435 } 1436 if (s->rx_level < 1) { 1437 printf("%s: SSP Rx Underrun\n", __func__); 1438 return 0xffffffff; 1439 } 1440 s->rx_level--; 1441 retval = s->rx_fifo[s->rx_start++]; 1442 s->rx_start &= 0x7; 1443 strongarm_ssp_fifo_update(s); 1444 return retval; 1445 default: 1446 printf("%s: Bad register 0x" HWADDR_FMT_plx "\n", __func__, addr); 1447 break; 1448 } 1449 return 0; 1450 } 1451 1452 static void strongarm_ssp_write(void *opaque, hwaddr addr, 1453 uint64_t value, unsigned size) 1454 { 1455 StrongARMSSPState *s = opaque; 1456 1457 switch (addr) { 1458 case SSCR0: 1459 s->sscr[0] = value & 0xffbf; 1460 if ((s->sscr[0] & SSCR0_SSE) && SSCR0_DSS(value) < 4) { 1461 printf("%s: Wrong data size: %i bits\n", __func__, 1462 (int)SSCR0_DSS(value)); 1463 } 1464 if (!(value & SSCR0_SSE)) { 1465 s->sssr = 0; 1466 s->rx_level = 0; 1467 } 1468 strongarm_ssp_fifo_update(s); 1469 break; 1470 1471 case SSCR1: 1472 s->sscr[1] = value & 0x2f; 1473 if (value & SSCR1_LBM) { 1474 printf("%s: Attempt to use SSP LBM mode\n", __func__); 1475 } 1476 strongarm_ssp_fifo_update(s); 1477 break; 1478 1479 case SSSR: 1480 s->sssr &= ~(value & SSSR_RW); 1481 strongarm_ssp_int_update(s); 1482 break; 1483 1484 case SSDR: 1485 if (SSCR0_UWIRE(s->sscr[0])) { 1486 value &= 0xff; 1487 } else 1488 /* Note how 32bits overflow does no harm here */ 1489 value &= (1 << SSCR0_DSS(s->sscr[0])) - 1; 1490 1491 /* Data goes from here to the Tx FIFO and is shifted out from 1492 * there directly to the slave, no need to buffer it. 1493 */ 1494 if (s->sscr[0] & SSCR0_SSE) { 1495 uint32_t readval; 1496 if (s->sscr[1] & SSCR1_LBM) { 1497 readval = value; 1498 } else { 1499 readval = ssi_transfer(s->bus, value); 1500 } 1501 1502 if (s->rx_level < 0x08) { 1503 s->rx_fifo[(s->rx_start + s->rx_level++) & 0x7] = readval; 1504 } else { 1505 s->sssr |= SSSR_ROR; 1506 } 1507 } 1508 strongarm_ssp_fifo_update(s); 1509 break; 1510 1511 default: 1512 printf("%s: Bad register 0x" HWADDR_FMT_plx "\n", __func__, addr); 1513 break; 1514 } 1515 } 1516 1517 static const MemoryRegionOps strongarm_ssp_ops = { 1518 .read = strongarm_ssp_read, 1519 .write = strongarm_ssp_write, 1520 .endianness = DEVICE_NATIVE_ENDIAN, 1521 }; 1522 1523 static int strongarm_ssp_post_load(void *opaque, int version_id) 1524 { 1525 StrongARMSSPState *s = opaque; 1526 1527 strongarm_ssp_fifo_update(s); 1528 1529 return 0; 1530 } 1531 1532 static void strongarm_ssp_init(Object *obj) 1533 { 1534 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 1535 DeviceState *dev = DEVICE(sbd); 1536 StrongARMSSPState *s = STRONGARM_SSP(dev); 1537 1538 sysbus_init_irq(sbd, &s->irq); 1539 1540 memory_region_init_io(&s->iomem, obj, &strongarm_ssp_ops, s, 1541 "ssp", 0x1000); 1542 sysbus_init_mmio(sbd, &s->iomem); 1543 1544 s->bus = ssi_create_bus(dev, "ssi"); 1545 } 1546 1547 static void strongarm_ssp_reset(DeviceState *dev) 1548 { 1549 StrongARMSSPState *s = STRONGARM_SSP(dev); 1550 1551 s->sssr = 0x03; /* 3 bit data, SPI, disabled */ 1552 s->rx_start = 0; 1553 s->rx_level = 0; 1554 } 1555 1556 static const VMStateDescription vmstate_strongarm_ssp_regs = { 1557 .name = "strongarm-ssp", 1558 .version_id = 0, 1559 .minimum_version_id = 0, 1560 .post_load = strongarm_ssp_post_load, 1561 .fields = (VMStateField[]) { 1562 VMSTATE_UINT16_ARRAY(sscr, StrongARMSSPState, 2), 1563 VMSTATE_UINT16(sssr, StrongARMSSPState), 1564 VMSTATE_UINT16_ARRAY(rx_fifo, StrongARMSSPState, 8), 1565 VMSTATE_UINT8(rx_start, StrongARMSSPState), 1566 VMSTATE_UINT8(rx_level, StrongARMSSPState), 1567 VMSTATE_END_OF_LIST(), 1568 }, 1569 }; 1570 1571 static void strongarm_ssp_class_init(ObjectClass *klass, void *data) 1572 { 1573 DeviceClass *dc = DEVICE_CLASS(klass); 1574 1575 dc->desc = "StrongARM SSP controller"; 1576 dc->reset = strongarm_ssp_reset; 1577 dc->vmsd = &vmstate_strongarm_ssp_regs; 1578 } 1579 1580 static const TypeInfo strongarm_ssp_info = { 1581 .name = TYPE_STRONGARM_SSP, 1582 .parent = TYPE_SYS_BUS_DEVICE, 1583 .instance_size = sizeof(StrongARMSSPState), 1584 .instance_init = strongarm_ssp_init, 1585 .class_init = strongarm_ssp_class_init, 1586 }; 1587 1588 /* Main CPU functions */ 1589 StrongARMState *sa1110_init(const char *cpu_type) 1590 { 1591 StrongARMState *s; 1592 int i; 1593 1594 s = g_new0(StrongARMState, 1); 1595 1596 if (strncmp(cpu_type, "sa1110", 6)) { 1597 error_report("Machine requires a SA1110 processor."); 1598 exit(1); 1599 } 1600 1601 s->cpu = ARM_CPU(cpu_create(cpu_type)); 1602 1603 s->pic = sysbus_create_varargs("strongarm_pic", 0x90050000, 1604 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ), 1605 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_FIQ), 1606 NULL); 1607 1608 sysbus_create_varargs("pxa25x-timer", 0x90000000, 1609 qdev_get_gpio_in(s->pic, SA_PIC_OSTC0), 1610 qdev_get_gpio_in(s->pic, SA_PIC_OSTC1), 1611 qdev_get_gpio_in(s->pic, SA_PIC_OSTC2), 1612 qdev_get_gpio_in(s->pic, SA_PIC_OSTC3), 1613 NULL); 1614 1615 sysbus_create_simple(TYPE_STRONGARM_RTC, 0x90010000, 1616 qdev_get_gpio_in(s->pic, SA_PIC_RTC_ALARM)); 1617 1618 s->gpio = strongarm_gpio_init(0x90040000, s->pic); 1619 1620 s->ppc = sysbus_create_varargs(TYPE_STRONGARM_PPC, 0x90060000, NULL); 1621 1622 for (i = 0; sa_serial[i].io_base; i++) { 1623 DeviceState *dev = qdev_new(TYPE_STRONGARM_UART); 1624 qdev_prop_set_chr(dev, "chardev", serial_hd(i)); 1625 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1626 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 1627 sa_serial[i].io_base); 1628 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, 1629 qdev_get_gpio_in(s->pic, sa_serial[i].irq)); 1630 } 1631 1632 s->ssp = sysbus_create_varargs(TYPE_STRONGARM_SSP, 0x80070000, 1633 qdev_get_gpio_in(s->pic, SA_PIC_SSP), NULL); 1634 s->ssp_bus = (SSIBus *)qdev_get_child_bus(s->ssp, "ssi"); 1635 1636 return s; 1637 } 1638 1639 static void strongarm_register_types(void) 1640 { 1641 type_register_static(&strongarm_pic_info); 1642 type_register_static(&strongarm_rtc_sysbus_info); 1643 type_register_static(&strongarm_gpio_info); 1644 type_register_static(&strongarm_ppc_info); 1645 type_register_static(&strongarm_uart_info); 1646 type_register_static(&strongarm_ssp_info); 1647 } 1648 1649 type_init(strongarm_register_types) 1650