1 /* 2 * StrongARM SA-1100/SA-1110 emulation 3 * 4 * Copyright (C) 2011 Dmitry Eremin-Solenikov 5 * 6 * Largely based on StrongARM emulation: 7 * Copyright (c) 2006 Openedhand Ltd. 8 * Written by Andrzej Zaborowski <balrog@zabor.org> 9 * 10 * UART code based on QEMU 16550A UART emulation 11 * Copyright (c) 2003-2004 Fabrice Bellard 12 * Copyright (c) 2008 Citrix Systems, Inc. 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License version 2 as 16 * published by the Free Software Foundation. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License along 24 * with this program; if not, see <http://www.gnu.org/licenses/>. 25 * 26 * Contributions after 2012-01-13 are licensed under the terms of the 27 * GNU GPL, version 2 or (at your option) any later version. 28 */ 29 30 #include "qemu/osdep.h" 31 #include "cpu.h" 32 #include "hw/boards.h" 33 #include "hw/sysbus.h" 34 #include "strongarm.h" 35 #include "qemu/error-report.h" 36 #include "hw/arm/arm.h" 37 #include "chardev/char-fe.h" 38 #include "chardev/char-serial.h" 39 #include "sysemu/sysemu.h" 40 #include "hw/ssi/ssi.h" 41 #include "qemu/cutils.h" 42 #include "qemu/log.h" 43 44 //#define DEBUG 45 46 /* 47 TODO 48 - Implement cp15, c14 ? 49 - Implement cp15, c15 !!! (idle used in L) 50 - Implement idle mode handling/DIM 51 - Implement sleep mode/Wake sources 52 - Implement reset control 53 - Implement memory control regs 54 - PCMCIA handling 55 - Maybe support MBGNT/MBREQ 56 - DMA channels 57 - GPCLK 58 - IrDA 59 - MCP 60 - Enhance UART with modem signals 61 */ 62 63 #ifdef DEBUG 64 # define DPRINTF(format, ...) printf(format , ## __VA_ARGS__) 65 #else 66 # define DPRINTF(format, ...) do { } while (0) 67 #endif 68 69 static struct { 70 hwaddr io_base; 71 int irq; 72 } sa_serial[] = { 73 { 0x80010000, SA_PIC_UART1 }, 74 { 0x80030000, SA_PIC_UART2 }, 75 { 0x80050000, SA_PIC_UART3 }, 76 { 0, 0 } 77 }; 78 79 /* Interrupt Controller */ 80 81 #define TYPE_STRONGARM_PIC "strongarm_pic" 82 #define STRONGARM_PIC(obj) \ 83 OBJECT_CHECK(StrongARMPICState, (obj), TYPE_STRONGARM_PIC) 84 85 typedef struct StrongARMPICState { 86 SysBusDevice parent_obj; 87 88 MemoryRegion iomem; 89 qemu_irq irq; 90 qemu_irq fiq; 91 92 uint32_t pending; 93 uint32_t enabled; 94 uint32_t is_fiq; 95 uint32_t int_idle; 96 } StrongARMPICState; 97 98 #define ICIP 0x00 99 #define ICMR 0x04 100 #define ICLR 0x08 101 #define ICFP 0x10 102 #define ICPR 0x20 103 #define ICCR 0x0c 104 105 #define SA_PIC_SRCS 32 106 107 108 static void strongarm_pic_update(void *opaque) 109 { 110 StrongARMPICState *s = opaque; 111 112 /* FIXME: reflect DIM */ 113 qemu_set_irq(s->fiq, s->pending & s->enabled & s->is_fiq); 114 qemu_set_irq(s->irq, s->pending & s->enabled & ~s->is_fiq); 115 } 116 117 static void strongarm_pic_set_irq(void *opaque, int irq, int level) 118 { 119 StrongARMPICState *s = opaque; 120 121 if (level) { 122 s->pending |= 1 << irq; 123 } else { 124 s->pending &= ~(1 << irq); 125 } 126 127 strongarm_pic_update(s); 128 } 129 130 static uint64_t strongarm_pic_mem_read(void *opaque, hwaddr offset, 131 unsigned size) 132 { 133 StrongARMPICState *s = opaque; 134 135 switch (offset) { 136 case ICIP: 137 return s->pending & ~s->is_fiq & s->enabled; 138 case ICMR: 139 return s->enabled; 140 case ICLR: 141 return s->is_fiq; 142 case ICCR: 143 return s->int_idle == 0; 144 case ICFP: 145 return s->pending & s->is_fiq & s->enabled; 146 case ICPR: 147 return s->pending; 148 default: 149 printf("%s: Bad register offset 0x" TARGET_FMT_plx "\n", 150 __func__, offset); 151 return 0; 152 } 153 } 154 155 static void strongarm_pic_mem_write(void *opaque, hwaddr offset, 156 uint64_t value, unsigned size) 157 { 158 StrongARMPICState *s = opaque; 159 160 switch (offset) { 161 case ICMR: 162 s->enabled = value; 163 break; 164 case ICLR: 165 s->is_fiq = value; 166 break; 167 case ICCR: 168 s->int_idle = (value & 1) ? 0 : ~0; 169 break; 170 default: 171 printf("%s: Bad register offset 0x" TARGET_FMT_plx "\n", 172 __func__, offset); 173 break; 174 } 175 strongarm_pic_update(s); 176 } 177 178 static const MemoryRegionOps strongarm_pic_ops = { 179 .read = strongarm_pic_mem_read, 180 .write = strongarm_pic_mem_write, 181 .endianness = DEVICE_NATIVE_ENDIAN, 182 }; 183 184 static void strongarm_pic_initfn(Object *obj) 185 { 186 DeviceState *dev = DEVICE(obj); 187 StrongARMPICState *s = STRONGARM_PIC(obj); 188 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 189 190 qdev_init_gpio_in(dev, strongarm_pic_set_irq, SA_PIC_SRCS); 191 memory_region_init_io(&s->iomem, obj, &strongarm_pic_ops, s, 192 "pic", 0x1000); 193 sysbus_init_mmio(sbd, &s->iomem); 194 sysbus_init_irq(sbd, &s->irq); 195 sysbus_init_irq(sbd, &s->fiq); 196 } 197 198 static int strongarm_pic_post_load(void *opaque, int version_id) 199 { 200 strongarm_pic_update(opaque); 201 return 0; 202 } 203 204 static VMStateDescription vmstate_strongarm_pic_regs = { 205 .name = "strongarm_pic", 206 .version_id = 0, 207 .minimum_version_id = 0, 208 .post_load = strongarm_pic_post_load, 209 .fields = (VMStateField[]) { 210 VMSTATE_UINT32(pending, StrongARMPICState), 211 VMSTATE_UINT32(enabled, StrongARMPICState), 212 VMSTATE_UINT32(is_fiq, StrongARMPICState), 213 VMSTATE_UINT32(int_idle, StrongARMPICState), 214 VMSTATE_END_OF_LIST(), 215 }, 216 }; 217 218 static void strongarm_pic_class_init(ObjectClass *klass, void *data) 219 { 220 DeviceClass *dc = DEVICE_CLASS(klass); 221 222 dc->desc = "StrongARM PIC"; 223 dc->vmsd = &vmstate_strongarm_pic_regs; 224 } 225 226 static const TypeInfo strongarm_pic_info = { 227 .name = TYPE_STRONGARM_PIC, 228 .parent = TYPE_SYS_BUS_DEVICE, 229 .instance_size = sizeof(StrongARMPICState), 230 .instance_init = strongarm_pic_initfn, 231 .class_init = strongarm_pic_class_init, 232 }; 233 234 /* Real-Time Clock */ 235 #define RTAR 0x00 /* RTC Alarm register */ 236 #define RCNR 0x04 /* RTC Counter register */ 237 #define RTTR 0x08 /* RTC Timer Trim register */ 238 #define RTSR 0x10 /* RTC Status register */ 239 240 #define RTSR_AL (1 << 0) /* RTC Alarm detected */ 241 #define RTSR_HZ (1 << 1) /* RTC 1Hz detected */ 242 #define RTSR_ALE (1 << 2) /* RTC Alarm enable */ 243 #define RTSR_HZE (1 << 3) /* RTC 1Hz enable */ 244 245 /* 16 LSB of RTTR are clockdiv for internal trim logic, 246 * trim delete isn't emulated, so 247 * f = 32 768 / (RTTR_trim + 1) */ 248 249 #define TYPE_STRONGARM_RTC "strongarm-rtc" 250 #define STRONGARM_RTC(obj) \ 251 OBJECT_CHECK(StrongARMRTCState, (obj), TYPE_STRONGARM_RTC) 252 253 typedef struct StrongARMRTCState { 254 SysBusDevice parent_obj; 255 256 MemoryRegion iomem; 257 uint32_t rttr; 258 uint32_t rtsr; 259 uint32_t rtar; 260 uint32_t last_rcnr; 261 int64_t last_hz; 262 QEMUTimer *rtc_alarm; 263 QEMUTimer *rtc_hz; 264 qemu_irq rtc_irq; 265 qemu_irq rtc_hz_irq; 266 } StrongARMRTCState; 267 268 static inline void strongarm_rtc_int_update(StrongARMRTCState *s) 269 { 270 qemu_set_irq(s->rtc_irq, s->rtsr & RTSR_AL); 271 qemu_set_irq(s->rtc_hz_irq, s->rtsr & RTSR_HZ); 272 } 273 274 static void strongarm_rtc_hzupdate(StrongARMRTCState *s) 275 { 276 int64_t rt = qemu_clock_get_ms(rtc_clock); 277 s->last_rcnr += ((rt - s->last_hz) << 15) / 278 (1000 * ((s->rttr & 0xffff) + 1)); 279 s->last_hz = rt; 280 } 281 282 static inline void strongarm_rtc_timer_update(StrongARMRTCState *s) 283 { 284 if ((s->rtsr & RTSR_HZE) && !(s->rtsr & RTSR_HZ)) { 285 timer_mod(s->rtc_hz, s->last_hz + 1000); 286 } else { 287 timer_del(s->rtc_hz); 288 } 289 290 if ((s->rtsr & RTSR_ALE) && !(s->rtsr & RTSR_AL)) { 291 timer_mod(s->rtc_alarm, s->last_hz + 292 (((s->rtar - s->last_rcnr) * 1000 * 293 ((s->rttr & 0xffff) + 1)) >> 15)); 294 } else { 295 timer_del(s->rtc_alarm); 296 } 297 } 298 299 static inline void strongarm_rtc_alarm_tick(void *opaque) 300 { 301 StrongARMRTCState *s = opaque; 302 s->rtsr |= RTSR_AL; 303 strongarm_rtc_timer_update(s); 304 strongarm_rtc_int_update(s); 305 } 306 307 static inline void strongarm_rtc_hz_tick(void *opaque) 308 { 309 StrongARMRTCState *s = opaque; 310 s->rtsr |= RTSR_HZ; 311 strongarm_rtc_timer_update(s); 312 strongarm_rtc_int_update(s); 313 } 314 315 static uint64_t strongarm_rtc_read(void *opaque, hwaddr addr, 316 unsigned size) 317 { 318 StrongARMRTCState *s = opaque; 319 320 switch (addr) { 321 case RTTR: 322 return s->rttr; 323 case RTSR: 324 return s->rtsr; 325 case RTAR: 326 return s->rtar; 327 case RCNR: 328 return s->last_rcnr + 329 ((qemu_clock_get_ms(rtc_clock) - s->last_hz) << 15) / 330 (1000 * ((s->rttr & 0xffff) + 1)); 331 default: 332 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr); 333 return 0; 334 } 335 } 336 337 static void strongarm_rtc_write(void *opaque, hwaddr addr, 338 uint64_t value, unsigned size) 339 { 340 StrongARMRTCState *s = opaque; 341 uint32_t old_rtsr; 342 343 switch (addr) { 344 case RTTR: 345 strongarm_rtc_hzupdate(s); 346 s->rttr = value; 347 strongarm_rtc_timer_update(s); 348 break; 349 350 case RTSR: 351 old_rtsr = s->rtsr; 352 s->rtsr = (value & (RTSR_ALE | RTSR_HZE)) | 353 (s->rtsr & ~(value & (RTSR_AL | RTSR_HZ))); 354 355 if (s->rtsr != old_rtsr) { 356 strongarm_rtc_timer_update(s); 357 } 358 359 strongarm_rtc_int_update(s); 360 break; 361 362 case RTAR: 363 s->rtar = value; 364 strongarm_rtc_timer_update(s); 365 break; 366 367 case RCNR: 368 strongarm_rtc_hzupdate(s); 369 s->last_rcnr = value; 370 strongarm_rtc_timer_update(s); 371 break; 372 373 default: 374 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr); 375 } 376 } 377 378 static const MemoryRegionOps strongarm_rtc_ops = { 379 .read = strongarm_rtc_read, 380 .write = strongarm_rtc_write, 381 .endianness = DEVICE_NATIVE_ENDIAN, 382 }; 383 384 static void strongarm_rtc_init(Object *obj) 385 { 386 StrongARMRTCState *s = STRONGARM_RTC(obj); 387 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 388 struct tm tm; 389 390 s->rttr = 0x0; 391 s->rtsr = 0; 392 393 qemu_get_timedate(&tm, 0); 394 395 s->last_rcnr = (uint32_t) mktimegm(&tm); 396 s->last_hz = qemu_clock_get_ms(rtc_clock); 397 398 s->rtc_alarm = timer_new_ms(rtc_clock, strongarm_rtc_alarm_tick, s); 399 s->rtc_hz = timer_new_ms(rtc_clock, strongarm_rtc_hz_tick, s); 400 401 sysbus_init_irq(dev, &s->rtc_irq); 402 sysbus_init_irq(dev, &s->rtc_hz_irq); 403 404 memory_region_init_io(&s->iomem, obj, &strongarm_rtc_ops, s, 405 "rtc", 0x10000); 406 sysbus_init_mmio(dev, &s->iomem); 407 } 408 409 static int strongarm_rtc_pre_save(void *opaque) 410 { 411 StrongARMRTCState *s = opaque; 412 413 strongarm_rtc_hzupdate(s); 414 415 return 0; 416 } 417 418 static int strongarm_rtc_post_load(void *opaque, int version_id) 419 { 420 StrongARMRTCState *s = opaque; 421 422 strongarm_rtc_timer_update(s); 423 strongarm_rtc_int_update(s); 424 425 return 0; 426 } 427 428 static const VMStateDescription vmstate_strongarm_rtc_regs = { 429 .name = "strongarm-rtc", 430 .version_id = 0, 431 .minimum_version_id = 0, 432 .pre_save = strongarm_rtc_pre_save, 433 .post_load = strongarm_rtc_post_load, 434 .fields = (VMStateField[]) { 435 VMSTATE_UINT32(rttr, StrongARMRTCState), 436 VMSTATE_UINT32(rtsr, StrongARMRTCState), 437 VMSTATE_UINT32(rtar, StrongARMRTCState), 438 VMSTATE_UINT32(last_rcnr, StrongARMRTCState), 439 VMSTATE_INT64(last_hz, StrongARMRTCState), 440 VMSTATE_END_OF_LIST(), 441 }, 442 }; 443 444 static void strongarm_rtc_sysbus_class_init(ObjectClass *klass, void *data) 445 { 446 DeviceClass *dc = DEVICE_CLASS(klass); 447 448 dc->desc = "StrongARM RTC Controller"; 449 dc->vmsd = &vmstate_strongarm_rtc_regs; 450 } 451 452 static const TypeInfo strongarm_rtc_sysbus_info = { 453 .name = TYPE_STRONGARM_RTC, 454 .parent = TYPE_SYS_BUS_DEVICE, 455 .instance_size = sizeof(StrongARMRTCState), 456 .instance_init = strongarm_rtc_init, 457 .class_init = strongarm_rtc_sysbus_class_init, 458 }; 459 460 /* GPIO */ 461 #define GPLR 0x00 462 #define GPDR 0x04 463 #define GPSR 0x08 464 #define GPCR 0x0c 465 #define GRER 0x10 466 #define GFER 0x14 467 #define GEDR 0x18 468 #define GAFR 0x1c 469 470 #define TYPE_STRONGARM_GPIO "strongarm-gpio" 471 #define STRONGARM_GPIO(obj) \ 472 OBJECT_CHECK(StrongARMGPIOInfo, (obj), TYPE_STRONGARM_GPIO) 473 474 typedef struct StrongARMGPIOInfo StrongARMGPIOInfo; 475 struct StrongARMGPIOInfo { 476 SysBusDevice busdev; 477 MemoryRegion iomem; 478 qemu_irq handler[28]; 479 qemu_irq irqs[11]; 480 qemu_irq irqX; 481 482 uint32_t ilevel; 483 uint32_t olevel; 484 uint32_t dir; 485 uint32_t rising; 486 uint32_t falling; 487 uint32_t status; 488 uint32_t gafr; 489 490 uint32_t prev_level; 491 }; 492 493 494 static void strongarm_gpio_irq_update(StrongARMGPIOInfo *s) 495 { 496 int i; 497 for (i = 0; i < 11; i++) { 498 qemu_set_irq(s->irqs[i], s->status & (1 << i)); 499 } 500 501 qemu_set_irq(s->irqX, (s->status & ~0x7ff)); 502 } 503 504 static void strongarm_gpio_set(void *opaque, int line, int level) 505 { 506 StrongARMGPIOInfo *s = opaque; 507 uint32_t mask; 508 509 mask = 1 << line; 510 511 if (level) { 512 s->status |= s->rising & mask & 513 ~s->ilevel & ~s->dir; 514 s->ilevel |= mask; 515 } else { 516 s->status |= s->falling & mask & 517 s->ilevel & ~s->dir; 518 s->ilevel &= ~mask; 519 } 520 521 if (s->status & mask) { 522 strongarm_gpio_irq_update(s); 523 } 524 } 525 526 static void strongarm_gpio_handler_update(StrongARMGPIOInfo *s) 527 { 528 uint32_t level, diff; 529 int bit; 530 531 level = s->olevel & s->dir; 532 533 for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) { 534 bit = ctz32(diff); 535 qemu_set_irq(s->handler[bit], (level >> bit) & 1); 536 } 537 538 s->prev_level = level; 539 } 540 541 static uint64_t strongarm_gpio_read(void *opaque, hwaddr offset, 542 unsigned size) 543 { 544 StrongARMGPIOInfo *s = opaque; 545 546 switch (offset) { 547 case GPDR: /* GPIO Pin-Direction registers */ 548 return s->dir; 549 550 case GPSR: /* GPIO Pin-Output Set registers */ 551 qemu_log_mask(LOG_GUEST_ERROR, 552 "strongarm GPIO: read from write only register GPSR\n"); 553 return 0; 554 555 case GPCR: /* GPIO Pin-Output Clear registers */ 556 qemu_log_mask(LOG_GUEST_ERROR, 557 "strongarm GPIO: read from write only register GPCR\n"); 558 return 0; 559 560 case GRER: /* GPIO Rising-Edge Detect Enable registers */ 561 return s->rising; 562 563 case GFER: /* GPIO Falling-Edge Detect Enable registers */ 564 return s->falling; 565 566 case GAFR: /* GPIO Alternate Function registers */ 567 return s->gafr; 568 569 case GPLR: /* GPIO Pin-Level registers */ 570 return (s->olevel & s->dir) | 571 (s->ilevel & ~s->dir); 572 573 case GEDR: /* GPIO Edge Detect Status registers */ 574 return s->status; 575 576 default: 577 printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset); 578 } 579 580 return 0; 581 } 582 583 static void strongarm_gpio_write(void *opaque, hwaddr offset, 584 uint64_t value, unsigned size) 585 { 586 StrongARMGPIOInfo *s = opaque; 587 588 switch (offset) { 589 case GPDR: /* GPIO Pin-Direction registers */ 590 s->dir = value & 0x0fffffff; 591 strongarm_gpio_handler_update(s); 592 break; 593 594 case GPSR: /* GPIO Pin-Output Set registers */ 595 s->olevel |= value & 0x0fffffff; 596 strongarm_gpio_handler_update(s); 597 break; 598 599 case GPCR: /* GPIO Pin-Output Clear registers */ 600 s->olevel &= ~value; 601 strongarm_gpio_handler_update(s); 602 break; 603 604 case GRER: /* GPIO Rising-Edge Detect Enable registers */ 605 s->rising = value; 606 break; 607 608 case GFER: /* GPIO Falling-Edge Detect Enable registers */ 609 s->falling = value; 610 break; 611 612 case GAFR: /* GPIO Alternate Function registers */ 613 s->gafr = value; 614 break; 615 616 case GEDR: /* GPIO Edge Detect Status registers */ 617 s->status &= ~value; 618 strongarm_gpio_irq_update(s); 619 break; 620 621 default: 622 printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset); 623 } 624 } 625 626 static const MemoryRegionOps strongarm_gpio_ops = { 627 .read = strongarm_gpio_read, 628 .write = strongarm_gpio_write, 629 .endianness = DEVICE_NATIVE_ENDIAN, 630 }; 631 632 static DeviceState *strongarm_gpio_init(hwaddr base, 633 DeviceState *pic) 634 { 635 DeviceState *dev; 636 int i; 637 638 dev = qdev_create(NULL, TYPE_STRONGARM_GPIO); 639 qdev_init_nofail(dev); 640 641 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 642 for (i = 0; i < 12; i++) 643 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 644 qdev_get_gpio_in(pic, SA_PIC_GPIO0_EDGE + i)); 645 646 return dev; 647 } 648 649 static void strongarm_gpio_initfn(Object *obj) 650 { 651 DeviceState *dev = DEVICE(obj); 652 StrongARMGPIOInfo *s = STRONGARM_GPIO(obj); 653 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 654 int i; 655 656 qdev_init_gpio_in(dev, strongarm_gpio_set, 28); 657 qdev_init_gpio_out(dev, s->handler, 28); 658 659 memory_region_init_io(&s->iomem, obj, &strongarm_gpio_ops, s, 660 "gpio", 0x1000); 661 662 sysbus_init_mmio(sbd, &s->iomem); 663 for (i = 0; i < 11; i++) { 664 sysbus_init_irq(sbd, &s->irqs[i]); 665 } 666 sysbus_init_irq(sbd, &s->irqX); 667 } 668 669 static const VMStateDescription vmstate_strongarm_gpio_regs = { 670 .name = "strongarm-gpio", 671 .version_id = 0, 672 .minimum_version_id = 0, 673 .fields = (VMStateField[]) { 674 VMSTATE_UINT32(ilevel, StrongARMGPIOInfo), 675 VMSTATE_UINT32(olevel, StrongARMGPIOInfo), 676 VMSTATE_UINT32(dir, StrongARMGPIOInfo), 677 VMSTATE_UINT32(rising, StrongARMGPIOInfo), 678 VMSTATE_UINT32(falling, StrongARMGPIOInfo), 679 VMSTATE_UINT32(status, StrongARMGPIOInfo), 680 VMSTATE_UINT32(gafr, StrongARMGPIOInfo), 681 VMSTATE_UINT32(prev_level, StrongARMGPIOInfo), 682 VMSTATE_END_OF_LIST(), 683 }, 684 }; 685 686 static void strongarm_gpio_class_init(ObjectClass *klass, void *data) 687 { 688 DeviceClass *dc = DEVICE_CLASS(klass); 689 690 dc->desc = "StrongARM GPIO controller"; 691 dc->vmsd = &vmstate_strongarm_gpio_regs; 692 } 693 694 static const TypeInfo strongarm_gpio_info = { 695 .name = TYPE_STRONGARM_GPIO, 696 .parent = TYPE_SYS_BUS_DEVICE, 697 .instance_size = sizeof(StrongARMGPIOInfo), 698 .instance_init = strongarm_gpio_initfn, 699 .class_init = strongarm_gpio_class_init, 700 }; 701 702 /* Peripheral Pin Controller */ 703 #define PPDR 0x00 704 #define PPSR 0x04 705 #define PPAR 0x08 706 #define PSDR 0x0c 707 #define PPFR 0x10 708 709 #define TYPE_STRONGARM_PPC "strongarm-ppc" 710 #define STRONGARM_PPC(obj) \ 711 OBJECT_CHECK(StrongARMPPCInfo, (obj), TYPE_STRONGARM_PPC) 712 713 typedef struct StrongARMPPCInfo StrongARMPPCInfo; 714 struct StrongARMPPCInfo { 715 SysBusDevice parent_obj; 716 717 MemoryRegion iomem; 718 qemu_irq handler[28]; 719 720 uint32_t ilevel; 721 uint32_t olevel; 722 uint32_t dir; 723 uint32_t ppar; 724 uint32_t psdr; 725 uint32_t ppfr; 726 727 uint32_t prev_level; 728 }; 729 730 static void strongarm_ppc_set(void *opaque, int line, int level) 731 { 732 StrongARMPPCInfo *s = opaque; 733 734 if (level) { 735 s->ilevel |= 1 << line; 736 } else { 737 s->ilevel &= ~(1 << line); 738 } 739 } 740 741 static void strongarm_ppc_handler_update(StrongARMPPCInfo *s) 742 { 743 uint32_t level, diff; 744 int bit; 745 746 level = s->olevel & s->dir; 747 748 for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) { 749 bit = ctz32(diff); 750 qemu_set_irq(s->handler[bit], (level >> bit) & 1); 751 } 752 753 s->prev_level = level; 754 } 755 756 static uint64_t strongarm_ppc_read(void *opaque, hwaddr offset, 757 unsigned size) 758 { 759 StrongARMPPCInfo *s = opaque; 760 761 switch (offset) { 762 case PPDR: /* PPC Pin Direction registers */ 763 return s->dir | ~0x3fffff; 764 765 case PPSR: /* PPC Pin State registers */ 766 return (s->olevel & s->dir) | 767 (s->ilevel & ~s->dir) | 768 ~0x3fffff; 769 770 case PPAR: 771 return s->ppar | ~0x41000; 772 773 case PSDR: 774 return s->psdr; 775 776 case PPFR: 777 return s->ppfr | ~0x7f001; 778 779 default: 780 printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset); 781 } 782 783 return 0; 784 } 785 786 static void strongarm_ppc_write(void *opaque, hwaddr offset, 787 uint64_t value, unsigned size) 788 { 789 StrongARMPPCInfo *s = opaque; 790 791 switch (offset) { 792 case PPDR: /* PPC Pin Direction registers */ 793 s->dir = value & 0x3fffff; 794 strongarm_ppc_handler_update(s); 795 break; 796 797 case PPSR: /* PPC Pin State registers */ 798 s->olevel = value & s->dir & 0x3fffff; 799 strongarm_ppc_handler_update(s); 800 break; 801 802 case PPAR: 803 s->ppar = value & 0x41000; 804 break; 805 806 case PSDR: 807 s->psdr = value & 0x3fffff; 808 break; 809 810 case PPFR: 811 s->ppfr = value & 0x7f001; 812 break; 813 814 default: 815 printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset); 816 } 817 } 818 819 static const MemoryRegionOps strongarm_ppc_ops = { 820 .read = strongarm_ppc_read, 821 .write = strongarm_ppc_write, 822 .endianness = DEVICE_NATIVE_ENDIAN, 823 }; 824 825 static void strongarm_ppc_init(Object *obj) 826 { 827 DeviceState *dev = DEVICE(obj); 828 StrongARMPPCInfo *s = STRONGARM_PPC(obj); 829 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 830 831 qdev_init_gpio_in(dev, strongarm_ppc_set, 22); 832 qdev_init_gpio_out(dev, s->handler, 22); 833 834 memory_region_init_io(&s->iomem, obj, &strongarm_ppc_ops, s, 835 "ppc", 0x1000); 836 837 sysbus_init_mmio(sbd, &s->iomem); 838 } 839 840 static const VMStateDescription vmstate_strongarm_ppc_regs = { 841 .name = "strongarm-ppc", 842 .version_id = 0, 843 .minimum_version_id = 0, 844 .fields = (VMStateField[]) { 845 VMSTATE_UINT32(ilevel, StrongARMPPCInfo), 846 VMSTATE_UINT32(olevel, StrongARMPPCInfo), 847 VMSTATE_UINT32(dir, StrongARMPPCInfo), 848 VMSTATE_UINT32(ppar, StrongARMPPCInfo), 849 VMSTATE_UINT32(psdr, StrongARMPPCInfo), 850 VMSTATE_UINT32(ppfr, StrongARMPPCInfo), 851 VMSTATE_UINT32(prev_level, StrongARMPPCInfo), 852 VMSTATE_END_OF_LIST(), 853 }, 854 }; 855 856 static void strongarm_ppc_class_init(ObjectClass *klass, void *data) 857 { 858 DeviceClass *dc = DEVICE_CLASS(klass); 859 860 dc->desc = "StrongARM PPC controller"; 861 dc->vmsd = &vmstate_strongarm_ppc_regs; 862 } 863 864 static const TypeInfo strongarm_ppc_info = { 865 .name = TYPE_STRONGARM_PPC, 866 .parent = TYPE_SYS_BUS_DEVICE, 867 .instance_size = sizeof(StrongARMPPCInfo), 868 .instance_init = strongarm_ppc_init, 869 .class_init = strongarm_ppc_class_init, 870 }; 871 872 /* UART Ports */ 873 #define UTCR0 0x00 874 #define UTCR1 0x04 875 #define UTCR2 0x08 876 #define UTCR3 0x0c 877 #define UTDR 0x14 878 #define UTSR0 0x1c 879 #define UTSR1 0x20 880 881 #define UTCR0_PE (1 << 0) /* Parity enable */ 882 #define UTCR0_OES (1 << 1) /* Even parity */ 883 #define UTCR0_SBS (1 << 2) /* 2 stop bits */ 884 #define UTCR0_DSS (1 << 3) /* 8-bit data */ 885 886 #define UTCR3_RXE (1 << 0) /* Rx enable */ 887 #define UTCR3_TXE (1 << 1) /* Tx enable */ 888 #define UTCR3_BRK (1 << 2) /* Force Break */ 889 #define UTCR3_RIE (1 << 3) /* Rx int enable */ 890 #define UTCR3_TIE (1 << 4) /* Tx int enable */ 891 #define UTCR3_LBM (1 << 5) /* Loopback */ 892 893 #define UTSR0_TFS (1 << 0) /* Tx FIFO nearly empty */ 894 #define UTSR0_RFS (1 << 1) /* Rx FIFO nearly full */ 895 #define UTSR0_RID (1 << 2) /* Receiver Idle */ 896 #define UTSR0_RBB (1 << 3) /* Receiver begin break */ 897 #define UTSR0_REB (1 << 4) /* Receiver end break */ 898 #define UTSR0_EIF (1 << 5) /* Error in FIFO */ 899 900 #define UTSR1_RNE (1 << 1) /* Receive FIFO not empty */ 901 #define UTSR1_TNF (1 << 2) /* Transmit FIFO not full */ 902 #define UTSR1_PRE (1 << 3) /* Parity error */ 903 #define UTSR1_FRE (1 << 4) /* Frame error */ 904 #define UTSR1_ROR (1 << 5) /* Receive Over Run */ 905 906 #define RX_FIFO_PRE (1 << 8) 907 #define RX_FIFO_FRE (1 << 9) 908 #define RX_FIFO_ROR (1 << 10) 909 910 #define TYPE_STRONGARM_UART "strongarm-uart" 911 #define STRONGARM_UART(obj) \ 912 OBJECT_CHECK(StrongARMUARTState, (obj), TYPE_STRONGARM_UART) 913 914 typedef struct StrongARMUARTState { 915 SysBusDevice parent_obj; 916 917 MemoryRegion iomem; 918 CharBackend chr; 919 qemu_irq irq; 920 921 uint8_t utcr0; 922 uint16_t brd; 923 uint8_t utcr3; 924 uint8_t utsr0; 925 uint8_t utsr1; 926 927 uint8_t tx_fifo[8]; 928 uint8_t tx_start; 929 uint8_t tx_len; 930 uint16_t rx_fifo[12]; /* value + error flags in high bits */ 931 uint8_t rx_start; 932 uint8_t rx_len; 933 934 uint64_t char_transmit_time; /* time to transmit a char in ticks*/ 935 bool wait_break_end; 936 QEMUTimer *rx_timeout_timer; 937 QEMUTimer *tx_timer; 938 } StrongARMUARTState; 939 940 static void strongarm_uart_update_status(StrongARMUARTState *s) 941 { 942 uint16_t utsr1 = 0; 943 944 if (s->tx_len != 8) { 945 utsr1 |= UTSR1_TNF; 946 } 947 948 if (s->rx_len != 0) { 949 uint16_t ent = s->rx_fifo[s->rx_start]; 950 951 utsr1 |= UTSR1_RNE; 952 if (ent & RX_FIFO_PRE) { 953 s->utsr1 |= UTSR1_PRE; 954 } 955 if (ent & RX_FIFO_FRE) { 956 s->utsr1 |= UTSR1_FRE; 957 } 958 if (ent & RX_FIFO_ROR) { 959 s->utsr1 |= UTSR1_ROR; 960 } 961 } 962 963 s->utsr1 = utsr1; 964 } 965 966 static void strongarm_uart_update_int_status(StrongARMUARTState *s) 967 { 968 uint16_t utsr0 = s->utsr0 & 969 (UTSR0_REB | UTSR0_RBB | UTSR0_RID); 970 int i; 971 972 if ((s->utcr3 & UTCR3_TXE) && 973 (s->utcr3 & UTCR3_TIE) && 974 s->tx_len <= 4) { 975 utsr0 |= UTSR0_TFS; 976 } 977 978 if ((s->utcr3 & UTCR3_RXE) && 979 (s->utcr3 & UTCR3_RIE) && 980 s->rx_len > 4) { 981 utsr0 |= UTSR0_RFS; 982 } 983 984 for (i = 0; i < s->rx_len && i < 4; i++) 985 if (s->rx_fifo[(s->rx_start + i) % 12] & ~0xff) { 986 utsr0 |= UTSR0_EIF; 987 break; 988 } 989 990 s->utsr0 = utsr0; 991 qemu_set_irq(s->irq, utsr0); 992 } 993 994 static void strongarm_uart_update_parameters(StrongARMUARTState *s) 995 { 996 int speed, parity, data_bits, stop_bits, frame_size; 997 QEMUSerialSetParams ssp; 998 999 /* Start bit. */ 1000 frame_size = 1; 1001 if (s->utcr0 & UTCR0_PE) { 1002 /* Parity bit. */ 1003 frame_size++; 1004 if (s->utcr0 & UTCR0_OES) { 1005 parity = 'E'; 1006 } else { 1007 parity = 'O'; 1008 } 1009 } else { 1010 parity = 'N'; 1011 } 1012 if (s->utcr0 & UTCR0_SBS) { 1013 stop_bits = 2; 1014 } else { 1015 stop_bits = 1; 1016 } 1017 1018 data_bits = (s->utcr0 & UTCR0_DSS) ? 8 : 7; 1019 frame_size += data_bits + stop_bits; 1020 speed = 3686400 / 16 / (s->brd + 1); 1021 ssp.speed = speed; 1022 ssp.parity = parity; 1023 ssp.data_bits = data_bits; 1024 ssp.stop_bits = stop_bits; 1025 s->char_transmit_time = (NANOSECONDS_PER_SECOND / speed) * frame_size; 1026 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); 1027 1028 DPRINTF(stderr, "%s speed=%d parity=%c data=%d stop=%d\n", s->chr->label, 1029 speed, parity, data_bits, stop_bits); 1030 } 1031 1032 static void strongarm_uart_rx_to(void *opaque) 1033 { 1034 StrongARMUARTState *s = opaque; 1035 1036 if (s->rx_len) { 1037 s->utsr0 |= UTSR0_RID; 1038 strongarm_uart_update_int_status(s); 1039 } 1040 } 1041 1042 static void strongarm_uart_rx_push(StrongARMUARTState *s, uint16_t c) 1043 { 1044 if ((s->utcr3 & UTCR3_RXE) == 0) { 1045 /* rx disabled */ 1046 return; 1047 } 1048 1049 if (s->wait_break_end) { 1050 s->utsr0 |= UTSR0_REB; 1051 s->wait_break_end = false; 1052 } 1053 1054 if (s->rx_len < 12) { 1055 s->rx_fifo[(s->rx_start + s->rx_len) % 12] = c; 1056 s->rx_len++; 1057 } else 1058 s->rx_fifo[(s->rx_start + 11) % 12] |= RX_FIFO_ROR; 1059 } 1060 1061 static int strongarm_uart_can_receive(void *opaque) 1062 { 1063 StrongARMUARTState *s = opaque; 1064 1065 if (s->rx_len == 12) { 1066 return 0; 1067 } 1068 /* It's best not to get more than 2/3 of RX FIFO, so advertise that much */ 1069 if (s->rx_len < 8) { 1070 return 8 - s->rx_len; 1071 } 1072 return 1; 1073 } 1074 1075 static void strongarm_uart_receive(void *opaque, const uint8_t *buf, int size) 1076 { 1077 StrongARMUARTState *s = opaque; 1078 int i; 1079 1080 for (i = 0; i < size; i++) { 1081 strongarm_uart_rx_push(s, buf[i]); 1082 } 1083 1084 /* call the timeout receive callback in 3 char transmit time */ 1085 timer_mod(s->rx_timeout_timer, 1086 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 3); 1087 1088 strongarm_uart_update_status(s); 1089 strongarm_uart_update_int_status(s); 1090 } 1091 1092 static void strongarm_uart_event(void *opaque, int event) 1093 { 1094 StrongARMUARTState *s = opaque; 1095 if (event == CHR_EVENT_BREAK) { 1096 s->utsr0 |= UTSR0_RBB; 1097 strongarm_uart_rx_push(s, RX_FIFO_FRE); 1098 s->wait_break_end = true; 1099 strongarm_uart_update_status(s); 1100 strongarm_uart_update_int_status(s); 1101 } 1102 } 1103 1104 static void strongarm_uart_tx(void *opaque) 1105 { 1106 StrongARMUARTState *s = opaque; 1107 uint64_t new_xmit_ts = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 1108 1109 if (s->utcr3 & UTCR3_LBM) /* loopback */ { 1110 strongarm_uart_receive(s, &s->tx_fifo[s->tx_start], 1); 1111 } else if (qemu_chr_fe_backend_connected(&s->chr)) { 1112 /* XXX this blocks entire thread. Rewrite to use 1113 * qemu_chr_fe_write and background I/O callbacks */ 1114 qemu_chr_fe_write_all(&s->chr, &s->tx_fifo[s->tx_start], 1); 1115 } 1116 1117 s->tx_start = (s->tx_start + 1) % 8; 1118 s->tx_len--; 1119 if (s->tx_len) { 1120 timer_mod(s->tx_timer, new_xmit_ts + s->char_transmit_time); 1121 } 1122 strongarm_uart_update_status(s); 1123 strongarm_uart_update_int_status(s); 1124 } 1125 1126 static uint64_t strongarm_uart_read(void *opaque, hwaddr addr, 1127 unsigned size) 1128 { 1129 StrongARMUARTState *s = opaque; 1130 uint16_t ret; 1131 1132 switch (addr) { 1133 case UTCR0: 1134 return s->utcr0; 1135 1136 case UTCR1: 1137 return s->brd >> 8; 1138 1139 case UTCR2: 1140 return s->brd & 0xff; 1141 1142 case UTCR3: 1143 return s->utcr3; 1144 1145 case UTDR: 1146 if (s->rx_len != 0) { 1147 ret = s->rx_fifo[s->rx_start]; 1148 s->rx_start = (s->rx_start + 1) % 12; 1149 s->rx_len--; 1150 strongarm_uart_update_status(s); 1151 strongarm_uart_update_int_status(s); 1152 return ret; 1153 } 1154 return 0; 1155 1156 case UTSR0: 1157 return s->utsr0; 1158 1159 case UTSR1: 1160 return s->utsr1; 1161 1162 default: 1163 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr); 1164 return 0; 1165 } 1166 } 1167 1168 static void strongarm_uart_write(void *opaque, hwaddr addr, 1169 uint64_t value, unsigned size) 1170 { 1171 StrongARMUARTState *s = opaque; 1172 1173 switch (addr) { 1174 case UTCR0: 1175 s->utcr0 = value & 0x7f; 1176 strongarm_uart_update_parameters(s); 1177 break; 1178 1179 case UTCR1: 1180 s->brd = (s->brd & 0xff) | ((value & 0xf) << 8); 1181 strongarm_uart_update_parameters(s); 1182 break; 1183 1184 case UTCR2: 1185 s->brd = (s->brd & 0xf00) | (value & 0xff); 1186 strongarm_uart_update_parameters(s); 1187 break; 1188 1189 case UTCR3: 1190 s->utcr3 = value & 0x3f; 1191 if ((s->utcr3 & UTCR3_RXE) == 0) { 1192 s->rx_len = 0; 1193 } 1194 if ((s->utcr3 & UTCR3_TXE) == 0) { 1195 s->tx_len = 0; 1196 } 1197 strongarm_uart_update_status(s); 1198 strongarm_uart_update_int_status(s); 1199 break; 1200 1201 case UTDR: 1202 if ((s->utcr3 & UTCR3_TXE) && s->tx_len != 8) { 1203 s->tx_fifo[(s->tx_start + s->tx_len) % 8] = value; 1204 s->tx_len++; 1205 strongarm_uart_update_status(s); 1206 strongarm_uart_update_int_status(s); 1207 if (s->tx_len == 1) { 1208 strongarm_uart_tx(s); 1209 } 1210 } 1211 break; 1212 1213 case UTSR0: 1214 s->utsr0 = s->utsr0 & ~(value & 1215 (UTSR0_REB | UTSR0_RBB | UTSR0_RID)); 1216 strongarm_uart_update_int_status(s); 1217 break; 1218 1219 default: 1220 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr); 1221 } 1222 } 1223 1224 static const MemoryRegionOps strongarm_uart_ops = { 1225 .read = strongarm_uart_read, 1226 .write = strongarm_uart_write, 1227 .endianness = DEVICE_NATIVE_ENDIAN, 1228 }; 1229 1230 static void strongarm_uart_init(Object *obj) 1231 { 1232 StrongARMUARTState *s = STRONGARM_UART(obj); 1233 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 1234 1235 memory_region_init_io(&s->iomem, obj, &strongarm_uart_ops, s, 1236 "uart", 0x10000); 1237 sysbus_init_mmio(dev, &s->iomem); 1238 sysbus_init_irq(dev, &s->irq); 1239 1240 s->rx_timeout_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, strongarm_uart_rx_to, s); 1241 s->tx_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, strongarm_uart_tx, s); 1242 } 1243 1244 static void strongarm_uart_realize(DeviceState *dev, Error **errp) 1245 { 1246 StrongARMUARTState *s = STRONGARM_UART(dev); 1247 1248 qemu_chr_fe_set_handlers(&s->chr, 1249 strongarm_uart_can_receive, 1250 strongarm_uart_receive, 1251 strongarm_uart_event, 1252 NULL, s, NULL, true); 1253 } 1254 1255 static void strongarm_uart_reset(DeviceState *dev) 1256 { 1257 StrongARMUARTState *s = STRONGARM_UART(dev); 1258 1259 s->utcr0 = UTCR0_DSS; /* 8 data, no parity */ 1260 s->brd = 23; /* 9600 */ 1261 /* enable send & recv - this actually violates spec */ 1262 s->utcr3 = UTCR3_TXE | UTCR3_RXE; 1263 1264 s->rx_len = s->tx_len = 0; 1265 1266 strongarm_uart_update_parameters(s); 1267 strongarm_uart_update_status(s); 1268 strongarm_uart_update_int_status(s); 1269 } 1270 1271 static int strongarm_uart_post_load(void *opaque, int version_id) 1272 { 1273 StrongARMUARTState *s = opaque; 1274 1275 strongarm_uart_update_parameters(s); 1276 strongarm_uart_update_status(s); 1277 strongarm_uart_update_int_status(s); 1278 1279 /* tx and restart timer */ 1280 if (s->tx_len) { 1281 strongarm_uart_tx(s); 1282 } 1283 1284 /* restart rx timeout timer */ 1285 if (s->rx_len) { 1286 timer_mod(s->rx_timeout_timer, 1287 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 3); 1288 } 1289 1290 return 0; 1291 } 1292 1293 static const VMStateDescription vmstate_strongarm_uart_regs = { 1294 .name = "strongarm-uart", 1295 .version_id = 0, 1296 .minimum_version_id = 0, 1297 .post_load = strongarm_uart_post_load, 1298 .fields = (VMStateField[]) { 1299 VMSTATE_UINT8(utcr0, StrongARMUARTState), 1300 VMSTATE_UINT16(brd, StrongARMUARTState), 1301 VMSTATE_UINT8(utcr3, StrongARMUARTState), 1302 VMSTATE_UINT8(utsr0, StrongARMUARTState), 1303 VMSTATE_UINT8_ARRAY(tx_fifo, StrongARMUARTState, 8), 1304 VMSTATE_UINT8(tx_start, StrongARMUARTState), 1305 VMSTATE_UINT8(tx_len, StrongARMUARTState), 1306 VMSTATE_UINT16_ARRAY(rx_fifo, StrongARMUARTState, 12), 1307 VMSTATE_UINT8(rx_start, StrongARMUARTState), 1308 VMSTATE_UINT8(rx_len, StrongARMUARTState), 1309 VMSTATE_BOOL(wait_break_end, StrongARMUARTState), 1310 VMSTATE_END_OF_LIST(), 1311 }, 1312 }; 1313 1314 static Property strongarm_uart_properties[] = { 1315 DEFINE_PROP_CHR("chardev", StrongARMUARTState, chr), 1316 DEFINE_PROP_END_OF_LIST(), 1317 }; 1318 1319 static void strongarm_uart_class_init(ObjectClass *klass, void *data) 1320 { 1321 DeviceClass *dc = DEVICE_CLASS(klass); 1322 1323 dc->desc = "StrongARM UART controller"; 1324 dc->reset = strongarm_uart_reset; 1325 dc->vmsd = &vmstate_strongarm_uart_regs; 1326 dc->props = strongarm_uart_properties; 1327 dc->realize = strongarm_uart_realize; 1328 } 1329 1330 static const TypeInfo strongarm_uart_info = { 1331 .name = TYPE_STRONGARM_UART, 1332 .parent = TYPE_SYS_BUS_DEVICE, 1333 .instance_size = sizeof(StrongARMUARTState), 1334 .instance_init = strongarm_uart_init, 1335 .class_init = strongarm_uart_class_init, 1336 }; 1337 1338 /* Synchronous Serial Ports */ 1339 1340 #define TYPE_STRONGARM_SSP "strongarm-ssp" 1341 #define STRONGARM_SSP(obj) \ 1342 OBJECT_CHECK(StrongARMSSPState, (obj), TYPE_STRONGARM_SSP) 1343 1344 typedef struct StrongARMSSPState { 1345 SysBusDevice parent_obj; 1346 1347 MemoryRegion iomem; 1348 qemu_irq irq; 1349 SSIBus *bus; 1350 1351 uint16_t sscr[2]; 1352 uint16_t sssr; 1353 1354 uint16_t rx_fifo[8]; 1355 uint8_t rx_level; 1356 uint8_t rx_start; 1357 } StrongARMSSPState; 1358 1359 #define SSCR0 0x60 /* SSP Control register 0 */ 1360 #define SSCR1 0x64 /* SSP Control register 1 */ 1361 #define SSDR 0x6c /* SSP Data register */ 1362 #define SSSR 0x74 /* SSP Status register */ 1363 1364 /* Bitfields for above registers */ 1365 #define SSCR0_SPI(x) (((x) & 0x30) == 0x00) 1366 #define SSCR0_SSP(x) (((x) & 0x30) == 0x10) 1367 #define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20) 1368 #define SSCR0_PSP(x) (((x) & 0x30) == 0x30) 1369 #define SSCR0_SSE (1 << 7) 1370 #define SSCR0_DSS(x) (((x) & 0xf) + 1) 1371 #define SSCR1_RIE (1 << 0) 1372 #define SSCR1_TIE (1 << 1) 1373 #define SSCR1_LBM (1 << 2) 1374 #define SSSR_TNF (1 << 2) 1375 #define SSSR_RNE (1 << 3) 1376 #define SSSR_TFS (1 << 5) 1377 #define SSSR_RFS (1 << 6) 1378 #define SSSR_ROR (1 << 7) 1379 #define SSSR_RW 0x0080 1380 1381 static void strongarm_ssp_int_update(StrongARMSSPState *s) 1382 { 1383 int level = 0; 1384 1385 level |= (s->sssr & SSSR_ROR); 1386 level |= (s->sssr & SSSR_RFS) && (s->sscr[1] & SSCR1_RIE); 1387 level |= (s->sssr & SSSR_TFS) && (s->sscr[1] & SSCR1_TIE); 1388 qemu_set_irq(s->irq, level); 1389 } 1390 1391 static void strongarm_ssp_fifo_update(StrongARMSSPState *s) 1392 { 1393 s->sssr &= ~SSSR_TFS; 1394 s->sssr &= ~SSSR_TNF; 1395 if (s->sscr[0] & SSCR0_SSE) { 1396 if (s->rx_level >= 4) { 1397 s->sssr |= SSSR_RFS; 1398 } else { 1399 s->sssr &= ~SSSR_RFS; 1400 } 1401 if (s->rx_level) { 1402 s->sssr |= SSSR_RNE; 1403 } else { 1404 s->sssr &= ~SSSR_RNE; 1405 } 1406 /* TX FIFO is never filled, so it is always in underrun 1407 condition if SSP is enabled */ 1408 s->sssr |= SSSR_TFS; 1409 s->sssr |= SSSR_TNF; 1410 } 1411 1412 strongarm_ssp_int_update(s); 1413 } 1414 1415 static uint64_t strongarm_ssp_read(void *opaque, hwaddr addr, 1416 unsigned size) 1417 { 1418 StrongARMSSPState *s = opaque; 1419 uint32_t retval; 1420 1421 switch (addr) { 1422 case SSCR0: 1423 return s->sscr[0]; 1424 case SSCR1: 1425 return s->sscr[1]; 1426 case SSSR: 1427 return s->sssr; 1428 case SSDR: 1429 if (~s->sscr[0] & SSCR0_SSE) { 1430 return 0xffffffff; 1431 } 1432 if (s->rx_level < 1) { 1433 printf("%s: SSP Rx Underrun\n", __func__); 1434 return 0xffffffff; 1435 } 1436 s->rx_level--; 1437 retval = s->rx_fifo[s->rx_start++]; 1438 s->rx_start &= 0x7; 1439 strongarm_ssp_fifo_update(s); 1440 return retval; 1441 default: 1442 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr); 1443 break; 1444 } 1445 return 0; 1446 } 1447 1448 static void strongarm_ssp_write(void *opaque, hwaddr addr, 1449 uint64_t value, unsigned size) 1450 { 1451 StrongARMSSPState *s = opaque; 1452 1453 switch (addr) { 1454 case SSCR0: 1455 s->sscr[0] = value & 0xffbf; 1456 if ((s->sscr[0] & SSCR0_SSE) && SSCR0_DSS(value) < 4) { 1457 printf("%s: Wrong data size: %i bits\n", __func__, 1458 (int)SSCR0_DSS(value)); 1459 } 1460 if (!(value & SSCR0_SSE)) { 1461 s->sssr = 0; 1462 s->rx_level = 0; 1463 } 1464 strongarm_ssp_fifo_update(s); 1465 break; 1466 1467 case SSCR1: 1468 s->sscr[1] = value & 0x2f; 1469 if (value & SSCR1_LBM) { 1470 printf("%s: Attempt to use SSP LBM mode\n", __func__); 1471 } 1472 strongarm_ssp_fifo_update(s); 1473 break; 1474 1475 case SSSR: 1476 s->sssr &= ~(value & SSSR_RW); 1477 strongarm_ssp_int_update(s); 1478 break; 1479 1480 case SSDR: 1481 if (SSCR0_UWIRE(s->sscr[0])) { 1482 value &= 0xff; 1483 } else 1484 /* Note how 32bits overflow does no harm here */ 1485 value &= (1 << SSCR0_DSS(s->sscr[0])) - 1; 1486 1487 /* Data goes from here to the Tx FIFO and is shifted out from 1488 * there directly to the slave, no need to buffer it. 1489 */ 1490 if (s->sscr[0] & SSCR0_SSE) { 1491 uint32_t readval; 1492 if (s->sscr[1] & SSCR1_LBM) { 1493 readval = value; 1494 } else { 1495 readval = ssi_transfer(s->bus, value); 1496 } 1497 1498 if (s->rx_level < 0x08) { 1499 s->rx_fifo[(s->rx_start + s->rx_level++) & 0x7] = readval; 1500 } else { 1501 s->sssr |= SSSR_ROR; 1502 } 1503 } 1504 strongarm_ssp_fifo_update(s); 1505 break; 1506 1507 default: 1508 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr); 1509 break; 1510 } 1511 } 1512 1513 static const MemoryRegionOps strongarm_ssp_ops = { 1514 .read = strongarm_ssp_read, 1515 .write = strongarm_ssp_write, 1516 .endianness = DEVICE_NATIVE_ENDIAN, 1517 }; 1518 1519 static int strongarm_ssp_post_load(void *opaque, int version_id) 1520 { 1521 StrongARMSSPState *s = opaque; 1522 1523 strongarm_ssp_fifo_update(s); 1524 1525 return 0; 1526 } 1527 1528 static void strongarm_ssp_init(Object *obj) 1529 { 1530 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 1531 DeviceState *dev = DEVICE(sbd); 1532 StrongARMSSPState *s = STRONGARM_SSP(dev); 1533 1534 sysbus_init_irq(sbd, &s->irq); 1535 1536 memory_region_init_io(&s->iomem, obj, &strongarm_ssp_ops, s, 1537 "ssp", 0x1000); 1538 sysbus_init_mmio(sbd, &s->iomem); 1539 1540 s->bus = ssi_create_bus(dev, "ssi"); 1541 } 1542 1543 static void strongarm_ssp_reset(DeviceState *dev) 1544 { 1545 StrongARMSSPState *s = STRONGARM_SSP(dev); 1546 1547 s->sssr = 0x03; /* 3 bit data, SPI, disabled */ 1548 s->rx_start = 0; 1549 s->rx_level = 0; 1550 } 1551 1552 static const VMStateDescription vmstate_strongarm_ssp_regs = { 1553 .name = "strongarm-ssp", 1554 .version_id = 0, 1555 .minimum_version_id = 0, 1556 .post_load = strongarm_ssp_post_load, 1557 .fields = (VMStateField[]) { 1558 VMSTATE_UINT16_ARRAY(sscr, StrongARMSSPState, 2), 1559 VMSTATE_UINT16(sssr, StrongARMSSPState), 1560 VMSTATE_UINT16_ARRAY(rx_fifo, StrongARMSSPState, 8), 1561 VMSTATE_UINT8(rx_start, StrongARMSSPState), 1562 VMSTATE_UINT8(rx_level, StrongARMSSPState), 1563 VMSTATE_END_OF_LIST(), 1564 }, 1565 }; 1566 1567 static void strongarm_ssp_class_init(ObjectClass *klass, void *data) 1568 { 1569 DeviceClass *dc = DEVICE_CLASS(klass); 1570 1571 dc->desc = "StrongARM SSP controller"; 1572 dc->reset = strongarm_ssp_reset; 1573 dc->vmsd = &vmstate_strongarm_ssp_regs; 1574 } 1575 1576 static const TypeInfo strongarm_ssp_info = { 1577 .name = TYPE_STRONGARM_SSP, 1578 .parent = TYPE_SYS_BUS_DEVICE, 1579 .instance_size = sizeof(StrongARMSSPState), 1580 .instance_init = strongarm_ssp_init, 1581 .class_init = strongarm_ssp_class_init, 1582 }; 1583 1584 /* Main CPU functions */ 1585 StrongARMState *sa1110_init(MemoryRegion *sysmem, 1586 unsigned int sdram_size, const char *cpu_type) 1587 { 1588 StrongARMState *s; 1589 int i; 1590 1591 s = g_new0(StrongARMState, 1); 1592 1593 if (strncmp(cpu_type, "sa1110", 6)) { 1594 error_report("Machine requires a SA1110 processor."); 1595 exit(1); 1596 } 1597 1598 s->cpu = ARM_CPU(cpu_create(cpu_type)); 1599 1600 memory_region_allocate_system_memory(&s->sdram, NULL, "strongarm.sdram", 1601 sdram_size); 1602 memory_region_add_subregion(sysmem, SA_SDCS0, &s->sdram); 1603 1604 s->pic = sysbus_create_varargs("strongarm_pic", 0x90050000, 1605 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ), 1606 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_FIQ), 1607 NULL); 1608 1609 sysbus_create_varargs("pxa25x-timer", 0x90000000, 1610 qdev_get_gpio_in(s->pic, SA_PIC_OSTC0), 1611 qdev_get_gpio_in(s->pic, SA_PIC_OSTC1), 1612 qdev_get_gpio_in(s->pic, SA_PIC_OSTC2), 1613 qdev_get_gpio_in(s->pic, SA_PIC_OSTC3), 1614 NULL); 1615 1616 sysbus_create_simple(TYPE_STRONGARM_RTC, 0x90010000, 1617 qdev_get_gpio_in(s->pic, SA_PIC_RTC_ALARM)); 1618 1619 s->gpio = strongarm_gpio_init(0x90040000, s->pic); 1620 1621 s->ppc = sysbus_create_varargs(TYPE_STRONGARM_PPC, 0x90060000, NULL); 1622 1623 for (i = 0; sa_serial[i].io_base; i++) { 1624 DeviceState *dev = qdev_create(NULL, TYPE_STRONGARM_UART); 1625 qdev_prop_set_chr(dev, "chardev", serial_hd(i)); 1626 qdev_init_nofail(dev); 1627 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 1628 sa_serial[i].io_base); 1629 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, 1630 qdev_get_gpio_in(s->pic, sa_serial[i].irq)); 1631 } 1632 1633 s->ssp = sysbus_create_varargs(TYPE_STRONGARM_SSP, 0x80070000, 1634 qdev_get_gpio_in(s->pic, SA_PIC_SSP), NULL); 1635 s->ssp_bus = (SSIBus *)qdev_get_child_bus(s->ssp, "ssi"); 1636 1637 return s; 1638 } 1639 1640 static void strongarm_register_types(void) 1641 { 1642 type_register_static(&strongarm_pic_info); 1643 type_register_static(&strongarm_rtc_sysbus_info); 1644 type_register_static(&strongarm_gpio_info); 1645 type_register_static(&strongarm_ppc_info); 1646 type_register_static(&strongarm_uart_info); 1647 type_register_static(&strongarm_ssp_info); 1648 } 1649 1650 type_init(strongarm_register_types) 1651