1 /* 2 * StrongARM SA-1100/SA-1110 emulation 3 * 4 * Copyright (C) 2011 Dmitry Eremin-Solenikov 5 * 6 * Largely based on StrongARM emulation: 7 * Copyright (c) 2006 Openedhand Ltd. 8 * Written by Andrzej Zaborowski <balrog@zabor.org> 9 * 10 * UART code based on QEMU 16550A UART emulation 11 * Copyright (c) 2003-2004 Fabrice Bellard 12 * Copyright (c) 2008 Citrix Systems, Inc. 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License version 2 as 16 * published by the Free Software Foundation. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License along 24 * with this program; if not, see <http://www.gnu.org/licenses/>. 25 * 26 * Contributions after 2012-01-13 are licensed under the terms of the 27 * GNU GPL, version 2 or (at your option) any later version. 28 */ 29 #include "hw/sysbus.h" 30 #include "strongarm.h" 31 #include "qemu/error-report.h" 32 #include "hw/arm/arm.h" 33 #include "sysemu/char.h" 34 #include "sysemu/sysemu.h" 35 #include "hw/ssi.h" 36 37 //#define DEBUG 38 39 /* 40 TODO 41 - Implement cp15, c14 ? 42 - Implement cp15, c15 !!! (idle used in L) 43 - Implement idle mode handling/DIM 44 - Implement sleep mode/Wake sources 45 - Implement reset control 46 - Implement memory control regs 47 - PCMCIA handling 48 - Maybe support MBGNT/MBREQ 49 - DMA channels 50 - GPCLK 51 - IrDA 52 - MCP 53 - Enhance UART with modem signals 54 */ 55 56 #ifdef DEBUG 57 # define DPRINTF(format, ...) printf(format , ## __VA_ARGS__) 58 #else 59 # define DPRINTF(format, ...) do { } while (0) 60 #endif 61 62 static struct { 63 hwaddr io_base; 64 int irq; 65 } sa_serial[] = { 66 { 0x80010000, SA_PIC_UART1 }, 67 { 0x80030000, SA_PIC_UART2 }, 68 { 0x80050000, SA_PIC_UART3 }, 69 { 0, 0 } 70 }; 71 72 /* Interrupt Controller */ 73 74 #define TYPE_STRONGARM_PIC "strongarm_pic" 75 #define STRONGARM_PIC(obj) \ 76 OBJECT_CHECK(StrongARMPICState, (obj), TYPE_STRONGARM_PIC) 77 78 typedef struct StrongARMPICState { 79 SysBusDevice parent_obj; 80 81 MemoryRegion iomem; 82 qemu_irq irq; 83 qemu_irq fiq; 84 85 uint32_t pending; 86 uint32_t enabled; 87 uint32_t is_fiq; 88 uint32_t int_idle; 89 } StrongARMPICState; 90 91 #define ICIP 0x00 92 #define ICMR 0x04 93 #define ICLR 0x08 94 #define ICFP 0x10 95 #define ICPR 0x20 96 #define ICCR 0x0c 97 98 #define SA_PIC_SRCS 32 99 100 101 static void strongarm_pic_update(void *opaque) 102 { 103 StrongARMPICState *s = opaque; 104 105 /* FIXME: reflect DIM */ 106 qemu_set_irq(s->fiq, s->pending & s->enabled & s->is_fiq); 107 qemu_set_irq(s->irq, s->pending & s->enabled & ~s->is_fiq); 108 } 109 110 static void strongarm_pic_set_irq(void *opaque, int irq, int level) 111 { 112 StrongARMPICState *s = opaque; 113 114 if (level) { 115 s->pending |= 1 << irq; 116 } else { 117 s->pending &= ~(1 << irq); 118 } 119 120 strongarm_pic_update(s); 121 } 122 123 static uint64_t strongarm_pic_mem_read(void *opaque, hwaddr offset, 124 unsigned size) 125 { 126 StrongARMPICState *s = opaque; 127 128 switch (offset) { 129 case ICIP: 130 return s->pending & ~s->is_fiq & s->enabled; 131 case ICMR: 132 return s->enabled; 133 case ICLR: 134 return s->is_fiq; 135 case ICCR: 136 return s->int_idle == 0; 137 case ICFP: 138 return s->pending & s->is_fiq & s->enabled; 139 case ICPR: 140 return s->pending; 141 default: 142 printf("%s: Bad register offset 0x" TARGET_FMT_plx "\n", 143 __func__, offset); 144 return 0; 145 } 146 } 147 148 static void strongarm_pic_mem_write(void *opaque, hwaddr offset, 149 uint64_t value, unsigned size) 150 { 151 StrongARMPICState *s = opaque; 152 153 switch (offset) { 154 case ICMR: 155 s->enabled = value; 156 break; 157 case ICLR: 158 s->is_fiq = value; 159 break; 160 case ICCR: 161 s->int_idle = (value & 1) ? 0 : ~0; 162 break; 163 default: 164 printf("%s: Bad register offset 0x" TARGET_FMT_plx "\n", 165 __func__, offset); 166 break; 167 } 168 strongarm_pic_update(s); 169 } 170 171 static const MemoryRegionOps strongarm_pic_ops = { 172 .read = strongarm_pic_mem_read, 173 .write = strongarm_pic_mem_write, 174 .endianness = DEVICE_NATIVE_ENDIAN, 175 }; 176 177 static int strongarm_pic_initfn(SysBusDevice *sbd) 178 { 179 DeviceState *dev = DEVICE(sbd); 180 StrongARMPICState *s = STRONGARM_PIC(dev); 181 182 qdev_init_gpio_in(dev, strongarm_pic_set_irq, SA_PIC_SRCS); 183 memory_region_init_io(&s->iomem, OBJECT(s), &strongarm_pic_ops, s, 184 "pic", 0x1000); 185 sysbus_init_mmio(sbd, &s->iomem); 186 sysbus_init_irq(sbd, &s->irq); 187 sysbus_init_irq(sbd, &s->fiq); 188 189 return 0; 190 } 191 192 static int strongarm_pic_post_load(void *opaque, int version_id) 193 { 194 strongarm_pic_update(opaque); 195 return 0; 196 } 197 198 static VMStateDescription vmstate_strongarm_pic_regs = { 199 .name = "strongarm_pic", 200 .version_id = 0, 201 .minimum_version_id = 0, 202 .post_load = strongarm_pic_post_load, 203 .fields = (VMStateField[]) { 204 VMSTATE_UINT32(pending, StrongARMPICState), 205 VMSTATE_UINT32(enabled, StrongARMPICState), 206 VMSTATE_UINT32(is_fiq, StrongARMPICState), 207 VMSTATE_UINT32(int_idle, StrongARMPICState), 208 VMSTATE_END_OF_LIST(), 209 }, 210 }; 211 212 static void strongarm_pic_class_init(ObjectClass *klass, void *data) 213 { 214 DeviceClass *dc = DEVICE_CLASS(klass); 215 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 216 217 k->init = strongarm_pic_initfn; 218 dc->desc = "StrongARM PIC"; 219 dc->vmsd = &vmstate_strongarm_pic_regs; 220 } 221 222 static const TypeInfo strongarm_pic_info = { 223 .name = TYPE_STRONGARM_PIC, 224 .parent = TYPE_SYS_BUS_DEVICE, 225 .instance_size = sizeof(StrongARMPICState), 226 .class_init = strongarm_pic_class_init, 227 }; 228 229 /* Real-Time Clock */ 230 #define RTAR 0x00 /* RTC Alarm register */ 231 #define RCNR 0x04 /* RTC Counter register */ 232 #define RTTR 0x08 /* RTC Timer Trim register */ 233 #define RTSR 0x10 /* RTC Status register */ 234 235 #define RTSR_AL (1 << 0) /* RTC Alarm detected */ 236 #define RTSR_HZ (1 << 1) /* RTC 1Hz detected */ 237 #define RTSR_ALE (1 << 2) /* RTC Alarm enable */ 238 #define RTSR_HZE (1 << 3) /* RTC 1Hz enable */ 239 240 /* 16 LSB of RTTR are clockdiv for internal trim logic, 241 * trim delete isn't emulated, so 242 * f = 32 768 / (RTTR_trim + 1) */ 243 244 #define TYPE_STRONGARM_RTC "strongarm-rtc" 245 #define STRONGARM_RTC(obj) \ 246 OBJECT_CHECK(StrongARMRTCState, (obj), TYPE_STRONGARM_RTC) 247 248 typedef struct StrongARMRTCState { 249 SysBusDevice parent_obj; 250 251 MemoryRegion iomem; 252 uint32_t rttr; 253 uint32_t rtsr; 254 uint32_t rtar; 255 uint32_t last_rcnr; 256 int64_t last_hz; 257 QEMUTimer *rtc_alarm; 258 QEMUTimer *rtc_hz; 259 qemu_irq rtc_irq; 260 qemu_irq rtc_hz_irq; 261 } StrongARMRTCState; 262 263 static inline void strongarm_rtc_int_update(StrongARMRTCState *s) 264 { 265 qemu_set_irq(s->rtc_irq, s->rtsr & RTSR_AL); 266 qemu_set_irq(s->rtc_hz_irq, s->rtsr & RTSR_HZ); 267 } 268 269 static void strongarm_rtc_hzupdate(StrongARMRTCState *s) 270 { 271 int64_t rt = qemu_clock_get_ms(rtc_clock); 272 s->last_rcnr += ((rt - s->last_hz) << 15) / 273 (1000 * ((s->rttr & 0xffff) + 1)); 274 s->last_hz = rt; 275 } 276 277 static inline void strongarm_rtc_timer_update(StrongARMRTCState *s) 278 { 279 if ((s->rtsr & RTSR_HZE) && !(s->rtsr & RTSR_HZ)) { 280 timer_mod(s->rtc_hz, s->last_hz + 1000); 281 } else { 282 timer_del(s->rtc_hz); 283 } 284 285 if ((s->rtsr & RTSR_ALE) && !(s->rtsr & RTSR_AL)) { 286 timer_mod(s->rtc_alarm, s->last_hz + 287 (((s->rtar - s->last_rcnr) * 1000 * 288 ((s->rttr & 0xffff) + 1)) >> 15)); 289 } else { 290 timer_del(s->rtc_alarm); 291 } 292 } 293 294 static inline void strongarm_rtc_alarm_tick(void *opaque) 295 { 296 StrongARMRTCState *s = opaque; 297 s->rtsr |= RTSR_AL; 298 strongarm_rtc_timer_update(s); 299 strongarm_rtc_int_update(s); 300 } 301 302 static inline void strongarm_rtc_hz_tick(void *opaque) 303 { 304 StrongARMRTCState *s = opaque; 305 s->rtsr |= RTSR_HZ; 306 strongarm_rtc_timer_update(s); 307 strongarm_rtc_int_update(s); 308 } 309 310 static uint64_t strongarm_rtc_read(void *opaque, hwaddr addr, 311 unsigned size) 312 { 313 StrongARMRTCState *s = opaque; 314 315 switch (addr) { 316 case RTTR: 317 return s->rttr; 318 case RTSR: 319 return s->rtsr; 320 case RTAR: 321 return s->rtar; 322 case RCNR: 323 return s->last_rcnr + 324 ((qemu_clock_get_ms(rtc_clock) - s->last_hz) << 15) / 325 (1000 * ((s->rttr & 0xffff) + 1)); 326 default: 327 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr); 328 return 0; 329 } 330 } 331 332 static void strongarm_rtc_write(void *opaque, hwaddr addr, 333 uint64_t value, unsigned size) 334 { 335 StrongARMRTCState *s = opaque; 336 uint32_t old_rtsr; 337 338 switch (addr) { 339 case RTTR: 340 strongarm_rtc_hzupdate(s); 341 s->rttr = value; 342 strongarm_rtc_timer_update(s); 343 break; 344 345 case RTSR: 346 old_rtsr = s->rtsr; 347 s->rtsr = (value & (RTSR_ALE | RTSR_HZE)) | 348 (s->rtsr & ~(value & (RTSR_AL | RTSR_HZ))); 349 350 if (s->rtsr != old_rtsr) { 351 strongarm_rtc_timer_update(s); 352 } 353 354 strongarm_rtc_int_update(s); 355 break; 356 357 case RTAR: 358 s->rtar = value; 359 strongarm_rtc_timer_update(s); 360 break; 361 362 case RCNR: 363 strongarm_rtc_hzupdate(s); 364 s->last_rcnr = value; 365 strongarm_rtc_timer_update(s); 366 break; 367 368 default: 369 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr); 370 } 371 } 372 373 static const MemoryRegionOps strongarm_rtc_ops = { 374 .read = strongarm_rtc_read, 375 .write = strongarm_rtc_write, 376 .endianness = DEVICE_NATIVE_ENDIAN, 377 }; 378 379 static int strongarm_rtc_init(SysBusDevice *dev) 380 { 381 StrongARMRTCState *s = STRONGARM_RTC(dev); 382 struct tm tm; 383 384 s->rttr = 0x0; 385 s->rtsr = 0; 386 387 qemu_get_timedate(&tm, 0); 388 389 s->last_rcnr = (uint32_t) mktimegm(&tm); 390 s->last_hz = qemu_clock_get_ms(rtc_clock); 391 392 s->rtc_alarm = timer_new_ms(rtc_clock, strongarm_rtc_alarm_tick, s); 393 s->rtc_hz = timer_new_ms(rtc_clock, strongarm_rtc_hz_tick, s); 394 395 sysbus_init_irq(dev, &s->rtc_irq); 396 sysbus_init_irq(dev, &s->rtc_hz_irq); 397 398 memory_region_init_io(&s->iomem, OBJECT(s), &strongarm_rtc_ops, s, 399 "rtc", 0x10000); 400 sysbus_init_mmio(dev, &s->iomem); 401 402 return 0; 403 } 404 405 static void strongarm_rtc_pre_save(void *opaque) 406 { 407 StrongARMRTCState *s = opaque; 408 409 strongarm_rtc_hzupdate(s); 410 } 411 412 static int strongarm_rtc_post_load(void *opaque, int version_id) 413 { 414 StrongARMRTCState *s = opaque; 415 416 strongarm_rtc_timer_update(s); 417 strongarm_rtc_int_update(s); 418 419 return 0; 420 } 421 422 static const VMStateDescription vmstate_strongarm_rtc_regs = { 423 .name = "strongarm-rtc", 424 .version_id = 0, 425 .minimum_version_id = 0, 426 .pre_save = strongarm_rtc_pre_save, 427 .post_load = strongarm_rtc_post_load, 428 .fields = (VMStateField[]) { 429 VMSTATE_UINT32(rttr, StrongARMRTCState), 430 VMSTATE_UINT32(rtsr, StrongARMRTCState), 431 VMSTATE_UINT32(rtar, StrongARMRTCState), 432 VMSTATE_UINT32(last_rcnr, StrongARMRTCState), 433 VMSTATE_INT64(last_hz, StrongARMRTCState), 434 VMSTATE_END_OF_LIST(), 435 }, 436 }; 437 438 static void strongarm_rtc_sysbus_class_init(ObjectClass *klass, void *data) 439 { 440 DeviceClass *dc = DEVICE_CLASS(klass); 441 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 442 443 k->init = strongarm_rtc_init; 444 dc->desc = "StrongARM RTC Controller"; 445 dc->vmsd = &vmstate_strongarm_rtc_regs; 446 } 447 448 static const TypeInfo strongarm_rtc_sysbus_info = { 449 .name = TYPE_STRONGARM_RTC, 450 .parent = TYPE_SYS_BUS_DEVICE, 451 .instance_size = sizeof(StrongARMRTCState), 452 .class_init = strongarm_rtc_sysbus_class_init, 453 }; 454 455 /* GPIO */ 456 #define GPLR 0x00 457 #define GPDR 0x04 458 #define GPSR 0x08 459 #define GPCR 0x0c 460 #define GRER 0x10 461 #define GFER 0x14 462 #define GEDR 0x18 463 #define GAFR 0x1c 464 465 #define TYPE_STRONGARM_GPIO "strongarm-gpio" 466 #define STRONGARM_GPIO(obj) \ 467 OBJECT_CHECK(StrongARMGPIOInfo, (obj), TYPE_STRONGARM_GPIO) 468 469 typedef struct StrongARMGPIOInfo StrongARMGPIOInfo; 470 struct StrongARMGPIOInfo { 471 SysBusDevice busdev; 472 MemoryRegion iomem; 473 qemu_irq handler[28]; 474 qemu_irq irqs[11]; 475 qemu_irq irqX; 476 477 uint32_t ilevel; 478 uint32_t olevel; 479 uint32_t dir; 480 uint32_t rising; 481 uint32_t falling; 482 uint32_t status; 483 uint32_t gafr; 484 485 uint32_t prev_level; 486 }; 487 488 489 static void strongarm_gpio_irq_update(StrongARMGPIOInfo *s) 490 { 491 int i; 492 for (i = 0; i < 11; i++) { 493 qemu_set_irq(s->irqs[i], s->status & (1 << i)); 494 } 495 496 qemu_set_irq(s->irqX, (s->status & ~0x7ff)); 497 } 498 499 static void strongarm_gpio_set(void *opaque, int line, int level) 500 { 501 StrongARMGPIOInfo *s = opaque; 502 uint32_t mask; 503 504 mask = 1 << line; 505 506 if (level) { 507 s->status |= s->rising & mask & 508 ~s->ilevel & ~s->dir; 509 s->ilevel |= mask; 510 } else { 511 s->status |= s->falling & mask & 512 s->ilevel & ~s->dir; 513 s->ilevel &= ~mask; 514 } 515 516 if (s->status & mask) { 517 strongarm_gpio_irq_update(s); 518 } 519 } 520 521 static void strongarm_gpio_handler_update(StrongARMGPIOInfo *s) 522 { 523 uint32_t level, diff; 524 int bit; 525 526 level = s->olevel & s->dir; 527 528 for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) { 529 bit = ffs(diff) - 1; 530 qemu_set_irq(s->handler[bit], (level >> bit) & 1); 531 } 532 533 s->prev_level = level; 534 } 535 536 static uint64_t strongarm_gpio_read(void *opaque, hwaddr offset, 537 unsigned size) 538 { 539 StrongARMGPIOInfo *s = opaque; 540 541 switch (offset) { 542 case GPDR: /* GPIO Pin-Direction registers */ 543 return s->dir; 544 545 case GPSR: /* GPIO Pin-Output Set registers */ 546 qemu_log_mask(LOG_GUEST_ERROR, 547 "strongarm GPIO: read from write only register GPSR\n"); 548 return 0; 549 550 case GPCR: /* GPIO Pin-Output Clear registers */ 551 qemu_log_mask(LOG_GUEST_ERROR, 552 "strongarm GPIO: read from write only register GPCR\n"); 553 return 0; 554 555 case GRER: /* GPIO Rising-Edge Detect Enable registers */ 556 return s->rising; 557 558 case GFER: /* GPIO Falling-Edge Detect Enable registers */ 559 return s->falling; 560 561 case GAFR: /* GPIO Alternate Function registers */ 562 return s->gafr; 563 564 case GPLR: /* GPIO Pin-Level registers */ 565 return (s->olevel & s->dir) | 566 (s->ilevel & ~s->dir); 567 568 case GEDR: /* GPIO Edge Detect Status registers */ 569 return s->status; 570 571 default: 572 printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset); 573 } 574 575 return 0; 576 } 577 578 static void strongarm_gpio_write(void *opaque, hwaddr offset, 579 uint64_t value, unsigned size) 580 { 581 StrongARMGPIOInfo *s = opaque; 582 583 switch (offset) { 584 case GPDR: /* GPIO Pin-Direction registers */ 585 s->dir = value; 586 strongarm_gpio_handler_update(s); 587 break; 588 589 case GPSR: /* GPIO Pin-Output Set registers */ 590 s->olevel |= value; 591 strongarm_gpio_handler_update(s); 592 break; 593 594 case GPCR: /* GPIO Pin-Output Clear registers */ 595 s->olevel &= ~value; 596 strongarm_gpio_handler_update(s); 597 break; 598 599 case GRER: /* GPIO Rising-Edge Detect Enable registers */ 600 s->rising = value; 601 break; 602 603 case GFER: /* GPIO Falling-Edge Detect Enable registers */ 604 s->falling = value; 605 break; 606 607 case GAFR: /* GPIO Alternate Function registers */ 608 s->gafr = value; 609 break; 610 611 case GEDR: /* GPIO Edge Detect Status registers */ 612 s->status &= ~value; 613 strongarm_gpio_irq_update(s); 614 break; 615 616 default: 617 printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset); 618 } 619 } 620 621 static const MemoryRegionOps strongarm_gpio_ops = { 622 .read = strongarm_gpio_read, 623 .write = strongarm_gpio_write, 624 .endianness = DEVICE_NATIVE_ENDIAN, 625 }; 626 627 static DeviceState *strongarm_gpio_init(hwaddr base, 628 DeviceState *pic) 629 { 630 DeviceState *dev; 631 int i; 632 633 dev = qdev_create(NULL, TYPE_STRONGARM_GPIO); 634 qdev_init_nofail(dev); 635 636 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 637 for (i = 0; i < 12; i++) 638 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 639 qdev_get_gpio_in(pic, SA_PIC_GPIO0_EDGE + i)); 640 641 return dev; 642 } 643 644 static int strongarm_gpio_initfn(SysBusDevice *sbd) 645 { 646 DeviceState *dev = DEVICE(sbd); 647 StrongARMGPIOInfo *s = STRONGARM_GPIO(dev); 648 int i; 649 650 qdev_init_gpio_in(dev, strongarm_gpio_set, 28); 651 qdev_init_gpio_out(dev, s->handler, 28); 652 653 memory_region_init_io(&s->iomem, OBJECT(s), &strongarm_gpio_ops, s, 654 "gpio", 0x1000); 655 656 sysbus_init_mmio(sbd, &s->iomem); 657 for (i = 0; i < 11; i++) { 658 sysbus_init_irq(sbd, &s->irqs[i]); 659 } 660 sysbus_init_irq(sbd, &s->irqX); 661 662 return 0; 663 } 664 665 static const VMStateDescription vmstate_strongarm_gpio_regs = { 666 .name = "strongarm-gpio", 667 .version_id = 0, 668 .minimum_version_id = 0, 669 .fields = (VMStateField[]) { 670 VMSTATE_UINT32(ilevel, StrongARMGPIOInfo), 671 VMSTATE_UINT32(olevel, StrongARMGPIOInfo), 672 VMSTATE_UINT32(dir, StrongARMGPIOInfo), 673 VMSTATE_UINT32(rising, StrongARMGPIOInfo), 674 VMSTATE_UINT32(falling, StrongARMGPIOInfo), 675 VMSTATE_UINT32(status, StrongARMGPIOInfo), 676 VMSTATE_UINT32(gafr, StrongARMGPIOInfo), 677 VMSTATE_UINT32(prev_level, StrongARMGPIOInfo), 678 VMSTATE_END_OF_LIST(), 679 }, 680 }; 681 682 static void strongarm_gpio_class_init(ObjectClass *klass, void *data) 683 { 684 DeviceClass *dc = DEVICE_CLASS(klass); 685 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 686 687 k->init = strongarm_gpio_initfn; 688 dc->desc = "StrongARM GPIO controller"; 689 dc->vmsd = &vmstate_strongarm_gpio_regs; 690 } 691 692 static const TypeInfo strongarm_gpio_info = { 693 .name = TYPE_STRONGARM_GPIO, 694 .parent = TYPE_SYS_BUS_DEVICE, 695 .instance_size = sizeof(StrongARMGPIOInfo), 696 .class_init = strongarm_gpio_class_init, 697 }; 698 699 /* Peripheral Pin Controller */ 700 #define PPDR 0x00 701 #define PPSR 0x04 702 #define PPAR 0x08 703 #define PSDR 0x0c 704 #define PPFR 0x10 705 706 #define TYPE_STRONGARM_PPC "strongarm-ppc" 707 #define STRONGARM_PPC(obj) \ 708 OBJECT_CHECK(StrongARMPPCInfo, (obj), TYPE_STRONGARM_PPC) 709 710 typedef struct StrongARMPPCInfo StrongARMPPCInfo; 711 struct StrongARMPPCInfo { 712 SysBusDevice parent_obj; 713 714 MemoryRegion iomem; 715 qemu_irq handler[28]; 716 717 uint32_t ilevel; 718 uint32_t olevel; 719 uint32_t dir; 720 uint32_t ppar; 721 uint32_t psdr; 722 uint32_t ppfr; 723 724 uint32_t prev_level; 725 }; 726 727 static void strongarm_ppc_set(void *opaque, int line, int level) 728 { 729 StrongARMPPCInfo *s = opaque; 730 731 if (level) { 732 s->ilevel |= 1 << line; 733 } else { 734 s->ilevel &= ~(1 << line); 735 } 736 } 737 738 static void strongarm_ppc_handler_update(StrongARMPPCInfo *s) 739 { 740 uint32_t level, diff; 741 int bit; 742 743 level = s->olevel & s->dir; 744 745 for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) { 746 bit = ffs(diff) - 1; 747 qemu_set_irq(s->handler[bit], (level >> bit) & 1); 748 } 749 750 s->prev_level = level; 751 } 752 753 static uint64_t strongarm_ppc_read(void *opaque, hwaddr offset, 754 unsigned size) 755 { 756 StrongARMPPCInfo *s = opaque; 757 758 switch (offset) { 759 case PPDR: /* PPC Pin Direction registers */ 760 return s->dir | ~0x3fffff; 761 762 case PPSR: /* PPC Pin State registers */ 763 return (s->olevel & s->dir) | 764 (s->ilevel & ~s->dir) | 765 ~0x3fffff; 766 767 case PPAR: 768 return s->ppar | ~0x41000; 769 770 case PSDR: 771 return s->psdr; 772 773 case PPFR: 774 return s->ppfr | ~0x7f001; 775 776 default: 777 printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset); 778 } 779 780 return 0; 781 } 782 783 static void strongarm_ppc_write(void *opaque, hwaddr offset, 784 uint64_t value, unsigned size) 785 { 786 StrongARMPPCInfo *s = opaque; 787 788 switch (offset) { 789 case PPDR: /* PPC Pin Direction registers */ 790 s->dir = value & 0x3fffff; 791 strongarm_ppc_handler_update(s); 792 break; 793 794 case PPSR: /* PPC Pin State registers */ 795 s->olevel = value & s->dir & 0x3fffff; 796 strongarm_ppc_handler_update(s); 797 break; 798 799 case PPAR: 800 s->ppar = value & 0x41000; 801 break; 802 803 case PSDR: 804 s->psdr = value & 0x3fffff; 805 break; 806 807 case PPFR: 808 s->ppfr = value & 0x7f001; 809 break; 810 811 default: 812 printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset); 813 } 814 } 815 816 static const MemoryRegionOps strongarm_ppc_ops = { 817 .read = strongarm_ppc_read, 818 .write = strongarm_ppc_write, 819 .endianness = DEVICE_NATIVE_ENDIAN, 820 }; 821 822 static int strongarm_ppc_init(SysBusDevice *sbd) 823 { 824 DeviceState *dev = DEVICE(sbd); 825 StrongARMPPCInfo *s = STRONGARM_PPC(dev); 826 827 qdev_init_gpio_in(dev, strongarm_ppc_set, 22); 828 qdev_init_gpio_out(dev, s->handler, 22); 829 830 memory_region_init_io(&s->iomem, OBJECT(s), &strongarm_ppc_ops, s, 831 "ppc", 0x1000); 832 833 sysbus_init_mmio(sbd, &s->iomem); 834 835 return 0; 836 } 837 838 static const VMStateDescription vmstate_strongarm_ppc_regs = { 839 .name = "strongarm-ppc", 840 .version_id = 0, 841 .minimum_version_id = 0, 842 .fields = (VMStateField[]) { 843 VMSTATE_UINT32(ilevel, StrongARMPPCInfo), 844 VMSTATE_UINT32(olevel, StrongARMPPCInfo), 845 VMSTATE_UINT32(dir, StrongARMPPCInfo), 846 VMSTATE_UINT32(ppar, StrongARMPPCInfo), 847 VMSTATE_UINT32(psdr, StrongARMPPCInfo), 848 VMSTATE_UINT32(ppfr, StrongARMPPCInfo), 849 VMSTATE_UINT32(prev_level, StrongARMPPCInfo), 850 VMSTATE_END_OF_LIST(), 851 }, 852 }; 853 854 static void strongarm_ppc_class_init(ObjectClass *klass, void *data) 855 { 856 DeviceClass *dc = DEVICE_CLASS(klass); 857 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 858 859 k->init = strongarm_ppc_init; 860 dc->desc = "StrongARM PPC controller"; 861 dc->vmsd = &vmstate_strongarm_ppc_regs; 862 } 863 864 static const TypeInfo strongarm_ppc_info = { 865 .name = TYPE_STRONGARM_PPC, 866 .parent = TYPE_SYS_BUS_DEVICE, 867 .instance_size = sizeof(StrongARMPPCInfo), 868 .class_init = strongarm_ppc_class_init, 869 }; 870 871 /* UART Ports */ 872 #define UTCR0 0x00 873 #define UTCR1 0x04 874 #define UTCR2 0x08 875 #define UTCR3 0x0c 876 #define UTDR 0x14 877 #define UTSR0 0x1c 878 #define UTSR1 0x20 879 880 #define UTCR0_PE (1 << 0) /* Parity enable */ 881 #define UTCR0_OES (1 << 1) /* Even parity */ 882 #define UTCR0_SBS (1 << 2) /* 2 stop bits */ 883 #define UTCR0_DSS (1 << 3) /* 8-bit data */ 884 885 #define UTCR3_RXE (1 << 0) /* Rx enable */ 886 #define UTCR3_TXE (1 << 1) /* Tx enable */ 887 #define UTCR3_BRK (1 << 2) /* Force Break */ 888 #define UTCR3_RIE (1 << 3) /* Rx int enable */ 889 #define UTCR3_TIE (1 << 4) /* Tx int enable */ 890 #define UTCR3_LBM (1 << 5) /* Loopback */ 891 892 #define UTSR0_TFS (1 << 0) /* Tx FIFO nearly empty */ 893 #define UTSR0_RFS (1 << 1) /* Rx FIFO nearly full */ 894 #define UTSR0_RID (1 << 2) /* Receiver Idle */ 895 #define UTSR0_RBB (1 << 3) /* Receiver begin break */ 896 #define UTSR0_REB (1 << 4) /* Receiver end break */ 897 #define UTSR0_EIF (1 << 5) /* Error in FIFO */ 898 899 #define UTSR1_RNE (1 << 1) /* Receive FIFO not empty */ 900 #define UTSR1_TNF (1 << 2) /* Transmit FIFO not full */ 901 #define UTSR1_PRE (1 << 3) /* Parity error */ 902 #define UTSR1_FRE (1 << 4) /* Frame error */ 903 #define UTSR1_ROR (1 << 5) /* Receive Over Run */ 904 905 #define RX_FIFO_PRE (1 << 8) 906 #define RX_FIFO_FRE (1 << 9) 907 #define RX_FIFO_ROR (1 << 10) 908 909 #define TYPE_STRONGARM_UART "strongarm-uart" 910 #define STRONGARM_UART(obj) \ 911 OBJECT_CHECK(StrongARMUARTState, (obj), TYPE_STRONGARM_UART) 912 913 typedef struct StrongARMUARTState { 914 SysBusDevice parent_obj; 915 916 MemoryRegion iomem; 917 CharDriverState *chr; 918 qemu_irq irq; 919 920 uint8_t utcr0; 921 uint16_t brd; 922 uint8_t utcr3; 923 uint8_t utsr0; 924 uint8_t utsr1; 925 926 uint8_t tx_fifo[8]; 927 uint8_t tx_start; 928 uint8_t tx_len; 929 uint16_t rx_fifo[12]; /* value + error flags in high bits */ 930 uint8_t rx_start; 931 uint8_t rx_len; 932 933 uint64_t char_transmit_time; /* time to transmit a char in ticks*/ 934 bool wait_break_end; 935 QEMUTimer *rx_timeout_timer; 936 QEMUTimer *tx_timer; 937 } StrongARMUARTState; 938 939 static void strongarm_uart_update_status(StrongARMUARTState *s) 940 { 941 uint16_t utsr1 = 0; 942 943 if (s->tx_len != 8) { 944 utsr1 |= UTSR1_TNF; 945 } 946 947 if (s->rx_len != 0) { 948 uint16_t ent = s->rx_fifo[s->rx_start]; 949 950 utsr1 |= UTSR1_RNE; 951 if (ent & RX_FIFO_PRE) { 952 s->utsr1 |= UTSR1_PRE; 953 } 954 if (ent & RX_FIFO_FRE) { 955 s->utsr1 |= UTSR1_FRE; 956 } 957 if (ent & RX_FIFO_ROR) { 958 s->utsr1 |= UTSR1_ROR; 959 } 960 } 961 962 s->utsr1 = utsr1; 963 } 964 965 static void strongarm_uart_update_int_status(StrongARMUARTState *s) 966 { 967 uint16_t utsr0 = s->utsr0 & 968 (UTSR0_REB | UTSR0_RBB | UTSR0_RID); 969 int i; 970 971 if ((s->utcr3 & UTCR3_TXE) && 972 (s->utcr3 & UTCR3_TIE) && 973 s->tx_len <= 4) { 974 utsr0 |= UTSR0_TFS; 975 } 976 977 if ((s->utcr3 & UTCR3_RXE) && 978 (s->utcr3 & UTCR3_RIE) && 979 s->rx_len > 4) { 980 utsr0 |= UTSR0_RFS; 981 } 982 983 for (i = 0; i < s->rx_len && i < 4; i++) 984 if (s->rx_fifo[(s->rx_start + i) % 12] & ~0xff) { 985 utsr0 |= UTSR0_EIF; 986 break; 987 } 988 989 s->utsr0 = utsr0; 990 qemu_set_irq(s->irq, utsr0); 991 } 992 993 static void strongarm_uart_update_parameters(StrongARMUARTState *s) 994 { 995 int speed, parity, data_bits, stop_bits, frame_size; 996 QEMUSerialSetParams ssp; 997 998 /* Start bit. */ 999 frame_size = 1; 1000 if (s->utcr0 & UTCR0_PE) { 1001 /* Parity bit. */ 1002 frame_size++; 1003 if (s->utcr0 & UTCR0_OES) { 1004 parity = 'E'; 1005 } else { 1006 parity = 'O'; 1007 } 1008 } else { 1009 parity = 'N'; 1010 } 1011 if (s->utcr0 & UTCR0_SBS) { 1012 stop_bits = 2; 1013 } else { 1014 stop_bits = 1; 1015 } 1016 1017 data_bits = (s->utcr0 & UTCR0_DSS) ? 8 : 7; 1018 frame_size += data_bits + stop_bits; 1019 speed = 3686400 / 16 / (s->brd + 1); 1020 ssp.speed = speed; 1021 ssp.parity = parity; 1022 ssp.data_bits = data_bits; 1023 ssp.stop_bits = stop_bits; 1024 s->char_transmit_time = (get_ticks_per_sec() / speed) * frame_size; 1025 if (s->chr) { 1026 qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); 1027 } 1028 1029 DPRINTF(stderr, "%s speed=%d parity=%c data=%d stop=%d\n", s->chr->label, 1030 speed, parity, data_bits, stop_bits); 1031 } 1032 1033 static void strongarm_uart_rx_to(void *opaque) 1034 { 1035 StrongARMUARTState *s = opaque; 1036 1037 if (s->rx_len) { 1038 s->utsr0 |= UTSR0_RID; 1039 strongarm_uart_update_int_status(s); 1040 } 1041 } 1042 1043 static void strongarm_uart_rx_push(StrongARMUARTState *s, uint16_t c) 1044 { 1045 if ((s->utcr3 & UTCR3_RXE) == 0) { 1046 /* rx disabled */ 1047 return; 1048 } 1049 1050 if (s->wait_break_end) { 1051 s->utsr0 |= UTSR0_REB; 1052 s->wait_break_end = false; 1053 } 1054 1055 if (s->rx_len < 12) { 1056 s->rx_fifo[(s->rx_start + s->rx_len) % 12] = c; 1057 s->rx_len++; 1058 } else 1059 s->rx_fifo[(s->rx_start + 11) % 12] |= RX_FIFO_ROR; 1060 } 1061 1062 static int strongarm_uart_can_receive(void *opaque) 1063 { 1064 StrongARMUARTState *s = opaque; 1065 1066 if (s->rx_len == 12) { 1067 return 0; 1068 } 1069 /* It's best not to get more than 2/3 of RX FIFO, so advertise that much */ 1070 if (s->rx_len < 8) { 1071 return 8 - s->rx_len; 1072 } 1073 return 1; 1074 } 1075 1076 static void strongarm_uart_receive(void *opaque, const uint8_t *buf, int size) 1077 { 1078 StrongARMUARTState *s = opaque; 1079 int i; 1080 1081 for (i = 0; i < size; i++) { 1082 strongarm_uart_rx_push(s, buf[i]); 1083 } 1084 1085 /* call the timeout receive callback in 3 char transmit time */ 1086 timer_mod(s->rx_timeout_timer, 1087 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 3); 1088 1089 strongarm_uart_update_status(s); 1090 strongarm_uart_update_int_status(s); 1091 } 1092 1093 static void strongarm_uart_event(void *opaque, int event) 1094 { 1095 StrongARMUARTState *s = opaque; 1096 if (event == CHR_EVENT_BREAK) { 1097 s->utsr0 |= UTSR0_RBB; 1098 strongarm_uart_rx_push(s, RX_FIFO_FRE); 1099 s->wait_break_end = true; 1100 strongarm_uart_update_status(s); 1101 strongarm_uart_update_int_status(s); 1102 } 1103 } 1104 1105 static void strongarm_uart_tx(void *opaque) 1106 { 1107 StrongARMUARTState *s = opaque; 1108 uint64_t new_xmit_ts = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 1109 1110 if (s->utcr3 & UTCR3_LBM) /* loopback */ { 1111 strongarm_uart_receive(s, &s->tx_fifo[s->tx_start], 1); 1112 } else if (s->chr) { 1113 qemu_chr_fe_write(s->chr, &s->tx_fifo[s->tx_start], 1); 1114 } 1115 1116 s->tx_start = (s->tx_start + 1) % 8; 1117 s->tx_len--; 1118 if (s->tx_len) { 1119 timer_mod(s->tx_timer, new_xmit_ts + s->char_transmit_time); 1120 } 1121 strongarm_uart_update_status(s); 1122 strongarm_uart_update_int_status(s); 1123 } 1124 1125 static uint64_t strongarm_uart_read(void *opaque, hwaddr addr, 1126 unsigned size) 1127 { 1128 StrongARMUARTState *s = opaque; 1129 uint16_t ret; 1130 1131 switch (addr) { 1132 case UTCR0: 1133 return s->utcr0; 1134 1135 case UTCR1: 1136 return s->brd >> 8; 1137 1138 case UTCR2: 1139 return s->brd & 0xff; 1140 1141 case UTCR3: 1142 return s->utcr3; 1143 1144 case UTDR: 1145 if (s->rx_len != 0) { 1146 ret = s->rx_fifo[s->rx_start]; 1147 s->rx_start = (s->rx_start + 1) % 12; 1148 s->rx_len--; 1149 strongarm_uart_update_status(s); 1150 strongarm_uart_update_int_status(s); 1151 return ret; 1152 } 1153 return 0; 1154 1155 case UTSR0: 1156 return s->utsr0; 1157 1158 case UTSR1: 1159 return s->utsr1; 1160 1161 default: 1162 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr); 1163 return 0; 1164 } 1165 } 1166 1167 static void strongarm_uart_write(void *opaque, hwaddr addr, 1168 uint64_t value, unsigned size) 1169 { 1170 StrongARMUARTState *s = opaque; 1171 1172 switch (addr) { 1173 case UTCR0: 1174 s->utcr0 = value & 0x7f; 1175 strongarm_uart_update_parameters(s); 1176 break; 1177 1178 case UTCR1: 1179 s->brd = (s->brd & 0xff) | ((value & 0xf) << 8); 1180 strongarm_uart_update_parameters(s); 1181 break; 1182 1183 case UTCR2: 1184 s->brd = (s->brd & 0xf00) | (value & 0xff); 1185 strongarm_uart_update_parameters(s); 1186 break; 1187 1188 case UTCR3: 1189 s->utcr3 = value & 0x3f; 1190 if ((s->utcr3 & UTCR3_RXE) == 0) { 1191 s->rx_len = 0; 1192 } 1193 if ((s->utcr3 & UTCR3_TXE) == 0) { 1194 s->tx_len = 0; 1195 } 1196 strongarm_uart_update_status(s); 1197 strongarm_uart_update_int_status(s); 1198 break; 1199 1200 case UTDR: 1201 if ((s->utcr3 & UTCR3_TXE) && s->tx_len != 8) { 1202 s->tx_fifo[(s->tx_start + s->tx_len) % 8] = value; 1203 s->tx_len++; 1204 strongarm_uart_update_status(s); 1205 strongarm_uart_update_int_status(s); 1206 if (s->tx_len == 1) { 1207 strongarm_uart_tx(s); 1208 } 1209 } 1210 break; 1211 1212 case UTSR0: 1213 s->utsr0 = s->utsr0 & ~(value & 1214 (UTSR0_REB | UTSR0_RBB | UTSR0_RID)); 1215 strongarm_uart_update_int_status(s); 1216 break; 1217 1218 default: 1219 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr); 1220 } 1221 } 1222 1223 static const MemoryRegionOps strongarm_uart_ops = { 1224 .read = strongarm_uart_read, 1225 .write = strongarm_uart_write, 1226 .endianness = DEVICE_NATIVE_ENDIAN, 1227 }; 1228 1229 static int strongarm_uart_init(SysBusDevice *dev) 1230 { 1231 StrongARMUARTState *s = STRONGARM_UART(dev); 1232 1233 memory_region_init_io(&s->iomem, OBJECT(s), &strongarm_uart_ops, s, 1234 "uart", 0x10000); 1235 sysbus_init_mmio(dev, &s->iomem); 1236 sysbus_init_irq(dev, &s->irq); 1237 1238 s->rx_timeout_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, strongarm_uart_rx_to, s); 1239 s->tx_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, strongarm_uart_tx, s); 1240 1241 if (s->chr) { 1242 qemu_chr_add_handlers(s->chr, 1243 strongarm_uart_can_receive, 1244 strongarm_uart_receive, 1245 strongarm_uart_event, 1246 s); 1247 } 1248 1249 return 0; 1250 } 1251 1252 static void strongarm_uart_reset(DeviceState *dev) 1253 { 1254 StrongARMUARTState *s = STRONGARM_UART(dev); 1255 1256 s->utcr0 = UTCR0_DSS; /* 8 data, no parity */ 1257 s->brd = 23; /* 9600 */ 1258 /* enable send & recv - this actually violates spec */ 1259 s->utcr3 = UTCR3_TXE | UTCR3_RXE; 1260 1261 s->rx_len = s->tx_len = 0; 1262 1263 strongarm_uart_update_parameters(s); 1264 strongarm_uart_update_status(s); 1265 strongarm_uart_update_int_status(s); 1266 } 1267 1268 static int strongarm_uart_post_load(void *opaque, int version_id) 1269 { 1270 StrongARMUARTState *s = opaque; 1271 1272 strongarm_uart_update_parameters(s); 1273 strongarm_uart_update_status(s); 1274 strongarm_uart_update_int_status(s); 1275 1276 /* tx and restart timer */ 1277 if (s->tx_len) { 1278 strongarm_uart_tx(s); 1279 } 1280 1281 /* restart rx timeout timer */ 1282 if (s->rx_len) { 1283 timer_mod(s->rx_timeout_timer, 1284 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 3); 1285 } 1286 1287 return 0; 1288 } 1289 1290 static const VMStateDescription vmstate_strongarm_uart_regs = { 1291 .name = "strongarm-uart", 1292 .version_id = 0, 1293 .minimum_version_id = 0, 1294 .post_load = strongarm_uart_post_load, 1295 .fields = (VMStateField[]) { 1296 VMSTATE_UINT8(utcr0, StrongARMUARTState), 1297 VMSTATE_UINT16(brd, StrongARMUARTState), 1298 VMSTATE_UINT8(utcr3, StrongARMUARTState), 1299 VMSTATE_UINT8(utsr0, StrongARMUARTState), 1300 VMSTATE_UINT8_ARRAY(tx_fifo, StrongARMUARTState, 8), 1301 VMSTATE_UINT8(tx_start, StrongARMUARTState), 1302 VMSTATE_UINT8(tx_len, StrongARMUARTState), 1303 VMSTATE_UINT16_ARRAY(rx_fifo, StrongARMUARTState, 12), 1304 VMSTATE_UINT8(rx_start, StrongARMUARTState), 1305 VMSTATE_UINT8(rx_len, StrongARMUARTState), 1306 VMSTATE_BOOL(wait_break_end, StrongARMUARTState), 1307 VMSTATE_END_OF_LIST(), 1308 }, 1309 }; 1310 1311 static Property strongarm_uart_properties[] = { 1312 DEFINE_PROP_CHR("chardev", StrongARMUARTState, chr), 1313 DEFINE_PROP_END_OF_LIST(), 1314 }; 1315 1316 static void strongarm_uart_class_init(ObjectClass *klass, void *data) 1317 { 1318 DeviceClass *dc = DEVICE_CLASS(klass); 1319 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 1320 1321 k->init = strongarm_uart_init; 1322 dc->desc = "StrongARM UART controller"; 1323 dc->reset = strongarm_uart_reset; 1324 dc->vmsd = &vmstate_strongarm_uart_regs; 1325 dc->props = strongarm_uart_properties; 1326 } 1327 1328 static const TypeInfo strongarm_uart_info = { 1329 .name = TYPE_STRONGARM_UART, 1330 .parent = TYPE_SYS_BUS_DEVICE, 1331 .instance_size = sizeof(StrongARMUARTState), 1332 .class_init = strongarm_uart_class_init, 1333 }; 1334 1335 /* Synchronous Serial Ports */ 1336 1337 #define TYPE_STRONGARM_SSP "strongarm-ssp" 1338 #define STRONGARM_SSP(obj) \ 1339 OBJECT_CHECK(StrongARMSSPState, (obj), TYPE_STRONGARM_SSP) 1340 1341 typedef struct StrongARMSSPState { 1342 SysBusDevice parent_obj; 1343 1344 MemoryRegion iomem; 1345 qemu_irq irq; 1346 SSIBus *bus; 1347 1348 uint16_t sscr[2]; 1349 uint16_t sssr; 1350 1351 uint16_t rx_fifo[8]; 1352 uint8_t rx_level; 1353 uint8_t rx_start; 1354 } StrongARMSSPState; 1355 1356 #define SSCR0 0x60 /* SSP Control register 0 */ 1357 #define SSCR1 0x64 /* SSP Control register 1 */ 1358 #define SSDR 0x6c /* SSP Data register */ 1359 #define SSSR 0x74 /* SSP Status register */ 1360 1361 /* Bitfields for above registers */ 1362 #define SSCR0_SPI(x) (((x) & 0x30) == 0x00) 1363 #define SSCR0_SSP(x) (((x) & 0x30) == 0x10) 1364 #define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20) 1365 #define SSCR0_PSP(x) (((x) & 0x30) == 0x30) 1366 #define SSCR0_SSE (1 << 7) 1367 #define SSCR0_DSS(x) (((x) & 0xf) + 1) 1368 #define SSCR1_RIE (1 << 0) 1369 #define SSCR1_TIE (1 << 1) 1370 #define SSCR1_LBM (1 << 2) 1371 #define SSSR_TNF (1 << 2) 1372 #define SSSR_RNE (1 << 3) 1373 #define SSSR_TFS (1 << 5) 1374 #define SSSR_RFS (1 << 6) 1375 #define SSSR_ROR (1 << 7) 1376 #define SSSR_RW 0x0080 1377 1378 static void strongarm_ssp_int_update(StrongARMSSPState *s) 1379 { 1380 int level = 0; 1381 1382 level |= (s->sssr & SSSR_ROR); 1383 level |= (s->sssr & SSSR_RFS) && (s->sscr[1] & SSCR1_RIE); 1384 level |= (s->sssr & SSSR_TFS) && (s->sscr[1] & SSCR1_TIE); 1385 qemu_set_irq(s->irq, level); 1386 } 1387 1388 static void strongarm_ssp_fifo_update(StrongARMSSPState *s) 1389 { 1390 s->sssr &= ~SSSR_TFS; 1391 s->sssr &= ~SSSR_TNF; 1392 if (s->sscr[0] & SSCR0_SSE) { 1393 if (s->rx_level >= 4) { 1394 s->sssr |= SSSR_RFS; 1395 } else { 1396 s->sssr &= ~SSSR_RFS; 1397 } 1398 if (s->rx_level) { 1399 s->sssr |= SSSR_RNE; 1400 } else { 1401 s->sssr &= ~SSSR_RNE; 1402 } 1403 /* TX FIFO is never filled, so it is always in underrun 1404 condition if SSP is enabled */ 1405 s->sssr |= SSSR_TFS; 1406 s->sssr |= SSSR_TNF; 1407 } 1408 1409 strongarm_ssp_int_update(s); 1410 } 1411 1412 static uint64_t strongarm_ssp_read(void *opaque, hwaddr addr, 1413 unsigned size) 1414 { 1415 StrongARMSSPState *s = opaque; 1416 uint32_t retval; 1417 1418 switch (addr) { 1419 case SSCR0: 1420 return s->sscr[0]; 1421 case SSCR1: 1422 return s->sscr[1]; 1423 case SSSR: 1424 return s->sssr; 1425 case SSDR: 1426 if (~s->sscr[0] & SSCR0_SSE) { 1427 return 0xffffffff; 1428 } 1429 if (s->rx_level < 1) { 1430 printf("%s: SSP Rx Underrun\n", __func__); 1431 return 0xffffffff; 1432 } 1433 s->rx_level--; 1434 retval = s->rx_fifo[s->rx_start++]; 1435 s->rx_start &= 0x7; 1436 strongarm_ssp_fifo_update(s); 1437 return retval; 1438 default: 1439 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr); 1440 break; 1441 } 1442 return 0; 1443 } 1444 1445 static void strongarm_ssp_write(void *opaque, hwaddr addr, 1446 uint64_t value, unsigned size) 1447 { 1448 StrongARMSSPState *s = opaque; 1449 1450 switch (addr) { 1451 case SSCR0: 1452 s->sscr[0] = value & 0xffbf; 1453 if ((s->sscr[0] & SSCR0_SSE) && SSCR0_DSS(value) < 4) { 1454 printf("%s: Wrong data size: %i bits\n", __func__, 1455 (int)SSCR0_DSS(value)); 1456 } 1457 if (!(value & SSCR0_SSE)) { 1458 s->sssr = 0; 1459 s->rx_level = 0; 1460 } 1461 strongarm_ssp_fifo_update(s); 1462 break; 1463 1464 case SSCR1: 1465 s->sscr[1] = value & 0x2f; 1466 if (value & SSCR1_LBM) { 1467 printf("%s: Attempt to use SSP LBM mode\n", __func__); 1468 } 1469 strongarm_ssp_fifo_update(s); 1470 break; 1471 1472 case SSSR: 1473 s->sssr &= ~(value & SSSR_RW); 1474 strongarm_ssp_int_update(s); 1475 break; 1476 1477 case SSDR: 1478 if (SSCR0_UWIRE(s->sscr[0])) { 1479 value &= 0xff; 1480 } else 1481 /* Note how 32bits overflow does no harm here */ 1482 value &= (1 << SSCR0_DSS(s->sscr[0])) - 1; 1483 1484 /* Data goes from here to the Tx FIFO and is shifted out from 1485 * there directly to the slave, no need to buffer it. 1486 */ 1487 if (s->sscr[0] & SSCR0_SSE) { 1488 uint32_t readval; 1489 if (s->sscr[1] & SSCR1_LBM) { 1490 readval = value; 1491 } else { 1492 readval = ssi_transfer(s->bus, value); 1493 } 1494 1495 if (s->rx_level < 0x08) { 1496 s->rx_fifo[(s->rx_start + s->rx_level++) & 0x7] = readval; 1497 } else { 1498 s->sssr |= SSSR_ROR; 1499 } 1500 } 1501 strongarm_ssp_fifo_update(s); 1502 break; 1503 1504 default: 1505 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr); 1506 break; 1507 } 1508 } 1509 1510 static const MemoryRegionOps strongarm_ssp_ops = { 1511 .read = strongarm_ssp_read, 1512 .write = strongarm_ssp_write, 1513 .endianness = DEVICE_NATIVE_ENDIAN, 1514 }; 1515 1516 static int strongarm_ssp_post_load(void *opaque, int version_id) 1517 { 1518 StrongARMSSPState *s = opaque; 1519 1520 strongarm_ssp_fifo_update(s); 1521 1522 return 0; 1523 } 1524 1525 static int strongarm_ssp_init(SysBusDevice *sbd) 1526 { 1527 DeviceState *dev = DEVICE(sbd); 1528 StrongARMSSPState *s = STRONGARM_SSP(dev); 1529 1530 sysbus_init_irq(sbd, &s->irq); 1531 1532 memory_region_init_io(&s->iomem, OBJECT(s), &strongarm_ssp_ops, s, 1533 "ssp", 0x1000); 1534 sysbus_init_mmio(sbd, &s->iomem); 1535 1536 s->bus = ssi_create_bus(dev, "ssi"); 1537 return 0; 1538 } 1539 1540 static void strongarm_ssp_reset(DeviceState *dev) 1541 { 1542 StrongARMSSPState *s = STRONGARM_SSP(dev); 1543 1544 s->sssr = 0x03; /* 3 bit data, SPI, disabled */ 1545 s->rx_start = 0; 1546 s->rx_level = 0; 1547 } 1548 1549 static const VMStateDescription vmstate_strongarm_ssp_regs = { 1550 .name = "strongarm-ssp", 1551 .version_id = 0, 1552 .minimum_version_id = 0, 1553 .post_load = strongarm_ssp_post_load, 1554 .fields = (VMStateField[]) { 1555 VMSTATE_UINT16_ARRAY(sscr, StrongARMSSPState, 2), 1556 VMSTATE_UINT16(sssr, StrongARMSSPState), 1557 VMSTATE_UINT16_ARRAY(rx_fifo, StrongARMSSPState, 8), 1558 VMSTATE_UINT8(rx_start, StrongARMSSPState), 1559 VMSTATE_UINT8(rx_level, StrongARMSSPState), 1560 VMSTATE_END_OF_LIST(), 1561 }, 1562 }; 1563 1564 static void strongarm_ssp_class_init(ObjectClass *klass, void *data) 1565 { 1566 DeviceClass *dc = DEVICE_CLASS(klass); 1567 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 1568 1569 k->init = strongarm_ssp_init; 1570 dc->desc = "StrongARM SSP controller"; 1571 dc->reset = strongarm_ssp_reset; 1572 dc->vmsd = &vmstate_strongarm_ssp_regs; 1573 } 1574 1575 static const TypeInfo strongarm_ssp_info = { 1576 .name = TYPE_STRONGARM_SSP, 1577 .parent = TYPE_SYS_BUS_DEVICE, 1578 .instance_size = sizeof(StrongARMSSPState), 1579 .class_init = strongarm_ssp_class_init, 1580 }; 1581 1582 /* Main CPU functions */ 1583 StrongARMState *sa1110_init(MemoryRegion *sysmem, 1584 unsigned int sdram_size, const char *rev) 1585 { 1586 StrongARMState *s; 1587 int i; 1588 1589 s = g_malloc0(sizeof(StrongARMState)); 1590 1591 if (!rev) { 1592 rev = "sa1110-b5"; 1593 } 1594 1595 if (strncmp(rev, "sa1110", 6)) { 1596 error_report("Machine requires a SA1110 processor."); 1597 exit(1); 1598 } 1599 1600 s->cpu = cpu_arm_init(rev); 1601 1602 if (!s->cpu) { 1603 error_report("Unable to find CPU definition"); 1604 exit(1); 1605 } 1606 1607 memory_region_init_ram(&s->sdram, NULL, "strongarm.sdram", sdram_size, 1608 &error_abort); 1609 vmstate_register_ram_global(&s->sdram); 1610 memory_region_add_subregion(sysmem, SA_SDCS0, &s->sdram); 1611 1612 s->pic = sysbus_create_varargs("strongarm_pic", 0x90050000, 1613 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ), 1614 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_FIQ), 1615 NULL); 1616 1617 sysbus_create_varargs("pxa25x-timer", 0x90000000, 1618 qdev_get_gpio_in(s->pic, SA_PIC_OSTC0), 1619 qdev_get_gpio_in(s->pic, SA_PIC_OSTC1), 1620 qdev_get_gpio_in(s->pic, SA_PIC_OSTC2), 1621 qdev_get_gpio_in(s->pic, SA_PIC_OSTC3), 1622 NULL); 1623 1624 sysbus_create_simple(TYPE_STRONGARM_RTC, 0x90010000, 1625 qdev_get_gpio_in(s->pic, SA_PIC_RTC_ALARM)); 1626 1627 s->gpio = strongarm_gpio_init(0x90040000, s->pic); 1628 1629 s->ppc = sysbus_create_varargs(TYPE_STRONGARM_PPC, 0x90060000, NULL); 1630 1631 for (i = 0; sa_serial[i].io_base; i++) { 1632 DeviceState *dev = qdev_create(NULL, TYPE_STRONGARM_UART); 1633 qdev_prop_set_chr(dev, "chardev", serial_hds[i]); 1634 qdev_init_nofail(dev); 1635 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 1636 sa_serial[i].io_base); 1637 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, 1638 qdev_get_gpio_in(s->pic, sa_serial[i].irq)); 1639 } 1640 1641 s->ssp = sysbus_create_varargs(TYPE_STRONGARM_SSP, 0x80070000, 1642 qdev_get_gpio_in(s->pic, SA_PIC_SSP), NULL); 1643 s->ssp_bus = (SSIBus *)qdev_get_child_bus(s->ssp, "ssi"); 1644 1645 return s; 1646 } 1647 1648 static void strongarm_register_types(void) 1649 { 1650 type_register_static(&strongarm_pic_info); 1651 type_register_static(&strongarm_rtc_sysbus_info); 1652 type_register_static(&strongarm_gpio_info); 1653 type_register_static(&strongarm_ppc_info); 1654 type_register_static(&strongarm_uart_info); 1655 type_register_static(&strongarm_ssp_info); 1656 } 1657 1658 type_init(strongarm_register_types) 1659