1 /* 2 * StrongARM SA-1100/SA-1110 emulation 3 * 4 * Copyright (C) 2011 Dmitry Eremin-Solenikov 5 * 6 * Largely based on StrongARM emulation: 7 * Copyright (c) 2006 Openedhand Ltd. 8 * Written by Andrzej Zaborowski <balrog@zabor.org> 9 * 10 * UART code based on QEMU 16550A UART emulation 11 * Copyright (c) 2003-2004 Fabrice Bellard 12 * Copyright (c) 2008 Citrix Systems, Inc. 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License version 2 as 16 * published by the Free Software Foundation. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License along 24 * with this program; if not, see <http://www.gnu.org/licenses/>. 25 * 26 * Contributions after 2012-01-13 are licensed under the terms of the 27 * GNU GPL, version 2 or (at your option) any later version. 28 */ 29 #include "hw/sysbus.h" 30 #include "strongarm.h" 31 #include "qemu/error-report.h" 32 #include "hw/arm/arm.h" 33 #include "sysemu/char.h" 34 #include "sysemu/sysemu.h" 35 #include "hw/ssi.h" 36 37 //#define DEBUG 38 39 /* 40 TODO 41 - Implement cp15, c14 ? 42 - Implement cp15, c15 !!! (idle used in L) 43 - Implement idle mode handling/DIM 44 - Implement sleep mode/Wake sources 45 - Implement reset control 46 - Implement memory control regs 47 - PCMCIA handling 48 - Maybe support MBGNT/MBREQ 49 - DMA channels 50 - GPCLK 51 - IrDA 52 - MCP 53 - Enhance UART with modem signals 54 */ 55 56 #ifdef DEBUG 57 # define DPRINTF(format, ...) printf(format , ## __VA_ARGS__) 58 #else 59 # define DPRINTF(format, ...) do { } while (0) 60 #endif 61 62 static struct { 63 hwaddr io_base; 64 int irq; 65 } sa_serial[] = { 66 { 0x80010000, SA_PIC_UART1 }, 67 { 0x80030000, SA_PIC_UART2 }, 68 { 0x80050000, SA_PIC_UART3 }, 69 { 0, 0 } 70 }; 71 72 /* Interrupt Controller */ 73 74 #define TYPE_STRONGARM_PIC "strongarm_pic" 75 #define STRONGARM_PIC(obj) \ 76 OBJECT_CHECK(StrongARMPICState, (obj), TYPE_STRONGARM_PIC) 77 78 typedef struct StrongARMPICState { 79 SysBusDevice parent_obj; 80 81 MemoryRegion iomem; 82 qemu_irq irq; 83 qemu_irq fiq; 84 85 uint32_t pending; 86 uint32_t enabled; 87 uint32_t is_fiq; 88 uint32_t int_idle; 89 } StrongARMPICState; 90 91 #define ICIP 0x00 92 #define ICMR 0x04 93 #define ICLR 0x08 94 #define ICFP 0x10 95 #define ICPR 0x20 96 #define ICCR 0x0c 97 98 #define SA_PIC_SRCS 32 99 100 101 static void strongarm_pic_update(void *opaque) 102 { 103 StrongARMPICState *s = opaque; 104 105 /* FIXME: reflect DIM */ 106 qemu_set_irq(s->fiq, s->pending & s->enabled & s->is_fiq); 107 qemu_set_irq(s->irq, s->pending & s->enabled & ~s->is_fiq); 108 } 109 110 static void strongarm_pic_set_irq(void *opaque, int irq, int level) 111 { 112 StrongARMPICState *s = opaque; 113 114 if (level) { 115 s->pending |= 1 << irq; 116 } else { 117 s->pending &= ~(1 << irq); 118 } 119 120 strongarm_pic_update(s); 121 } 122 123 static uint64_t strongarm_pic_mem_read(void *opaque, hwaddr offset, 124 unsigned size) 125 { 126 StrongARMPICState *s = opaque; 127 128 switch (offset) { 129 case ICIP: 130 return s->pending & ~s->is_fiq & s->enabled; 131 case ICMR: 132 return s->enabled; 133 case ICLR: 134 return s->is_fiq; 135 case ICCR: 136 return s->int_idle == 0; 137 case ICFP: 138 return s->pending & s->is_fiq & s->enabled; 139 case ICPR: 140 return s->pending; 141 default: 142 printf("%s: Bad register offset 0x" TARGET_FMT_plx "\n", 143 __func__, offset); 144 return 0; 145 } 146 } 147 148 static void strongarm_pic_mem_write(void *opaque, hwaddr offset, 149 uint64_t value, unsigned size) 150 { 151 StrongARMPICState *s = opaque; 152 153 switch (offset) { 154 case ICMR: 155 s->enabled = value; 156 break; 157 case ICLR: 158 s->is_fiq = value; 159 break; 160 case ICCR: 161 s->int_idle = (value & 1) ? 0 : ~0; 162 break; 163 default: 164 printf("%s: Bad register offset 0x" TARGET_FMT_plx "\n", 165 __func__, offset); 166 break; 167 } 168 strongarm_pic_update(s); 169 } 170 171 static const MemoryRegionOps strongarm_pic_ops = { 172 .read = strongarm_pic_mem_read, 173 .write = strongarm_pic_mem_write, 174 .endianness = DEVICE_NATIVE_ENDIAN, 175 }; 176 177 static int strongarm_pic_initfn(SysBusDevice *sbd) 178 { 179 DeviceState *dev = DEVICE(sbd); 180 StrongARMPICState *s = STRONGARM_PIC(dev); 181 182 qdev_init_gpio_in(dev, strongarm_pic_set_irq, SA_PIC_SRCS); 183 memory_region_init_io(&s->iomem, OBJECT(s), &strongarm_pic_ops, s, 184 "pic", 0x1000); 185 sysbus_init_mmio(sbd, &s->iomem); 186 sysbus_init_irq(sbd, &s->irq); 187 sysbus_init_irq(sbd, &s->fiq); 188 189 return 0; 190 } 191 192 static int strongarm_pic_post_load(void *opaque, int version_id) 193 { 194 strongarm_pic_update(opaque); 195 return 0; 196 } 197 198 static VMStateDescription vmstate_strongarm_pic_regs = { 199 .name = "strongarm_pic", 200 .version_id = 0, 201 .minimum_version_id = 0, 202 .post_load = strongarm_pic_post_load, 203 .fields = (VMStateField[]) { 204 VMSTATE_UINT32(pending, StrongARMPICState), 205 VMSTATE_UINT32(enabled, StrongARMPICState), 206 VMSTATE_UINT32(is_fiq, StrongARMPICState), 207 VMSTATE_UINT32(int_idle, StrongARMPICState), 208 VMSTATE_END_OF_LIST(), 209 }, 210 }; 211 212 static void strongarm_pic_class_init(ObjectClass *klass, void *data) 213 { 214 DeviceClass *dc = DEVICE_CLASS(klass); 215 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 216 217 k->init = strongarm_pic_initfn; 218 dc->desc = "StrongARM PIC"; 219 dc->vmsd = &vmstate_strongarm_pic_regs; 220 } 221 222 static const TypeInfo strongarm_pic_info = { 223 .name = TYPE_STRONGARM_PIC, 224 .parent = TYPE_SYS_BUS_DEVICE, 225 .instance_size = sizeof(StrongARMPICState), 226 .class_init = strongarm_pic_class_init, 227 }; 228 229 /* Real-Time Clock */ 230 #define RTAR 0x00 /* RTC Alarm register */ 231 #define RCNR 0x04 /* RTC Counter register */ 232 #define RTTR 0x08 /* RTC Timer Trim register */ 233 #define RTSR 0x10 /* RTC Status register */ 234 235 #define RTSR_AL (1 << 0) /* RTC Alarm detected */ 236 #define RTSR_HZ (1 << 1) /* RTC 1Hz detected */ 237 #define RTSR_ALE (1 << 2) /* RTC Alarm enable */ 238 #define RTSR_HZE (1 << 3) /* RTC 1Hz enable */ 239 240 /* 16 LSB of RTTR are clockdiv for internal trim logic, 241 * trim delete isn't emulated, so 242 * f = 32 768 / (RTTR_trim + 1) */ 243 244 #define TYPE_STRONGARM_RTC "strongarm-rtc" 245 #define STRONGARM_RTC(obj) \ 246 OBJECT_CHECK(StrongARMRTCState, (obj), TYPE_STRONGARM_RTC) 247 248 typedef struct StrongARMRTCState { 249 SysBusDevice parent_obj; 250 251 MemoryRegion iomem; 252 uint32_t rttr; 253 uint32_t rtsr; 254 uint32_t rtar; 255 uint32_t last_rcnr; 256 int64_t last_hz; 257 QEMUTimer *rtc_alarm; 258 QEMUTimer *rtc_hz; 259 qemu_irq rtc_irq; 260 qemu_irq rtc_hz_irq; 261 } StrongARMRTCState; 262 263 static inline void strongarm_rtc_int_update(StrongARMRTCState *s) 264 { 265 qemu_set_irq(s->rtc_irq, s->rtsr & RTSR_AL); 266 qemu_set_irq(s->rtc_hz_irq, s->rtsr & RTSR_HZ); 267 } 268 269 static void strongarm_rtc_hzupdate(StrongARMRTCState *s) 270 { 271 int64_t rt = qemu_clock_get_ms(rtc_clock); 272 s->last_rcnr += ((rt - s->last_hz) << 15) / 273 (1000 * ((s->rttr & 0xffff) + 1)); 274 s->last_hz = rt; 275 } 276 277 static inline void strongarm_rtc_timer_update(StrongARMRTCState *s) 278 { 279 if ((s->rtsr & RTSR_HZE) && !(s->rtsr & RTSR_HZ)) { 280 timer_mod(s->rtc_hz, s->last_hz + 1000); 281 } else { 282 timer_del(s->rtc_hz); 283 } 284 285 if ((s->rtsr & RTSR_ALE) && !(s->rtsr & RTSR_AL)) { 286 timer_mod(s->rtc_alarm, s->last_hz + 287 (((s->rtar - s->last_rcnr) * 1000 * 288 ((s->rttr & 0xffff) + 1)) >> 15)); 289 } else { 290 timer_del(s->rtc_alarm); 291 } 292 } 293 294 static inline void strongarm_rtc_alarm_tick(void *opaque) 295 { 296 StrongARMRTCState *s = opaque; 297 s->rtsr |= RTSR_AL; 298 strongarm_rtc_timer_update(s); 299 strongarm_rtc_int_update(s); 300 } 301 302 static inline void strongarm_rtc_hz_tick(void *opaque) 303 { 304 StrongARMRTCState *s = opaque; 305 s->rtsr |= RTSR_HZ; 306 strongarm_rtc_timer_update(s); 307 strongarm_rtc_int_update(s); 308 } 309 310 static uint64_t strongarm_rtc_read(void *opaque, hwaddr addr, 311 unsigned size) 312 { 313 StrongARMRTCState *s = opaque; 314 315 switch (addr) { 316 case RTTR: 317 return s->rttr; 318 case RTSR: 319 return s->rtsr; 320 case RTAR: 321 return s->rtar; 322 case RCNR: 323 return s->last_rcnr + 324 ((qemu_clock_get_ms(rtc_clock) - s->last_hz) << 15) / 325 (1000 * ((s->rttr & 0xffff) + 1)); 326 default: 327 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr); 328 return 0; 329 } 330 } 331 332 static void strongarm_rtc_write(void *opaque, hwaddr addr, 333 uint64_t value, unsigned size) 334 { 335 StrongARMRTCState *s = opaque; 336 uint32_t old_rtsr; 337 338 switch (addr) { 339 case RTTR: 340 strongarm_rtc_hzupdate(s); 341 s->rttr = value; 342 strongarm_rtc_timer_update(s); 343 break; 344 345 case RTSR: 346 old_rtsr = s->rtsr; 347 s->rtsr = (value & (RTSR_ALE | RTSR_HZE)) | 348 (s->rtsr & ~(value & (RTSR_AL | RTSR_HZ))); 349 350 if (s->rtsr != old_rtsr) { 351 strongarm_rtc_timer_update(s); 352 } 353 354 strongarm_rtc_int_update(s); 355 break; 356 357 case RTAR: 358 s->rtar = value; 359 strongarm_rtc_timer_update(s); 360 break; 361 362 case RCNR: 363 strongarm_rtc_hzupdate(s); 364 s->last_rcnr = value; 365 strongarm_rtc_timer_update(s); 366 break; 367 368 default: 369 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr); 370 } 371 } 372 373 static const MemoryRegionOps strongarm_rtc_ops = { 374 .read = strongarm_rtc_read, 375 .write = strongarm_rtc_write, 376 .endianness = DEVICE_NATIVE_ENDIAN, 377 }; 378 379 static int strongarm_rtc_init(SysBusDevice *dev) 380 { 381 StrongARMRTCState *s = STRONGARM_RTC(dev); 382 struct tm tm; 383 384 s->rttr = 0x0; 385 s->rtsr = 0; 386 387 qemu_get_timedate(&tm, 0); 388 389 s->last_rcnr = (uint32_t) mktimegm(&tm); 390 s->last_hz = qemu_clock_get_ms(rtc_clock); 391 392 s->rtc_alarm = timer_new_ms(rtc_clock, strongarm_rtc_alarm_tick, s); 393 s->rtc_hz = timer_new_ms(rtc_clock, strongarm_rtc_hz_tick, s); 394 395 sysbus_init_irq(dev, &s->rtc_irq); 396 sysbus_init_irq(dev, &s->rtc_hz_irq); 397 398 memory_region_init_io(&s->iomem, OBJECT(s), &strongarm_rtc_ops, s, 399 "rtc", 0x10000); 400 sysbus_init_mmio(dev, &s->iomem); 401 402 return 0; 403 } 404 405 static void strongarm_rtc_pre_save(void *opaque) 406 { 407 StrongARMRTCState *s = opaque; 408 409 strongarm_rtc_hzupdate(s); 410 } 411 412 static int strongarm_rtc_post_load(void *opaque, int version_id) 413 { 414 StrongARMRTCState *s = opaque; 415 416 strongarm_rtc_timer_update(s); 417 strongarm_rtc_int_update(s); 418 419 return 0; 420 } 421 422 static const VMStateDescription vmstate_strongarm_rtc_regs = { 423 .name = "strongarm-rtc", 424 .version_id = 0, 425 .minimum_version_id = 0, 426 .pre_save = strongarm_rtc_pre_save, 427 .post_load = strongarm_rtc_post_load, 428 .fields = (VMStateField[]) { 429 VMSTATE_UINT32(rttr, StrongARMRTCState), 430 VMSTATE_UINT32(rtsr, StrongARMRTCState), 431 VMSTATE_UINT32(rtar, StrongARMRTCState), 432 VMSTATE_UINT32(last_rcnr, StrongARMRTCState), 433 VMSTATE_INT64(last_hz, StrongARMRTCState), 434 VMSTATE_END_OF_LIST(), 435 }, 436 }; 437 438 static void strongarm_rtc_sysbus_class_init(ObjectClass *klass, void *data) 439 { 440 DeviceClass *dc = DEVICE_CLASS(klass); 441 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 442 443 k->init = strongarm_rtc_init; 444 dc->desc = "StrongARM RTC Controller"; 445 dc->vmsd = &vmstate_strongarm_rtc_regs; 446 } 447 448 static const TypeInfo strongarm_rtc_sysbus_info = { 449 .name = TYPE_STRONGARM_RTC, 450 .parent = TYPE_SYS_BUS_DEVICE, 451 .instance_size = sizeof(StrongARMRTCState), 452 .class_init = strongarm_rtc_sysbus_class_init, 453 }; 454 455 /* GPIO */ 456 #define GPLR 0x00 457 #define GPDR 0x04 458 #define GPSR 0x08 459 #define GPCR 0x0c 460 #define GRER 0x10 461 #define GFER 0x14 462 #define GEDR 0x18 463 #define GAFR 0x1c 464 465 #define TYPE_STRONGARM_GPIO "strongarm-gpio" 466 #define STRONGARM_GPIO(obj) \ 467 OBJECT_CHECK(StrongARMGPIOInfo, (obj), TYPE_STRONGARM_GPIO) 468 469 typedef struct StrongARMGPIOInfo StrongARMGPIOInfo; 470 struct StrongARMGPIOInfo { 471 SysBusDevice busdev; 472 MemoryRegion iomem; 473 qemu_irq handler[28]; 474 qemu_irq irqs[11]; 475 qemu_irq irqX; 476 477 uint32_t ilevel; 478 uint32_t olevel; 479 uint32_t dir; 480 uint32_t rising; 481 uint32_t falling; 482 uint32_t status; 483 uint32_t gpsr; 484 uint32_t gafr; 485 486 uint32_t prev_level; 487 }; 488 489 490 static void strongarm_gpio_irq_update(StrongARMGPIOInfo *s) 491 { 492 int i; 493 for (i = 0; i < 11; i++) { 494 qemu_set_irq(s->irqs[i], s->status & (1 << i)); 495 } 496 497 qemu_set_irq(s->irqX, (s->status & ~0x7ff)); 498 } 499 500 static void strongarm_gpio_set(void *opaque, int line, int level) 501 { 502 StrongARMGPIOInfo *s = opaque; 503 uint32_t mask; 504 505 mask = 1 << line; 506 507 if (level) { 508 s->status |= s->rising & mask & 509 ~s->ilevel & ~s->dir; 510 s->ilevel |= mask; 511 } else { 512 s->status |= s->falling & mask & 513 s->ilevel & ~s->dir; 514 s->ilevel &= ~mask; 515 } 516 517 if (s->status & mask) { 518 strongarm_gpio_irq_update(s); 519 } 520 } 521 522 static void strongarm_gpio_handler_update(StrongARMGPIOInfo *s) 523 { 524 uint32_t level, diff; 525 int bit; 526 527 level = s->olevel & s->dir; 528 529 for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) { 530 bit = ffs(diff) - 1; 531 qemu_set_irq(s->handler[bit], (level >> bit) & 1); 532 } 533 534 s->prev_level = level; 535 } 536 537 static uint64_t strongarm_gpio_read(void *opaque, hwaddr offset, 538 unsigned size) 539 { 540 StrongARMGPIOInfo *s = opaque; 541 542 switch (offset) { 543 case GPDR: /* GPIO Pin-Direction registers */ 544 return s->dir; 545 546 case GPSR: /* GPIO Pin-Output Set registers */ 547 DPRINTF("%s: Read from a write-only register 0x" TARGET_FMT_plx "\n", 548 __func__, offset); 549 return s->gpsr; /* Return last written value. */ 550 551 case GPCR: /* GPIO Pin-Output Clear registers */ 552 DPRINTF("%s: Read from a write-only register 0x" TARGET_FMT_plx "\n", 553 __func__, offset); 554 return 31337; /* Specified as unpredictable in the docs. */ 555 556 case GRER: /* GPIO Rising-Edge Detect Enable registers */ 557 return s->rising; 558 559 case GFER: /* GPIO Falling-Edge Detect Enable registers */ 560 return s->falling; 561 562 case GAFR: /* GPIO Alternate Function registers */ 563 return s->gafr; 564 565 case GPLR: /* GPIO Pin-Level registers */ 566 return (s->olevel & s->dir) | 567 (s->ilevel & ~s->dir); 568 569 case GEDR: /* GPIO Edge Detect Status registers */ 570 return s->status; 571 572 default: 573 printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset); 574 } 575 576 return 0; 577 } 578 579 static void strongarm_gpio_write(void *opaque, hwaddr offset, 580 uint64_t value, unsigned size) 581 { 582 StrongARMGPIOInfo *s = opaque; 583 584 switch (offset) { 585 case GPDR: /* GPIO Pin-Direction registers */ 586 s->dir = value; 587 strongarm_gpio_handler_update(s); 588 break; 589 590 case GPSR: /* GPIO Pin-Output Set registers */ 591 s->olevel |= value; 592 strongarm_gpio_handler_update(s); 593 s->gpsr = value; 594 break; 595 596 case GPCR: /* GPIO Pin-Output Clear registers */ 597 s->olevel &= ~value; 598 strongarm_gpio_handler_update(s); 599 break; 600 601 case GRER: /* GPIO Rising-Edge Detect Enable registers */ 602 s->rising = value; 603 break; 604 605 case GFER: /* GPIO Falling-Edge Detect Enable registers */ 606 s->falling = value; 607 break; 608 609 case GAFR: /* GPIO Alternate Function registers */ 610 s->gafr = value; 611 break; 612 613 case GEDR: /* GPIO Edge Detect Status registers */ 614 s->status &= ~value; 615 strongarm_gpio_irq_update(s); 616 break; 617 618 default: 619 printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset); 620 } 621 } 622 623 static const MemoryRegionOps strongarm_gpio_ops = { 624 .read = strongarm_gpio_read, 625 .write = strongarm_gpio_write, 626 .endianness = DEVICE_NATIVE_ENDIAN, 627 }; 628 629 static DeviceState *strongarm_gpio_init(hwaddr base, 630 DeviceState *pic) 631 { 632 DeviceState *dev; 633 int i; 634 635 dev = qdev_create(NULL, TYPE_STRONGARM_GPIO); 636 qdev_init_nofail(dev); 637 638 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 639 for (i = 0; i < 12; i++) 640 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 641 qdev_get_gpio_in(pic, SA_PIC_GPIO0_EDGE + i)); 642 643 return dev; 644 } 645 646 static int strongarm_gpio_initfn(SysBusDevice *sbd) 647 { 648 DeviceState *dev = DEVICE(sbd); 649 StrongARMGPIOInfo *s = STRONGARM_GPIO(dev); 650 int i; 651 652 qdev_init_gpio_in(dev, strongarm_gpio_set, 28); 653 qdev_init_gpio_out(dev, s->handler, 28); 654 655 memory_region_init_io(&s->iomem, OBJECT(s), &strongarm_gpio_ops, s, 656 "gpio", 0x1000); 657 658 sysbus_init_mmio(sbd, &s->iomem); 659 for (i = 0; i < 11; i++) { 660 sysbus_init_irq(sbd, &s->irqs[i]); 661 } 662 sysbus_init_irq(sbd, &s->irqX); 663 664 return 0; 665 } 666 667 static const VMStateDescription vmstate_strongarm_gpio_regs = { 668 .name = "strongarm-gpio", 669 .version_id = 0, 670 .minimum_version_id = 0, 671 .fields = (VMStateField[]) { 672 VMSTATE_UINT32(ilevel, StrongARMGPIOInfo), 673 VMSTATE_UINT32(olevel, StrongARMGPIOInfo), 674 VMSTATE_UINT32(dir, StrongARMGPIOInfo), 675 VMSTATE_UINT32(rising, StrongARMGPIOInfo), 676 VMSTATE_UINT32(falling, StrongARMGPIOInfo), 677 VMSTATE_UINT32(status, StrongARMGPIOInfo), 678 VMSTATE_UINT32(gafr, StrongARMGPIOInfo), 679 VMSTATE_END_OF_LIST(), 680 }, 681 }; 682 683 static void strongarm_gpio_class_init(ObjectClass *klass, void *data) 684 { 685 DeviceClass *dc = DEVICE_CLASS(klass); 686 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 687 688 k->init = strongarm_gpio_initfn; 689 dc->desc = "StrongARM GPIO controller"; 690 } 691 692 static const TypeInfo strongarm_gpio_info = { 693 .name = TYPE_STRONGARM_GPIO, 694 .parent = TYPE_SYS_BUS_DEVICE, 695 .instance_size = sizeof(StrongARMGPIOInfo), 696 .class_init = strongarm_gpio_class_init, 697 }; 698 699 /* Peripheral Pin Controller */ 700 #define PPDR 0x00 701 #define PPSR 0x04 702 #define PPAR 0x08 703 #define PSDR 0x0c 704 #define PPFR 0x10 705 706 #define TYPE_STRONGARM_PPC "strongarm-ppc" 707 #define STRONGARM_PPC(obj) \ 708 OBJECT_CHECK(StrongARMPPCInfo, (obj), TYPE_STRONGARM_PPC) 709 710 typedef struct StrongARMPPCInfo StrongARMPPCInfo; 711 struct StrongARMPPCInfo { 712 SysBusDevice parent_obj; 713 714 MemoryRegion iomem; 715 qemu_irq handler[28]; 716 717 uint32_t ilevel; 718 uint32_t olevel; 719 uint32_t dir; 720 uint32_t ppar; 721 uint32_t psdr; 722 uint32_t ppfr; 723 724 uint32_t prev_level; 725 }; 726 727 static void strongarm_ppc_set(void *opaque, int line, int level) 728 { 729 StrongARMPPCInfo *s = opaque; 730 731 if (level) { 732 s->ilevel |= 1 << line; 733 } else { 734 s->ilevel &= ~(1 << line); 735 } 736 } 737 738 static void strongarm_ppc_handler_update(StrongARMPPCInfo *s) 739 { 740 uint32_t level, diff; 741 int bit; 742 743 level = s->olevel & s->dir; 744 745 for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) { 746 bit = ffs(diff) - 1; 747 qemu_set_irq(s->handler[bit], (level >> bit) & 1); 748 } 749 750 s->prev_level = level; 751 } 752 753 static uint64_t strongarm_ppc_read(void *opaque, hwaddr offset, 754 unsigned size) 755 { 756 StrongARMPPCInfo *s = opaque; 757 758 switch (offset) { 759 case PPDR: /* PPC Pin Direction registers */ 760 return s->dir | ~0x3fffff; 761 762 case PPSR: /* PPC Pin State registers */ 763 return (s->olevel & s->dir) | 764 (s->ilevel & ~s->dir) | 765 ~0x3fffff; 766 767 case PPAR: 768 return s->ppar | ~0x41000; 769 770 case PSDR: 771 return s->psdr; 772 773 case PPFR: 774 return s->ppfr | ~0x7f001; 775 776 default: 777 printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset); 778 } 779 780 return 0; 781 } 782 783 static void strongarm_ppc_write(void *opaque, hwaddr offset, 784 uint64_t value, unsigned size) 785 { 786 StrongARMPPCInfo *s = opaque; 787 788 switch (offset) { 789 case PPDR: /* PPC Pin Direction registers */ 790 s->dir = value & 0x3fffff; 791 strongarm_ppc_handler_update(s); 792 break; 793 794 case PPSR: /* PPC Pin State registers */ 795 s->olevel = value & s->dir & 0x3fffff; 796 strongarm_ppc_handler_update(s); 797 break; 798 799 case PPAR: 800 s->ppar = value & 0x41000; 801 break; 802 803 case PSDR: 804 s->psdr = value & 0x3fffff; 805 break; 806 807 case PPFR: 808 s->ppfr = value & 0x7f001; 809 break; 810 811 default: 812 printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset); 813 } 814 } 815 816 static const MemoryRegionOps strongarm_ppc_ops = { 817 .read = strongarm_ppc_read, 818 .write = strongarm_ppc_write, 819 .endianness = DEVICE_NATIVE_ENDIAN, 820 }; 821 822 static int strongarm_ppc_init(SysBusDevice *sbd) 823 { 824 DeviceState *dev = DEVICE(sbd); 825 StrongARMPPCInfo *s = STRONGARM_PPC(dev); 826 827 qdev_init_gpio_in(dev, strongarm_ppc_set, 22); 828 qdev_init_gpio_out(dev, s->handler, 22); 829 830 memory_region_init_io(&s->iomem, OBJECT(s), &strongarm_ppc_ops, s, 831 "ppc", 0x1000); 832 833 sysbus_init_mmio(sbd, &s->iomem); 834 835 return 0; 836 } 837 838 static const VMStateDescription vmstate_strongarm_ppc_regs = { 839 .name = "strongarm-ppc", 840 .version_id = 0, 841 .minimum_version_id = 0, 842 .fields = (VMStateField[]) { 843 VMSTATE_UINT32(ilevel, StrongARMPPCInfo), 844 VMSTATE_UINT32(olevel, StrongARMPPCInfo), 845 VMSTATE_UINT32(dir, StrongARMPPCInfo), 846 VMSTATE_UINT32(ppar, StrongARMPPCInfo), 847 VMSTATE_UINT32(psdr, StrongARMPPCInfo), 848 VMSTATE_UINT32(ppfr, StrongARMPPCInfo), 849 VMSTATE_END_OF_LIST(), 850 }, 851 }; 852 853 static void strongarm_ppc_class_init(ObjectClass *klass, void *data) 854 { 855 DeviceClass *dc = DEVICE_CLASS(klass); 856 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 857 858 k->init = strongarm_ppc_init; 859 dc->desc = "StrongARM PPC controller"; 860 } 861 862 static const TypeInfo strongarm_ppc_info = { 863 .name = TYPE_STRONGARM_PPC, 864 .parent = TYPE_SYS_BUS_DEVICE, 865 .instance_size = sizeof(StrongARMPPCInfo), 866 .class_init = strongarm_ppc_class_init, 867 }; 868 869 /* UART Ports */ 870 #define UTCR0 0x00 871 #define UTCR1 0x04 872 #define UTCR2 0x08 873 #define UTCR3 0x0c 874 #define UTDR 0x14 875 #define UTSR0 0x1c 876 #define UTSR1 0x20 877 878 #define UTCR0_PE (1 << 0) /* Parity enable */ 879 #define UTCR0_OES (1 << 1) /* Even parity */ 880 #define UTCR0_SBS (1 << 2) /* 2 stop bits */ 881 #define UTCR0_DSS (1 << 3) /* 8-bit data */ 882 883 #define UTCR3_RXE (1 << 0) /* Rx enable */ 884 #define UTCR3_TXE (1 << 1) /* Tx enable */ 885 #define UTCR3_BRK (1 << 2) /* Force Break */ 886 #define UTCR3_RIE (1 << 3) /* Rx int enable */ 887 #define UTCR3_TIE (1 << 4) /* Tx int enable */ 888 #define UTCR3_LBM (1 << 5) /* Loopback */ 889 890 #define UTSR0_TFS (1 << 0) /* Tx FIFO nearly empty */ 891 #define UTSR0_RFS (1 << 1) /* Rx FIFO nearly full */ 892 #define UTSR0_RID (1 << 2) /* Receiver Idle */ 893 #define UTSR0_RBB (1 << 3) /* Receiver begin break */ 894 #define UTSR0_REB (1 << 4) /* Receiver end break */ 895 #define UTSR0_EIF (1 << 5) /* Error in FIFO */ 896 897 #define UTSR1_RNE (1 << 1) /* Receive FIFO not empty */ 898 #define UTSR1_TNF (1 << 2) /* Transmit FIFO not full */ 899 #define UTSR1_PRE (1 << 3) /* Parity error */ 900 #define UTSR1_FRE (1 << 4) /* Frame error */ 901 #define UTSR1_ROR (1 << 5) /* Receive Over Run */ 902 903 #define RX_FIFO_PRE (1 << 8) 904 #define RX_FIFO_FRE (1 << 9) 905 #define RX_FIFO_ROR (1 << 10) 906 907 #define TYPE_STRONGARM_UART "strongarm-uart" 908 #define STRONGARM_UART(obj) \ 909 OBJECT_CHECK(StrongARMUARTState, (obj), TYPE_STRONGARM_UART) 910 911 typedef struct StrongARMUARTState { 912 SysBusDevice parent_obj; 913 914 MemoryRegion iomem; 915 CharDriverState *chr; 916 qemu_irq irq; 917 918 uint8_t utcr0; 919 uint16_t brd; 920 uint8_t utcr3; 921 uint8_t utsr0; 922 uint8_t utsr1; 923 924 uint8_t tx_fifo[8]; 925 uint8_t tx_start; 926 uint8_t tx_len; 927 uint16_t rx_fifo[12]; /* value + error flags in high bits */ 928 uint8_t rx_start; 929 uint8_t rx_len; 930 931 uint64_t char_transmit_time; /* time to transmit a char in ticks*/ 932 bool wait_break_end; 933 QEMUTimer *rx_timeout_timer; 934 QEMUTimer *tx_timer; 935 } StrongARMUARTState; 936 937 static void strongarm_uart_update_status(StrongARMUARTState *s) 938 { 939 uint16_t utsr1 = 0; 940 941 if (s->tx_len != 8) { 942 utsr1 |= UTSR1_TNF; 943 } 944 945 if (s->rx_len != 0) { 946 uint16_t ent = s->rx_fifo[s->rx_start]; 947 948 utsr1 |= UTSR1_RNE; 949 if (ent & RX_FIFO_PRE) { 950 s->utsr1 |= UTSR1_PRE; 951 } 952 if (ent & RX_FIFO_FRE) { 953 s->utsr1 |= UTSR1_FRE; 954 } 955 if (ent & RX_FIFO_ROR) { 956 s->utsr1 |= UTSR1_ROR; 957 } 958 } 959 960 s->utsr1 = utsr1; 961 } 962 963 static void strongarm_uart_update_int_status(StrongARMUARTState *s) 964 { 965 uint16_t utsr0 = s->utsr0 & 966 (UTSR0_REB | UTSR0_RBB | UTSR0_RID); 967 int i; 968 969 if ((s->utcr3 & UTCR3_TXE) && 970 (s->utcr3 & UTCR3_TIE) && 971 s->tx_len <= 4) { 972 utsr0 |= UTSR0_TFS; 973 } 974 975 if ((s->utcr3 & UTCR3_RXE) && 976 (s->utcr3 & UTCR3_RIE) && 977 s->rx_len > 4) { 978 utsr0 |= UTSR0_RFS; 979 } 980 981 for (i = 0; i < s->rx_len && i < 4; i++) 982 if (s->rx_fifo[(s->rx_start + i) % 12] & ~0xff) { 983 utsr0 |= UTSR0_EIF; 984 break; 985 } 986 987 s->utsr0 = utsr0; 988 qemu_set_irq(s->irq, utsr0); 989 } 990 991 static void strongarm_uart_update_parameters(StrongARMUARTState *s) 992 { 993 int speed, parity, data_bits, stop_bits, frame_size; 994 QEMUSerialSetParams ssp; 995 996 /* Start bit. */ 997 frame_size = 1; 998 if (s->utcr0 & UTCR0_PE) { 999 /* Parity bit. */ 1000 frame_size++; 1001 if (s->utcr0 & UTCR0_OES) { 1002 parity = 'E'; 1003 } else { 1004 parity = 'O'; 1005 } 1006 } else { 1007 parity = 'N'; 1008 } 1009 if (s->utcr0 & UTCR0_SBS) { 1010 stop_bits = 2; 1011 } else { 1012 stop_bits = 1; 1013 } 1014 1015 data_bits = (s->utcr0 & UTCR0_DSS) ? 8 : 7; 1016 frame_size += data_bits + stop_bits; 1017 speed = 3686400 / 16 / (s->brd + 1); 1018 ssp.speed = speed; 1019 ssp.parity = parity; 1020 ssp.data_bits = data_bits; 1021 ssp.stop_bits = stop_bits; 1022 s->char_transmit_time = (get_ticks_per_sec() / speed) * frame_size; 1023 if (s->chr) { 1024 qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); 1025 } 1026 1027 DPRINTF(stderr, "%s speed=%d parity=%c data=%d stop=%d\n", s->chr->label, 1028 speed, parity, data_bits, stop_bits); 1029 } 1030 1031 static void strongarm_uart_rx_to(void *opaque) 1032 { 1033 StrongARMUARTState *s = opaque; 1034 1035 if (s->rx_len) { 1036 s->utsr0 |= UTSR0_RID; 1037 strongarm_uart_update_int_status(s); 1038 } 1039 } 1040 1041 static void strongarm_uart_rx_push(StrongARMUARTState *s, uint16_t c) 1042 { 1043 if ((s->utcr3 & UTCR3_RXE) == 0) { 1044 /* rx disabled */ 1045 return; 1046 } 1047 1048 if (s->wait_break_end) { 1049 s->utsr0 |= UTSR0_REB; 1050 s->wait_break_end = false; 1051 } 1052 1053 if (s->rx_len < 12) { 1054 s->rx_fifo[(s->rx_start + s->rx_len) % 12] = c; 1055 s->rx_len++; 1056 } else 1057 s->rx_fifo[(s->rx_start + 11) % 12] |= RX_FIFO_ROR; 1058 } 1059 1060 static int strongarm_uart_can_receive(void *opaque) 1061 { 1062 StrongARMUARTState *s = opaque; 1063 1064 if (s->rx_len == 12) { 1065 return 0; 1066 } 1067 /* It's best not to get more than 2/3 of RX FIFO, so advertise that much */ 1068 if (s->rx_len < 8) { 1069 return 8 - s->rx_len; 1070 } 1071 return 1; 1072 } 1073 1074 static void strongarm_uart_receive(void *opaque, const uint8_t *buf, int size) 1075 { 1076 StrongARMUARTState *s = opaque; 1077 int i; 1078 1079 for (i = 0; i < size; i++) { 1080 strongarm_uart_rx_push(s, buf[i]); 1081 } 1082 1083 /* call the timeout receive callback in 3 char transmit time */ 1084 timer_mod(s->rx_timeout_timer, 1085 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 3); 1086 1087 strongarm_uart_update_status(s); 1088 strongarm_uart_update_int_status(s); 1089 } 1090 1091 static void strongarm_uart_event(void *opaque, int event) 1092 { 1093 StrongARMUARTState *s = opaque; 1094 if (event == CHR_EVENT_BREAK) { 1095 s->utsr0 |= UTSR0_RBB; 1096 strongarm_uart_rx_push(s, RX_FIFO_FRE); 1097 s->wait_break_end = true; 1098 strongarm_uart_update_status(s); 1099 strongarm_uart_update_int_status(s); 1100 } 1101 } 1102 1103 static void strongarm_uart_tx(void *opaque) 1104 { 1105 StrongARMUARTState *s = opaque; 1106 uint64_t new_xmit_ts = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 1107 1108 if (s->utcr3 & UTCR3_LBM) /* loopback */ { 1109 strongarm_uart_receive(s, &s->tx_fifo[s->tx_start], 1); 1110 } else if (s->chr) { 1111 qemu_chr_fe_write(s->chr, &s->tx_fifo[s->tx_start], 1); 1112 } 1113 1114 s->tx_start = (s->tx_start + 1) % 8; 1115 s->tx_len--; 1116 if (s->tx_len) { 1117 timer_mod(s->tx_timer, new_xmit_ts + s->char_transmit_time); 1118 } 1119 strongarm_uart_update_status(s); 1120 strongarm_uart_update_int_status(s); 1121 } 1122 1123 static uint64_t strongarm_uart_read(void *opaque, hwaddr addr, 1124 unsigned size) 1125 { 1126 StrongARMUARTState *s = opaque; 1127 uint16_t ret; 1128 1129 switch (addr) { 1130 case UTCR0: 1131 return s->utcr0; 1132 1133 case UTCR1: 1134 return s->brd >> 8; 1135 1136 case UTCR2: 1137 return s->brd & 0xff; 1138 1139 case UTCR3: 1140 return s->utcr3; 1141 1142 case UTDR: 1143 if (s->rx_len != 0) { 1144 ret = s->rx_fifo[s->rx_start]; 1145 s->rx_start = (s->rx_start + 1) % 12; 1146 s->rx_len--; 1147 strongarm_uart_update_status(s); 1148 strongarm_uart_update_int_status(s); 1149 return ret; 1150 } 1151 return 0; 1152 1153 case UTSR0: 1154 return s->utsr0; 1155 1156 case UTSR1: 1157 return s->utsr1; 1158 1159 default: 1160 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr); 1161 return 0; 1162 } 1163 } 1164 1165 static void strongarm_uart_write(void *opaque, hwaddr addr, 1166 uint64_t value, unsigned size) 1167 { 1168 StrongARMUARTState *s = opaque; 1169 1170 switch (addr) { 1171 case UTCR0: 1172 s->utcr0 = value & 0x7f; 1173 strongarm_uart_update_parameters(s); 1174 break; 1175 1176 case UTCR1: 1177 s->brd = (s->brd & 0xff) | ((value & 0xf) << 8); 1178 strongarm_uart_update_parameters(s); 1179 break; 1180 1181 case UTCR2: 1182 s->brd = (s->brd & 0xf00) | (value & 0xff); 1183 strongarm_uart_update_parameters(s); 1184 break; 1185 1186 case UTCR3: 1187 s->utcr3 = value & 0x3f; 1188 if ((s->utcr3 & UTCR3_RXE) == 0) { 1189 s->rx_len = 0; 1190 } 1191 if ((s->utcr3 & UTCR3_TXE) == 0) { 1192 s->tx_len = 0; 1193 } 1194 strongarm_uart_update_status(s); 1195 strongarm_uart_update_int_status(s); 1196 break; 1197 1198 case UTDR: 1199 if ((s->utcr3 & UTCR3_TXE) && s->tx_len != 8) { 1200 s->tx_fifo[(s->tx_start + s->tx_len) % 8] = value; 1201 s->tx_len++; 1202 strongarm_uart_update_status(s); 1203 strongarm_uart_update_int_status(s); 1204 if (s->tx_len == 1) { 1205 strongarm_uart_tx(s); 1206 } 1207 } 1208 break; 1209 1210 case UTSR0: 1211 s->utsr0 = s->utsr0 & ~(value & 1212 (UTSR0_REB | UTSR0_RBB | UTSR0_RID)); 1213 strongarm_uart_update_int_status(s); 1214 break; 1215 1216 default: 1217 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr); 1218 } 1219 } 1220 1221 static const MemoryRegionOps strongarm_uart_ops = { 1222 .read = strongarm_uart_read, 1223 .write = strongarm_uart_write, 1224 .endianness = DEVICE_NATIVE_ENDIAN, 1225 }; 1226 1227 static int strongarm_uart_init(SysBusDevice *dev) 1228 { 1229 StrongARMUARTState *s = STRONGARM_UART(dev); 1230 1231 memory_region_init_io(&s->iomem, OBJECT(s), &strongarm_uart_ops, s, 1232 "uart", 0x10000); 1233 sysbus_init_mmio(dev, &s->iomem); 1234 sysbus_init_irq(dev, &s->irq); 1235 1236 s->rx_timeout_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, strongarm_uart_rx_to, s); 1237 s->tx_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, strongarm_uart_tx, s); 1238 1239 if (s->chr) { 1240 qemu_chr_add_handlers(s->chr, 1241 strongarm_uart_can_receive, 1242 strongarm_uart_receive, 1243 strongarm_uart_event, 1244 s); 1245 } 1246 1247 return 0; 1248 } 1249 1250 static void strongarm_uart_reset(DeviceState *dev) 1251 { 1252 StrongARMUARTState *s = STRONGARM_UART(dev); 1253 1254 s->utcr0 = UTCR0_DSS; /* 8 data, no parity */ 1255 s->brd = 23; /* 9600 */ 1256 /* enable send & recv - this actually violates spec */ 1257 s->utcr3 = UTCR3_TXE | UTCR3_RXE; 1258 1259 s->rx_len = s->tx_len = 0; 1260 1261 strongarm_uart_update_parameters(s); 1262 strongarm_uart_update_status(s); 1263 strongarm_uart_update_int_status(s); 1264 } 1265 1266 static int strongarm_uart_post_load(void *opaque, int version_id) 1267 { 1268 StrongARMUARTState *s = opaque; 1269 1270 strongarm_uart_update_parameters(s); 1271 strongarm_uart_update_status(s); 1272 strongarm_uart_update_int_status(s); 1273 1274 /* tx and restart timer */ 1275 if (s->tx_len) { 1276 strongarm_uart_tx(s); 1277 } 1278 1279 /* restart rx timeout timer */ 1280 if (s->rx_len) { 1281 timer_mod(s->rx_timeout_timer, 1282 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 3); 1283 } 1284 1285 return 0; 1286 } 1287 1288 static const VMStateDescription vmstate_strongarm_uart_regs = { 1289 .name = "strongarm-uart", 1290 .version_id = 0, 1291 .minimum_version_id = 0, 1292 .post_load = strongarm_uart_post_load, 1293 .fields = (VMStateField[]) { 1294 VMSTATE_UINT8(utcr0, StrongARMUARTState), 1295 VMSTATE_UINT16(brd, StrongARMUARTState), 1296 VMSTATE_UINT8(utcr3, StrongARMUARTState), 1297 VMSTATE_UINT8(utsr0, StrongARMUARTState), 1298 VMSTATE_UINT8_ARRAY(tx_fifo, StrongARMUARTState, 8), 1299 VMSTATE_UINT8(tx_start, StrongARMUARTState), 1300 VMSTATE_UINT8(tx_len, StrongARMUARTState), 1301 VMSTATE_UINT16_ARRAY(rx_fifo, StrongARMUARTState, 12), 1302 VMSTATE_UINT8(rx_start, StrongARMUARTState), 1303 VMSTATE_UINT8(rx_len, StrongARMUARTState), 1304 VMSTATE_BOOL(wait_break_end, StrongARMUARTState), 1305 VMSTATE_END_OF_LIST(), 1306 }, 1307 }; 1308 1309 static Property strongarm_uart_properties[] = { 1310 DEFINE_PROP_CHR("chardev", StrongARMUARTState, chr), 1311 DEFINE_PROP_END_OF_LIST(), 1312 }; 1313 1314 static void strongarm_uart_class_init(ObjectClass *klass, void *data) 1315 { 1316 DeviceClass *dc = DEVICE_CLASS(klass); 1317 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 1318 1319 k->init = strongarm_uart_init; 1320 dc->desc = "StrongARM UART controller"; 1321 dc->reset = strongarm_uart_reset; 1322 dc->vmsd = &vmstate_strongarm_uart_regs; 1323 dc->props = strongarm_uart_properties; 1324 } 1325 1326 static const TypeInfo strongarm_uart_info = { 1327 .name = TYPE_STRONGARM_UART, 1328 .parent = TYPE_SYS_BUS_DEVICE, 1329 .instance_size = sizeof(StrongARMUARTState), 1330 .class_init = strongarm_uart_class_init, 1331 }; 1332 1333 /* Synchronous Serial Ports */ 1334 1335 #define TYPE_STRONGARM_SSP "strongarm-ssp" 1336 #define STRONGARM_SSP(obj) \ 1337 OBJECT_CHECK(StrongARMSSPState, (obj), TYPE_STRONGARM_SSP) 1338 1339 typedef struct StrongARMSSPState { 1340 SysBusDevice parent_obj; 1341 1342 MemoryRegion iomem; 1343 qemu_irq irq; 1344 SSIBus *bus; 1345 1346 uint16_t sscr[2]; 1347 uint16_t sssr; 1348 1349 uint16_t rx_fifo[8]; 1350 uint8_t rx_level; 1351 uint8_t rx_start; 1352 } StrongARMSSPState; 1353 1354 #define SSCR0 0x60 /* SSP Control register 0 */ 1355 #define SSCR1 0x64 /* SSP Control register 1 */ 1356 #define SSDR 0x6c /* SSP Data register */ 1357 #define SSSR 0x74 /* SSP Status register */ 1358 1359 /* Bitfields for above registers */ 1360 #define SSCR0_SPI(x) (((x) & 0x30) == 0x00) 1361 #define SSCR0_SSP(x) (((x) & 0x30) == 0x10) 1362 #define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20) 1363 #define SSCR0_PSP(x) (((x) & 0x30) == 0x30) 1364 #define SSCR0_SSE (1 << 7) 1365 #define SSCR0_DSS(x) (((x) & 0xf) + 1) 1366 #define SSCR1_RIE (1 << 0) 1367 #define SSCR1_TIE (1 << 1) 1368 #define SSCR1_LBM (1 << 2) 1369 #define SSSR_TNF (1 << 2) 1370 #define SSSR_RNE (1 << 3) 1371 #define SSSR_TFS (1 << 5) 1372 #define SSSR_RFS (1 << 6) 1373 #define SSSR_ROR (1 << 7) 1374 #define SSSR_RW 0x0080 1375 1376 static void strongarm_ssp_int_update(StrongARMSSPState *s) 1377 { 1378 int level = 0; 1379 1380 level |= (s->sssr & SSSR_ROR); 1381 level |= (s->sssr & SSSR_RFS) && (s->sscr[1] & SSCR1_RIE); 1382 level |= (s->sssr & SSSR_TFS) && (s->sscr[1] & SSCR1_TIE); 1383 qemu_set_irq(s->irq, level); 1384 } 1385 1386 static void strongarm_ssp_fifo_update(StrongARMSSPState *s) 1387 { 1388 s->sssr &= ~SSSR_TFS; 1389 s->sssr &= ~SSSR_TNF; 1390 if (s->sscr[0] & SSCR0_SSE) { 1391 if (s->rx_level >= 4) { 1392 s->sssr |= SSSR_RFS; 1393 } else { 1394 s->sssr &= ~SSSR_RFS; 1395 } 1396 if (s->rx_level) { 1397 s->sssr |= SSSR_RNE; 1398 } else { 1399 s->sssr &= ~SSSR_RNE; 1400 } 1401 /* TX FIFO is never filled, so it is always in underrun 1402 condition if SSP is enabled */ 1403 s->sssr |= SSSR_TFS; 1404 s->sssr |= SSSR_TNF; 1405 } 1406 1407 strongarm_ssp_int_update(s); 1408 } 1409 1410 static uint64_t strongarm_ssp_read(void *opaque, hwaddr addr, 1411 unsigned size) 1412 { 1413 StrongARMSSPState *s = opaque; 1414 uint32_t retval; 1415 1416 switch (addr) { 1417 case SSCR0: 1418 return s->sscr[0]; 1419 case SSCR1: 1420 return s->sscr[1]; 1421 case SSSR: 1422 return s->sssr; 1423 case SSDR: 1424 if (~s->sscr[0] & SSCR0_SSE) { 1425 return 0xffffffff; 1426 } 1427 if (s->rx_level < 1) { 1428 printf("%s: SSP Rx Underrun\n", __func__); 1429 return 0xffffffff; 1430 } 1431 s->rx_level--; 1432 retval = s->rx_fifo[s->rx_start++]; 1433 s->rx_start &= 0x7; 1434 strongarm_ssp_fifo_update(s); 1435 return retval; 1436 default: 1437 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr); 1438 break; 1439 } 1440 return 0; 1441 } 1442 1443 static void strongarm_ssp_write(void *opaque, hwaddr addr, 1444 uint64_t value, unsigned size) 1445 { 1446 StrongARMSSPState *s = opaque; 1447 1448 switch (addr) { 1449 case SSCR0: 1450 s->sscr[0] = value & 0xffbf; 1451 if ((s->sscr[0] & SSCR0_SSE) && SSCR0_DSS(value) < 4) { 1452 printf("%s: Wrong data size: %i bits\n", __func__, 1453 (int)SSCR0_DSS(value)); 1454 } 1455 if (!(value & SSCR0_SSE)) { 1456 s->sssr = 0; 1457 s->rx_level = 0; 1458 } 1459 strongarm_ssp_fifo_update(s); 1460 break; 1461 1462 case SSCR1: 1463 s->sscr[1] = value & 0x2f; 1464 if (value & SSCR1_LBM) { 1465 printf("%s: Attempt to use SSP LBM mode\n", __func__); 1466 } 1467 strongarm_ssp_fifo_update(s); 1468 break; 1469 1470 case SSSR: 1471 s->sssr &= ~(value & SSSR_RW); 1472 strongarm_ssp_int_update(s); 1473 break; 1474 1475 case SSDR: 1476 if (SSCR0_UWIRE(s->sscr[0])) { 1477 value &= 0xff; 1478 } else 1479 /* Note how 32bits overflow does no harm here */ 1480 value &= (1 << SSCR0_DSS(s->sscr[0])) - 1; 1481 1482 /* Data goes from here to the Tx FIFO and is shifted out from 1483 * there directly to the slave, no need to buffer it. 1484 */ 1485 if (s->sscr[0] & SSCR0_SSE) { 1486 uint32_t readval; 1487 if (s->sscr[1] & SSCR1_LBM) { 1488 readval = value; 1489 } else { 1490 readval = ssi_transfer(s->bus, value); 1491 } 1492 1493 if (s->rx_level < 0x08) { 1494 s->rx_fifo[(s->rx_start + s->rx_level++) & 0x7] = readval; 1495 } else { 1496 s->sssr |= SSSR_ROR; 1497 } 1498 } 1499 strongarm_ssp_fifo_update(s); 1500 break; 1501 1502 default: 1503 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr); 1504 break; 1505 } 1506 } 1507 1508 static const MemoryRegionOps strongarm_ssp_ops = { 1509 .read = strongarm_ssp_read, 1510 .write = strongarm_ssp_write, 1511 .endianness = DEVICE_NATIVE_ENDIAN, 1512 }; 1513 1514 static int strongarm_ssp_post_load(void *opaque, int version_id) 1515 { 1516 StrongARMSSPState *s = opaque; 1517 1518 strongarm_ssp_fifo_update(s); 1519 1520 return 0; 1521 } 1522 1523 static int strongarm_ssp_init(SysBusDevice *sbd) 1524 { 1525 DeviceState *dev = DEVICE(sbd); 1526 StrongARMSSPState *s = STRONGARM_SSP(dev); 1527 1528 sysbus_init_irq(sbd, &s->irq); 1529 1530 memory_region_init_io(&s->iomem, OBJECT(s), &strongarm_ssp_ops, s, 1531 "ssp", 0x1000); 1532 sysbus_init_mmio(sbd, &s->iomem); 1533 1534 s->bus = ssi_create_bus(dev, "ssi"); 1535 return 0; 1536 } 1537 1538 static void strongarm_ssp_reset(DeviceState *dev) 1539 { 1540 StrongARMSSPState *s = STRONGARM_SSP(dev); 1541 1542 s->sssr = 0x03; /* 3 bit data, SPI, disabled */ 1543 s->rx_start = 0; 1544 s->rx_level = 0; 1545 } 1546 1547 static const VMStateDescription vmstate_strongarm_ssp_regs = { 1548 .name = "strongarm-ssp", 1549 .version_id = 0, 1550 .minimum_version_id = 0, 1551 .post_load = strongarm_ssp_post_load, 1552 .fields = (VMStateField[]) { 1553 VMSTATE_UINT16_ARRAY(sscr, StrongARMSSPState, 2), 1554 VMSTATE_UINT16(sssr, StrongARMSSPState), 1555 VMSTATE_UINT16_ARRAY(rx_fifo, StrongARMSSPState, 8), 1556 VMSTATE_UINT8(rx_start, StrongARMSSPState), 1557 VMSTATE_UINT8(rx_level, StrongARMSSPState), 1558 VMSTATE_END_OF_LIST(), 1559 }, 1560 }; 1561 1562 static void strongarm_ssp_class_init(ObjectClass *klass, void *data) 1563 { 1564 DeviceClass *dc = DEVICE_CLASS(klass); 1565 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 1566 1567 k->init = strongarm_ssp_init; 1568 dc->desc = "StrongARM SSP controller"; 1569 dc->reset = strongarm_ssp_reset; 1570 dc->vmsd = &vmstate_strongarm_ssp_regs; 1571 } 1572 1573 static const TypeInfo strongarm_ssp_info = { 1574 .name = TYPE_STRONGARM_SSP, 1575 .parent = TYPE_SYS_BUS_DEVICE, 1576 .instance_size = sizeof(StrongARMSSPState), 1577 .class_init = strongarm_ssp_class_init, 1578 }; 1579 1580 /* Main CPU functions */ 1581 StrongARMState *sa1110_init(MemoryRegion *sysmem, 1582 unsigned int sdram_size, const char *rev) 1583 { 1584 StrongARMState *s; 1585 int i; 1586 1587 s = g_malloc0(sizeof(StrongARMState)); 1588 1589 if (!rev) { 1590 rev = "sa1110-b5"; 1591 } 1592 1593 if (strncmp(rev, "sa1110", 6)) { 1594 error_report("Machine requires a SA1110 processor."); 1595 exit(1); 1596 } 1597 1598 s->cpu = cpu_arm_init(rev); 1599 1600 if (!s->cpu) { 1601 error_report("Unable to find CPU definition"); 1602 exit(1); 1603 } 1604 1605 memory_region_init_ram(&s->sdram, NULL, "strongarm.sdram", sdram_size); 1606 vmstate_register_ram_global(&s->sdram); 1607 memory_region_add_subregion(sysmem, SA_SDCS0, &s->sdram); 1608 1609 s->pic = sysbus_create_varargs("strongarm_pic", 0x90050000, 1610 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ), 1611 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_FIQ), 1612 NULL); 1613 1614 sysbus_create_varargs("pxa25x-timer", 0x90000000, 1615 qdev_get_gpio_in(s->pic, SA_PIC_OSTC0), 1616 qdev_get_gpio_in(s->pic, SA_PIC_OSTC1), 1617 qdev_get_gpio_in(s->pic, SA_PIC_OSTC2), 1618 qdev_get_gpio_in(s->pic, SA_PIC_OSTC3), 1619 NULL); 1620 1621 sysbus_create_simple(TYPE_STRONGARM_RTC, 0x90010000, 1622 qdev_get_gpio_in(s->pic, SA_PIC_RTC_ALARM)); 1623 1624 s->gpio = strongarm_gpio_init(0x90040000, s->pic); 1625 1626 s->ppc = sysbus_create_varargs(TYPE_STRONGARM_PPC, 0x90060000, NULL); 1627 1628 for (i = 0; sa_serial[i].io_base; i++) { 1629 DeviceState *dev = qdev_create(NULL, TYPE_STRONGARM_UART); 1630 qdev_prop_set_chr(dev, "chardev", serial_hds[i]); 1631 qdev_init_nofail(dev); 1632 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 1633 sa_serial[i].io_base); 1634 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, 1635 qdev_get_gpio_in(s->pic, sa_serial[i].irq)); 1636 } 1637 1638 s->ssp = sysbus_create_varargs(TYPE_STRONGARM_SSP, 0x80070000, 1639 qdev_get_gpio_in(s->pic, SA_PIC_SSP), NULL); 1640 s->ssp_bus = (SSIBus *)qdev_get_child_bus(s->ssp, "ssi"); 1641 1642 return s; 1643 } 1644 1645 static void strongarm_register_types(void) 1646 { 1647 type_register_static(&strongarm_pic_info); 1648 type_register_static(&strongarm_rtc_sysbus_info); 1649 type_register_static(&strongarm_gpio_info); 1650 type_register_static(&strongarm_ppc_info); 1651 type_register_static(&strongarm_uart_info); 1652 type_register_static(&strongarm_ssp_info); 1653 } 1654 1655 type_init(strongarm_register_types) 1656