1 /* 2 * StrongARM SA-1100/SA-1110 emulation 3 * 4 * Copyright (C) 2011 Dmitry Eremin-Solenikov 5 * 6 * Largely based on StrongARM emulation: 7 * Copyright (c) 2006 Openedhand Ltd. 8 * Written by Andrzej Zaborowski <balrog@zabor.org> 9 * 10 * UART code based on QEMU 16550A UART emulation 11 * Copyright (c) 2003-2004 Fabrice Bellard 12 * Copyright (c) 2008 Citrix Systems, Inc. 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License version 2 as 16 * published by the Free Software Foundation. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License along 24 * with this program; if not, see <http://www.gnu.org/licenses/>. 25 * 26 * Contributions after 2012-01-13 are licensed under the terms of the 27 * GNU GPL, version 2 or (at your option) any later version. 28 */ 29 #include "hw/sysbus.h" 30 #include "strongarm.h" 31 #include "qemu/error-report.h" 32 #include "hw/arm/arm.h" 33 #include "sysemu/char.h" 34 #include "sysemu/sysemu.h" 35 #include "hw/ssi.h" 36 37 //#define DEBUG 38 39 /* 40 TODO 41 - Implement cp15, c14 ? 42 - Implement cp15, c15 !!! (idle used in L) 43 - Implement idle mode handling/DIM 44 - Implement sleep mode/Wake sources 45 - Implement reset control 46 - Implement memory control regs 47 - PCMCIA handling 48 - Maybe support MBGNT/MBREQ 49 - DMA channels 50 - GPCLK 51 - IrDA 52 - MCP 53 - Enhance UART with modem signals 54 */ 55 56 #ifdef DEBUG 57 # define DPRINTF(format, ...) printf(format , ## __VA_ARGS__) 58 #else 59 # define DPRINTF(format, ...) do { } while (0) 60 #endif 61 62 static struct { 63 hwaddr io_base; 64 int irq; 65 } sa_serial[] = { 66 { 0x80010000, SA_PIC_UART1 }, 67 { 0x80030000, SA_PIC_UART2 }, 68 { 0x80050000, SA_PIC_UART3 }, 69 { 0, 0 } 70 }; 71 72 /* Interrupt Controller */ 73 74 #define TYPE_STRONGARM_PIC "strongarm_pic" 75 #define STRONGARM_PIC(obj) \ 76 OBJECT_CHECK(StrongARMPICState, (obj), TYPE_STRONGARM_PIC) 77 78 typedef struct StrongARMPICState { 79 SysBusDevice parent_obj; 80 81 MemoryRegion iomem; 82 qemu_irq irq; 83 qemu_irq fiq; 84 85 uint32_t pending; 86 uint32_t enabled; 87 uint32_t is_fiq; 88 uint32_t int_idle; 89 } StrongARMPICState; 90 91 #define ICIP 0x00 92 #define ICMR 0x04 93 #define ICLR 0x08 94 #define ICFP 0x10 95 #define ICPR 0x20 96 #define ICCR 0x0c 97 98 #define SA_PIC_SRCS 32 99 100 101 static void strongarm_pic_update(void *opaque) 102 { 103 StrongARMPICState *s = opaque; 104 105 /* FIXME: reflect DIM */ 106 qemu_set_irq(s->fiq, s->pending & s->enabled & s->is_fiq); 107 qemu_set_irq(s->irq, s->pending & s->enabled & ~s->is_fiq); 108 } 109 110 static void strongarm_pic_set_irq(void *opaque, int irq, int level) 111 { 112 StrongARMPICState *s = opaque; 113 114 if (level) { 115 s->pending |= 1 << irq; 116 } else { 117 s->pending &= ~(1 << irq); 118 } 119 120 strongarm_pic_update(s); 121 } 122 123 static uint64_t strongarm_pic_mem_read(void *opaque, hwaddr offset, 124 unsigned size) 125 { 126 StrongARMPICState *s = opaque; 127 128 switch (offset) { 129 case ICIP: 130 return s->pending & ~s->is_fiq & s->enabled; 131 case ICMR: 132 return s->enabled; 133 case ICLR: 134 return s->is_fiq; 135 case ICCR: 136 return s->int_idle == 0; 137 case ICFP: 138 return s->pending & s->is_fiq & s->enabled; 139 case ICPR: 140 return s->pending; 141 default: 142 printf("%s: Bad register offset 0x" TARGET_FMT_plx "\n", 143 __func__, offset); 144 return 0; 145 } 146 } 147 148 static void strongarm_pic_mem_write(void *opaque, hwaddr offset, 149 uint64_t value, unsigned size) 150 { 151 StrongARMPICState *s = opaque; 152 153 switch (offset) { 154 case ICMR: 155 s->enabled = value; 156 break; 157 case ICLR: 158 s->is_fiq = value; 159 break; 160 case ICCR: 161 s->int_idle = (value & 1) ? 0 : ~0; 162 break; 163 default: 164 printf("%s: Bad register offset 0x" TARGET_FMT_plx "\n", 165 __func__, offset); 166 break; 167 } 168 strongarm_pic_update(s); 169 } 170 171 static const MemoryRegionOps strongarm_pic_ops = { 172 .read = strongarm_pic_mem_read, 173 .write = strongarm_pic_mem_write, 174 .endianness = DEVICE_NATIVE_ENDIAN, 175 }; 176 177 static int strongarm_pic_initfn(SysBusDevice *sbd) 178 { 179 DeviceState *dev = DEVICE(sbd); 180 StrongARMPICState *s = STRONGARM_PIC(dev); 181 182 qdev_init_gpio_in(dev, strongarm_pic_set_irq, SA_PIC_SRCS); 183 memory_region_init_io(&s->iomem, OBJECT(s), &strongarm_pic_ops, s, 184 "pic", 0x1000); 185 sysbus_init_mmio(sbd, &s->iomem); 186 sysbus_init_irq(sbd, &s->irq); 187 sysbus_init_irq(sbd, &s->fiq); 188 189 return 0; 190 } 191 192 static int strongarm_pic_post_load(void *opaque, int version_id) 193 { 194 strongarm_pic_update(opaque); 195 return 0; 196 } 197 198 static VMStateDescription vmstate_strongarm_pic_regs = { 199 .name = "strongarm_pic", 200 .version_id = 0, 201 .minimum_version_id = 0, 202 .minimum_version_id_old = 0, 203 .post_load = strongarm_pic_post_load, 204 .fields = (VMStateField[]) { 205 VMSTATE_UINT32(pending, StrongARMPICState), 206 VMSTATE_UINT32(enabled, StrongARMPICState), 207 VMSTATE_UINT32(is_fiq, StrongARMPICState), 208 VMSTATE_UINT32(int_idle, StrongARMPICState), 209 VMSTATE_END_OF_LIST(), 210 }, 211 }; 212 213 static void strongarm_pic_class_init(ObjectClass *klass, void *data) 214 { 215 DeviceClass *dc = DEVICE_CLASS(klass); 216 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 217 218 k->init = strongarm_pic_initfn; 219 dc->desc = "StrongARM PIC"; 220 dc->vmsd = &vmstate_strongarm_pic_regs; 221 } 222 223 static const TypeInfo strongarm_pic_info = { 224 .name = TYPE_STRONGARM_PIC, 225 .parent = TYPE_SYS_BUS_DEVICE, 226 .instance_size = sizeof(StrongARMPICState), 227 .class_init = strongarm_pic_class_init, 228 }; 229 230 /* Real-Time Clock */ 231 #define RTAR 0x00 /* RTC Alarm register */ 232 #define RCNR 0x04 /* RTC Counter register */ 233 #define RTTR 0x08 /* RTC Timer Trim register */ 234 #define RTSR 0x10 /* RTC Status register */ 235 236 #define RTSR_AL (1 << 0) /* RTC Alarm detected */ 237 #define RTSR_HZ (1 << 1) /* RTC 1Hz detected */ 238 #define RTSR_ALE (1 << 2) /* RTC Alarm enable */ 239 #define RTSR_HZE (1 << 3) /* RTC 1Hz enable */ 240 241 /* 16 LSB of RTTR are clockdiv for internal trim logic, 242 * trim delete isn't emulated, so 243 * f = 32 768 / (RTTR_trim + 1) */ 244 245 #define TYPE_STRONGARM_RTC "strongarm-rtc" 246 #define STRONGARM_RTC(obj) \ 247 OBJECT_CHECK(StrongARMRTCState, (obj), TYPE_STRONGARM_RTC) 248 249 typedef struct StrongARMRTCState { 250 SysBusDevice parent_obj; 251 252 MemoryRegion iomem; 253 uint32_t rttr; 254 uint32_t rtsr; 255 uint32_t rtar; 256 uint32_t last_rcnr; 257 int64_t last_hz; 258 QEMUTimer *rtc_alarm; 259 QEMUTimer *rtc_hz; 260 qemu_irq rtc_irq; 261 qemu_irq rtc_hz_irq; 262 } StrongARMRTCState; 263 264 static inline void strongarm_rtc_int_update(StrongARMRTCState *s) 265 { 266 qemu_set_irq(s->rtc_irq, s->rtsr & RTSR_AL); 267 qemu_set_irq(s->rtc_hz_irq, s->rtsr & RTSR_HZ); 268 } 269 270 static void strongarm_rtc_hzupdate(StrongARMRTCState *s) 271 { 272 int64_t rt = qemu_clock_get_ms(rtc_clock); 273 s->last_rcnr += ((rt - s->last_hz) << 15) / 274 (1000 * ((s->rttr & 0xffff) + 1)); 275 s->last_hz = rt; 276 } 277 278 static inline void strongarm_rtc_timer_update(StrongARMRTCState *s) 279 { 280 if ((s->rtsr & RTSR_HZE) && !(s->rtsr & RTSR_HZ)) { 281 timer_mod(s->rtc_hz, s->last_hz + 1000); 282 } else { 283 timer_del(s->rtc_hz); 284 } 285 286 if ((s->rtsr & RTSR_ALE) && !(s->rtsr & RTSR_AL)) { 287 timer_mod(s->rtc_alarm, s->last_hz + 288 (((s->rtar - s->last_rcnr) * 1000 * 289 ((s->rttr & 0xffff) + 1)) >> 15)); 290 } else { 291 timer_del(s->rtc_alarm); 292 } 293 } 294 295 static inline void strongarm_rtc_alarm_tick(void *opaque) 296 { 297 StrongARMRTCState *s = opaque; 298 s->rtsr |= RTSR_AL; 299 strongarm_rtc_timer_update(s); 300 strongarm_rtc_int_update(s); 301 } 302 303 static inline void strongarm_rtc_hz_tick(void *opaque) 304 { 305 StrongARMRTCState *s = opaque; 306 s->rtsr |= RTSR_HZ; 307 strongarm_rtc_timer_update(s); 308 strongarm_rtc_int_update(s); 309 } 310 311 static uint64_t strongarm_rtc_read(void *opaque, hwaddr addr, 312 unsigned size) 313 { 314 StrongARMRTCState *s = opaque; 315 316 switch (addr) { 317 case RTTR: 318 return s->rttr; 319 case RTSR: 320 return s->rtsr; 321 case RTAR: 322 return s->rtar; 323 case RCNR: 324 return s->last_rcnr + 325 ((qemu_clock_get_ms(rtc_clock) - s->last_hz) << 15) / 326 (1000 * ((s->rttr & 0xffff) + 1)); 327 default: 328 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr); 329 return 0; 330 } 331 } 332 333 static void strongarm_rtc_write(void *opaque, hwaddr addr, 334 uint64_t value, unsigned size) 335 { 336 StrongARMRTCState *s = opaque; 337 uint32_t old_rtsr; 338 339 switch (addr) { 340 case RTTR: 341 strongarm_rtc_hzupdate(s); 342 s->rttr = value; 343 strongarm_rtc_timer_update(s); 344 break; 345 346 case RTSR: 347 old_rtsr = s->rtsr; 348 s->rtsr = (value & (RTSR_ALE | RTSR_HZE)) | 349 (s->rtsr & ~(value & (RTSR_AL | RTSR_HZ))); 350 351 if (s->rtsr != old_rtsr) { 352 strongarm_rtc_timer_update(s); 353 } 354 355 strongarm_rtc_int_update(s); 356 break; 357 358 case RTAR: 359 s->rtar = value; 360 strongarm_rtc_timer_update(s); 361 break; 362 363 case RCNR: 364 strongarm_rtc_hzupdate(s); 365 s->last_rcnr = value; 366 strongarm_rtc_timer_update(s); 367 break; 368 369 default: 370 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr); 371 } 372 } 373 374 static const MemoryRegionOps strongarm_rtc_ops = { 375 .read = strongarm_rtc_read, 376 .write = strongarm_rtc_write, 377 .endianness = DEVICE_NATIVE_ENDIAN, 378 }; 379 380 static int strongarm_rtc_init(SysBusDevice *dev) 381 { 382 StrongARMRTCState *s = STRONGARM_RTC(dev); 383 struct tm tm; 384 385 s->rttr = 0x0; 386 s->rtsr = 0; 387 388 qemu_get_timedate(&tm, 0); 389 390 s->last_rcnr = (uint32_t) mktimegm(&tm); 391 s->last_hz = qemu_clock_get_ms(rtc_clock); 392 393 s->rtc_alarm = timer_new_ms(rtc_clock, strongarm_rtc_alarm_tick, s); 394 s->rtc_hz = timer_new_ms(rtc_clock, strongarm_rtc_hz_tick, s); 395 396 sysbus_init_irq(dev, &s->rtc_irq); 397 sysbus_init_irq(dev, &s->rtc_hz_irq); 398 399 memory_region_init_io(&s->iomem, OBJECT(s), &strongarm_rtc_ops, s, 400 "rtc", 0x10000); 401 sysbus_init_mmio(dev, &s->iomem); 402 403 return 0; 404 } 405 406 static void strongarm_rtc_pre_save(void *opaque) 407 { 408 StrongARMRTCState *s = opaque; 409 410 strongarm_rtc_hzupdate(s); 411 } 412 413 static int strongarm_rtc_post_load(void *opaque, int version_id) 414 { 415 StrongARMRTCState *s = opaque; 416 417 strongarm_rtc_timer_update(s); 418 strongarm_rtc_int_update(s); 419 420 return 0; 421 } 422 423 static const VMStateDescription vmstate_strongarm_rtc_regs = { 424 .name = "strongarm-rtc", 425 .version_id = 0, 426 .minimum_version_id = 0, 427 .minimum_version_id_old = 0, 428 .pre_save = strongarm_rtc_pre_save, 429 .post_load = strongarm_rtc_post_load, 430 .fields = (VMStateField[]) { 431 VMSTATE_UINT32(rttr, StrongARMRTCState), 432 VMSTATE_UINT32(rtsr, StrongARMRTCState), 433 VMSTATE_UINT32(rtar, StrongARMRTCState), 434 VMSTATE_UINT32(last_rcnr, StrongARMRTCState), 435 VMSTATE_INT64(last_hz, StrongARMRTCState), 436 VMSTATE_END_OF_LIST(), 437 }, 438 }; 439 440 static void strongarm_rtc_sysbus_class_init(ObjectClass *klass, void *data) 441 { 442 DeviceClass *dc = DEVICE_CLASS(klass); 443 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 444 445 k->init = strongarm_rtc_init; 446 dc->desc = "StrongARM RTC Controller"; 447 dc->vmsd = &vmstate_strongarm_rtc_regs; 448 } 449 450 static const TypeInfo strongarm_rtc_sysbus_info = { 451 .name = TYPE_STRONGARM_RTC, 452 .parent = TYPE_SYS_BUS_DEVICE, 453 .instance_size = sizeof(StrongARMRTCState), 454 .class_init = strongarm_rtc_sysbus_class_init, 455 }; 456 457 /* GPIO */ 458 #define GPLR 0x00 459 #define GPDR 0x04 460 #define GPSR 0x08 461 #define GPCR 0x0c 462 #define GRER 0x10 463 #define GFER 0x14 464 #define GEDR 0x18 465 #define GAFR 0x1c 466 467 #define TYPE_STRONGARM_GPIO "strongarm-gpio" 468 #define STRONGARM_GPIO(obj) \ 469 OBJECT_CHECK(StrongARMGPIOInfo, (obj), TYPE_STRONGARM_GPIO) 470 471 typedef struct StrongARMGPIOInfo StrongARMGPIOInfo; 472 struct StrongARMGPIOInfo { 473 SysBusDevice busdev; 474 MemoryRegion iomem; 475 qemu_irq handler[28]; 476 qemu_irq irqs[11]; 477 qemu_irq irqX; 478 479 uint32_t ilevel; 480 uint32_t olevel; 481 uint32_t dir; 482 uint32_t rising; 483 uint32_t falling; 484 uint32_t status; 485 uint32_t gpsr; 486 uint32_t gafr; 487 488 uint32_t prev_level; 489 }; 490 491 492 static void strongarm_gpio_irq_update(StrongARMGPIOInfo *s) 493 { 494 int i; 495 for (i = 0; i < 11; i++) { 496 qemu_set_irq(s->irqs[i], s->status & (1 << i)); 497 } 498 499 qemu_set_irq(s->irqX, (s->status & ~0x7ff)); 500 } 501 502 static void strongarm_gpio_set(void *opaque, int line, int level) 503 { 504 StrongARMGPIOInfo *s = opaque; 505 uint32_t mask; 506 507 mask = 1 << line; 508 509 if (level) { 510 s->status |= s->rising & mask & 511 ~s->ilevel & ~s->dir; 512 s->ilevel |= mask; 513 } else { 514 s->status |= s->falling & mask & 515 s->ilevel & ~s->dir; 516 s->ilevel &= ~mask; 517 } 518 519 if (s->status & mask) { 520 strongarm_gpio_irq_update(s); 521 } 522 } 523 524 static void strongarm_gpio_handler_update(StrongARMGPIOInfo *s) 525 { 526 uint32_t level, diff; 527 int bit; 528 529 level = s->olevel & s->dir; 530 531 for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) { 532 bit = ffs(diff) - 1; 533 qemu_set_irq(s->handler[bit], (level >> bit) & 1); 534 } 535 536 s->prev_level = level; 537 } 538 539 static uint64_t strongarm_gpio_read(void *opaque, hwaddr offset, 540 unsigned size) 541 { 542 StrongARMGPIOInfo *s = opaque; 543 544 switch (offset) { 545 case GPDR: /* GPIO Pin-Direction registers */ 546 return s->dir; 547 548 case GPSR: /* GPIO Pin-Output Set registers */ 549 DPRINTF("%s: Read from a write-only register 0x" TARGET_FMT_plx "\n", 550 __func__, offset); 551 return s->gpsr; /* Return last written value. */ 552 553 case GPCR: /* GPIO Pin-Output Clear registers */ 554 DPRINTF("%s: Read from a write-only register 0x" TARGET_FMT_plx "\n", 555 __func__, offset); 556 return 31337; /* Specified as unpredictable in the docs. */ 557 558 case GRER: /* GPIO Rising-Edge Detect Enable registers */ 559 return s->rising; 560 561 case GFER: /* GPIO Falling-Edge Detect Enable registers */ 562 return s->falling; 563 564 case GAFR: /* GPIO Alternate Function registers */ 565 return s->gafr; 566 567 case GPLR: /* GPIO Pin-Level registers */ 568 return (s->olevel & s->dir) | 569 (s->ilevel & ~s->dir); 570 571 case GEDR: /* GPIO Edge Detect Status registers */ 572 return s->status; 573 574 default: 575 printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset); 576 } 577 578 return 0; 579 } 580 581 static void strongarm_gpio_write(void *opaque, hwaddr offset, 582 uint64_t value, unsigned size) 583 { 584 StrongARMGPIOInfo *s = opaque; 585 586 switch (offset) { 587 case GPDR: /* GPIO Pin-Direction registers */ 588 s->dir = value; 589 strongarm_gpio_handler_update(s); 590 break; 591 592 case GPSR: /* GPIO Pin-Output Set registers */ 593 s->olevel |= value; 594 strongarm_gpio_handler_update(s); 595 s->gpsr = value; 596 break; 597 598 case GPCR: /* GPIO Pin-Output Clear registers */ 599 s->olevel &= ~value; 600 strongarm_gpio_handler_update(s); 601 break; 602 603 case GRER: /* GPIO Rising-Edge Detect Enable registers */ 604 s->rising = value; 605 break; 606 607 case GFER: /* GPIO Falling-Edge Detect Enable registers */ 608 s->falling = value; 609 break; 610 611 case GAFR: /* GPIO Alternate Function registers */ 612 s->gafr = value; 613 break; 614 615 case GEDR: /* GPIO Edge Detect Status registers */ 616 s->status &= ~value; 617 strongarm_gpio_irq_update(s); 618 break; 619 620 default: 621 printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset); 622 } 623 } 624 625 static const MemoryRegionOps strongarm_gpio_ops = { 626 .read = strongarm_gpio_read, 627 .write = strongarm_gpio_write, 628 .endianness = DEVICE_NATIVE_ENDIAN, 629 }; 630 631 static DeviceState *strongarm_gpio_init(hwaddr base, 632 DeviceState *pic) 633 { 634 DeviceState *dev; 635 int i; 636 637 dev = qdev_create(NULL, TYPE_STRONGARM_GPIO); 638 qdev_init_nofail(dev); 639 640 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 641 for (i = 0; i < 12; i++) 642 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 643 qdev_get_gpio_in(pic, SA_PIC_GPIO0_EDGE + i)); 644 645 return dev; 646 } 647 648 static int strongarm_gpio_initfn(SysBusDevice *sbd) 649 { 650 DeviceState *dev = DEVICE(sbd); 651 StrongARMGPIOInfo *s = STRONGARM_GPIO(dev); 652 int i; 653 654 qdev_init_gpio_in(dev, strongarm_gpio_set, 28); 655 qdev_init_gpio_out(dev, s->handler, 28); 656 657 memory_region_init_io(&s->iomem, OBJECT(s), &strongarm_gpio_ops, s, 658 "gpio", 0x1000); 659 660 sysbus_init_mmio(sbd, &s->iomem); 661 for (i = 0; i < 11; i++) { 662 sysbus_init_irq(sbd, &s->irqs[i]); 663 } 664 sysbus_init_irq(sbd, &s->irqX); 665 666 return 0; 667 } 668 669 static const VMStateDescription vmstate_strongarm_gpio_regs = { 670 .name = "strongarm-gpio", 671 .version_id = 0, 672 .minimum_version_id = 0, 673 .minimum_version_id_old = 0, 674 .fields = (VMStateField[]) { 675 VMSTATE_UINT32(ilevel, StrongARMGPIOInfo), 676 VMSTATE_UINT32(olevel, StrongARMGPIOInfo), 677 VMSTATE_UINT32(dir, StrongARMGPIOInfo), 678 VMSTATE_UINT32(rising, StrongARMGPIOInfo), 679 VMSTATE_UINT32(falling, StrongARMGPIOInfo), 680 VMSTATE_UINT32(status, StrongARMGPIOInfo), 681 VMSTATE_UINT32(gafr, StrongARMGPIOInfo), 682 VMSTATE_END_OF_LIST(), 683 }, 684 }; 685 686 static void strongarm_gpio_class_init(ObjectClass *klass, void *data) 687 { 688 DeviceClass *dc = DEVICE_CLASS(klass); 689 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 690 691 k->init = strongarm_gpio_initfn; 692 dc->desc = "StrongARM GPIO controller"; 693 } 694 695 static const TypeInfo strongarm_gpio_info = { 696 .name = TYPE_STRONGARM_GPIO, 697 .parent = TYPE_SYS_BUS_DEVICE, 698 .instance_size = sizeof(StrongARMGPIOInfo), 699 .class_init = strongarm_gpio_class_init, 700 }; 701 702 /* Peripheral Pin Controller */ 703 #define PPDR 0x00 704 #define PPSR 0x04 705 #define PPAR 0x08 706 #define PSDR 0x0c 707 #define PPFR 0x10 708 709 #define TYPE_STRONGARM_PPC "strongarm-ppc" 710 #define STRONGARM_PPC(obj) \ 711 OBJECT_CHECK(StrongARMPPCInfo, (obj), TYPE_STRONGARM_PPC) 712 713 typedef struct StrongARMPPCInfo StrongARMPPCInfo; 714 struct StrongARMPPCInfo { 715 SysBusDevice parent_obj; 716 717 MemoryRegion iomem; 718 qemu_irq handler[28]; 719 720 uint32_t ilevel; 721 uint32_t olevel; 722 uint32_t dir; 723 uint32_t ppar; 724 uint32_t psdr; 725 uint32_t ppfr; 726 727 uint32_t prev_level; 728 }; 729 730 static void strongarm_ppc_set(void *opaque, int line, int level) 731 { 732 StrongARMPPCInfo *s = opaque; 733 734 if (level) { 735 s->ilevel |= 1 << line; 736 } else { 737 s->ilevel &= ~(1 << line); 738 } 739 } 740 741 static void strongarm_ppc_handler_update(StrongARMPPCInfo *s) 742 { 743 uint32_t level, diff; 744 int bit; 745 746 level = s->olevel & s->dir; 747 748 for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) { 749 bit = ffs(diff) - 1; 750 qemu_set_irq(s->handler[bit], (level >> bit) & 1); 751 } 752 753 s->prev_level = level; 754 } 755 756 static uint64_t strongarm_ppc_read(void *opaque, hwaddr offset, 757 unsigned size) 758 { 759 StrongARMPPCInfo *s = opaque; 760 761 switch (offset) { 762 case PPDR: /* PPC Pin Direction registers */ 763 return s->dir | ~0x3fffff; 764 765 case PPSR: /* PPC Pin State registers */ 766 return (s->olevel & s->dir) | 767 (s->ilevel & ~s->dir) | 768 ~0x3fffff; 769 770 case PPAR: 771 return s->ppar | ~0x41000; 772 773 case PSDR: 774 return s->psdr; 775 776 case PPFR: 777 return s->ppfr | ~0x7f001; 778 779 default: 780 printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset); 781 } 782 783 return 0; 784 } 785 786 static void strongarm_ppc_write(void *opaque, hwaddr offset, 787 uint64_t value, unsigned size) 788 { 789 StrongARMPPCInfo *s = opaque; 790 791 switch (offset) { 792 case PPDR: /* PPC Pin Direction registers */ 793 s->dir = value & 0x3fffff; 794 strongarm_ppc_handler_update(s); 795 break; 796 797 case PPSR: /* PPC Pin State registers */ 798 s->olevel = value & s->dir & 0x3fffff; 799 strongarm_ppc_handler_update(s); 800 break; 801 802 case PPAR: 803 s->ppar = value & 0x41000; 804 break; 805 806 case PSDR: 807 s->psdr = value & 0x3fffff; 808 break; 809 810 case PPFR: 811 s->ppfr = value & 0x7f001; 812 break; 813 814 default: 815 printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset); 816 } 817 } 818 819 static const MemoryRegionOps strongarm_ppc_ops = { 820 .read = strongarm_ppc_read, 821 .write = strongarm_ppc_write, 822 .endianness = DEVICE_NATIVE_ENDIAN, 823 }; 824 825 static int strongarm_ppc_init(SysBusDevice *sbd) 826 { 827 DeviceState *dev = DEVICE(sbd); 828 StrongARMPPCInfo *s = STRONGARM_PPC(dev); 829 830 qdev_init_gpio_in(dev, strongarm_ppc_set, 22); 831 qdev_init_gpio_out(dev, s->handler, 22); 832 833 memory_region_init_io(&s->iomem, OBJECT(s), &strongarm_ppc_ops, s, 834 "ppc", 0x1000); 835 836 sysbus_init_mmio(sbd, &s->iomem); 837 838 return 0; 839 } 840 841 static const VMStateDescription vmstate_strongarm_ppc_regs = { 842 .name = "strongarm-ppc", 843 .version_id = 0, 844 .minimum_version_id = 0, 845 .minimum_version_id_old = 0, 846 .fields = (VMStateField[]) { 847 VMSTATE_UINT32(ilevel, StrongARMPPCInfo), 848 VMSTATE_UINT32(olevel, StrongARMPPCInfo), 849 VMSTATE_UINT32(dir, StrongARMPPCInfo), 850 VMSTATE_UINT32(ppar, StrongARMPPCInfo), 851 VMSTATE_UINT32(psdr, StrongARMPPCInfo), 852 VMSTATE_UINT32(ppfr, StrongARMPPCInfo), 853 VMSTATE_END_OF_LIST(), 854 }, 855 }; 856 857 static void strongarm_ppc_class_init(ObjectClass *klass, void *data) 858 { 859 DeviceClass *dc = DEVICE_CLASS(klass); 860 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 861 862 k->init = strongarm_ppc_init; 863 dc->desc = "StrongARM PPC controller"; 864 } 865 866 static const TypeInfo strongarm_ppc_info = { 867 .name = TYPE_STRONGARM_PPC, 868 .parent = TYPE_SYS_BUS_DEVICE, 869 .instance_size = sizeof(StrongARMPPCInfo), 870 .class_init = strongarm_ppc_class_init, 871 }; 872 873 /* UART Ports */ 874 #define UTCR0 0x00 875 #define UTCR1 0x04 876 #define UTCR2 0x08 877 #define UTCR3 0x0c 878 #define UTDR 0x14 879 #define UTSR0 0x1c 880 #define UTSR1 0x20 881 882 #define UTCR0_PE (1 << 0) /* Parity enable */ 883 #define UTCR0_OES (1 << 1) /* Even parity */ 884 #define UTCR0_SBS (1 << 2) /* 2 stop bits */ 885 #define UTCR0_DSS (1 << 3) /* 8-bit data */ 886 887 #define UTCR3_RXE (1 << 0) /* Rx enable */ 888 #define UTCR3_TXE (1 << 1) /* Tx enable */ 889 #define UTCR3_BRK (1 << 2) /* Force Break */ 890 #define UTCR3_RIE (1 << 3) /* Rx int enable */ 891 #define UTCR3_TIE (1 << 4) /* Tx int enable */ 892 #define UTCR3_LBM (1 << 5) /* Loopback */ 893 894 #define UTSR0_TFS (1 << 0) /* Tx FIFO nearly empty */ 895 #define UTSR0_RFS (1 << 1) /* Rx FIFO nearly full */ 896 #define UTSR0_RID (1 << 2) /* Receiver Idle */ 897 #define UTSR0_RBB (1 << 3) /* Receiver begin break */ 898 #define UTSR0_REB (1 << 4) /* Receiver end break */ 899 #define UTSR0_EIF (1 << 5) /* Error in FIFO */ 900 901 #define UTSR1_RNE (1 << 1) /* Receive FIFO not empty */ 902 #define UTSR1_TNF (1 << 2) /* Transmit FIFO not full */ 903 #define UTSR1_PRE (1 << 3) /* Parity error */ 904 #define UTSR1_FRE (1 << 4) /* Frame error */ 905 #define UTSR1_ROR (1 << 5) /* Receive Over Run */ 906 907 #define RX_FIFO_PRE (1 << 8) 908 #define RX_FIFO_FRE (1 << 9) 909 #define RX_FIFO_ROR (1 << 10) 910 911 #define TYPE_STRONGARM_UART "strongarm-uart" 912 #define STRONGARM_UART(obj) \ 913 OBJECT_CHECK(StrongARMUARTState, (obj), TYPE_STRONGARM_UART) 914 915 typedef struct StrongARMUARTState { 916 SysBusDevice parent_obj; 917 918 MemoryRegion iomem; 919 CharDriverState *chr; 920 qemu_irq irq; 921 922 uint8_t utcr0; 923 uint16_t brd; 924 uint8_t utcr3; 925 uint8_t utsr0; 926 uint8_t utsr1; 927 928 uint8_t tx_fifo[8]; 929 uint8_t tx_start; 930 uint8_t tx_len; 931 uint16_t rx_fifo[12]; /* value + error flags in high bits */ 932 uint8_t rx_start; 933 uint8_t rx_len; 934 935 uint64_t char_transmit_time; /* time to transmit a char in ticks*/ 936 bool wait_break_end; 937 QEMUTimer *rx_timeout_timer; 938 QEMUTimer *tx_timer; 939 } StrongARMUARTState; 940 941 static void strongarm_uart_update_status(StrongARMUARTState *s) 942 { 943 uint16_t utsr1 = 0; 944 945 if (s->tx_len != 8) { 946 utsr1 |= UTSR1_TNF; 947 } 948 949 if (s->rx_len != 0) { 950 uint16_t ent = s->rx_fifo[s->rx_start]; 951 952 utsr1 |= UTSR1_RNE; 953 if (ent & RX_FIFO_PRE) { 954 s->utsr1 |= UTSR1_PRE; 955 } 956 if (ent & RX_FIFO_FRE) { 957 s->utsr1 |= UTSR1_FRE; 958 } 959 if (ent & RX_FIFO_ROR) { 960 s->utsr1 |= UTSR1_ROR; 961 } 962 } 963 964 s->utsr1 = utsr1; 965 } 966 967 static void strongarm_uart_update_int_status(StrongARMUARTState *s) 968 { 969 uint16_t utsr0 = s->utsr0 & 970 (UTSR0_REB | UTSR0_RBB | UTSR0_RID); 971 int i; 972 973 if ((s->utcr3 & UTCR3_TXE) && 974 (s->utcr3 & UTCR3_TIE) && 975 s->tx_len <= 4) { 976 utsr0 |= UTSR0_TFS; 977 } 978 979 if ((s->utcr3 & UTCR3_RXE) && 980 (s->utcr3 & UTCR3_RIE) && 981 s->rx_len > 4) { 982 utsr0 |= UTSR0_RFS; 983 } 984 985 for (i = 0; i < s->rx_len && i < 4; i++) 986 if (s->rx_fifo[(s->rx_start + i) % 12] & ~0xff) { 987 utsr0 |= UTSR0_EIF; 988 break; 989 } 990 991 s->utsr0 = utsr0; 992 qemu_set_irq(s->irq, utsr0); 993 } 994 995 static void strongarm_uart_update_parameters(StrongARMUARTState *s) 996 { 997 int speed, parity, data_bits, stop_bits, frame_size; 998 QEMUSerialSetParams ssp; 999 1000 /* Start bit. */ 1001 frame_size = 1; 1002 if (s->utcr0 & UTCR0_PE) { 1003 /* Parity bit. */ 1004 frame_size++; 1005 if (s->utcr0 & UTCR0_OES) { 1006 parity = 'E'; 1007 } else { 1008 parity = 'O'; 1009 } 1010 } else { 1011 parity = 'N'; 1012 } 1013 if (s->utcr0 & UTCR0_SBS) { 1014 stop_bits = 2; 1015 } else { 1016 stop_bits = 1; 1017 } 1018 1019 data_bits = (s->utcr0 & UTCR0_DSS) ? 8 : 7; 1020 frame_size += data_bits + stop_bits; 1021 speed = 3686400 / 16 / (s->brd + 1); 1022 ssp.speed = speed; 1023 ssp.parity = parity; 1024 ssp.data_bits = data_bits; 1025 ssp.stop_bits = stop_bits; 1026 s->char_transmit_time = (get_ticks_per_sec() / speed) * frame_size; 1027 if (s->chr) { 1028 qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); 1029 } 1030 1031 DPRINTF(stderr, "%s speed=%d parity=%c data=%d stop=%d\n", s->chr->label, 1032 speed, parity, data_bits, stop_bits); 1033 } 1034 1035 static void strongarm_uart_rx_to(void *opaque) 1036 { 1037 StrongARMUARTState *s = opaque; 1038 1039 if (s->rx_len) { 1040 s->utsr0 |= UTSR0_RID; 1041 strongarm_uart_update_int_status(s); 1042 } 1043 } 1044 1045 static void strongarm_uart_rx_push(StrongARMUARTState *s, uint16_t c) 1046 { 1047 if ((s->utcr3 & UTCR3_RXE) == 0) { 1048 /* rx disabled */ 1049 return; 1050 } 1051 1052 if (s->wait_break_end) { 1053 s->utsr0 |= UTSR0_REB; 1054 s->wait_break_end = false; 1055 } 1056 1057 if (s->rx_len < 12) { 1058 s->rx_fifo[(s->rx_start + s->rx_len) % 12] = c; 1059 s->rx_len++; 1060 } else 1061 s->rx_fifo[(s->rx_start + 11) % 12] |= RX_FIFO_ROR; 1062 } 1063 1064 static int strongarm_uart_can_receive(void *opaque) 1065 { 1066 StrongARMUARTState *s = opaque; 1067 1068 if (s->rx_len == 12) { 1069 return 0; 1070 } 1071 /* It's best not to get more than 2/3 of RX FIFO, so advertise that much */ 1072 if (s->rx_len < 8) { 1073 return 8 - s->rx_len; 1074 } 1075 return 1; 1076 } 1077 1078 static void strongarm_uart_receive(void *opaque, const uint8_t *buf, int size) 1079 { 1080 StrongARMUARTState *s = opaque; 1081 int i; 1082 1083 for (i = 0; i < size; i++) { 1084 strongarm_uart_rx_push(s, buf[i]); 1085 } 1086 1087 /* call the timeout receive callback in 3 char transmit time */ 1088 timer_mod(s->rx_timeout_timer, 1089 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 3); 1090 1091 strongarm_uart_update_status(s); 1092 strongarm_uart_update_int_status(s); 1093 } 1094 1095 static void strongarm_uart_event(void *opaque, int event) 1096 { 1097 StrongARMUARTState *s = opaque; 1098 if (event == CHR_EVENT_BREAK) { 1099 s->utsr0 |= UTSR0_RBB; 1100 strongarm_uart_rx_push(s, RX_FIFO_FRE); 1101 s->wait_break_end = true; 1102 strongarm_uart_update_status(s); 1103 strongarm_uart_update_int_status(s); 1104 } 1105 } 1106 1107 static void strongarm_uart_tx(void *opaque) 1108 { 1109 StrongARMUARTState *s = opaque; 1110 uint64_t new_xmit_ts = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 1111 1112 if (s->utcr3 & UTCR3_LBM) /* loopback */ { 1113 strongarm_uart_receive(s, &s->tx_fifo[s->tx_start], 1); 1114 } else if (s->chr) { 1115 qemu_chr_fe_write(s->chr, &s->tx_fifo[s->tx_start], 1); 1116 } 1117 1118 s->tx_start = (s->tx_start + 1) % 8; 1119 s->tx_len--; 1120 if (s->tx_len) { 1121 timer_mod(s->tx_timer, new_xmit_ts + s->char_transmit_time); 1122 } 1123 strongarm_uart_update_status(s); 1124 strongarm_uart_update_int_status(s); 1125 } 1126 1127 static uint64_t strongarm_uart_read(void *opaque, hwaddr addr, 1128 unsigned size) 1129 { 1130 StrongARMUARTState *s = opaque; 1131 uint16_t ret; 1132 1133 switch (addr) { 1134 case UTCR0: 1135 return s->utcr0; 1136 1137 case UTCR1: 1138 return s->brd >> 8; 1139 1140 case UTCR2: 1141 return s->brd & 0xff; 1142 1143 case UTCR3: 1144 return s->utcr3; 1145 1146 case UTDR: 1147 if (s->rx_len != 0) { 1148 ret = s->rx_fifo[s->rx_start]; 1149 s->rx_start = (s->rx_start + 1) % 12; 1150 s->rx_len--; 1151 strongarm_uart_update_status(s); 1152 strongarm_uart_update_int_status(s); 1153 return ret; 1154 } 1155 return 0; 1156 1157 case UTSR0: 1158 return s->utsr0; 1159 1160 case UTSR1: 1161 return s->utsr1; 1162 1163 default: 1164 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr); 1165 return 0; 1166 } 1167 } 1168 1169 static void strongarm_uart_write(void *opaque, hwaddr addr, 1170 uint64_t value, unsigned size) 1171 { 1172 StrongARMUARTState *s = opaque; 1173 1174 switch (addr) { 1175 case UTCR0: 1176 s->utcr0 = value & 0x7f; 1177 strongarm_uart_update_parameters(s); 1178 break; 1179 1180 case UTCR1: 1181 s->brd = (s->brd & 0xff) | ((value & 0xf) << 8); 1182 strongarm_uart_update_parameters(s); 1183 break; 1184 1185 case UTCR2: 1186 s->brd = (s->brd & 0xf00) | (value & 0xff); 1187 strongarm_uart_update_parameters(s); 1188 break; 1189 1190 case UTCR3: 1191 s->utcr3 = value & 0x3f; 1192 if ((s->utcr3 & UTCR3_RXE) == 0) { 1193 s->rx_len = 0; 1194 } 1195 if ((s->utcr3 & UTCR3_TXE) == 0) { 1196 s->tx_len = 0; 1197 } 1198 strongarm_uart_update_status(s); 1199 strongarm_uart_update_int_status(s); 1200 break; 1201 1202 case UTDR: 1203 if ((s->utcr3 & UTCR3_TXE) && s->tx_len != 8) { 1204 s->tx_fifo[(s->tx_start + s->tx_len) % 8] = value; 1205 s->tx_len++; 1206 strongarm_uart_update_status(s); 1207 strongarm_uart_update_int_status(s); 1208 if (s->tx_len == 1) { 1209 strongarm_uart_tx(s); 1210 } 1211 } 1212 break; 1213 1214 case UTSR0: 1215 s->utsr0 = s->utsr0 & ~(value & 1216 (UTSR0_REB | UTSR0_RBB | UTSR0_RID)); 1217 strongarm_uart_update_int_status(s); 1218 break; 1219 1220 default: 1221 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr); 1222 } 1223 } 1224 1225 static const MemoryRegionOps strongarm_uart_ops = { 1226 .read = strongarm_uart_read, 1227 .write = strongarm_uart_write, 1228 .endianness = DEVICE_NATIVE_ENDIAN, 1229 }; 1230 1231 static int strongarm_uart_init(SysBusDevice *dev) 1232 { 1233 StrongARMUARTState *s = STRONGARM_UART(dev); 1234 1235 memory_region_init_io(&s->iomem, OBJECT(s), &strongarm_uart_ops, s, 1236 "uart", 0x10000); 1237 sysbus_init_mmio(dev, &s->iomem); 1238 sysbus_init_irq(dev, &s->irq); 1239 1240 s->rx_timeout_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, strongarm_uart_rx_to, s); 1241 s->tx_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, strongarm_uart_tx, s); 1242 1243 if (s->chr) { 1244 qemu_chr_add_handlers(s->chr, 1245 strongarm_uart_can_receive, 1246 strongarm_uart_receive, 1247 strongarm_uart_event, 1248 s); 1249 } 1250 1251 return 0; 1252 } 1253 1254 static void strongarm_uart_reset(DeviceState *dev) 1255 { 1256 StrongARMUARTState *s = STRONGARM_UART(dev); 1257 1258 s->utcr0 = UTCR0_DSS; /* 8 data, no parity */ 1259 s->brd = 23; /* 9600 */ 1260 /* enable send & recv - this actually violates spec */ 1261 s->utcr3 = UTCR3_TXE | UTCR3_RXE; 1262 1263 s->rx_len = s->tx_len = 0; 1264 1265 strongarm_uart_update_parameters(s); 1266 strongarm_uart_update_status(s); 1267 strongarm_uart_update_int_status(s); 1268 } 1269 1270 static int strongarm_uart_post_load(void *opaque, int version_id) 1271 { 1272 StrongARMUARTState *s = opaque; 1273 1274 strongarm_uart_update_parameters(s); 1275 strongarm_uart_update_status(s); 1276 strongarm_uart_update_int_status(s); 1277 1278 /* tx and restart timer */ 1279 if (s->tx_len) { 1280 strongarm_uart_tx(s); 1281 } 1282 1283 /* restart rx timeout timer */ 1284 if (s->rx_len) { 1285 timer_mod(s->rx_timeout_timer, 1286 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 3); 1287 } 1288 1289 return 0; 1290 } 1291 1292 static const VMStateDescription vmstate_strongarm_uart_regs = { 1293 .name = "strongarm-uart", 1294 .version_id = 0, 1295 .minimum_version_id = 0, 1296 .minimum_version_id_old = 0, 1297 .post_load = strongarm_uart_post_load, 1298 .fields = (VMStateField[]) { 1299 VMSTATE_UINT8(utcr0, StrongARMUARTState), 1300 VMSTATE_UINT16(brd, StrongARMUARTState), 1301 VMSTATE_UINT8(utcr3, StrongARMUARTState), 1302 VMSTATE_UINT8(utsr0, StrongARMUARTState), 1303 VMSTATE_UINT8_ARRAY(tx_fifo, StrongARMUARTState, 8), 1304 VMSTATE_UINT8(tx_start, StrongARMUARTState), 1305 VMSTATE_UINT8(tx_len, StrongARMUARTState), 1306 VMSTATE_UINT16_ARRAY(rx_fifo, StrongARMUARTState, 12), 1307 VMSTATE_UINT8(rx_start, StrongARMUARTState), 1308 VMSTATE_UINT8(rx_len, StrongARMUARTState), 1309 VMSTATE_BOOL(wait_break_end, StrongARMUARTState), 1310 VMSTATE_END_OF_LIST(), 1311 }, 1312 }; 1313 1314 static Property strongarm_uart_properties[] = { 1315 DEFINE_PROP_CHR("chardev", StrongARMUARTState, chr), 1316 DEFINE_PROP_END_OF_LIST(), 1317 }; 1318 1319 static void strongarm_uart_class_init(ObjectClass *klass, void *data) 1320 { 1321 DeviceClass *dc = DEVICE_CLASS(klass); 1322 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 1323 1324 k->init = strongarm_uart_init; 1325 dc->desc = "StrongARM UART controller"; 1326 dc->reset = strongarm_uart_reset; 1327 dc->vmsd = &vmstate_strongarm_uart_regs; 1328 dc->props = strongarm_uart_properties; 1329 } 1330 1331 static const TypeInfo strongarm_uart_info = { 1332 .name = TYPE_STRONGARM_UART, 1333 .parent = TYPE_SYS_BUS_DEVICE, 1334 .instance_size = sizeof(StrongARMUARTState), 1335 .class_init = strongarm_uart_class_init, 1336 }; 1337 1338 /* Synchronous Serial Ports */ 1339 1340 #define TYPE_STRONGARM_SSP "strongarm-ssp" 1341 #define STRONGARM_SSP(obj) \ 1342 OBJECT_CHECK(StrongARMSSPState, (obj), TYPE_STRONGARM_SSP) 1343 1344 typedef struct StrongARMSSPState { 1345 SysBusDevice parent_obj; 1346 1347 MemoryRegion iomem; 1348 qemu_irq irq; 1349 SSIBus *bus; 1350 1351 uint16_t sscr[2]; 1352 uint16_t sssr; 1353 1354 uint16_t rx_fifo[8]; 1355 uint8_t rx_level; 1356 uint8_t rx_start; 1357 } StrongARMSSPState; 1358 1359 #define SSCR0 0x60 /* SSP Control register 0 */ 1360 #define SSCR1 0x64 /* SSP Control register 1 */ 1361 #define SSDR 0x6c /* SSP Data register */ 1362 #define SSSR 0x74 /* SSP Status register */ 1363 1364 /* Bitfields for above registers */ 1365 #define SSCR0_SPI(x) (((x) & 0x30) == 0x00) 1366 #define SSCR0_SSP(x) (((x) & 0x30) == 0x10) 1367 #define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20) 1368 #define SSCR0_PSP(x) (((x) & 0x30) == 0x30) 1369 #define SSCR0_SSE (1 << 7) 1370 #define SSCR0_DSS(x) (((x) & 0xf) + 1) 1371 #define SSCR1_RIE (1 << 0) 1372 #define SSCR1_TIE (1 << 1) 1373 #define SSCR1_LBM (1 << 2) 1374 #define SSSR_TNF (1 << 2) 1375 #define SSSR_RNE (1 << 3) 1376 #define SSSR_TFS (1 << 5) 1377 #define SSSR_RFS (1 << 6) 1378 #define SSSR_ROR (1 << 7) 1379 #define SSSR_RW 0x0080 1380 1381 static void strongarm_ssp_int_update(StrongARMSSPState *s) 1382 { 1383 int level = 0; 1384 1385 level |= (s->sssr & SSSR_ROR); 1386 level |= (s->sssr & SSSR_RFS) && (s->sscr[1] & SSCR1_RIE); 1387 level |= (s->sssr & SSSR_TFS) && (s->sscr[1] & SSCR1_TIE); 1388 qemu_set_irq(s->irq, level); 1389 } 1390 1391 static void strongarm_ssp_fifo_update(StrongARMSSPState *s) 1392 { 1393 s->sssr &= ~SSSR_TFS; 1394 s->sssr &= ~SSSR_TNF; 1395 if (s->sscr[0] & SSCR0_SSE) { 1396 if (s->rx_level >= 4) { 1397 s->sssr |= SSSR_RFS; 1398 } else { 1399 s->sssr &= ~SSSR_RFS; 1400 } 1401 if (s->rx_level) { 1402 s->sssr |= SSSR_RNE; 1403 } else { 1404 s->sssr &= ~SSSR_RNE; 1405 } 1406 /* TX FIFO is never filled, so it is always in underrun 1407 condition if SSP is enabled */ 1408 s->sssr |= SSSR_TFS; 1409 s->sssr |= SSSR_TNF; 1410 } 1411 1412 strongarm_ssp_int_update(s); 1413 } 1414 1415 static uint64_t strongarm_ssp_read(void *opaque, hwaddr addr, 1416 unsigned size) 1417 { 1418 StrongARMSSPState *s = opaque; 1419 uint32_t retval; 1420 1421 switch (addr) { 1422 case SSCR0: 1423 return s->sscr[0]; 1424 case SSCR1: 1425 return s->sscr[1]; 1426 case SSSR: 1427 return s->sssr; 1428 case SSDR: 1429 if (~s->sscr[0] & SSCR0_SSE) { 1430 return 0xffffffff; 1431 } 1432 if (s->rx_level < 1) { 1433 printf("%s: SSP Rx Underrun\n", __func__); 1434 return 0xffffffff; 1435 } 1436 s->rx_level--; 1437 retval = s->rx_fifo[s->rx_start++]; 1438 s->rx_start &= 0x7; 1439 strongarm_ssp_fifo_update(s); 1440 return retval; 1441 default: 1442 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr); 1443 break; 1444 } 1445 return 0; 1446 } 1447 1448 static void strongarm_ssp_write(void *opaque, hwaddr addr, 1449 uint64_t value, unsigned size) 1450 { 1451 StrongARMSSPState *s = opaque; 1452 1453 switch (addr) { 1454 case SSCR0: 1455 s->sscr[0] = value & 0xffbf; 1456 if ((s->sscr[0] & SSCR0_SSE) && SSCR0_DSS(value) < 4) { 1457 printf("%s: Wrong data size: %i bits\n", __func__, 1458 (int)SSCR0_DSS(value)); 1459 } 1460 if (!(value & SSCR0_SSE)) { 1461 s->sssr = 0; 1462 s->rx_level = 0; 1463 } 1464 strongarm_ssp_fifo_update(s); 1465 break; 1466 1467 case SSCR1: 1468 s->sscr[1] = value & 0x2f; 1469 if (value & SSCR1_LBM) { 1470 printf("%s: Attempt to use SSP LBM mode\n", __func__); 1471 } 1472 strongarm_ssp_fifo_update(s); 1473 break; 1474 1475 case SSSR: 1476 s->sssr &= ~(value & SSSR_RW); 1477 strongarm_ssp_int_update(s); 1478 break; 1479 1480 case SSDR: 1481 if (SSCR0_UWIRE(s->sscr[0])) { 1482 value &= 0xff; 1483 } else 1484 /* Note how 32bits overflow does no harm here */ 1485 value &= (1 << SSCR0_DSS(s->sscr[0])) - 1; 1486 1487 /* Data goes from here to the Tx FIFO and is shifted out from 1488 * there directly to the slave, no need to buffer it. 1489 */ 1490 if (s->sscr[0] & SSCR0_SSE) { 1491 uint32_t readval; 1492 if (s->sscr[1] & SSCR1_LBM) { 1493 readval = value; 1494 } else { 1495 readval = ssi_transfer(s->bus, value); 1496 } 1497 1498 if (s->rx_level < 0x08) { 1499 s->rx_fifo[(s->rx_start + s->rx_level++) & 0x7] = readval; 1500 } else { 1501 s->sssr |= SSSR_ROR; 1502 } 1503 } 1504 strongarm_ssp_fifo_update(s); 1505 break; 1506 1507 default: 1508 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr); 1509 break; 1510 } 1511 } 1512 1513 static const MemoryRegionOps strongarm_ssp_ops = { 1514 .read = strongarm_ssp_read, 1515 .write = strongarm_ssp_write, 1516 .endianness = DEVICE_NATIVE_ENDIAN, 1517 }; 1518 1519 static int strongarm_ssp_post_load(void *opaque, int version_id) 1520 { 1521 StrongARMSSPState *s = opaque; 1522 1523 strongarm_ssp_fifo_update(s); 1524 1525 return 0; 1526 } 1527 1528 static int strongarm_ssp_init(SysBusDevice *sbd) 1529 { 1530 DeviceState *dev = DEVICE(sbd); 1531 StrongARMSSPState *s = STRONGARM_SSP(dev); 1532 1533 sysbus_init_irq(sbd, &s->irq); 1534 1535 memory_region_init_io(&s->iomem, OBJECT(s), &strongarm_ssp_ops, s, 1536 "ssp", 0x1000); 1537 sysbus_init_mmio(sbd, &s->iomem); 1538 1539 s->bus = ssi_create_bus(dev, "ssi"); 1540 return 0; 1541 } 1542 1543 static void strongarm_ssp_reset(DeviceState *dev) 1544 { 1545 StrongARMSSPState *s = STRONGARM_SSP(dev); 1546 1547 s->sssr = 0x03; /* 3 bit data, SPI, disabled */ 1548 s->rx_start = 0; 1549 s->rx_level = 0; 1550 } 1551 1552 static const VMStateDescription vmstate_strongarm_ssp_regs = { 1553 .name = "strongarm-ssp", 1554 .version_id = 0, 1555 .minimum_version_id = 0, 1556 .minimum_version_id_old = 0, 1557 .post_load = strongarm_ssp_post_load, 1558 .fields = (VMStateField[]) { 1559 VMSTATE_UINT16_ARRAY(sscr, StrongARMSSPState, 2), 1560 VMSTATE_UINT16(sssr, StrongARMSSPState), 1561 VMSTATE_UINT16_ARRAY(rx_fifo, StrongARMSSPState, 8), 1562 VMSTATE_UINT8(rx_start, StrongARMSSPState), 1563 VMSTATE_UINT8(rx_level, StrongARMSSPState), 1564 VMSTATE_END_OF_LIST(), 1565 }, 1566 }; 1567 1568 static void strongarm_ssp_class_init(ObjectClass *klass, void *data) 1569 { 1570 DeviceClass *dc = DEVICE_CLASS(klass); 1571 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 1572 1573 k->init = strongarm_ssp_init; 1574 dc->desc = "StrongARM SSP controller"; 1575 dc->reset = strongarm_ssp_reset; 1576 dc->vmsd = &vmstate_strongarm_ssp_regs; 1577 } 1578 1579 static const TypeInfo strongarm_ssp_info = { 1580 .name = TYPE_STRONGARM_SSP, 1581 .parent = TYPE_SYS_BUS_DEVICE, 1582 .instance_size = sizeof(StrongARMSSPState), 1583 .class_init = strongarm_ssp_class_init, 1584 }; 1585 1586 /* Main CPU functions */ 1587 StrongARMState *sa1110_init(MemoryRegion *sysmem, 1588 unsigned int sdram_size, const char *rev) 1589 { 1590 StrongARMState *s; 1591 int i; 1592 1593 s = g_malloc0(sizeof(StrongARMState)); 1594 1595 if (!rev) { 1596 rev = "sa1110-b5"; 1597 } 1598 1599 if (strncmp(rev, "sa1110", 6)) { 1600 error_report("Machine requires a SA1110 processor."); 1601 exit(1); 1602 } 1603 1604 s->cpu = cpu_arm_init(rev); 1605 1606 if (!s->cpu) { 1607 error_report("Unable to find CPU definition"); 1608 exit(1); 1609 } 1610 1611 memory_region_init_ram(&s->sdram, NULL, "strongarm.sdram", sdram_size); 1612 vmstate_register_ram_global(&s->sdram); 1613 memory_region_add_subregion(sysmem, SA_SDCS0, &s->sdram); 1614 1615 s->pic = sysbus_create_varargs("strongarm_pic", 0x90050000, 1616 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ), 1617 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_FIQ), 1618 NULL); 1619 1620 sysbus_create_varargs("pxa25x-timer", 0x90000000, 1621 qdev_get_gpio_in(s->pic, SA_PIC_OSTC0), 1622 qdev_get_gpio_in(s->pic, SA_PIC_OSTC1), 1623 qdev_get_gpio_in(s->pic, SA_PIC_OSTC2), 1624 qdev_get_gpio_in(s->pic, SA_PIC_OSTC3), 1625 NULL); 1626 1627 sysbus_create_simple(TYPE_STRONGARM_RTC, 0x90010000, 1628 qdev_get_gpio_in(s->pic, SA_PIC_RTC_ALARM)); 1629 1630 s->gpio = strongarm_gpio_init(0x90040000, s->pic); 1631 1632 s->ppc = sysbus_create_varargs(TYPE_STRONGARM_PPC, 0x90060000, NULL); 1633 1634 for (i = 0; sa_serial[i].io_base; i++) { 1635 DeviceState *dev = qdev_create(NULL, TYPE_STRONGARM_UART); 1636 qdev_prop_set_chr(dev, "chardev", serial_hds[i]); 1637 qdev_init_nofail(dev); 1638 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 1639 sa_serial[i].io_base); 1640 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, 1641 qdev_get_gpio_in(s->pic, sa_serial[i].irq)); 1642 } 1643 1644 s->ssp = sysbus_create_varargs(TYPE_STRONGARM_SSP, 0x80070000, 1645 qdev_get_gpio_in(s->pic, SA_PIC_SSP), NULL); 1646 s->ssp_bus = (SSIBus *)qdev_get_child_bus(s->ssp, "ssi"); 1647 1648 return s; 1649 } 1650 1651 static void strongarm_register_types(void) 1652 { 1653 type_register_static(&strongarm_pic_info); 1654 type_register_static(&strongarm_rtc_sysbus_info); 1655 type_register_static(&strongarm_gpio_info); 1656 type_register_static(&strongarm_ppc_info); 1657 type_register_static(&strongarm_uart_info); 1658 type_register_static(&strongarm_ssp_info); 1659 } 1660 1661 type_init(strongarm_register_types) 1662