1 /* 2 * STM32F205 SoC 3 * 4 * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qapi/error.h" 27 #include "hw/arm/arm.h" 28 #include "exec/address-spaces.h" 29 #include "hw/arm/stm32f205_soc.h" 30 31 /* At the moment only Timer 2 to 5 are modelled */ 32 static const uint32_t timer_addr[STM_NUM_TIMERS] = { 0x40000000, 0x40000400, 33 0x40000800, 0x40000C00 }; 34 static const uint32_t usart_addr[STM_NUM_USARTS] = { 0x40011000, 0x40004400, 35 0x40004800, 0x40004C00, 0x40005000, 0x40011400 }; 36 37 static const int timer_irq[STM_NUM_TIMERS] = {28, 29, 30, 50}; 38 static const int usart_irq[STM_NUM_USARTS] = {37, 38, 39, 52, 53, 71}; 39 40 static void stm32f205_soc_initfn(Object *obj) 41 { 42 STM32F205State *s = STM32F205_SOC(obj); 43 int i; 44 45 object_initialize(&s->syscfg, sizeof(s->syscfg), TYPE_STM32F2XX_SYSCFG); 46 qdev_set_parent_bus(DEVICE(&s->syscfg), sysbus_get_default()); 47 48 for (i = 0; i < STM_NUM_USARTS; i++) { 49 object_initialize(&s->usart[i], sizeof(s->usart[i]), 50 TYPE_STM32F2XX_USART); 51 qdev_set_parent_bus(DEVICE(&s->usart[i]), sysbus_get_default()); 52 } 53 54 for (i = 0; i < STM_NUM_TIMERS; i++) { 55 object_initialize(&s->timer[i], sizeof(s->timer[i]), 56 TYPE_STM32F2XX_TIMER); 57 qdev_set_parent_bus(DEVICE(&s->timer[i]), sysbus_get_default()); 58 } 59 } 60 61 static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp) 62 { 63 STM32F205State *s = STM32F205_SOC(dev_soc); 64 DeviceState *syscfgdev, *usartdev, *timerdev, *nvic; 65 SysBusDevice *syscfgbusdev, *usartbusdev, *timerbusdev; 66 Error *err = NULL; 67 int i; 68 69 MemoryRegion *system_memory = get_system_memory(); 70 MemoryRegion *sram = g_new(MemoryRegion, 1); 71 MemoryRegion *flash = g_new(MemoryRegion, 1); 72 MemoryRegion *flash_alias = g_new(MemoryRegion, 1); 73 74 memory_region_init_ram(flash, NULL, "STM32F205.flash", FLASH_SIZE, 75 &error_fatal); 76 memory_region_init_alias(flash_alias, NULL, "STM32F205.flash.alias", 77 flash, 0, FLASH_SIZE); 78 79 vmstate_register_ram_global(flash); 80 81 memory_region_set_readonly(flash, true); 82 memory_region_set_readonly(flash_alias, true); 83 84 memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, flash); 85 memory_region_add_subregion(system_memory, 0, flash_alias); 86 87 memory_region_init_ram(sram, NULL, "STM32F205.sram", SRAM_SIZE, 88 &error_fatal); 89 vmstate_register_ram_global(sram); 90 memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram); 91 92 nvic = armv7m_init(get_system_memory(), FLASH_SIZE, 96, 93 s->kernel_filename, s->cpu_model); 94 95 /* System configuration controller */ 96 syscfgdev = DEVICE(&s->syscfg); 97 object_property_set_bool(OBJECT(&s->syscfg), true, "realized", &err); 98 if (err != NULL) { 99 error_propagate(errp, err); 100 return; 101 } 102 syscfgbusdev = SYS_BUS_DEVICE(syscfgdev); 103 sysbus_mmio_map(syscfgbusdev, 0, 0x40013800); 104 sysbus_connect_irq(syscfgbusdev, 0, qdev_get_gpio_in(nvic, 71)); 105 106 /* Attach UART (uses USART registers) and USART controllers */ 107 for (i = 0; i < STM_NUM_USARTS; i++) { 108 usartdev = DEVICE(&(s->usart[i])); 109 object_property_set_bool(OBJECT(&s->usart[i]), true, "realized", &err); 110 if (err != NULL) { 111 error_propagate(errp, err); 112 return; 113 } 114 usartbusdev = SYS_BUS_DEVICE(usartdev); 115 sysbus_mmio_map(usartbusdev, 0, usart_addr[i]); 116 sysbus_connect_irq(usartbusdev, 0, 117 qdev_get_gpio_in(nvic, usart_irq[i])); 118 } 119 120 /* Timer 2 to 5 */ 121 for (i = 0; i < STM_NUM_TIMERS; i++) { 122 timerdev = DEVICE(&(s->timer[i])); 123 qdev_prop_set_uint64(timerdev, "clock-frequency", 1000000000); 124 object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err); 125 if (err != NULL) { 126 error_propagate(errp, err); 127 return; 128 } 129 timerbusdev = SYS_BUS_DEVICE(timerdev); 130 sysbus_mmio_map(timerbusdev, 0, timer_addr[i]); 131 sysbus_connect_irq(timerbusdev, 0, 132 qdev_get_gpio_in(nvic, timer_irq[i])); 133 } 134 } 135 136 static Property stm32f205_soc_properties[] = { 137 DEFINE_PROP_STRING("kernel-filename", STM32F205State, kernel_filename), 138 DEFINE_PROP_STRING("cpu-model", STM32F205State, cpu_model), 139 DEFINE_PROP_END_OF_LIST(), 140 }; 141 142 static void stm32f205_soc_class_init(ObjectClass *klass, void *data) 143 { 144 DeviceClass *dc = DEVICE_CLASS(klass); 145 146 dc->realize = stm32f205_soc_realize; 147 dc->props = stm32f205_soc_properties; 148 } 149 150 static const TypeInfo stm32f205_soc_info = { 151 .name = TYPE_STM32F205_SOC, 152 .parent = TYPE_SYS_BUS_DEVICE, 153 .instance_size = sizeof(STM32F205State), 154 .instance_init = stm32f205_soc_initfn, 155 .class_init = stm32f205_soc_class_init, 156 }; 157 158 static void stm32f205_soc_types(void) 159 { 160 type_register_static(&stm32f205_soc_info); 161 } 162 163 type_init(stm32f205_soc_types) 164