xref: /openbmc/qemu/hw/arm/stm32f205_soc.c (revision b14df228)
1 /*
2  * STM32F205 SoC
3  *
4  * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a copy
7  * of this software and associated documentation files (the "Software"), to deal
8  * in the Software without restriction, including without limitation the rights
9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10  * copies of the Software, and to permit persons to whom the Software is
11  * furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22  * THE SOFTWARE.
23  */
24 
25 #include "qemu/osdep.h"
26 #include "qapi/error.h"
27 #include "qemu/module.h"
28 #include "hw/arm/boot.h"
29 #include "exec/address-spaces.h"
30 #include "hw/arm/stm32f205_soc.h"
31 #include "hw/qdev-properties.h"
32 #include "hw/qdev-clock.h"
33 #include "sysemu/sysemu.h"
34 
35 /* At the moment only Timer 2 to 5 are modelled */
36 static const uint32_t timer_addr[STM_NUM_TIMERS] = { 0x40000000, 0x40000400,
37     0x40000800, 0x40000C00 };
38 static const uint32_t usart_addr[STM_NUM_USARTS] = { 0x40011000, 0x40004400,
39     0x40004800, 0x40004C00, 0x40005000, 0x40011400 };
40 static const uint32_t adc_addr[STM_NUM_ADCS] = { 0x40012000, 0x40012100,
41     0x40012200 };
42 static const uint32_t spi_addr[STM_NUM_SPIS] = { 0x40013000, 0x40003800,
43     0x40003C00 };
44 
45 static const int timer_irq[STM_NUM_TIMERS] = {28, 29, 30, 50};
46 static const int usart_irq[STM_NUM_USARTS] = {37, 38, 39, 52, 53, 71};
47 #define ADC_IRQ 18
48 static const int spi_irq[STM_NUM_SPIS] = {35, 36, 51};
49 
50 static void stm32f205_soc_initfn(Object *obj)
51 {
52     STM32F205State *s = STM32F205_SOC(obj);
53     int i;
54 
55     object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M);
56 
57     object_initialize_child(obj, "syscfg", &s->syscfg, TYPE_STM32F2XX_SYSCFG);
58 
59     for (i = 0; i < STM_NUM_USARTS; i++) {
60         object_initialize_child(obj, "usart[*]", &s->usart[i],
61                                 TYPE_STM32F2XX_USART);
62     }
63 
64     for (i = 0; i < STM_NUM_TIMERS; i++) {
65         object_initialize_child(obj, "timer[*]", &s->timer[i],
66                                 TYPE_STM32F2XX_TIMER);
67     }
68 
69     s->adc_irqs = OR_IRQ(object_new(TYPE_OR_IRQ));
70 
71     for (i = 0; i < STM_NUM_ADCS; i++) {
72         object_initialize_child(obj, "adc[*]", &s->adc[i], TYPE_STM32F2XX_ADC);
73     }
74 
75     for (i = 0; i < STM_NUM_SPIS; i++) {
76         object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_STM32F2XX_SPI);
77     }
78 
79     s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
80     s->refclk = qdev_init_clock_in(DEVICE(s), "refclk", NULL, NULL, 0);
81 }
82 
83 static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
84 {
85     STM32F205State *s = STM32F205_SOC(dev_soc);
86     DeviceState *dev, *armv7m;
87     SysBusDevice *busdev;
88     int i;
89 
90     MemoryRegion *system_memory = get_system_memory();
91 
92     /*
93      * We use s->refclk internally and only define it with qdev_init_clock_in()
94      * so it is correctly parented and not leaked on an init/deinit; it is not
95      * intended as an externally exposed clock.
96      */
97     if (clock_has_source(s->refclk)) {
98         error_setg(errp, "refclk clock must not be wired up by the board code");
99         return;
100     }
101 
102     if (!clock_has_source(s->sysclk)) {
103         error_setg(errp, "sysclk clock must be wired up by the board code");
104         return;
105     }
106 
107     /*
108      * TODO: ideally we should model the SoC RCC and its ability to
109      * change the sysclk frequency and define different sysclk sources.
110      */
111 
112     /* The refclk always runs at frequency HCLK / 8 */
113     clock_set_mul_div(s->refclk, 8, 1);
114     clock_set_source(s->refclk, s->sysclk);
115 
116     memory_region_init_rom(&s->flash, OBJECT(dev_soc), "STM32F205.flash",
117                            FLASH_SIZE, &error_fatal);
118     memory_region_init_alias(&s->flash_alias, OBJECT(dev_soc),
119                              "STM32F205.flash.alias", &s->flash, 0, FLASH_SIZE);
120 
121     memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, &s->flash);
122     memory_region_add_subregion(system_memory, 0, &s->flash_alias);
123 
124     memory_region_init_ram(&s->sram, NULL, "STM32F205.sram", SRAM_SIZE,
125                            &error_fatal);
126     memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, &s->sram);
127 
128     armv7m = DEVICE(&s->armv7m);
129     qdev_prop_set_uint32(armv7m, "num-irq", 96);
130     qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
131     qdev_prop_set_bit(armv7m, "enable-bitband", true);
132     qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
133     qdev_connect_clock_in(armv7m, "refclk", s->refclk);
134     object_property_set_link(OBJECT(&s->armv7m), "memory",
135                              OBJECT(get_system_memory()), &error_abort);
136     if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) {
137         return;
138     }
139 
140     /* System configuration controller */
141     dev = DEVICE(&s->syscfg);
142     if (!sysbus_realize(SYS_BUS_DEVICE(&s->syscfg), errp)) {
143         return;
144     }
145     busdev = SYS_BUS_DEVICE(dev);
146     sysbus_mmio_map(busdev, 0, 0x40013800);
147 
148     /* Attach UART (uses USART registers) and USART controllers */
149     for (i = 0; i < STM_NUM_USARTS; i++) {
150         dev = DEVICE(&(s->usart[i]));
151         qdev_prop_set_chr(dev, "chardev", serial_hd(i));
152         if (!sysbus_realize(SYS_BUS_DEVICE(&s->usart[i]), errp)) {
153             return;
154         }
155         busdev = SYS_BUS_DEVICE(dev);
156         sysbus_mmio_map(busdev, 0, usart_addr[i]);
157         sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i]));
158     }
159 
160     /* Timer 2 to 5 */
161     for (i = 0; i < STM_NUM_TIMERS; i++) {
162         dev = DEVICE(&(s->timer[i]));
163         qdev_prop_set_uint64(dev, "clock-frequency", 1000000000);
164         if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer[i]), errp)) {
165             return;
166         }
167         busdev = SYS_BUS_DEVICE(dev);
168         sysbus_mmio_map(busdev, 0, timer_addr[i]);
169         sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, timer_irq[i]));
170     }
171 
172     /* ADC 1 to 3 */
173     object_property_set_int(OBJECT(s->adc_irqs), "num-lines", STM_NUM_ADCS,
174                             &error_abort);
175     if (!qdev_realize(DEVICE(s->adc_irqs), NULL, errp)) {
176         return;
177     }
178     qdev_connect_gpio_out(DEVICE(s->adc_irqs), 0,
179                           qdev_get_gpio_in(armv7m, ADC_IRQ));
180 
181     for (i = 0; i < STM_NUM_ADCS; i++) {
182         dev = DEVICE(&(s->adc[i]));
183         if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc[i]), errp)) {
184             return;
185         }
186         busdev = SYS_BUS_DEVICE(dev);
187         sysbus_mmio_map(busdev, 0, adc_addr[i]);
188         sysbus_connect_irq(busdev, 0,
189                            qdev_get_gpio_in(DEVICE(s->adc_irqs), i));
190     }
191 
192     /* SPI 1 and 2 */
193     for (i = 0; i < STM_NUM_SPIS; i++) {
194         dev = DEVICE(&(s->spi[i]));
195         if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
196             return;
197         }
198         busdev = SYS_BUS_DEVICE(dev);
199         sysbus_mmio_map(busdev, 0, spi_addr[i]);
200         sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, spi_irq[i]));
201     }
202 }
203 
204 static Property stm32f205_soc_properties[] = {
205     DEFINE_PROP_STRING("cpu-type", STM32F205State, cpu_type),
206     DEFINE_PROP_END_OF_LIST(),
207 };
208 
209 static void stm32f205_soc_class_init(ObjectClass *klass, void *data)
210 {
211     DeviceClass *dc = DEVICE_CLASS(klass);
212 
213     dc->realize = stm32f205_soc_realize;
214     device_class_set_props(dc, stm32f205_soc_properties);
215 }
216 
217 static const TypeInfo stm32f205_soc_info = {
218     .name          = TYPE_STM32F205_SOC,
219     .parent        = TYPE_SYS_BUS_DEVICE,
220     .instance_size = sizeof(STM32F205State),
221     .instance_init = stm32f205_soc_initfn,
222     .class_init    = stm32f205_soc_class_init,
223 };
224 
225 static void stm32f205_soc_types(void)
226 {
227     type_register_static(&stm32f205_soc_info);
228 }
229 
230 type_init(stm32f205_soc_types)
231