1 /* 2 * STM32F205 SoC 3 * 4 * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qapi/error.h" 27 #include "qemu/module.h" 28 #include "hw/arm/boot.h" 29 #include "exec/address-spaces.h" 30 #include "hw/arm/stm32f205_soc.h" 31 #include "hw/qdev-properties.h" 32 #include "sysemu/sysemu.h" 33 34 /* At the moment only Timer 2 to 5 are modelled */ 35 static const uint32_t timer_addr[STM_NUM_TIMERS] = { 0x40000000, 0x40000400, 36 0x40000800, 0x40000C00 }; 37 static const uint32_t usart_addr[STM_NUM_USARTS] = { 0x40011000, 0x40004400, 38 0x40004800, 0x40004C00, 0x40005000, 0x40011400 }; 39 static const uint32_t adc_addr[STM_NUM_ADCS] = { 0x40012000, 0x40012100, 40 0x40012200 }; 41 static const uint32_t spi_addr[STM_NUM_SPIS] = { 0x40013000, 0x40003800, 42 0x40003C00 }; 43 44 static const int timer_irq[STM_NUM_TIMERS] = {28, 29, 30, 50}; 45 static const int usart_irq[STM_NUM_USARTS] = {37, 38, 39, 52, 53, 71}; 46 #define ADC_IRQ 18 47 static const int spi_irq[STM_NUM_SPIS] = {35, 36, 51}; 48 49 static void stm32f205_soc_initfn(Object *obj) 50 { 51 STM32F205State *s = STM32F205_SOC(obj); 52 int i; 53 54 object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M); 55 56 object_initialize_child(obj, "syscfg", &s->syscfg, TYPE_STM32F2XX_SYSCFG); 57 58 for (i = 0; i < STM_NUM_USARTS; i++) { 59 object_initialize_child(obj, "usart[*]", &s->usart[i], 60 TYPE_STM32F2XX_USART); 61 } 62 63 for (i = 0; i < STM_NUM_TIMERS; i++) { 64 object_initialize_child(obj, "timer[*]", &s->timer[i], 65 TYPE_STM32F2XX_TIMER); 66 } 67 68 s->adc_irqs = OR_IRQ(object_new(TYPE_OR_IRQ)); 69 70 for (i = 0; i < STM_NUM_ADCS; i++) { 71 object_initialize_child(obj, "adc[*]", &s->adc[i], TYPE_STM32F2XX_ADC); 72 } 73 74 for (i = 0; i < STM_NUM_SPIS; i++) { 75 object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_STM32F2XX_SPI); 76 } 77 } 78 79 static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp) 80 { 81 STM32F205State *s = STM32F205_SOC(dev_soc); 82 DeviceState *dev, *armv7m; 83 SysBusDevice *busdev; 84 int i; 85 86 MemoryRegion *system_memory = get_system_memory(); 87 MemoryRegion *sram = g_new(MemoryRegion, 1); 88 MemoryRegion *flash = g_new(MemoryRegion, 1); 89 MemoryRegion *flash_alias = g_new(MemoryRegion, 1); 90 91 memory_region_init_rom(flash, OBJECT(dev_soc), "STM32F205.flash", 92 FLASH_SIZE, &error_fatal); 93 memory_region_init_alias(flash_alias, OBJECT(dev_soc), 94 "STM32F205.flash.alias", flash, 0, FLASH_SIZE); 95 96 memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, flash); 97 memory_region_add_subregion(system_memory, 0, flash_alias); 98 99 memory_region_init_ram(sram, NULL, "STM32F205.sram", SRAM_SIZE, 100 &error_fatal); 101 memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram); 102 103 armv7m = DEVICE(&s->armv7m); 104 qdev_prop_set_uint32(armv7m, "num-irq", 96); 105 qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type); 106 qdev_prop_set_bit(armv7m, "enable-bitband", true); 107 object_property_set_link(OBJECT(&s->armv7m), "memory", 108 OBJECT(get_system_memory()), &error_abort); 109 if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) { 110 return; 111 } 112 113 /* System configuration controller */ 114 dev = DEVICE(&s->syscfg); 115 if (!sysbus_realize(SYS_BUS_DEVICE(&s->syscfg), errp)) { 116 return; 117 } 118 busdev = SYS_BUS_DEVICE(dev); 119 sysbus_mmio_map(busdev, 0, 0x40013800); 120 121 /* Attach UART (uses USART registers) and USART controllers */ 122 for (i = 0; i < STM_NUM_USARTS; i++) { 123 dev = DEVICE(&(s->usart[i])); 124 qdev_prop_set_chr(dev, "chardev", serial_hd(i)); 125 if (!sysbus_realize(SYS_BUS_DEVICE(&s->usart[i]), errp)) { 126 return; 127 } 128 busdev = SYS_BUS_DEVICE(dev); 129 sysbus_mmio_map(busdev, 0, usart_addr[i]); 130 sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i])); 131 } 132 133 /* Timer 2 to 5 */ 134 for (i = 0; i < STM_NUM_TIMERS; i++) { 135 dev = DEVICE(&(s->timer[i])); 136 qdev_prop_set_uint64(dev, "clock-frequency", 1000000000); 137 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer[i]), errp)) { 138 return; 139 } 140 busdev = SYS_BUS_DEVICE(dev); 141 sysbus_mmio_map(busdev, 0, timer_addr[i]); 142 sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, timer_irq[i])); 143 } 144 145 /* ADC 1 to 3 */ 146 object_property_set_int(OBJECT(s->adc_irqs), "num-lines", STM_NUM_ADCS, 147 &error_abort); 148 if (!qdev_realize(DEVICE(s->adc_irqs), NULL, errp)) { 149 return; 150 } 151 qdev_connect_gpio_out(DEVICE(s->adc_irqs), 0, 152 qdev_get_gpio_in(armv7m, ADC_IRQ)); 153 154 for (i = 0; i < STM_NUM_ADCS; i++) { 155 dev = DEVICE(&(s->adc[i])); 156 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc[i]), errp)) { 157 return; 158 } 159 busdev = SYS_BUS_DEVICE(dev); 160 sysbus_mmio_map(busdev, 0, adc_addr[i]); 161 sysbus_connect_irq(busdev, 0, 162 qdev_get_gpio_in(DEVICE(s->adc_irqs), i)); 163 } 164 165 /* SPI 1 and 2 */ 166 for (i = 0; i < STM_NUM_SPIS; i++) { 167 dev = DEVICE(&(s->spi[i])); 168 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { 169 return; 170 } 171 busdev = SYS_BUS_DEVICE(dev); 172 sysbus_mmio_map(busdev, 0, spi_addr[i]); 173 sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, spi_irq[i])); 174 } 175 } 176 177 static Property stm32f205_soc_properties[] = { 178 DEFINE_PROP_STRING("cpu-type", STM32F205State, cpu_type), 179 DEFINE_PROP_END_OF_LIST(), 180 }; 181 182 static void stm32f205_soc_class_init(ObjectClass *klass, void *data) 183 { 184 DeviceClass *dc = DEVICE_CLASS(klass); 185 186 dc->realize = stm32f205_soc_realize; 187 device_class_set_props(dc, stm32f205_soc_properties); 188 } 189 190 static const TypeInfo stm32f205_soc_info = { 191 .name = TYPE_STM32F205_SOC, 192 .parent = TYPE_SYS_BUS_DEVICE, 193 .instance_size = sizeof(STM32F205State), 194 .instance_init = stm32f205_soc_initfn, 195 .class_init = stm32f205_soc_class_init, 196 }; 197 198 static void stm32f205_soc_types(void) 199 { 200 type_register_static(&stm32f205_soc_info); 201 } 202 203 type_init(stm32f205_soc_types) 204