1 /* 2 * STM32F205 SoC 3 * 4 * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qapi/error.h" 27 #include "qemu/module.h" 28 #include "hw/arm/boot.h" 29 #include "exec/address-spaces.h" 30 #include "hw/arm/stm32f205_soc.h" 31 #include "hw/qdev-properties.h" 32 #include "sysemu/sysemu.h" 33 34 /* At the moment only Timer 2 to 5 are modelled */ 35 static const uint32_t timer_addr[STM_NUM_TIMERS] = { 0x40000000, 0x40000400, 36 0x40000800, 0x40000C00 }; 37 static const uint32_t usart_addr[STM_NUM_USARTS] = { 0x40011000, 0x40004400, 38 0x40004800, 0x40004C00, 0x40005000, 0x40011400 }; 39 static const uint32_t adc_addr[STM_NUM_ADCS] = { 0x40012000, 0x40012100, 40 0x40012200 }; 41 static const uint32_t spi_addr[STM_NUM_SPIS] = { 0x40013000, 0x40003800, 42 0x40003C00 }; 43 44 static const int timer_irq[STM_NUM_TIMERS] = {28, 29, 30, 50}; 45 static const int usart_irq[STM_NUM_USARTS] = {37, 38, 39, 52, 53, 71}; 46 #define ADC_IRQ 18 47 static const int spi_irq[STM_NUM_SPIS] = {35, 36, 51}; 48 49 static void stm32f205_soc_initfn(Object *obj) 50 { 51 STM32F205State *s = STM32F205_SOC(obj); 52 int i; 53 54 sysbus_init_child_obj(obj, "armv7m", &s->armv7m, sizeof(s->armv7m), 55 TYPE_ARMV7M); 56 57 sysbus_init_child_obj(obj, "syscfg", &s->syscfg, sizeof(s->syscfg), 58 TYPE_STM32F2XX_SYSCFG); 59 60 for (i = 0; i < STM_NUM_USARTS; i++) { 61 sysbus_init_child_obj(obj, "usart[*]", &s->usart[i], 62 sizeof(s->usart[i]), TYPE_STM32F2XX_USART); 63 } 64 65 for (i = 0; i < STM_NUM_TIMERS; i++) { 66 sysbus_init_child_obj(obj, "timer[*]", &s->timer[i], 67 sizeof(s->timer[i]), TYPE_STM32F2XX_TIMER); 68 } 69 70 s->adc_irqs = OR_IRQ(object_new(TYPE_OR_IRQ)); 71 72 for (i = 0; i < STM_NUM_ADCS; i++) { 73 sysbus_init_child_obj(obj, "adc[*]", &s->adc[i], sizeof(s->adc[i]), 74 TYPE_STM32F2XX_ADC); 75 } 76 77 for (i = 0; i < STM_NUM_SPIS; i++) { 78 sysbus_init_child_obj(obj, "spi[*]", &s->spi[i], sizeof(s->spi[i]), 79 TYPE_STM32F2XX_SPI); 80 } 81 } 82 83 static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp) 84 { 85 STM32F205State *s = STM32F205_SOC(dev_soc); 86 DeviceState *dev, *armv7m; 87 SysBusDevice *busdev; 88 Error *err = NULL; 89 int i; 90 91 MemoryRegion *system_memory = get_system_memory(); 92 MemoryRegion *sram = g_new(MemoryRegion, 1); 93 MemoryRegion *flash = g_new(MemoryRegion, 1); 94 MemoryRegion *flash_alias = g_new(MemoryRegion, 1); 95 96 memory_region_init_ram(flash, NULL, "STM32F205.flash", FLASH_SIZE, 97 &error_fatal); 98 memory_region_init_alias(flash_alias, NULL, "STM32F205.flash.alias", 99 flash, 0, FLASH_SIZE); 100 101 memory_region_set_readonly(flash, true); 102 memory_region_set_readonly(flash_alias, true); 103 104 memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, flash); 105 memory_region_add_subregion(system_memory, 0, flash_alias); 106 107 memory_region_init_ram(sram, NULL, "STM32F205.sram", SRAM_SIZE, 108 &error_fatal); 109 memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram); 110 111 armv7m = DEVICE(&s->armv7m); 112 qdev_prop_set_uint32(armv7m, "num-irq", 96); 113 qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type); 114 qdev_prop_set_bit(armv7m, "enable-bitband", true); 115 object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()), 116 "memory", &error_abort); 117 object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err); 118 if (err != NULL) { 119 error_propagate(errp, err); 120 return; 121 } 122 123 /* System configuration controller */ 124 dev = DEVICE(&s->syscfg); 125 object_property_set_bool(OBJECT(&s->syscfg), true, "realized", &err); 126 if (err != NULL) { 127 error_propagate(errp, err); 128 return; 129 } 130 busdev = SYS_BUS_DEVICE(dev); 131 sysbus_mmio_map(busdev, 0, 0x40013800); 132 sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, 71)); 133 134 /* Attach UART (uses USART registers) and USART controllers */ 135 for (i = 0; i < STM_NUM_USARTS; i++) { 136 dev = DEVICE(&(s->usart[i])); 137 qdev_prop_set_chr(dev, "chardev", serial_hd(i)); 138 object_property_set_bool(OBJECT(&s->usart[i]), true, "realized", &err); 139 if (err != NULL) { 140 error_propagate(errp, err); 141 return; 142 } 143 busdev = SYS_BUS_DEVICE(dev); 144 sysbus_mmio_map(busdev, 0, usart_addr[i]); 145 sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i])); 146 } 147 148 /* Timer 2 to 5 */ 149 for (i = 0; i < STM_NUM_TIMERS; i++) { 150 dev = DEVICE(&(s->timer[i])); 151 qdev_prop_set_uint64(dev, "clock-frequency", 1000000000); 152 object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err); 153 if (err != NULL) { 154 error_propagate(errp, err); 155 return; 156 } 157 busdev = SYS_BUS_DEVICE(dev); 158 sysbus_mmio_map(busdev, 0, timer_addr[i]); 159 sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, timer_irq[i])); 160 } 161 162 /* ADC 1 to 3 */ 163 object_property_set_int(OBJECT(s->adc_irqs), STM_NUM_ADCS, 164 "num-lines", &err); 165 object_property_set_bool(OBJECT(s->adc_irqs), true, "realized", &err); 166 if (err != NULL) { 167 error_propagate(errp, err); 168 return; 169 } 170 qdev_connect_gpio_out(DEVICE(s->adc_irqs), 0, 171 qdev_get_gpio_in(armv7m, ADC_IRQ)); 172 173 for (i = 0; i < STM_NUM_ADCS; i++) { 174 dev = DEVICE(&(s->adc[i])); 175 object_property_set_bool(OBJECT(&s->adc[i]), true, "realized", &err); 176 if (err != NULL) { 177 error_propagate(errp, err); 178 return; 179 } 180 busdev = SYS_BUS_DEVICE(dev); 181 sysbus_mmio_map(busdev, 0, adc_addr[i]); 182 sysbus_connect_irq(busdev, 0, 183 qdev_get_gpio_in(DEVICE(s->adc_irqs), i)); 184 } 185 186 /* SPI 1 and 2 */ 187 for (i = 0; i < STM_NUM_SPIS; i++) { 188 dev = DEVICE(&(s->spi[i])); 189 object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err); 190 if (err != NULL) { 191 error_propagate(errp, err); 192 return; 193 } 194 busdev = SYS_BUS_DEVICE(dev); 195 sysbus_mmio_map(busdev, 0, spi_addr[i]); 196 sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, spi_irq[i])); 197 } 198 } 199 200 static Property stm32f205_soc_properties[] = { 201 DEFINE_PROP_STRING("cpu-type", STM32F205State, cpu_type), 202 DEFINE_PROP_END_OF_LIST(), 203 }; 204 205 static void stm32f205_soc_class_init(ObjectClass *klass, void *data) 206 { 207 DeviceClass *dc = DEVICE_CLASS(klass); 208 209 dc->realize = stm32f205_soc_realize; 210 dc->props = stm32f205_soc_properties; 211 } 212 213 static const TypeInfo stm32f205_soc_info = { 214 .name = TYPE_STM32F205_SOC, 215 .parent = TYPE_SYS_BUS_DEVICE, 216 .instance_size = sizeof(STM32F205State), 217 .instance_init = stm32f205_soc_initfn, 218 .class_init = stm32f205_soc_class_init, 219 }; 220 221 static void stm32f205_soc_types(void) 222 { 223 type_register_static(&stm32f205_soc_info); 224 } 225 226 type_init(stm32f205_soc_types) 227