1 /* 2 * STM32F205 SoC 3 * 4 * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "hw/arm/arm.h" 26 #include "exec/address-spaces.h" 27 #include "hw/arm/stm32f205_soc.h" 28 29 /* At the moment only Timer 2 to 5 are modelled */ 30 static const uint32_t timer_addr[STM_NUM_TIMERS] = { 0x40000000, 0x40000400, 31 0x40000800, 0x40000C00 }; 32 static const uint32_t usart_addr[STM_NUM_USARTS] = { 0x40011000, 0x40004400, 33 0x40004800, 0x40004C00, 0x40005000, 0x40011400 }; 34 35 static const int timer_irq[STM_NUM_TIMERS] = {28, 29, 30, 50}; 36 static const int usart_irq[STM_NUM_USARTS] = {37, 38, 39, 52, 53, 71}; 37 38 static void stm32f205_soc_initfn(Object *obj) 39 { 40 STM32F205State *s = STM32F205_SOC(obj); 41 int i; 42 43 object_initialize(&s->syscfg, sizeof(s->syscfg), TYPE_STM32F2XX_SYSCFG); 44 qdev_set_parent_bus(DEVICE(&s->syscfg), sysbus_get_default()); 45 46 for (i = 0; i < STM_NUM_USARTS; i++) { 47 object_initialize(&s->usart[i], sizeof(s->usart[i]), 48 TYPE_STM32F2XX_USART); 49 qdev_set_parent_bus(DEVICE(&s->usart[i]), sysbus_get_default()); 50 } 51 52 for (i = 0; i < STM_NUM_TIMERS; i++) { 53 object_initialize(&s->timer[i], sizeof(s->timer[i]), 54 TYPE_STM32F2XX_TIMER); 55 qdev_set_parent_bus(DEVICE(&s->timer[i]), sysbus_get_default()); 56 } 57 } 58 59 static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp) 60 { 61 STM32F205State *s = STM32F205_SOC(dev_soc); 62 DeviceState *syscfgdev, *usartdev, *timerdev, *nvic; 63 SysBusDevice *syscfgbusdev, *usartbusdev, *timerbusdev; 64 Error *err = NULL; 65 int i; 66 67 MemoryRegion *system_memory = get_system_memory(); 68 MemoryRegion *sram = g_new(MemoryRegion, 1); 69 MemoryRegion *flash = g_new(MemoryRegion, 1); 70 MemoryRegion *flash_alias = g_new(MemoryRegion, 1); 71 72 memory_region_init_ram(flash, NULL, "STM32F205.flash", FLASH_SIZE, 73 &error_fatal); 74 memory_region_init_alias(flash_alias, NULL, "STM32F205.flash.alias", 75 flash, 0, FLASH_SIZE); 76 77 vmstate_register_ram_global(flash); 78 79 memory_region_set_readonly(flash, true); 80 memory_region_set_readonly(flash_alias, true); 81 82 memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, flash); 83 memory_region_add_subregion(system_memory, 0, flash_alias); 84 85 memory_region_init_ram(sram, NULL, "STM32F205.sram", SRAM_SIZE, 86 &error_fatal); 87 vmstate_register_ram_global(sram); 88 memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram); 89 90 nvic = armv7m_init(get_system_memory(), FLASH_SIZE, 96, 91 s->kernel_filename, s->cpu_model); 92 93 /* System configuration controller */ 94 syscfgdev = DEVICE(&s->syscfg); 95 object_property_set_bool(OBJECT(&s->syscfg), true, "realized", &err); 96 if (err != NULL) { 97 error_propagate(errp, err); 98 return; 99 } 100 syscfgbusdev = SYS_BUS_DEVICE(syscfgdev); 101 sysbus_mmio_map(syscfgbusdev, 0, 0x40013800); 102 sysbus_connect_irq(syscfgbusdev, 0, qdev_get_gpio_in(nvic, 71)); 103 104 /* Attach UART (uses USART registers) and USART controllers */ 105 for (i = 0; i < STM_NUM_USARTS; i++) { 106 usartdev = DEVICE(&(s->usart[i])); 107 object_property_set_bool(OBJECT(&s->usart[i]), true, "realized", &err); 108 if (err != NULL) { 109 error_propagate(errp, err); 110 return; 111 } 112 usartbusdev = SYS_BUS_DEVICE(usartdev); 113 sysbus_mmio_map(usartbusdev, 0, usart_addr[i]); 114 sysbus_connect_irq(usartbusdev, 0, 115 qdev_get_gpio_in(nvic, usart_irq[i])); 116 } 117 118 /* Timer 2 to 5 */ 119 for (i = 0; i < STM_NUM_TIMERS; i++) { 120 timerdev = DEVICE(&(s->timer[i])); 121 qdev_prop_set_uint64(timerdev, "clock-frequency", 1000000000); 122 object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err); 123 if (err != NULL) { 124 error_propagate(errp, err); 125 return; 126 } 127 timerbusdev = SYS_BUS_DEVICE(timerdev); 128 sysbus_mmio_map(timerbusdev, 0, timer_addr[i]); 129 sysbus_connect_irq(timerbusdev, 0, 130 qdev_get_gpio_in(nvic, timer_irq[i])); 131 } 132 } 133 134 static Property stm32f205_soc_properties[] = { 135 DEFINE_PROP_STRING("kernel-filename", STM32F205State, kernel_filename), 136 DEFINE_PROP_STRING("cpu-model", STM32F205State, cpu_model), 137 DEFINE_PROP_END_OF_LIST(), 138 }; 139 140 static void stm32f205_soc_class_init(ObjectClass *klass, void *data) 141 { 142 DeviceClass *dc = DEVICE_CLASS(klass); 143 144 dc->realize = stm32f205_soc_realize; 145 dc->props = stm32f205_soc_properties; 146 } 147 148 static const TypeInfo stm32f205_soc_info = { 149 .name = TYPE_STM32F205_SOC, 150 .parent = TYPE_SYS_BUS_DEVICE, 151 .instance_size = sizeof(STM32F205State), 152 .instance_init = stm32f205_soc_initfn, 153 .class_init = stm32f205_soc_class_init, 154 }; 155 156 static void stm32f205_soc_types(void) 157 { 158 type_register_static(&stm32f205_soc_info); 159 } 160 161 type_init(stm32f205_soc_types) 162