1 /* 2 * Luminary Micro Stellaris peripherals 3 * 4 * Copyright (c) 2006 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qapi/error.h" 12 #include "hw/core/split-irq.h" 13 #include "hw/sysbus.h" 14 #include "hw/sd/sd.h" 15 #include "hw/ssi/ssi.h" 16 #include "hw/arm/boot.h" 17 #include "qemu/timer.h" 18 #include "hw/i2c/i2c.h" 19 #include "net/net.h" 20 #include "hw/boards.h" 21 #include "qemu/log.h" 22 #include "exec/address-spaces.h" 23 #include "sysemu/sysemu.h" 24 #include "hw/arm/armv7m.h" 25 #include "hw/char/pl011.h" 26 #include "hw/input/stellaris_gamepad.h" 27 #include "hw/irq.h" 28 #include "hw/watchdog/cmsdk-apb-watchdog.h" 29 #include "migration/vmstate.h" 30 #include "hw/misc/unimp.h" 31 #include "hw/timer/stellaris-gptm.h" 32 #include "hw/qdev-clock.h" 33 #include "qom/object.h" 34 #include "qapi/qmp/qlist.h" 35 #include "ui/input.h" 36 37 #define GPIO_A 0 38 #define GPIO_B 1 39 #define GPIO_C 2 40 #define GPIO_D 3 41 #define GPIO_E 4 42 #define GPIO_F 5 43 #define GPIO_G 6 44 45 #define BP_OLED_I2C 0x01 46 #define BP_OLED_SSI 0x02 47 #define BP_GAMEPAD 0x04 48 49 #define NUM_IRQ_LINES 64 50 #define NUM_PRIO_BITS 3 51 52 typedef const struct { 53 const char *name; 54 uint32_t did0; 55 uint32_t did1; 56 uint32_t dc0; 57 uint32_t dc1; 58 uint32_t dc2; 59 uint32_t dc3; 60 uint32_t dc4; 61 uint32_t peripherals; 62 } stellaris_board_info; 63 64 /* System controller. */ 65 66 #define TYPE_STELLARIS_SYS "stellaris-sys" 67 OBJECT_DECLARE_SIMPLE_TYPE(ssys_state, STELLARIS_SYS) 68 69 struct ssys_state { 70 SysBusDevice parent_obj; 71 72 MemoryRegion iomem; 73 uint32_t pborctl; 74 uint32_t ldopctl; 75 uint32_t int_status; 76 uint32_t int_mask; 77 uint32_t resc; 78 uint32_t rcc; 79 uint32_t rcc2; 80 uint32_t rcgc[3]; 81 uint32_t scgc[3]; 82 uint32_t dcgc[3]; 83 uint32_t clkvclr; 84 uint32_t ldoarst; 85 qemu_irq irq; 86 Clock *sysclk; 87 /* Properties (all read-only registers) */ 88 uint32_t user0; 89 uint32_t user1; 90 uint32_t did0; 91 uint32_t did1; 92 uint32_t dc0; 93 uint32_t dc1; 94 uint32_t dc2; 95 uint32_t dc3; 96 uint32_t dc4; 97 }; 98 99 static void ssys_update(ssys_state *s) 100 { 101 qemu_set_irq(s->irq, (s->int_status & s->int_mask) != 0); 102 } 103 104 static uint32_t pllcfg_sandstorm[16] = { 105 0x31c0, /* 1 Mhz */ 106 0x1ae0, /* 1.8432 Mhz */ 107 0x18c0, /* 2 Mhz */ 108 0xd573, /* 2.4576 Mhz */ 109 0x37a6, /* 3.57954 Mhz */ 110 0x1ae2, /* 3.6864 Mhz */ 111 0x0c40, /* 4 Mhz */ 112 0x98bc, /* 4.906 Mhz */ 113 0x935b, /* 4.9152 Mhz */ 114 0x09c0, /* 5 Mhz */ 115 0x4dee, /* 5.12 Mhz */ 116 0x0c41, /* 6 Mhz */ 117 0x75db, /* 6.144 Mhz */ 118 0x1ae6, /* 7.3728 Mhz */ 119 0x0600, /* 8 Mhz */ 120 0x585b /* 8.192 Mhz */ 121 }; 122 123 static uint32_t pllcfg_fury[16] = { 124 0x3200, /* 1 Mhz */ 125 0x1b20, /* 1.8432 Mhz */ 126 0x1900, /* 2 Mhz */ 127 0xf42b, /* 2.4576 Mhz */ 128 0x37e3, /* 3.57954 Mhz */ 129 0x1b21, /* 3.6864 Mhz */ 130 0x0c80, /* 4 Mhz */ 131 0x98ee, /* 4.906 Mhz */ 132 0xd5b4, /* 4.9152 Mhz */ 133 0x0a00, /* 5 Mhz */ 134 0x4e27, /* 5.12 Mhz */ 135 0x1902, /* 6 Mhz */ 136 0xec1c, /* 6.144 Mhz */ 137 0x1b23, /* 7.3728 Mhz */ 138 0x0640, /* 8 Mhz */ 139 0xb11c /* 8.192 Mhz */ 140 }; 141 142 #define DID0_VER_MASK 0x70000000 143 #define DID0_VER_0 0x00000000 144 #define DID0_VER_1 0x10000000 145 146 #define DID0_CLASS_MASK 0x00FF0000 147 #define DID0_CLASS_SANDSTORM 0x00000000 148 #define DID0_CLASS_FURY 0x00010000 149 150 static int ssys_board_class(const ssys_state *s) 151 { 152 uint32_t did0 = s->did0; 153 switch (did0 & DID0_VER_MASK) { 154 case DID0_VER_0: 155 return DID0_CLASS_SANDSTORM; 156 case DID0_VER_1: 157 switch (did0 & DID0_CLASS_MASK) { 158 case DID0_CLASS_SANDSTORM: 159 case DID0_CLASS_FURY: 160 return did0 & DID0_CLASS_MASK; 161 } 162 /* for unknown classes, fall through */ 163 default: 164 /* This can only happen if the hardwired constant did0 value 165 * in this board's stellaris_board_info struct is wrong. 166 */ 167 g_assert_not_reached(); 168 } 169 } 170 171 static uint64_t ssys_read(void *opaque, hwaddr offset, 172 unsigned size) 173 { 174 ssys_state *s = (ssys_state *)opaque; 175 176 switch (offset) { 177 case 0x000: /* DID0 */ 178 return s->did0; 179 case 0x004: /* DID1 */ 180 return s->did1; 181 case 0x008: /* DC0 */ 182 return s->dc0; 183 case 0x010: /* DC1 */ 184 return s->dc1; 185 case 0x014: /* DC2 */ 186 return s->dc2; 187 case 0x018: /* DC3 */ 188 return s->dc3; 189 case 0x01c: /* DC4 */ 190 return s->dc4; 191 case 0x030: /* PBORCTL */ 192 return s->pborctl; 193 case 0x034: /* LDOPCTL */ 194 return s->ldopctl; 195 case 0x040: /* SRCR0 */ 196 return 0; 197 case 0x044: /* SRCR1 */ 198 return 0; 199 case 0x048: /* SRCR2 */ 200 return 0; 201 case 0x050: /* RIS */ 202 return s->int_status; 203 case 0x054: /* IMC */ 204 return s->int_mask; 205 case 0x058: /* MISC */ 206 return s->int_status & s->int_mask; 207 case 0x05c: /* RESC */ 208 return s->resc; 209 case 0x060: /* RCC */ 210 return s->rcc; 211 case 0x064: /* PLLCFG */ 212 { 213 int xtal; 214 xtal = (s->rcc >> 6) & 0xf; 215 switch (ssys_board_class(s)) { 216 case DID0_CLASS_FURY: 217 return pllcfg_fury[xtal]; 218 case DID0_CLASS_SANDSTORM: 219 return pllcfg_sandstorm[xtal]; 220 default: 221 g_assert_not_reached(); 222 } 223 } 224 case 0x070: /* RCC2 */ 225 return s->rcc2; 226 case 0x100: /* RCGC0 */ 227 return s->rcgc[0]; 228 case 0x104: /* RCGC1 */ 229 return s->rcgc[1]; 230 case 0x108: /* RCGC2 */ 231 return s->rcgc[2]; 232 case 0x110: /* SCGC0 */ 233 return s->scgc[0]; 234 case 0x114: /* SCGC1 */ 235 return s->scgc[1]; 236 case 0x118: /* SCGC2 */ 237 return s->scgc[2]; 238 case 0x120: /* DCGC0 */ 239 return s->dcgc[0]; 240 case 0x124: /* DCGC1 */ 241 return s->dcgc[1]; 242 case 0x128: /* DCGC2 */ 243 return s->dcgc[2]; 244 case 0x150: /* CLKVCLR */ 245 return s->clkvclr; 246 case 0x160: /* LDOARST */ 247 return s->ldoarst; 248 case 0x1e0: /* USER0 */ 249 return s->user0; 250 case 0x1e4: /* USER1 */ 251 return s->user1; 252 default: 253 qemu_log_mask(LOG_GUEST_ERROR, 254 "SSYS: read at bad offset 0x%x\n", (int)offset); 255 return 0; 256 } 257 } 258 259 static bool ssys_use_rcc2(ssys_state *s) 260 { 261 return (s->rcc2 >> 31) & 0x1; 262 } 263 264 /* 265 * Calculate the system clock period. We only want to propagate 266 * this change to the rest of the system if we're not being called 267 * from migration post-load. 268 */ 269 static void ssys_calculate_system_clock(ssys_state *s, bool propagate_clock) 270 { 271 int period_ns; 272 /* 273 * SYSDIV field specifies divisor: 0 == /1, 1 == /2, etc. Input 274 * clock is 200MHz, which is a period of 5 ns. Dividing the clock 275 * frequency by X is the same as multiplying the period by X. 276 */ 277 if (ssys_use_rcc2(s)) { 278 period_ns = 5 * (((s->rcc2 >> 23) & 0x3f) + 1); 279 } else { 280 period_ns = 5 * (((s->rcc >> 23) & 0xf) + 1); 281 } 282 clock_set_ns(s->sysclk, period_ns); 283 if (propagate_clock) { 284 clock_propagate(s->sysclk); 285 } 286 } 287 288 static void ssys_write(void *opaque, hwaddr offset, 289 uint64_t value, unsigned size) 290 { 291 ssys_state *s = (ssys_state *)opaque; 292 293 switch (offset) { 294 case 0x030: /* PBORCTL */ 295 s->pborctl = value & 0xffff; 296 break; 297 case 0x034: /* LDOPCTL */ 298 s->ldopctl = value & 0x1f; 299 break; 300 case 0x040: /* SRCR0 */ 301 case 0x044: /* SRCR1 */ 302 case 0x048: /* SRCR2 */ 303 qemu_log_mask(LOG_UNIMP, "Peripheral reset not implemented\n"); 304 break; 305 case 0x054: /* IMC */ 306 s->int_mask = value & 0x7f; 307 break; 308 case 0x058: /* MISC */ 309 s->int_status &= ~value; 310 break; 311 case 0x05c: /* RESC */ 312 s->resc = value & 0x3f; 313 break; 314 case 0x060: /* RCC */ 315 if ((s->rcc & (1 << 13)) != 0 && (value & (1 << 13)) == 0) { 316 /* PLL enable. */ 317 s->int_status |= (1 << 6); 318 } 319 s->rcc = value; 320 ssys_calculate_system_clock(s, true); 321 break; 322 case 0x070: /* RCC2 */ 323 if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) { 324 break; 325 } 326 327 if ((s->rcc2 & (1 << 13)) != 0 && (value & (1 << 13)) == 0) { 328 /* PLL enable. */ 329 s->int_status |= (1 << 6); 330 } 331 s->rcc2 = value; 332 ssys_calculate_system_clock(s, true); 333 break; 334 case 0x100: /* RCGC0 */ 335 s->rcgc[0] = value; 336 break; 337 case 0x104: /* RCGC1 */ 338 s->rcgc[1] = value; 339 break; 340 case 0x108: /* RCGC2 */ 341 s->rcgc[2] = value; 342 break; 343 case 0x110: /* SCGC0 */ 344 s->scgc[0] = value; 345 break; 346 case 0x114: /* SCGC1 */ 347 s->scgc[1] = value; 348 break; 349 case 0x118: /* SCGC2 */ 350 s->scgc[2] = value; 351 break; 352 case 0x120: /* DCGC0 */ 353 s->dcgc[0] = value; 354 break; 355 case 0x124: /* DCGC1 */ 356 s->dcgc[1] = value; 357 break; 358 case 0x128: /* DCGC2 */ 359 s->dcgc[2] = value; 360 break; 361 case 0x150: /* CLKVCLR */ 362 s->clkvclr = value; 363 break; 364 case 0x160: /* LDOARST */ 365 s->ldoarst = value; 366 break; 367 default: 368 qemu_log_mask(LOG_GUEST_ERROR, 369 "SSYS: write at bad offset 0x%x\n", (int)offset); 370 } 371 ssys_update(s); 372 } 373 374 static const MemoryRegionOps ssys_ops = { 375 .read = ssys_read, 376 .write = ssys_write, 377 .endianness = DEVICE_NATIVE_ENDIAN, 378 }; 379 380 static void stellaris_sys_reset_enter(Object *obj, ResetType type) 381 { 382 ssys_state *s = STELLARIS_SYS(obj); 383 384 s->pborctl = 0x7ffd; 385 s->rcc = 0x078e3ac0; 386 387 if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) { 388 s->rcc2 = 0; 389 } else { 390 s->rcc2 = 0x07802810; 391 } 392 s->rcgc[0] = 1; 393 s->scgc[0] = 1; 394 s->dcgc[0] = 1; 395 } 396 397 static void stellaris_sys_reset_hold(Object *obj) 398 { 399 ssys_state *s = STELLARIS_SYS(obj); 400 401 /* OK to propagate clocks from the hold phase */ 402 ssys_calculate_system_clock(s, true); 403 } 404 405 static void stellaris_sys_reset_exit(Object *obj) 406 { 407 } 408 409 static int stellaris_sys_post_load(void *opaque, int version_id) 410 { 411 ssys_state *s = opaque; 412 413 ssys_calculate_system_clock(s, false); 414 415 return 0; 416 } 417 418 static const VMStateDescription vmstate_stellaris_sys = { 419 .name = "stellaris_sys", 420 .version_id = 2, 421 .minimum_version_id = 1, 422 .post_load = stellaris_sys_post_load, 423 .fields = (const VMStateField[]) { 424 VMSTATE_UINT32(pborctl, ssys_state), 425 VMSTATE_UINT32(ldopctl, ssys_state), 426 VMSTATE_UINT32(int_mask, ssys_state), 427 VMSTATE_UINT32(int_status, ssys_state), 428 VMSTATE_UINT32(resc, ssys_state), 429 VMSTATE_UINT32(rcc, ssys_state), 430 VMSTATE_UINT32_V(rcc2, ssys_state, 2), 431 VMSTATE_UINT32_ARRAY(rcgc, ssys_state, 3), 432 VMSTATE_UINT32_ARRAY(scgc, ssys_state, 3), 433 VMSTATE_UINT32_ARRAY(dcgc, ssys_state, 3), 434 VMSTATE_UINT32(clkvclr, ssys_state), 435 VMSTATE_UINT32(ldoarst, ssys_state), 436 /* No field for sysclk -- handled in post-load instead */ 437 VMSTATE_END_OF_LIST() 438 } 439 }; 440 441 static Property stellaris_sys_properties[] = { 442 DEFINE_PROP_UINT32("user0", ssys_state, user0, 0), 443 DEFINE_PROP_UINT32("user1", ssys_state, user1, 0), 444 DEFINE_PROP_UINT32("did0", ssys_state, did0, 0), 445 DEFINE_PROP_UINT32("did1", ssys_state, did1, 0), 446 DEFINE_PROP_UINT32("dc0", ssys_state, dc0, 0), 447 DEFINE_PROP_UINT32("dc1", ssys_state, dc1, 0), 448 DEFINE_PROP_UINT32("dc2", ssys_state, dc2, 0), 449 DEFINE_PROP_UINT32("dc3", ssys_state, dc3, 0), 450 DEFINE_PROP_UINT32("dc4", ssys_state, dc4, 0), 451 DEFINE_PROP_END_OF_LIST() 452 }; 453 454 static void stellaris_sys_instance_init(Object *obj) 455 { 456 ssys_state *s = STELLARIS_SYS(obj); 457 SysBusDevice *sbd = SYS_BUS_DEVICE(s); 458 459 memory_region_init_io(&s->iomem, obj, &ssys_ops, s, "ssys", 0x00001000); 460 sysbus_init_mmio(sbd, &s->iomem); 461 sysbus_init_irq(sbd, &s->irq); 462 s->sysclk = qdev_init_clock_out(DEVICE(s), "SYSCLK"); 463 } 464 465 /* I2C controller. */ 466 467 #define TYPE_STELLARIS_I2C "stellaris-i2c" 468 OBJECT_DECLARE_SIMPLE_TYPE(stellaris_i2c_state, STELLARIS_I2C) 469 470 struct stellaris_i2c_state { 471 SysBusDevice parent_obj; 472 473 I2CBus *bus; 474 qemu_irq irq; 475 MemoryRegion iomem; 476 uint32_t msa; 477 uint32_t mcs; 478 uint32_t mdr; 479 uint32_t mtpr; 480 uint32_t mimr; 481 uint32_t mris; 482 uint32_t mcr; 483 }; 484 485 #define STELLARIS_I2C_MCS_BUSY 0x01 486 #define STELLARIS_I2C_MCS_ERROR 0x02 487 #define STELLARIS_I2C_MCS_ADRACK 0x04 488 #define STELLARIS_I2C_MCS_DATACK 0x08 489 #define STELLARIS_I2C_MCS_ARBLST 0x10 490 #define STELLARIS_I2C_MCS_IDLE 0x20 491 #define STELLARIS_I2C_MCS_BUSBSY 0x40 492 493 static uint64_t stellaris_i2c_read(void *opaque, hwaddr offset, 494 unsigned size) 495 { 496 stellaris_i2c_state *s = (stellaris_i2c_state *)opaque; 497 498 switch (offset) { 499 case 0x00: /* MSA */ 500 return s->msa; 501 case 0x04: /* MCS */ 502 /* We don't emulate timing, so the controller is never busy. */ 503 return s->mcs | STELLARIS_I2C_MCS_IDLE; 504 case 0x08: /* MDR */ 505 return s->mdr; 506 case 0x0c: /* MTPR */ 507 return s->mtpr; 508 case 0x10: /* MIMR */ 509 return s->mimr; 510 case 0x14: /* MRIS */ 511 return s->mris; 512 case 0x18: /* MMIS */ 513 return s->mris & s->mimr; 514 case 0x20: /* MCR */ 515 return s->mcr; 516 default: 517 qemu_log_mask(LOG_GUEST_ERROR, 518 "stellaris_i2c: read at bad offset 0x%x\n", (int)offset); 519 return 0; 520 } 521 } 522 523 static void stellaris_i2c_update(stellaris_i2c_state *s) 524 { 525 int level; 526 527 level = (s->mris & s->mimr) != 0; 528 qemu_set_irq(s->irq, level); 529 } 530 531 static void stellaris_i2c_write(void *opaque, hwaddr offset, 532 uint64_t value, unsigned size) 533 { 534 stellaris_i2c_state *s = (stellaris_i2c_state *)opaque; 535 536 switch (offset) { 537 case 0x00: /* MSA */ 538 s->msa = value & 0xff; 539 break; 540 case 0x04: /* MCS */ 541 if ((s->mcr & 0x10) == 0) { 542 /* Disabled. Do nothing. */ 543 break; 544 } 545 /* Grab the bus if this is starting a transfer. */ 546 if ((value & 2) && (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) { 547 if (i2c_start_transfer(s->bus, s->msa >> 1, s->msa & 1)) { 548 s->mcs |= STELLARIS_I2C_MCS_ARBLST; 549 } else { 550 s->mcs &= ~STELLARIS_I2C_MCS_ARBLST; 551 s->mcs |= STELLARIS_I2C_MCS_BUSBSY; 552 } 553 } 554 /* If we don't have the bus then indicate an error. */ 555 if (!i2c_bus_busy(s->bus) 556 || (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) { 557 s->mcs |= STELLARIS_I2C_MCS_ERROR; 558 break; 559 } 560 s->mcs &= ~STELLARIS_I2C_MCS_ERROR; 561 if (value & 1) { 562 /* Transfer a byte. */ 563 /* TODO: Handle errors. */ 564 if (s->msa & 1) { 565 /* Recv */ 566 s->mdr = i2c_recv(s->bus); 567 } else { 568 /* Send */ 569 i2c_send(s->bus, s->mdr); 570 } 571 /* Raise an interrupt. */ 572 s->mris |= 1; 573 } 574 if (value & 4) { 575 /* Finish transfer. */ 576 i2c_end_transfer(s->bus); 577 s->mcs &= ~STELLARIS_I2C_MCS_BUSBSY; 578 } 579 break; 580 case 0x08: /* MDR */ 581 s->mdr = value & 0xff; 582 break; 583 case 0x0c: /* MTPR */ 584 s->mtpr = value & 0xff; 585 break; 586 case 0x10: /* MIMR */ 587 s->mimr = 1; 588 break; 589 case 0x1c: /* MICR */ 590 s->mris &= ~value; 591 break; 592 case 0x20: /* MCR */ 593 if (value & 1) { 594 qemu_log_mask(LOG_UNIMP, 595 "stellaris_i2c: Loopback not implemented\n"); 596 } 597 if (value & 0x20) { 598 qemu_log_mask(LOG_UNIMP, 599 "stellaris_i2c: Slave mode not implemented\n"); 600 } 601 s->mcr = value & 0x31; 602 break; 603 default: 604 qemu_log_mask(LOG_GUEST_ERROR, 605 "stellaris_i2c: write at bad offset 0x%x\n", (int)offset); 606 } 607 stellaris_i2c_update(s); 608 } 609 610 static void stellaris_i2c_reset(stellaris_i2c_state *s) 611 { 612 if (s->mcs & STELLARIS_I2C_MCS_BUSBSY) 613 i2c_end_transfer(s->bus); 614 615 s->msa = 0; 616 s->mcs = 0; 617 s->mdr = 0; 618 s->mtpr = 1; 619 s->mimr = 0; 620 s->mris = 0; 621 s->mcr = 0; 622 stellaris_i2c_update(s); 623 } 624 625 static const MemoryRegionOps stellaris_i2c_ops = { 626 .read = stellaris_i2c_read, 627 .write = stellaris_i2c_write, 628 .endianness = DEVICE_NATIVE_ENDIAN, 629 }; 630 631 static const VMStateDescription vmstate_stellaris_i2c = { 632 .name = "stellaris_i2c", 633 .version_id = 1, 634 .minimum_version_id = 1, 635 .fields = (const VMStateField[]) { 636 VMSTATE_UINT32(msa, stellaris_i2c_state), 637 VMSTATE_UINT32(mcs, stellaris_i2c_state), 638 VMSTATE_UINT32(mdr, stellaris_i2c_state), 639 VMSTATE_UINT32(mtpr, stellaris_i2c_state), 640 VMSTATE_UINT32(mimr, stellaris_i2c_state), 641 VMSTATE_UINT32(mris, stellaris_i2c_state), 642 VMSTATE_UINT32(mcr, stellaris_i2c_state), 643 VMSTATE_END_OF_LIST() 644 } 645 }; 646 647 static void stellaris_i2c_init(Object *obj) 648 { 649 DeviceState *dev = DEVICE(obj); 650 stellaris_i2c_state *s = STELLARIS_I2C(obj); 651 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 652 I2CBus *bus; 653 654 sysbus_init_irq(sbd, &s->irq); 655 bus = i2c_init_bus(dev, "i2c"); 656 s->bus = bus; 657 658 memory_region_init_io(&s->iomem, obj, &stellaris_i2c_ops, s, 659 "i2c", 0x1000); 660 sysbus_init_mmio(sbd, &s->iomem); 661 /* ??? For now we only implement the master interface. */ 662 stellaris_i2c_reset(s); 663 } 664 665 /* Analogue to Digital Converter. This is only partially implemented, 666 enough for applications that use a combined ADC and timer tick. */ 667 668 #define STELLARIS_ADC_EM_CONTROLLER 0 669 #define STELLARIS_ADC_EM_COMP 1 670 #define STELLARIS_ADC_EM_EXTERNAL 4 671 #define STELLARIS_ADC_EM_TIMER 5 672 #define STELLARIS_ADC_EM_PWM0 6 673 #define STELLARIS_ADC_EM_PWM1 7 674 #define STELLARIS_ADC_EM_PWM2 8 675 676 #define STELLARIS_ADC_FIFO_EMPTY 0x0100 677 #define STELLARIS_ADC_FIFO_FULL 0x1000 678 679 #define TYPE_STELLARIS_ADC "stellaris-adc" 680 typedef struct StellarisADCState StellarisADCState; 681 DECLARE_INSTANCE_CHECKER(StellarisADCState, STELLARIS_ADC, TYPE_STELLARIS_ADC) 682 683 struct StellarisADCState { 684 SysBusDevice parent_obj; 685 686 MemoryRegion iomem; 687 uint32_t actss; 688 uint32_t ris; 689 uint32_t im; 690 uint32_t emux; 691 uint32_t ostat; 692 uint32_t ustat; 693 uint32_t sspri; 694 uint32_t sac; 695 struct { 696 uint32_t state; 697 uint32_t data[16]; 698 } fifo[4]; 699 uint32_t ssmux[4]; 700 uint32_t ssctl[4]; 701 uint32_t noise; 702 qemu_irq irq[4]; 703 }; 704 705 static uint32_t stellaris_adc_fifo_read(StellarisADCState *s, int n) 706 { 707 int tail; 708 709 tail = s->fifo[n].state & 0xf; 710 if (s->fifo[n].state & STELLARIS_ADC_FIFO_EMPTY) { 711 s->ustat |= 1 << n; 712 } else { 713 s->fifo[n].state = (s->fifo[n].state & ~0xf) | ((tail + 1) & 0xf); 714 s->fifo[n].state &= ~STELLARIS_ADC_FIFO_FULL; 715 if (tail + 1 == ((s->fifo[n].state >> 4) & 0xf)) 716 s->fifo[n].state |= STELLARIS_ADC_FIFO_EMPTY; 717 } 718 return s->fifo[n].data[tail]; 719 } 720 721 static void stellaris_adc_fifo_write(StellarisADCState *s, int n, 722 uint32_t value) 723 { 724 int head; 725 726 /* TODO: Real hardware has limited size FIFOs. We have a full 16 entry 727 FIFO fir each sequencer. */ 728 head = (s->fifo[n].state >> 4) & 0xf; 729 if (s->fifo[n].state & STELLARIS_ADC_FIFO_FULL) { 730 s->ostat |= 1 << n; 731 return; 732 } 733 s->fifo[n].data[head] = value; 734 head = (head + 1) & 0xf; 735 s->fifo[n].state &= ~STELLARIS_ADC_FIFO_EMPTY; 736 s->fifo[n].state = (s->fifo[n].state & ~0xf0) | (head << 4); 737 if ((s->fifo[n].state & 0xf) == head) 738 s->fifo[n].state |= STELLARIS_ADC_FIFO_FULL; 739 } 740 741 static void stellaris_adc_update(StellarisADCState *s) 742 { 743 int level; 744 int n; 745 746 for (n = 0; n < 4; n++) { 747 level = (s->ris & s->im & (1 << n)) != 0; 748 qemu_set_irq(s->irq[n], level); 749 } 750 } 751 752 static void stellaris_adc_trigger(void *opaque, int irq, int level) 753 { 754 StellarisADCState *s = opaque; 755 int n; 756 757 for (n = 0; n < 4; n++) { 758 if ((s->actss & (1 << n)) == 0) { 759 continue; 760 } 761 762 if (((s->emux >> (n * 4)) & 0xff) != 5) { 763 continue; 764 } 765 766 /* Some applications use the ADC as a random number source, so introduce 767 some variation into the signal. */ 768 s->noise = s->noise * 314159 + 1; 769 /* ??? actual inputs not implemented. Return an arbitrary value. */ 770 stellaris_adc_fifo_write(s, n, 0x200 + ((s->noise >> 16) & 7)); 771 s->ris |= (1 << n); 772 stellaris_adc_update(s); 773 } 774 } 775 776 static void stellaris_adc_reset(StellarisADCState *s) 777 { 778 int n; 779 780 for (n = 0; n < 4; n++) { 781 s->ssmux[n] = 0; 782 s->ssctl[n] = 0; 783 s->fifo[n].state = STELLARIS_ADC_FIFO_EMPTY; 784 } 785 } 786 787 static uint64_t stellaris_adc_read(void *opaque, hwaddr offset, 788 unsigned size) 789 { 790 StellarisADCState *s = opaque; 791 792 /* TODO: Implement this. */ 793 if (offset >= 0x40 && offset < 0xc0) { 794 int n; 795 n = (offset - 0x40) >> 5; 796 switch (offset & 0x1f) { 797 case 0x00: /* SSMUX */ 798 return s->ssmux[n]; 799 case 0x04: /* SSCTL */ 800 return s->ssctl[n]; 801 case 0x08: /* SSFIFO */ 802 return stellaris_adc_fifo_read(s, n); 803 case 0x0c: /* SSFSTAT */ 804 return s->fifo[n].state; 805 default: 806 break; 807 } 808 } 809 switch (offset) { 810 case 0x00: /* ACTSS */ 811 return s->actss; 812 case 0x04: /* RIS */ 813 return s->ris; 814 case 0x08: /* IM */ 815 return s->im; 816 case 0x0c: /* ISC */ 817 return s->ris & s->im; 818 case 0x10: /* OSTAT */ 819 return s->ostat; 820 case 0x14: /* EMUX */ 821 return s->emux; 822 case 0x18: /* USTAT */ 823 return s->ustat; 824 case 0x20: /* SSPRI */ 825 return s->sspri; 826 case 0x30: /* SAC */ 827 return s->sac; 828 default: 829 qemu_log_mask(LOG_GUEST_ERROR, 830 "stellaris_adc: read at bad offset 0x%x\n", (int)offset); 831 return 0; 832 } 833 } 834 835 static void stellaris_adc_write(void *opaque, hwaddr offset, 836 uint64_t value, unsigned size) 837 { 838 StellarisADCState *s = opaque; 839 840 /* TODO: Implement this. */ 841 if (offset >= 0x40 && offset < 0xc0) { 842 int n; 843 n = (offset - 0x40) >> 5; 844 switch (offset & 0x1f) { 845 case 0x00: /* SSMUX */ 846 s->ssmux[n] = value & 0x33333333; 847 return; 848 case 0x04: /* SSCTL */ 849 if (value != 6) { 850 qemu_log_mask(LOG_UNIMP, 851 "ADC: Unimplemented sequence %" PRIx64 "\n", 852 value); 853 } 854 s->ssctl[n] = value; 855 return; 856 default: 857 break; 858 } 859 } 860 switch (offset) { 861 case 0x00: /* ACTSS */ 862 s->actss = value & 0xf; 863 break; 864 case 0x08: /* IM */ 865 s->im = value; 866 break; 867 case 0x0c: /* ISC */ 868 s->ris &= ~value; 869 break; 870 case 0x10: /* OSTAT */ 871 s->ostat &= ~value; 872 break; 873 case 0x14: /* EMUX */ 874 s->emux = value; 875 break; 876 case 0x18: /* USTAT */ 877 s->ustat &= ~value; 878 break; 879 case 0x20: /* SSPRI */ 880 s->sspri = value; 881 break; 882 case 0x28: /* PSSI */ 883 qemu_log_mask(LOG_UNIMP, "ADC: sample initiate unimplemented\n"); 884 break; 885 case 0x30: /* SAC */ 886 s->sac = value; 887 break; 888 default: 889 qemu_log_mask(LOG_GUEST_ERROR, 890 "stellaris_adc: write at bad offset 0x%x\n", (int)offset); 891 } 892 stellaris_adc_update(s); 893 } 894 895 static const MemoryRegionOps stellaris_adc_ops = { 896 .read = stellaris_adc_read, 897 .write = stellaris_adc_write, 898 .endianness = DEVICE_NATIVE_ENDIAN, 899 }; 900 901 static const VMStateDescription vmstate_stellaris_adc = { 902 .name = "stellaris_adc", 903 .version_id = 1, 904 .minimum_version_id = 1, 905 .fields = (const VMStateField[]) { 906 VMSTATE_UINT32(actss, StellarisADCState), 907 VMSTATE_UINT32(ris, StellarisADCState), 908 VMSTATE_UINT32(im, StellarisADCState), 909 VMSTATE_UINT32(emux, StellarisADCState), 910 VMSTATE_UINT32(ostat, StellarisADCState), 911 VMSTATE_UINT32(ustat, StellarisADCState), 912 VMSTATE_UINT32(sspri, StellarisADCState), 913 VMSTATE_UINT32(sac, StellarisADCState), 914 VMSTATE_UINT32(fifo[0].state, StellarisADCState), 915 VMSTATE_UINT32_ARRAY(fifo[0].data, StellarisADCState, 16), 916 VMSTATE_UINT32(ssmux[0], StellarisADCState), 917 VMSTATE_UINT32(ssctl[0], StellarisADCState), 918 VMSTATE_UINT32(fifo[1].state, StellarisADCState), 919 VMSTATE_UINT32_ARRAY(fifo[1].data, StellarisADCState, 16), 920 VMSTATE_UINT32(ssmux[1], StellarisADCState), 921 VMSTATE_UINT32(ssctl[1], StellarisADCState), 922 VMSTATE_UINT32(fifo[2].state, StellarisADCState), 923 VMSTATE_UINT32_ARRAY(fifo[2].data, StellarisADCState, 16), 924 VMSTATE_UINT32(ssmux[2], StellarisADCState), 925 VMSTATE_UINT32(ssctl[2], StellarisADCState), 926 VMSTATE_UINT32(fifo[3].state, StellarisADCState), 927 VMSTATE_UINT32_ARRAY(fifo[3].data, StellarisADCState, 16), 928 VMSTATE_UINT32(ssmux[3], StellarisADCState), 929 VMSTATE_UINT32(ssctl[3], StellarisADCState), 930 VMSTATE_UINT32(noise, StellarisADCState), 931 VMSTATE_END_OF_LIST() 932 } 933 }; 934 935 static void stellaris_adc_init(Object *obj) 936 { 937 DeviceState *dev = DEVICE(obj); 938 StellarisADCState *s = STELLARIS_ADC(obj); 939 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 940 int n; 941 942 for (n = 0; n < 4; n++) { 943 sysbus_init_irq(sbd, &s->irq[n]); 944 } 945 946 memory_region_init_io(&s->iomem, obj, &stellaris_adc_ops, s, 947 "adc", 0x1000); 948 sysbus_init_mmio(sbd, &s->iomem); 949 stellaris_adc_reset(s); 950 qdev_init_gpio_in(dev, stellaris_adc_trigger, 1); 951 } 952 953 /* Board init. */ 954 static stellaris_board_info stellaris_boards[] = { 955 { "LM3S811EVB", 956 0, 957 0x0032000e, 958 0x001f001f, /* dc0 */ 959 0x001132bf, 960 0x01071013, 961 0x3f0f01ff, 962 0x0000001f, 963 BP_OLED_I2C 964 }, 965 { "LM3S6965EVB", 966 0x10010002, 967 0x1073402e, 968 0x00ff007f, /* dc0 */ 969 0x001133ff, 970 0x030f5317, 971 0x0f0f87ff, 972 0x5000007f, 973 BP_OLED_SSI | BP_GAMEPAD 974 } 975 }; 976 977 static void stellaris_init(MachineState *ms, stellaris_board_info *board) 978 { 979 static const int uart_irq[] = {5, 6, 33, 34}; 980 static const int timer_irq[] = {19, 21, 23, 35}; 981 static const uint32_t gpio_addr[7] = 982 { 0x40004000, 0x40005000, 0x40006000, 0x40007000, 983 0x40024000, 0x40025000, 0x40026000}; 984 static const int gpio_irq[7] = {0, 1, 2, 3, 4, 30, 31}; 985 986 /* Memory map of SoC devices, from 987 * Stellaris LM3S6965 Microcontroller Data Sheet (rev I) 988 * http://www.ti.com/lit/ds/symlink/lm3s6965.pdf 989 * 990 * 40000000 wdtimer 991 * 40002000 i2c (unimplemented) 992 * 40004000 GPIO 993 * 40005000 GPIO 994 * 40006000 GPIO 995 * 40007000 GPIO 996 * 40008000 SSI 997 * 4000c000 UART 998 * 4000d000 UART 999 * 4000e000 UART 1000 * 40020000 i2c 1001 * 40021000 i2c (unimplemented) 1002 * 40024000 GPIO 1003 * 40025000 GPIO 1004 * 40026000 GPIO 1005 * 40028000 PWM (unimplemented) 1006 * 4002c000 QEI (unimplemented) 1007 * 4002d000 QEI (unimplemented) 1008 * 40030000 gptimer 1009 * 40031000 gptimer 1010 * 40032000 gptimer 1011 * 40033000 gptimer 1012 * 40038000 ADC 1013 * 4003c000 analogue comparator (unimplemented) 1014 * 40048000 ethernet 1015 * 400fc000 hibernation module (unimplemented) 1016 * 400fd000 flash memory control (unimplemented) 1017 * 400fe000 system control 1018 */ 1019 1020 DeviceState *gpio_dev[7], *nvic; 1021 qemu_irq gpio_in[7][8]; 1022 qemu_irq gpio_out[7][8]; 1023 qemu_irq adc; 1024 int sram_size; 1025 int flash_size; 1026 I2CBus *i2c; 1027 DeviceState *dev; 1028 DeviceState *ssys_dev; 1029 int i; 1030 int j; 1031 NICInfo *nd; 1032 MACAddr mac; 1033 1034 MemoryRegion *sram = g_new(MemoryRegion, 1); 1035 MemoryRegion *flash = g_new(MemoryRegion, 1); 1036 MemoryRegion *system_memory = get_system_memory(); 1037 1038 flash_size = (((board->dc0 & 0xffff) + 1) << 1) * 1024; 1039 sram_size = ((board->dc0 >> 18) + 1) * 1024; 1040 1041 /* Flash programming is done via the SCU, so pretend it is ROM. */ 1042 memory_region_init_rom(flash, NULL, "stellaris.flash", flash_size, 1043 &error_fatal); 1044 memory_region_add_subregion(system_memory, 0, flash); 1045 1046 memory_region_init_ram(sram, NULL, "stellaris.sram", sram_size, 1047 &error_fatal); 1048 memory_region_add_subregion(system_memory, 0x20000000, sram); 1049 1050 /* 1051 * Create the system-registers object early, because we will 1052 * need its sysclk output. 1053 */ 1054 ssys_dev = qdev_new(TYPE_STELLARIS_SYS); 1055 1056 /* 1057 * Most devices come preprogrammed with a MAC address in the user data. 1058 * Generate a MAC address now, if there isn't a matching -nic for it. 1059 */ 1060 nd = qemu_find_nic_info("stellaris_enet", true, "stellaris"); 1061 if (nd) { 1062 memcpy(mac.a, nd->macaddr.a, sizeof(mac.a)); 1063 } else { 1064 qemu_macaddr_default_if_unset(&mac); 1065 } 1066 1067 qdev_prop_set_uint32(ssys_dev, "user0", 1068 mac.a[0] | (mac.a[1] << 8) | (mac.a[2] << 16)); 1069 qdev_prop_set_uint32(ssys_dev, "user1", 1070 mac.a[3] | (mac.a[4] << 8) | (mac.a[5] << 16)); 1071 qdev_prop_set_uint32(ssys_dev, "did0", board->did0); 1072 qdev_prop_set_uint32(ssys_dev, "did1", board->did1); 1073 qdev_prop_set_uint32(ssys_dev, "dc0", board->dc0); 1074 qdev_prop_set_uint32(ssys_dev, "dc1", board->dc1); 1075 qdev_prop_set_uint32(ssys_dev, "dc2", board->dc2); 1076 qdev_prop_set_uint32(ssys_dev, "dc3", board->dc3); 1077 qdev_prop_set_uint32(ssys_dev, "dc4", board->dc4); 1078 sysbus_realize_and_unref(SYS_BUS_DEVICE(ssys_dev), &error_fatal); 1079 1080 nvic = qdev_new(TYPE_ARMV7M); 1081 qdev_prop_set_uint32(nvic, "num-irq", NUM_IRQ_LINES); 1082 qdev_prop_set_uint8(nvic, "num-prio-bits", NUM_PRIO_BITS); 1083 qdev_prop_set_string(nvic, "cpu-type", ms->cpu_type); 1084 qdev_prop_set_bit(nvic, "enable-bitband", true); 1085 qdev_connect_clock_in(nvic, "cpuclk", 1086 qdev_get_clock_out(ssys_dev, "SYSCLK")); 1087 /* This SoC does not connect the systick reference clock */ 1088 object_property_set_link(OBJECT(nvic), "memory", 1089 OBJECT(get_system_memory()), &error_abort); 1090 /* This will exit with an error if the user passed us a bad cpu_type */ 1091 sysbus_realize_and_unref(SYS_BUS_DEVICE(nvic), &error_fatal); 1092 1093 /* Now we can wire up the IRQ and MMIO of the system registers */ 1094 sysbus_mmio_map(SYS_BUS_DEVICE(ssys_dev), 0, 0x400fe000); 1095 sysbus_connect_irq(SYS_BUS_DEVICE(ssys_dev), 0, qdev_get_gpio_in(nvic, 28)); 1096 1097 if (board->dc1 & (1 << 16)) { 1098 dev = sysbus_create_varargs(TYPE_STELLARIS_ADC, 0x40038000, 1099 qdev_get_gpio_in(nvic, 14), 1100 qdev_get_gpio_in(nvic, 15), 1101 qdev_get_gpio_in(nvic, 16), 1102 qdev_get_gpio_in(nvic, 17), 1103 NULL); 1104 adc = qdev_get_gpio_in(dev, 0); 1105 } else { 1106 adc = NULL; 1107 } 1108 for (i = 0; i < 4; i++) { 1109 if (board->dc2 & (0x10000 << i)) { 1110 SysBusDevice *sbd; 1111 1112 dev = qdev_new(TYPE_STELLARIS_GPTM); 1113 sbd = SYS_BUS_DEVICE(dev); 1114 qdev_connect_clock_in(dev, "clk", 1115 qdev_get_clock_out(ssys_dev, "SYSCLK")); 1116 sysbus_realize_and_unref(sbd, &error_fatal); 1117 sysbus_mmio_map(sbd, 0, 0x40030000 + i * 0x1000); 1118 sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(nvic, timer_irq[i])); 1119 /* TODO: This is incorrect, but we get away with it because 1120 the ADC output is only ever pulsed. */ 1121 qdev_connect_gpio_out(dev, 0, adc); 1122 } 1123 } 1124 1125 if (board->dc1 & (1 << 3)) { /* watchdog present */ 1126 dev = qdev_new(TYPE_LUMINARY_WATCHDOG); 1127 1128 qdev_connect_clock_in(dev, "WDOGCLK", 1129 qdev_get_clock_out(ssys_dev, "SYSCLK")); 1130 1131 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1132 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1133 0, 1134 0x40000000u); 1135 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1136 0, 1137 qdev_get_gpio_in(nvic, 18)); 1138 } 1139 1140 1141 for (i = 0; i < 7; i++) { 1142 if (board->dc4 & (1 << i)) { 1143 gpio_dev[i] = sysbus_create_simple("pl061_luminary", gpio_addr[i], 1144 qdev_get_gpio_in(nvic, 1145 gpio_irq[i])); 1146 for (j = 0; j < 8; j++) { 1147 gpio_in[i][j] = qdev_get_gpio_in(gpio_dev[i], j); 1148 gpio_out[i][j] = NULL; 1149 } 1150 } 1151 } 1152 1153 if (board->dc2 & (1 << 12)) { 1154 dev = sysbus_create_simple(TYPE_STELLARIS_I2C, 0x40020000, 1155 qdev_get_gpio_in(nvic, 8)); 1156 i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c"); 1157 if (board->peripherals & BP_OLED_I2C) { 1158 i2c_slave_create_simple(i2c, "ssd0303", 0x3d); 1159 } 1160 } 1161 1162 for (i = 0; i < 4; i++) { 1163 if (board->dc2 & (1 << i)) { 1164 SysBusDevice *sbd; 1165 1166 dev = qdev_new("pl011_luminary"); 1167 sbd = SYS_BUS_DEVICE(dev); 1168 qdev_prop_set_chr(dev, "chardev", serial_hd(i)); 1169 sysbus_realize_and_unref(sbd, &error_fatal); 1170 sysbus_mmio_map(sbd, 0, 0x4000c000 + i * 0x1000); 1171 sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(nvic, uart_irq[i])); 1172 } 1173 } 1174 if (board->dc2 & (1 << 4)) { 1175 dev = sysbus_create_simple("pl022", 0x40008000, 1176 qdev_get_gpio_in(nvic, 7)); 1177 if (board->peripherals & BP_OLED_SSI) { 1178 void *bus; 1179 DeviceState *sddev; 1180 DeviceState *ssddev; 1181 DriveInfo *dinfo; 1182 DeviceState *carddev; 1183 DeviceState *gpio_d_splitter; 1184 BlockBackend *blk; 1185 1186 /* 1187 * Some boards have both an OLED controller and SD card connected to 1188 * the same SSI port, with the SD card chip select connected to a 1189 * GPIO pin. Technically the OLED chip select is connected to the 1190 * SSI Fss pin. We do not bother emulating that as both devices 1191 * should never be selected simultaneously, and our OLED controller 1192 * ignores stray 0xff commands that occur when deselecting the SD 1193 * card. 1194 * 1195 * The h/w wiring is: 1196 * - GPIO pin D0 is wired to the active-low SD card chip select 1197 * - GPIO pin A3 is wired to the active-low OLED chip select 1198 * - The SoC wiring of the PL061 "auxiliary function" for A3 is 1199 * SSI0Fss ("frame signal"), which is an output from the SoC's 1200 * SSI controller. The SSI controller takes SSI0Fss low when it 1201 * transmits a frame, so it can work as a chip-select signal. 1202 * - GPIO A4 is aux-function SSI0Rx, and wired to the SD card Tx 1203 * (the OLED never sends data to the CPU, so no wiring needed) 1204 * - GPIO A5 is aux-function SSI0Tx, and wired to the SD card Rx 1205 * and the OLED display-data-in 1206 * - GPIO A2 is aux-function SSI0Clk, wired to SD card and OLED 1207 * serial-clock input 1208 * So a guest that wants to use the OLED can configure the PL061 1209 * to make pins A2, A3, A5 aux-function, so they are connected 1210 * directly to the SSI controller. When the SSI controller sends 1211 * data it asserts SSI0Fss which selects the OLED. 1212 * A guest that wants to use the SD card configures A2, A4 and A5 1213 * as aux-function, but leaves A3 as a software-controlled GPIO 1214 * line. It asserts the SD card chip-select by using the PL061 1215 * to control pin D0, and lets the SSI controller handle Clk, Tx 1216 * and Rx. (The SSI controller asserts Fss during tx cycles as 1217 * usual, but because A3 is not set to aux-function this is not 1218 * forwarded to the OLED, and so the OLED stays unselected.) 1219 * 1220 * The QEMU implementation instead is: 1221 * - GPIO pin D0 is wired to the active-low SD card chip select, 1222 * and also to the OLED chip-select which is implemented 1223 * as *active-high* 1224 * - SSI controller signals go to the devices regardless of 1225 * whether the guest programs A2, A4, A5 as aux-function or not 1226 * 1227 * The problem with this implementation is if the guest doesn't 1228 * care about the SD card and only uses the OLED. In that case it 1229 * may choose never to do anything with D0 (leaving it in its 1230 * default floating state, which reliably leaves the card disabled 1231 * because an SD card has a pullup on CS within the card itself), 1232 * and only set up A2, A3, A5. This for us would mean the OLED 1233 * never gets the chip-select assert it needs. We work around 1234 * this with a manual raise of D0 here (despite board creation 1235 * code being the wrong place to raise IRQ lines) to put the OLED 1236 * into an initially selected state. 1237 * 1238 * In theory the right way to model this would be: 1239 * - Implement aux-function support in the PL061, with an 1240 * extra set of AFIN and AFOUT GPIO lines (set up so that 1241 * if a GPIO line is in auxfn mode the main GPIO in and out 1242 * track the AFIN and AFOUT lines) 1243 * - Wire the AFOUT for D0 up to either a line from the 1244 * SSI controller that's pulled low around every transmit, 1245 * or at least to an always-0 line here on the board 1246 * - Make the ssd0323 OLED controller chipselect active-low 1247 */ 1248 bus = qdev_get_child_bus(dev, "ssi"); 1249 sddev = ssi_create_peripheral(bus, "ssi-sd"); 1250 1251 dinfo = drive_get(IF_SD, 0, 0); 1252 blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL; 1253 carddev = qdev_new(TYPE_SD_CARD_SPI); 1254 qdev_prop_set_drive_err(carddev, "drive", blk, &error_fatal); 1255 qdev_realize_and_unref(carddev, 1256 qdev_get_child_bus(sddev, "sd-bus"), 1257 &error_fatal); 1258 1259 ssddev = qdev_new("ssd0323"); 1260 qdev_prop_set_uint8(ssddev, "cs", 1); 1261 qdev_realize_and_unref(ssddev, bus, &error_fatal); 1262 1263 gpio_d_splitter = qdev_new(TYPE_SPLIT_IRQ); 1264 qdev_prop_set_uint32(gpio_d_splitter, "num-lines", 2); 1265 qdev_realize_and_unref(gpio_d_splitter, NULL, &error_fatal); 1266 qdev_connect_gpio_out( 1267 gpio_d_splitter, 0, 1268 qdev_get_gpio_in_named(sddev, SSI_GPIO_CS, 0)); 1269 qdev_connect_gpio_out( 1270 gpio_d_splitter, 1, 1271 qdev_get_gpio_in_named(ssddev, SSI_GPIO_CS, 0)); 1272 gpio_out[GPIO_D][0] = qdev_get_gpio_in(gpio_d_splitter, 0); 1273 1274 gpio_out[GPIO_C][7] = qdev_get_gpio_in(ssddev, 0); 1275 1276 /* Make sure the select pin is high. */ 1277 qemu_irq_raise(gpio_out[GPIO_D][0]); 1278 } 1279 } 1280 if (board->dc4 & (1 << 28)) { 1281 DeviceState *enet; 1282 1283 enet = qdev_new("stellaris_enet"); 1284 if (nd) { 1285 qdev_set_nic_properties(enet, nd); 1286 } else { 1287 qdev_prop_set_macaddr(enet, "mac", mac.a); 1288 } 1289 1290 sysbus_realize_and_unref(SYS_BUS_DEVICE(enet), &error_fatal); 1291 sysbus_mmio_map(SYS_BUS_DEVICE(enet), 0, 0x40048000); 1292 sysbus_connect_irq(SYS_BUS_DEVICE(enet), 0, qdev_get_gpio_in(nvic, 42)); 1293 } 1294 if (board->peripherals & BP_GAMEPAD) { 1295 QList *gpad_keycode_list = qlist_new(); 1296 static const int gpad_keycode[5] = { 1297 Q_KEY_CODE_UP, Q_KEY_CODE_DOWN, Q_KEY_CODE_LEFT, 1298 Q_KEY_CODE_RIGHT, Q_KEY_CODE_CTRL, 1299 }; 1300 DeviceState *gpad; 1301 1302 gpad = qdev_new(TYPE_STELLARIS_GAMEPAD); 1303 for (i = 0; i < ARRAY_SIZE(gpad_keycode); i++) { 1304 qlist_append_int(gpad_keycode_list, gpad_keycode[i]); 1305 } 1306 qdev_prop_set_array(gpad, "keycodes", gpad_keycode_list); 1307 sysbus_realize_and_unref(SYS_BUS_DEVICE(gpad), &error_fatal); 1308 1309 qdev_connect_gpio_out(gpad, 0, 1310 qemu_irq_invert(gpio_in[GPIO_E][0])); /* up */ 1311 qdev_connect_gpio_out(gpad, 1, 1312 qemu_irq_invert(gpio_in[GPIO_E][1])); /* down */ 1313 qdev_connect_gpio_out(gpad, 2, 1314 qemu_irq_invert(gpio_in[GPIO_E][2])); /* left */ 1315 qdev_connect_gpio_out(gpad, 3, 1316 qemu_irq_invert(gpio_in[GPIO_E][3])); /* right */ 1317 qdev_connect_gpio_out(gpad, 4, 1318 qemu_irq_invert(gpio_in[GPIO_F][1])); /* select */ 1319 } 1320 for (i = 0; i < 7; i++) { 1321 if (board->dc4 & (1 << i)) { 1322 for (j = 0; j < 8; j++) { 1323 if (gpio_out[i][j]) { 1324 qdev_connect_gpio_out(gpio_dev[i], j, gpio_out[i][j]); 1325 } 1326 } 1327 } 1328 } 1329 1330 /* Add dummy regions for the devices we don't implement yet, 1331 * so guest accesses don't cause unlogged crashes. 1332 */ 1333 create_unimplemented_device("i2c-0", 0x40002000, 0x1000); 1334 create_unimplemented_device("i2c-2", 0x40021000, 0x1000); 1335 create_unimplemented_device("PWM", 0x40028000, 0x1000); 1336 create_unimplemented_device("QEI-0", 0x4002c000, 0x1000); 1337 create_unimplemented_device("QEI-1", 0x4002d000, 0x1000); 1338 create_unimplemented_device("analogue-comparator", 0x4003c000, 0x1000); 1339 create_unimplemented_device("hibernation", 0x400fc000, 0x1000); 1340 create_unimplemented_device("flash-control", 0x400fd000, 0x1000); 1341 1342 armv7m_load_kernel(ARM_CPU(first_cpu), ms->kernel_filename, 0, flash_size); 1343 } 1344 1345 /* FIXME: Figure out how to generate these from stellaris_boards. */ 1346 static void lm3s811evb_init(MachineState *machine) 1347 { 1348 stellaris_init(machine, &stellaris_boards[0]); 1349 } 1350 1351 static void lm3s6965evb_init(MachineState *machine) 1352 { 1353 stellaris_init(machine, &stellaris_boards[1]); 1354 } 1355 1356 static void lm3s811evb_class_init(ObjectClass *oc, void *data) 1357 { 1358 MachineClass *mc = MACHINE_CLASS(oc); 1359 1360 mc->desc = "Stellaris LM3S811EVB (Cortex-M3)"; 1361 mc->init = lm3s811evb_init; 1362 mc->ignore_memory_transaction_failures = true; 1363 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3"); 1364 } 1365 1366 static const TypeInfo lm3s811evb_type = { 1367 .name = MACHINE_TYPE_NAME("lm3s811evb"), 1368 .parent = TYPE_MACHINE, 1369 .class_init = lm3s811evb_class_init, 1370 }; 1371 1372 static void lm3s6965evb_class_init(ObjectClass *oc, void *data) 1373 { 1374 MachineClass *mc = MACHINE_CLASS(oc); 1375 1376 mc->desc = "Stellaris LM3S6965EVB (Cortex-M3)"; 1377 mc->init = lm3s6965evb_init; 1378 mc->ignore_memory_transaction_failures = true; 1379 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3"); 1380 } 1381 1382 static const TypeInfo lm3s6965evb_type = { 1383 .name = MACHINE_TYPE_NAME("lm3s6965evb"), 1384 .parent = TYPE_MACHINE, 1385 .class_init = lm3s6965evb_class_init, 1386 }; 1387 1388 static void stellaris_machine_init(void) 1389 { 1390 type_register_static(&lm3s811evb_type); 1391 type_register_static(&lm3s6965evb_type); 1392 } 1393 1394 type_init(stellaris_machine_init) 1395 1396 static void stellaris_i2c_class_init(ObjectClass *klass, void *data) 1397 { 1398 DeviceClass *dc = DEVICE_CLASS(klass); 1399 1400 dc->vmsd = &vmstate_stellaris_i2c; 1401 } 1402 1403 static const TypeInfo stellaris_i2c_info = { 1404 .name = TYPE_STELLARIS_I2C, 1405 .parent = TYPE_SYS_BUS_DEVICE, 1406 .instance_size = sizeof(stellaris_i2c_state), 1407 .instance_init = stellaris_i2c_init, 1408 .class_init = stellaris_i2c_class_init, 1409 }; 1410 1411 static void stellaris_adc_class_init(ObjectClass *klass, void *data) 1412 { 1413 DeviceClass *dc = DEVICE_CLASS(klass); 1414 1415 dc->vmsd = &vmstate_stellaris_adc; 1416 } 1417 1418 static const TypeInfo stellaris_adc_info = { 1419 .name = TYPE_STELLARIS_ADC, 1420 .parent = TYPE_SYS_BUS_DEVICE, 1421 .instance_size = sizeof(StellarisADCState), 1422 .instance_init = stellaris_adc_init, 1423 .class_init = stellaris_adc_class_init, 1424 }; 1425 1426 static void stellaris_sys_class_init(ObjectClass *klass, void *data) 1427 { 1428 DeviceClass *dc = DEVICE_CLASS(klass); 1429 ResettableClass *rc = RESETTABLE_CLASS(klass); 1430 1431 dc->vmsd = &vmstate_stellaris_sys; 1432 rc->phases.enter = stellaris_sys_reset_enter; 1433 rc->phases.hold = stellaris_sys_reset_hold; 1434 rc->phases.exit = stellaris_sys_reset_exit; 1435 device_class_set_props(dc, stellaris_sys_properties); 1436 } 1437 1438 static const TypeInfo stellaris_sys_info = { 1439 .name = TYPE_STELLARIS_SYS, 1440 .parent = TYPE_SYS_BUS_DEVICE, 1441 .instance_size = sizeof(ssys_state), 1442 .instance_init = stellaris_sys_instance_init, 1443 .class_init = stellaris_sys_class_init, 1444 }; 1445 1446 static void stellaris_register_types(void) 1447 { 1448 type_register_static(&stellaris_i2c_info); 1449 type_register_static(&stellaris_adc_info); 1450 type_register_static(&stellaris_sys_info); 1451 } 1452 1453 type_init(stellaris_register_types) 1454