1 /* 2 * Luminary Micro Stellaris peripherals 3 * 4 * Copyright (c) 2006 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qapi/error.h" 12 #include "hw/sysbus.h" 13 #include "hw/ssi/ssi.h" 14 #include "hw/arm/boot.h" 15 #include "qemu/timer.h" 16 #include "hw/i2c/i2c.h" 17 #include "net/net.h" 18 #include "hw/boards.h" 19 #include "qemu/log.h" 20 #include "exec/address-spaces.h" 21 #include "sysemu/sysemu.h" 22 #include "hw/arm/armv7m.h" 23 #include "hw/char/pl011.h" 24 #include "hw/input/gamepad.h" 25 #include "hw/irq.h" 26 #include "hw/watchdog/cmsdk-apb-watchdog.h" 27 #include "migration/vmstate.h" 28 #include "hw/misc/unimp.h" 29 #include "hw/qdev-clock.h" 30 #include "qom/object.h" 31 32 #define GPIO_A 0 33 #define GPIO_B 1 34 #define GPIO_C 2 35 #define GPIO_D 3 36 #define GPIO_E 4 37 #define GPIO_F 5 38 #define GPIO_G 6 39 40 #define BP_OLED_I2C 0x01 41 #define BP_OLED_SSI 0x02 42 #define BP_GAMEPAD 0x04 43 44 #define NUM_IRQ_LINES 64 45 46 typedef const struct { 47 const char *name; 48 uint32_t did0; 49 uint32_t did1; 50 uint32_t dc0; 51 uint32_t dc1; 52 uint32_t dc2; 53 uint32_t dc3; 54 uint32_t dc4; 55 uint32_t peripherals; 56 } stellaris_board_info; 57 58 /* General purpose timer module. */ 59 60 #define TYPE_STELLARIS_GPTM "stellaris-gptm" 61 OBJECT_DECLARE_SIMPLE_TYPE(gptm_state, STELLARIS_GPTM) 62 63 struct gptm_state { 64 SysBusDevice parent_obj; 65 66 MemoryRegion iomem; 67 uint32_t config; 68 uint32_t mode[2]; 69 uint32_t control; 70 uint32_t state; 71 uint32_t mask; 72 uint32_t load[2]; 73 uint32_t match[2]; 74 uint32_t prescale[2]; 75 uint32_t match_prescale[2]; 76 uint32_t rtc; 77 int64_t tick[2]; 78 struct gptm_state *opaque[2]; 79 QEMUTimer *timer[2]; 80 /* The timers have an alternate output used to trigger the ADC. */ 81 qemu_irq trigger; 82 qemu_irq irq; 83 }; 84 85 static void gptm_update_irq(gptm_state *s) 86 { 87 int level; 88 level = (s->state & s->mask) != 0; 89 qemu_set_irq(s->irq, level); 90 } 91 92 static void gptm_stop(gptm_state *s, int n) 93 { 94 timer_del(s->timer[n]); 95 } 96 97 static void gptm_reload(gptm_state *s, int n, int reset) 98 { 99 int64_t tick; 100 if (reset) 101 tick = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 102 else 103 tick = s->tick[n]; 104 105 if (s->config == 0) { 106 /* 32-bit CountDown. */ 107 uint32_t count; 108 count = s->load[0] | (s->load[1] << 16); 109 tick += (int64_t)count * system_clock_scale; 110 } else if (s->config == 1) { 111 /* 32-bit RTC. 1Hz tick. */ 112 tick += NANOSECONDS_PER_SECOND; 113 } else if (s->mode[n] == 0xa) { 114 /* PWM mode. Not implemented. */ 115 } else { 116 qemu_log_mask(LOG_UNIMP, 117 "GPTM: 16-bit timer mode unimplemented: 0x%x\n", 118 s->mode[n]); 119 return; 120 } 121 s->tick[n] = tick; 122 timer_mod(s->timer[n], tick); 123 } 124 125 static void gptm_tick(void *opaque) 126 { 127 gptm_state **p = (gptm_state **)opaque; 128 gptm_state *s; 129 int n; 130 131 s = *p; 132 n = p - s->opaque; 133 if (s->config == 0) { 134 s->state |= 1; 135 if ((s->control & 0x20)) { 136 /* Output trigger. */ 137 qemu_irq_pulse(s->trigger); 138 } 139 if (s->mode[0] & 1) { 140 /* One-shot. */ 141 s->control &= ~1; 142 } else { 143 /* Periodic. */ 144 gptm_reload(s, 0, 0); 145 } 146 } else if (s->config == 1) { 147 /* RTC. */ 148 uint32_t match; 149 s->rtc++; 150 match = s->match[0] | (s->match[1] << 16); 151 if (s->rtc > match) 152 s->rtc = 0; 153 if (s->rtc == 0) { 154 s->state |= 8; 155 } 156 gptm_reload(s, 0, 0); 157 } else if (s->mode[n] == 0xa) { 158 /* PWM mode. Not implemented. */ 159 } else { 160 qemu_log_mask(LOG_UNIMP, 161 "GPTM: 16-bit timer mode unimplemented: 0x%x\n", 162 s->mode[n]); 163 } 164 gptm_update_irq(s); 165 } 166 167 static uint64_t gptm_read(void *opaque, hwaddr offset, 168 unsigned size) 169 { 170 gptm_state *s = (gptm_state *)opaque; 171 172 switch (offset) { 173 case 0x00: /* CFG */ 174 return s->config; 175 case 0x04: /* TAMR */ 176 return s->mode[0]; 177 case 0x08: /* TBMR */ 178 return s->mode[1]; 179 case 0x0c: /* CTL */ 180 return s->control; 181 case 0x18: /* IMR */ 182 return s->mask; 183 case 0x1c: /* RIS */ 184 return s->state; 185 case 0x20: /* MIS */ 186 return s->state & s->mask; 187 case 0x24: /* CR */ 188 return 0; 189 case 0x28: /* TAILR */ 190 return s->load[0] | ((s->config < 4) ? (s->load[1] << 16) : 0); 191 case 0x2c: /* TBILR */ 192 return s->load[1]; 193 case 0x30: /* TAMARCHR */ 194 return s->match[0] | ((s->config < 4) ? (s->match[1] << 16) : 0); 195 case 0x34: /* TBMATCHR */ 196 return s->match[1]; 197 case 0x38: /* TAPR */ 198 return s->prescale[0]; 199 case 0x3c: /* TBPR */ 200 return s->prescale[1]; 201 case 0x40: /* TAPMR */ 202 return s->match_prescale[0]; 203 case 0x44: /* TBPMR */ 204 return s->match_prescale[1]; 205 case 0x48: /* TAR */ 206 if (s->config == 1) { 207 return s->rtc; 208 } 209 qemu_log_mask(LOG_UNIMP, 210 "GPTM: read of TAR but timer read not supported\n"); 211 return 0; 212 case 0x4c: /* TBR */ 213 qemu_log_mask(LOG_UNIMP, 214 "GPTM: read of TBR but timer read not supported\n"); 215 return 0; 216 default: 217 qemu_log_mask(LOG_GUEST_ERROR, 218 "GPTM: read at bad offset 0x02%" HWADDR_PRIx "\n", 219 offset); 220 return 0; 221 } 222 } 223 224 static void gptm_write(void *opaque, hwaddr offset, 225 uint64_t value, unsigned size) 226 { 227 gptm_state *s = (gptm_state *)opaque; 228 uint32_t oldval; 229 230 /* The timers should be disabled before changing the configuration. 231 We take advantage of this and defer everything until the timer 232 is enabled. */ 233 switch (offset) { 234 case 0x00: /* CFG */ 235 s->config = value; 236 break; 237 case 0x04: /* TAMR */ 238 s->mode[0] = value; 239 break; 240 case 0x08: /* TBMR */ 241 s->mode[1] = value; 242 break; 243 case 0x0c: /* CTL */ 244 oldval = s->control; 245 s->control = value; 246 /* TODO: Implement pause. */ 247 if ((oldval ^ value) & 1) { 248 if (value & 1) { 249 gptm_reload(s, 0, 1); 250 } else { 251 gptm_stop(s, 0); 252 } 253 } 254 if (((oldval ^ value) & 0x100) && s->config >= 4) { 255 if (value & 0x100) { 256 gptm_reload(s, 1, 1); 257 } else { 258 gptm_stop(s, 1); 259 } 260 } 261 break; 262 case 0x18: /* IMR */ 263 s->mask = value & 0x77; 264 gptm_update_irq(s); 265 break; 266 case 0x24: /* CR */ 267 s->state &= ~value; 268 break; 269 case 0x28: /* TAILR */ 270 s->load[0] = value & 0xffff; 271 if (s->config < 4) { 272 s->load[1] = value >> 16; 273 } 274 break; 275 case 0x2c: /* TBILR */ 276 s->load[1] = value & 0xffff; 277 break; 278 case 0x30: /* TAMARCHR */ 279 s->match[0] = value & 0xffff; 280 if (s->config < 4) { 281 s->match[1] = value >> 16; 282 } 283 break; 284 case 0x34: /* TBMATCHR */ 285 s->match[1] = value >> 16; 286 break; 287 case 0x38: /* TAPR */ 288 s->prescale[0] = value; 289 break; 290 case 0x3c: /* TBPR */ 291 s->prescale[1] = value; 292 break; 293 case 0x40: /* TAPMR */ 294 s->match_prescale[0] = value; 295 break; 296 case 0x44: /* TBPMR */ 297 s->match_prescale[0] = value; 298 break; 299 default: 300 qemu_log_mask(LOG_GUEST_ERROR, 301 "GPTM: write at bad offset 0x02%" HWADDR_PRIx "\n", 302 offset); 303 } 304 gptm_update_irq(s); 305 } 306 307 static const MemoryRegionOps gptm_ops = { 308 .read = gptm_read, 309 .write = gptm_write, 310 .endianness = DEVICE_NATIVE_ENDIAN, 311 }; 312 313 static const VMStateDescription vmstate_stellaris_gptm = { 314 .name = "stellaris_gptm", 315 .version_id = 1, 316 .minimum_version_id = 1, 317 .fields = (VMStateField[]) { 318 VMSTATE_UINT32(config, gptm_state), 319 VMSTATE_UINT32_ARRAY(mode, gptm_state, 2), 320 VMSTATE_UINT32(control, gptm_state), 321 VMSTATE_UINT32(state, gptm_state), 322 VMSTATE_UINT32(mask, gptm_state), 323 VMSTATE_UNUSED(8), 324 VMSTATE_UINT32_ARRAY(load, gptm_state, 2), 325 VMSTATE_UINT32_ARRAY(match, gptm_state, 2), 326 VMSTATE_UINT32_ARRAY(prescale, gptm_state, 2), 327 VMSTATE_UINT32_ARRAY(match_prescale, gptm_state, 2), 328 VMSTATE_UINT32(rtc, gptm_state), 329 VMSTATE_INT64_ARRAY(tick, gptm_state, 2), 330 VMSTATE_TIMER_PTR_ARRAY(timer, gptm_state, 2), 331 VMSTATE_END_OF_LIST() 332 } 333 }; 334 335 static void stellaris_gptm_init(Object *obj) 336 { 337 DeviceState *dev = DEVICE(obj); 338 gptm_state *s = STELLARIS_GPTM(obj); 339 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 340 341 sysbus_init_irq(sbd, &s->irq); 342 qdev_init_gpio_out(dev, &s->trigger, 1); 343 344 memory_region_init_io(&s->iomem, obj, &gptm_ops, s, 345 "gptm", 0x1000); 346 sysbus_init_mmio(sbd, &s->iomem); 347 348 s->opaque[0] = s->opaque[1] = s; 349 } 350 351 static void stellaris_gptm_realize(DeviceState *dev, Error **errp) 352 { 353 gptm_state *s = STELLARIS_GPTM(dev); 354 s->timer[0] = timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque[0]); 355 s->timer[1] = timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque[1]); 356 } 357 358 /* System controller. */ 359 360 #define TYPE_STELLARIS_SYS "stellaris-sys" 361 OBJECT_DECLARE_SIMPLE_TYPE(ssys_state, STELLARIS_SYS) 362 363 struct ssys_state { 364 SysBusDevice parent_obj; 365 366 MemoryRegion iomem; 367 uint32_t pborctl; 368 uint32_t ldopctl; 369 uint32_t int_status; 370 uint32_t int_mask; 371 uint32_t resc; 372 uint32_t rcc; 373 uint32_t rcc2; 374 uint32_t rcgc[3]; 375 uint32_t scgc[3]; 376 uint32_t dcgc[3]; 377 uint32_t clkvclr; 378 uint32_t ldoarst; 379 qemu_irq irq; 380 Clock *sysclk; 381 /* Properties (all read-only registers) */ 382 uint32_t user0; 383 uint32_t user1; 384 uint32_t did0; 385 uint32_t did1; 386 uint32_t dc0; 387 uint32_t dc1; 388 uint32_t dc2; 389 uint32_t dc3; 390 uint32_t dc4; 391 }; 392 393 static void ssys_update(ssys_state *s) 394 { 395 qemu_set_irq(s->irq, (s->int_status & s->int_mask) != 0); 396 } 397 398 static uint32_t pllcfg_sandstorm[16] = { 399 0x31c0, /* 1 Mhz */ 400 0x1ae0, /* 1.8432 Mhz */ 401 0x18c0, /* 2 Mhz */ 402 0xd573, /* 2.4576 Mhz */ 403 0x37a6, /* 3.57954 Mhz */ 404 0x1ae2, /* 3.6864 Mhz */ 405 0x0c40, /* 4 Mhz */ 406 0x98bc, /* 4.906 Mhz */ 407 0x935b, /* 4.9152 Mhz */ 408 0x09c0, /* 5 Mhz */ 409 0x4dee, /* 5.12 Mhz */ 410 0x0c41, /* 6 Mhz */ 411 0x75db, /* 6.144 Mhz */ 412 0x1ae6, /* 7.3728 Mhz */ 413 0x0600, /* 8 Mhz */ 414 0x585b /* 8.192 Mhz */ 415 }; 416 417 static uint32_t pllcfg_fury[16] = { 418 0x3200, /* 1 Mhz */ 419 0x1b20, /* 1.8432 Mhz */ 420 0x1900, /* 2 Mhz */ 421 0xf42b, /* 2.4576 Mhz */ 422 0x37e3, /* 3.57954 Mhz */ 423 0x1b21, /* 3.6864 Mhz */ 424 0x0c80, /* 4 Mhz */ 425 0x98ee, /* 4.906 Mhz */ 426 0xd5b4, /* 4.9152 Mhz */ 427 0x0a00, /* 5 Mhz */ 428 0x4e27, /* 5.12 Mhz */ 429 0x1902, /* 6 Mhz */ 430 0xec1c, /* 6.144 Mhz */ 431 0x1b23, /* 7.3728 Mhz */ 432 0x0640, /* 8 Mhz */ 433 0xb11c /* 8.192 Mhz */ 434 }; 435 436 #define DID0_VER_MASK 0x70000000 437 #define DID0_VER_0 0x00000000 438 #define DID0_VER_1 0x10000000 439 440 #define DID0_CLASS_MASK 0x00FF0000 441 #define DID0_CLASS_SANDSTORM 0x00000000 442 #define DID0_CLASS_FURY 0x00010000 443 444 static int ssys_board_class(const ssys_state *s) 445 { 446 uint32_t did0 = s->did0; 447 switch (did0 & DID0_VER_MASK) { 448 case DID0_VER_0: 449 return DID0_CLASS_SANDSTORM; 450 case DID0_VER_1: 451 switch (did0 & DID0_CLASS_MASK) { 452 case DID0_CLASS_SANDSTORM: 453 case DID0_CLASS_FURY: 454 return did0 & DID0_CLASS_MASK; 455 } 456 /* for unknown classes, fall through */ 457 default: 458 /* This can only happen if the hardwired constant did0 value 459 * in this board's stellaris_board_info struct is wrong. 460 */ 461 g_assert_not_reached(); 462 } 463 } 464 465 static uint64_t ssys_read(void *opaque, hwaddr offset, 466 unsigned size) 467 { 468 ssys_state *s = (ssys_state *)opaque; 469 470 switch (offset) { 471 case 0x000: /* DID0 */ 472 return s->did0; 473 case 0x004: /* DID1 */ 474 return s->did1; 475 case 0x008: /* DC0 */ 476 return s->dc0; 477 case 0x010: /* DC1 */ 478 return s->dc1; 479 case 0x014: /* DC2 */ 480 return s->dc2; 481 case 0x018: /* DC3 */ 482 return s->dc3; 483 case 0x01c: /* DC4 */ 484 return s->dc4; 485 case 0x030: /* PBORCTL */ 486 return s->pborctl; 487 case 0x034: /* LDOPCTL */ 488 return s->ldopctl; 489 case 0x040: /* SRCR0 */ 490 return 0; 491 case 0x044: /* SRCR1 */ 492 return 0; 493 case 0x048: /* SRCR2 */ 494 return 0; 495 case 0x050: /* RIS */ 496 return s->int_status; 497 case 0x054: /* IMC */ 498 return s->int_mask; 499 case 0x058: /* MISC */ 500 return s->int_status & s->int_mask; 501 case 0x05c: /* RESC */ 502 return s->resc; 503 case 0x060: /* RCC */ 504 return s->rcc; 505 case 0x064: /* PLLCFG */ 506 { 507 int xtal; 508 xtal = (s->rcc >> 6) & 0xf; 509 switch (ssys_board_class(s)) { 510 case DID0_CLASS_FURY: 511 return pllcfg_fury[xtal]; 512 case DID0_CLASS_SANDSTORM: 513 return pllcfg_sandstorm[xtal]; 514 default: 515 g_assert_not_reached(); 516 } 517 } 518 case 0x070: /* RCC2 */ 519 return s->rcc2; 520 case 0x100: /* RCGC0 */ 521 return s->rcgc[0]; 522 case 0x104: /* RCGC1 */ 523 return s->rcgc[1]; 524 case 0x108: /* RCGC2 */ 525 return s->rcgc[2]; 526 case 0x110: /* SCGC0 */ 527 return s->scgc[0]; 528 case 0x114: /* SCGC1 */ 529 return s->scgc[1]; 530 case 0x118: /* SCGC2 */ 531 return s->scgc[2]; 532 case 0x120: /* DCGC0 */ 533 return s->dcgc[0]; 534 case 0x124: /* DCGC1 */ 535 return s->dcgc[1]; 536 case 0x128: /* DCGC2 */ 537 return s->dcgc[2]; 538 case 0x150: /* CLKVCLR */ 539 return s->clkvclr; 540 case 0x160: /* LDOARST */ 541 return s->ldoarst; 542 case 0x1e0: /* USER0 */ 543 return s->user0; 544 case 0x1e4: /* USER1 */ 545 return s->user1; 546 default: 547 qemu_log_mask(LOG_GUEST_ERROR, 548 "SSYS: read at bad offset 0x%x\n", (int)offset); 549 return 0; 550 } 551 } 552 553 static bool ssys_use_rcc2(ssys_state *s) 554 { 555 return (s->rcc2 >> 31) & 0x1; 556 } 557 558 /* 559 * Calculate the system clock period. We only want to propagate 560 * this change to the rest of the system if we're not being called 561 * from migration post-load. 562 */ 563 static void ssys_calculate_system_clock(ssys_state *s, bool propagate_clock) 564 { 565 /* 566 * SYSDIV field specifies divisor: 0 == /1, 1 == /2, etc. Input 567 * clock is 200MHz, which is a period of 5 ns. Dividing the clock 568 * frequency by X is the same as multiplying the period by X. 569 */ 570 if (ssys_use_rcc2(s)) { 571 system_clock_scale = 5 * (((s->rcc2 >> 23) & 0x3f) + 1); 572 } else { 573 system_clock_scale = 5 * (((s->rcc >> 23) & 0xf) + 1); 574 } 575 clock_set_ns(s->sysclk, system_clock_scale); 576 if (propagate_clock) { 577 clock_propagate(s->sysclk); 578 } 579 } 580 581 static void ssys_write(void *opaque, hwaddr offset, 582 uint64_t value, unsigned size) 583 { 584 ssys_state *s = (ssys_state *)opaque; 585 586 switch (offset) { 587 case 0x030: /* PBORCTL */ 588 s->pborctl = value & 0xffff; 589 break; 590 case 0x034: /* LDOPCTL */ 591 s->ldopctl = value & 0x1f; 592 break; 593 case 0x040: /* SRCR0 */ 594 case 0x044: /* SRCR1 */ 595 case 0x048: /* SRCR2 */ 596 qemu_log_mask(LOG_UNIMP, "Peripheral reset not implemented\n"); 597 break; 598 case 0x054: /* IMC */ 599 s->int_mask = value & 0x7f; 600 break; 601 case 0x058: /* MISC */ 602 s->int_status &= ~value; 603 break; 604 case 0x05c: /* RESC */ 605 s->resc = value & 0x3f; 606 break; 607 case 0x060: /* RCC */ 608 if ((s->rcc & (1 << 13)) != 0 && (value & (1 << 13)) == 0) { 609 /* PLL enable. */ 610 s->int_status |= (1 << 6); 611 } 612 s->rcc = value; 613 ssys_calculate_system_clock(s, true); 614 break; 615 case 0x070: /* RCC2 */ 616 if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) { 617 break; 618 } 619 620 if ((s->rcc2 & (1 << 13)) != 0 && (value & (1 << 13)) == 0) { 621 /* PLL enable. */ 622 s->int_status |= (1 << 6); 623 } 624 s->rcc2 = value; 625 ssys_calculate_system_clock(s, true); 626 break; 627 case 0x100: /* RCGC0 */ 628 s->rcgc[0] = value; 629 break; 630 case 0x104: /* RCGC1 */ 631 s->rcgc[1] = value; 632 break; 633 case 0x108: /* RCGC2 */ 634 s->rcgc[2] = value; 635 break; 636 case 0x110: /* SCGC0 */ 637 s->scgc[0] = value; 638 break; 639 case 0x114: /* SCGC1 */ 640 s->scgc[1] = value; 641 break; 642 case 0x118: /* SCGC2 */ 643 s->scgc[2] = value; 644 break; 645 case 0x120: /* DCGC0 */ 646 s->dcgc[0] = value; 647 break; 648 case 0x124: /* DCGC1 */ 649 s->dcgc[1] = value; 650 break; 651 case 0x128: /* DCGC2 */ 652 s->dcgc[2] = value; 653 break; 654 case 0x150: /* CLKVCLR */ 655 s->clkvclr = value; 656 break; 657 case 0x160: /* LDOARST */ 658 s->ldoarst = value; 659 break; 660 default: 661 qemu_log_mask(LOG_GUEST_ERROR, 662 "SSYS: write at bad offset 0x%x\n", (int)offset); 663 } 664 ssys_update(s); 665 } 666 667 static const MemoryRegionOps ssys_ops = { 668 .read = ssys_read, 669 .write = ssys_write, 670 .endianness = DEVICE_NATIVE_ENDIAN, 671 }; 672 673 static void stellaris_sys_reset_enter(Object *obj, ResetType type) 674 { 675 ssys_state *s = STELLARIS_SYS(obj); 676 677 s->pborctl = 0x7ffd; 678 s->rcc = 0x078e3ac0; 679 680 if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) { 681 s->rcc2 = 0; 682 } else { 683 s->rcc2 = 0x07802810; 684 } 685 s->rcgc[0] = 1; 686 s->scgc[0] = 1; 687 s->dcgc[0] = 1; 688 } 689 690 static void stellaris_sys_reset_hold(Object *obj) 691 { 692 ssys_state *s = STELLARIS_SYS(obj); 693 694 /* OK to propagate clocks from the hold phase */ 695 ssys_calculate_system_clock(s, true); 696 } 697 698 static void stellaris_sys_reset_exit(Object *obj) 699 { 700 } 701 702 static int stellaris_sys_post_load(void *opaque, int version_id) 703 { 704 ssys_state *s = opaque; 705 706 ssys_calculate_system_clock(s, false); 707 708 return 0; 709 } 710 711 static const VMStateDescription vmstate_stellaris_sys = { 712 .name = "stellaris_sys", 713 .version_id = 2, 714 .minimum_version_id = 1, 715 .post_load = stellaris_sys_post_load, 716 .fields = (VMStateField[]) { 717 VMSTATE_UINT32(pborctl, ssys_state), 718 VMSTATE_UINT32(ldopctl, ssys_state), 719 VMSTATE_UINT32(int_mask, ssys_state), 720 VMSTATE_UINT32(int_status, ssys_state), 721 VMSTATE_UINT32(resc, ssys_state), 722 VMSTATE_UINT32(rcc, ssys_state), 723 VMSTATE_UINT32_V(rcc2, ssys_state, 2), 724 VMSTATE_UINT32_ARRAY(rcgc, ssys_state, 3), 725 VMSTATE_UINT32_ARRAY(scgc, ssys_state, 3), 726 VMSTATE_UINT32_ARRAY(dcgc, ssys_state, 3), 727 VMSTATE_UINT32(clkvclr, ssys_state), 728 VMSTATE_UINT32(ldoarst, ssys_state), 729 /* No field for sysclk -- handled in post-load instead */ 730 VMSTATE_END_OF_LIST() 731 } 732 }; 733 734 static Property stellaris_sys_properties[] = { 735 DEFINE_PROP_UINT32("user0", ssys_state, user0, 0), 736 DEFINE_PROP_UINT32("user1", ssys_state, user1, 0), 737 DEFINE_PROP_UINT32("did0", ssys_state, did0, 0), 738 DEFINE_PROP_UINT32("did1", ssys_state, did1, 0), 739 DEFINE_PROP_UINT32("dc0", ssys_state, dc0, 0), 740 DEFINE_PROP_UINT32("dc1", ssys_state, dc1, 0), 741 DEFINE_PROP_UINT32("dc2", ssys_state, dc2, 0), 742 DEFINE_PROP_UINT32("dc3", ssys_state, dc3, 0), 743 DEFINE_PROP_UINT32("dc4", ssys_state, dc4, 0), 744 DEFINE_PROP_END_OF_LIST() 745 }; 746 747 static void stellaris_sys_instance_init(Object *obj) 748 { 749 ssys_state *s = STELLARIS_SYS(obj); 750 SysBusDevice *sbd = SYS_BUS_DEVICE(s); 751 752 memory_region_init_io(&s->iomem, obj, &ssys_ops, s, "ssys", 0x00001000); 753 sysbus_init_mmio(sbd, &s->iomem); 754 sysbus_init_irq(sbd, &s->irq); 755 s->sysclk = qdev_init_clock_out(DEVICE(s), "SYSCLK"); 756 } 757 758 static DeviceState *stellaris_sys_init(uint32_t base, qemu_irq irq, 759 stellaris_board_info *board, 760 uint8_t *macaddr) 761 { 762 DeviceState *dev = qdev_new(TYPE_STELLARIS_SYS); 763 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 764 765 /* Most devices come preprogrammed with a MAC address in the user data. */ 766 qdev_prop_set_uint32(dev, "user0", 767 macaddr[0] | (macaddr[1] << 8) | (macaddr[2] << 16)); 768 qdev_prop_set_uint32(dev, "user1", 769 macaddr[3] | (macaddr[4] << 8) | (macaddr[5] << 16)); 770 qdev_prop_set_uint32(dev, "did0", board->did0); 771 qdev_prop_set_uint32(dev, "did1", board->did1); 772 qdev_prop_set_uint32(dev, "dc0", board->dc0); 773 qdev_prop_set_uint32(dev, "dc1", board->dc1); 774 qdev_prop_set_uint32(dev, "dc2", board->dc2); 775 qdev_prop_set_uint32(dev, "dc3", board->dc3); 776 qdev_prop_set_uint32(dev, "dc4", board->dc4); 777 778 sysbus_realize_and_unref(sbd, &error_fatal); 779 sysbus_mmio_map(sbd, 0, base); 780 sysbus_connect_irq(sbd, 0, irq); 781 782 return dev; 783 } 784 785 /* I2C controller. */ 786 787 #define TYPE_STELLARIS_I2C "stellaris-i2c" 788 OBJECT_DECLARE_SIMPLE_TYPE(stellaris_i2c_state, STELLARIS_I2C) 789 790 struct stellaris_i2c_state { 791 SysBusDevice parent_obj; 792 793 I2CBus *bus; 794 qemu_irq irq; 795 MemoryRegion iomem; 796 uint32_t msa; 797 uint32_t mcs; 798 uint32_t mdr; 799 uint32_t mtpr; 800 uint32_t mimr; 801 uint32_t mris; 802 uint32_t mcr; 803 }; 804 805 #define STELLARIS_I2C_MCS_BUSY 0x01 806 #define STELLARIS_I2C_MCS_ERROR 0x02 807 #define STELLARIS_I2C_MCS_ADRACK 0x04 808 #define STELLARIS_I2C_MCS_DATACK 0x08 809 #define STELLARIS_I2C_MCS_ARBLST 0x10 810 #define STELLARIS_I2C_MCS_IDLE 0x20 811 #define STELLARIS_I2C_MCS_BUSBSY 0x40 812 813 static uint64_t stellaris_i2c_read(void *opaque, hwaddr offset, 814 unsigned size) 815 { 816 stellaris_i2c_state *s = (stellaris_i2c_state *)opaque; 817 818 switch (offset) { 819 case 0x00: /* MSA */ 820 return s->msa; 821 case 0x04: /* MCS */ 822 /* We don't emulate timing, so the controller is never busy. */ 823 return s->mcs | STELLARIS_I2C_MCS_IDLE; 824 case 0x08: /* MDR */ 825 return s->mdr; 826 case 0x0c: /* MTPR */ 827 return s->mtpr; 828 case 0x10: /* MIMR */ 829 return s->mimr; 830 case 0x14: /* MRIS */ 831 return s->mris; 832 case 0x18: /* MMIS */ 833 return s->mris & s->mimr; 834 case 0x20: /* MCR */ 835 return s->mcr; 836 default: 837 qemu_log_mask(LOG_GUEST_ERROR, 838 "stellaris_i2c: read at bad offset 0x%x\n", (int)offset); 839 return 0; 840 } 841 } 842 843 static void stellaris_i2c_update(stellaris_i2c_state *s) 844 { 845 int level; 846 847 level = (s->mris & s->mimr) != 0; 848 qemu_set_irq(s->irq, level); 849 } 850 851 static void stellaris_i2c_write(void *opaque, hwaddr offset, 852 uint64_t value, unsigned size) 853 { 854 stellaris_i2c_state *s = (stellaris_i2c_state *)opaque; 855 856 switch (offset) { 857 case 0x00: /* MSA */ 858 s->msa = value & 0xff; 859 break; 860 case 0x04: /* MCS */ 861 if ((s->mcr & 0x10) == 0) { 862 /* Disabled. Do nothing. */ 863 break; 864 } 865 /* Grab the bus if this is starting a transfer. */ 866 if ((value & 2) && (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) { 867 if (i2c_start_transfer(s->bus, s->msa >> 1, s->msa & 1)) { 868 s->mcs |= STELLARIS_I2C_MCS_ARBLST; 869 } else { 870 s->mcs &= ~STELLARIS_I2C_MCS_ARBLST; 871 s->mcs |= STELLARIS_I2C_MCS_BUSBSY; 872 } 873 } 874 /* If we don't have the bus then indicate an error. */ 875 if (!i2c_bus_busy(s->bus) 876 || (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) { 877 s->mcs |= STELLARIS_I2C_MCS_ERROR; 878 break; 879 } 880 s->mcs &= ~STELLARIS_I2C_MCS_ERROR; 881 if (value & 1) { 882 /* Transfer a byte. */ 883 /* TODO: Handle errors. */ 884 if (s->msa & 1) { 885 /* Recv */ 886 s->mdr = i2c_recv(s->bus); 887 } else { 888 /* Send */ 889 i2c_send(s->bus, s->mdr); 890 } 891 /* Raise an interrupt. */ 892 s->mris |= 1; 893 } 894 if (value & 4) { 895 /* Finish transfer. */ 896 i2c_end_transfer(s->bus); 897 s->mcs &= ~STELLARIS_I2C_MCS_BUSBSY; 898 } 899 break; 900 case 0x08: /* MDR */ 901 s->mdr = value & 0xff; 902 break; 903 case 0x0c: /* MTPR */ 904 s->mtpr = value & 0xff; 905 break; 906 case 0x10: /* MIMR */ 907 s->mimr = 1; 908 break; 909 case 0x1c: /* MICR */ 910 s->mris &= ~value; 911 break; 912 case 0x20: /* MCR */ 913 if (value & 1) { 914 qemu_log_mask(LOG_UNIMP, 915 "stellaris_i2c: Loopback not implemented\n"); 916 } 917 if (value & 0x20) { 918 qemu_log_mask(LOG_UNIMP, 919 "stellaris_i2c: Slave mode not implemented\n"); 920 } 921 s->mcr = value & 0x31; 922 break; 923 default: 924 qemu_log_mask(LOG_GUEST_ERROR, 925 "stellaris_i2c: write at bad offset 0x%x\n", (int)offset); 926 } 927 stellaris_i2c_update(s); 928 } 929 930 static void stellaris_i2c_reset(stellaris_i2c_state *s) 931 { 932 if (s->mcs & STELLARIS_I2C_MCS_BUSBSY) 933 i2c_end_transfer(s->bus); 934 935 s->msa = 0; 936 s->mcs = 0; 937 s->mdr = 0; 938 s->mtpr = 1; 939 s->mimr = 0; 940 s->mris = 0; 941 s->mcr = 0; 942 stellaris_i2c_update(s); 943 } 944 945 static const MemoryRegionOps stellaris_i2c_ops = { 946 .read = stellaris_i2c_read, 947 .write = stellaris_i2c_write, 948 .endianness = DEVICE_NATIVE_ENDIAN, 949 }; 950 951 static const VMStateDescription vmstate_stellaris_i2c = { 952 .name = "stellaris_i2c", 953 .version_id = 1, 954 .minimum_version_id = 1, 955 .fields = (VMStateField[]) { 956 VMSTATE_UINT32(msa, stellaris_i2c_state), 957 VMSTATE_UINT32(mcs, stellaris_i2c_state), 958 VMSTATE_UINT32(mdr, stellaris_i2c_state), 959 VMSTATE_UINT32(mtpr, stellaris_i2c_state), 960 VMSTATE_UINT32(mimr, stellaris_i2c_state), 961 VMSTATE_UINT32(mris, stellaris_i2c_state), 962 VMSTATE_UINT32(mcr, stellaris_i2c_state), 963 VMSTATE_END_OF_LIST() 964 } 965 }; 966 967 static void stellaris_i2c_init(Object *obj) 968 { 969 DeviceState *dev = DEVICE(obj); 970 stellaris_i2c_state *s = STELLARIS_I2C(obj); 971 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 972 I2CBus *bus; 973 974 sysbus_init_irq(sbd, &s->irq); 975 bus = i2c_init_bus(dev, "i2c"); 976 s->bus = bus; 977 978 memory_region_init_io(&s->iomem, obj, &stellaris_i2c_ops, s, 979 "i2c", 0x1000); 980 sysbus_init_mmio(sbd, &s->iomem); 981 /* ??? For now we only implement the master interface. */ 982 stellaris_i2c_reset(s); 983 } 984 985 /* Analogue to Digital Converter. This is only partially implemented, 986 enough for applications that use a combined ADC and timer tick. */ 987 988 #define STELLARIS_ADC_EM_CONTROLLER 0 989 #define STELLARIS_ADC_EM_COMP 1 990 #define STELLARIS_ADC_EM_EXTERNAL 4 991 #define STELLARIS_ADC_EM_TIMER 5 992 #define STELLARIS_ADC_EM_PWM0 6 993 #define STELLARIS_ADC_EM_PWM1 7 994 #define STELLARIS_ADC_EM_PWM2 8 995 996 #define STELLARIS_ADC_FIFO_EMPTY 0x0100 997 #define STELLARIS_ADC_FIFO_FULL 0x1000 998 999 #define TYPE_STELLARIS_ADC "stellaris-adc" 1000 typedef struct StellarisADCState stellaris_adc_state; 1001 DECLARE_INSTANCE_CHECKER(stellaris_adc_state, STELLARIS_ADC, 1002 TYPE_STELLARIS_ADC) 1003 1004 struct StellarisADCState { 1005 SysBusDevice parent_obj; 1006 1007 MemoryRegion iomem; 1008 uint32_t actss; 1009 uint32_t ris; 1010 uint32_t im; 1011 uint32_t emux; 1012 uint32_t ostat; 1013 uint32_t ustat; 1014 uint32_t sspri; 1015 uint32_t sac; 1016 struct { 1017 uint32_t state; 1018 uint32_t data[16]; 1019 } fifo[4]; 1020 uint32_t ssmux[4]; 1021 uint32_t ssctl[4]; 1022 uint32_t noise; 1023 qemu_irq irq[4]; 1024 }; 1025 1026 static uint32_t stellaris_adc_fifo_read(stellaris_adc_state *s, int n) 1027 { 1028 int tail; 1029 1030 tail = s->fifo[n].state & 0xf; 1031 if (s->fifo[n].state & STELLARIS_ADC_FIFO_EMPTY) { 1032 s->ustat |= 1 << n; 1033 } else { 1034 s->fifo[n].state = (s->fifo[n].state & ~0xf) | ((tail + 1) & 0xf); 1035 s->fifo[n].state &= ~STELLARIS_ADC_FIFO_FULL; 1036 if (tail + 1 == ((s->fifo[n].state >> 4) & 0xf)) 1037 s->fifo[n].state |= STELLARIS_ADC_FIFO_EMPTY; 1038 } 1039 return s->fifo[n].data[tail]; 1040 } 1041 1042 static void stellaris_adc_fifo_write(stellaris_adc_state *s, int n, 1043 uint32_t value) 1044 { 1045 int head; 1046 1047 /* TODO: Real hardware has limited size FIFOs. We have a full 16 entry 1048 FIFO fir each sequencer. */ 1049 head = (s->fifo[n].state >> 4) & 0xf; 1050 if (s->fifo[n].state & STELLARIS_ADC_FIFO_FULL) { 1051 s->ostat |= 1 << n; 1052 return; 1053 } 1054 s->fifo[n].data[head] = value; 1055 head = (head + 1) & 0xf; 1056 s->fifo[n].state &= ~STELLARIS_ADC_FIFO_EMPTY; 1057 s->fifo[n].state = (s->fifo[n].state & ~0xf0) | (head << 4); 1058 if ((s->fifo[n].state & 0xf) == head) 1059 s->fifo[n].state |= STELLARIS_ADC_FIFO_FULL; 1060 } 1061 1062 static void stellaris_adc_update(stellaris_adc_state *s) 1063 { 1064 int level; 1065 int n; 1066 1067 for (n = 0; n < 4; n++) { 1068 level = (s->ris & s->im & (1 << n)) != 0; 1069 qemu_set_irq(s->irq[n], level); 1070 } 1071 } 1072 1073 static void stellaris_adc_trigger(void *opaque, int irq, int level) 1074 { 1075 stellaris_adc_state *s = (stellaris_adc_state *)opaque; 1076 int n; 1077 1078 for (n = 0; n < 4; n++) { 1079 if ((s->actss & (1 << n)) == 0) { 1080 continue; 1081 } 1082 1083 if (((s->emux >> (n * 4)) & 0xff) != 5) { 1084 continue; 1085 } 1086 1087 /* Some applications use the ADC as a random number source, so introduce 1088 some variation into the signal. */ 1089 s->noise = s->noise * 314159 + 1; 1090 /* ??? actual inputs not implemented. Return an arbitrary value. */ 1091 stellaris_adc_fifo_write(s, n, 0x200 + ((s->noise >> 16) & 7)); 1092 s->ris |= (1 << n); 1093 stellaris_adc_update(s); 1094 } 1095 } 1096 1097 static void stellaris_adc_reset(stellaris_adc_state *s) 1098 { 1099 int n; 1100 1101 for (n = 0; n < 4; n++) { 1102 s->ssmux[n] = 0; 1103 s->ssctl[n] = 0; 1104 s->fifo[n].state = STELLARIS_ADC_FIFO_EMPTY; 1105 } 1106 } 1107 1108 static uint64_t stellaris_adc_read(void *opaque, hwaddr offset, 1109 unsigned size) 1110 { 1111 stellaris_adc_state *s = (stellaris_adc_state *)opaque; 1112 1113 /* TODO: Implement this. */ 1114 if (offset >= 0x40 && offset < 0xc0) { 1115 int n; 1116 n = (offset - 0x40) >> 5; 1117 switch (offset & 0x1f) { 1118 case 0x00: /* SSMUX */ 1119 return s->ssmux[n]; 1120 case 0x04: /* SSCTL */ 1121 return s->ssctl[n]; 1122 case 0x08: /* SSFIFO */ 1123 return stellaris_adc_fifo_read(s, n); 1124 case 0x0c: /* SSFSTAT */ 1125 return s->fifo[n].state; 1126 default: 1127 break; 1128 } 1129 } 1130 switch (offset) { 1131 case 0x00: /* ACTSS */ 1132 return s->actss; 1133 case 0x04: /* RIS */ 1134 return s->ris; 1135 case 0x08: /* IM */ 1136 return s->im; 1137 case 0x0c: /* ISC */ 1138 return s->ris & s->im; 1139 case 0x10: /* OSTAT */ 1140 return s->ostat; 1141 case 0x14: /* EMUX */ 1142 return s->emux; 1143 case 0x18: /* USTAT */ 1144 return s->ustat; 1145 case 0x20: /* SSPRI */ 1146 return s->sspri; 1147 case 0x30: /* SAC */ 1148 return s->sac; 1149 default: 1150 qemu_log_mask(LOG_GUEST_ERROR, 1151 "stellaris_adc: read at bad offset 0x%x\n", (int)offset); 1152 return 0; 1153 } 1154 } 1155 1156 static void stellaris_adc_write(void *opaque, hwaddr offset, 1157 uint64_t value, unsigned size) 1158 { 1159 stellaris_adc_state *s = (stellaris_adc_state *)opaque; 1160 1161 /* TODO: Implement this. */ 1162 if (offset >= 0x40 && offset < 0xc0) { 1163 int n; 1164 n = (offset - 0x40) >> 5; 1165 switch (offset & 0x1f) { 1166 case 0x00: /* SSMUX */ 1167 s->ssmux[n] = value & 0x33333333; 1168 return; 1169 case 0x04: /* SSCTL */ 1170 if (value != 6) { 1171 qemu_log_mask(LOG_UNIMP, 1172 "ADC: Unimplemented sequence %" PRIx64 "\n", 1173 value); 1174 } 1175 s->ssctl[n] = value; 1176 return; 1177 default: 1178 break; 1179 } 1180 } 1181 switch (offset) { 1182 case 0x00: /* ACTSS */ 1183 s->actss = value & 0xf; 1184 break; 1185 case 0x08: /* IM */ 1186 s->im = value; 1187 break; 1188 case 0x0c: /* ISC */ 1189 s->ris &= ~value; 1190 break; 1191 case 0x10: /* OSTAT */ 1192 s->ostat &= ~value; 1193 break; 1194 case 0x14: /* EMUX */ 1195 s->emux = value; 1196 break; 1197 case 0x18: /* USTAT */ 1198 s->ustat &= ~value; 1199 break; 1200 case 0x20: /* SSPRI */ 1201 s->sspri = value; 1202 break; 1203 case 0x28: /* PSSI */ 1204 qemu_log_mask(LOG_UNIMP, "ADC: sample initiate unimplemented\n"); 1205 break; 1206 case 0x30: /* SAC */ 1207 s->sac = value; 1208 break; 1209 default: 1210 qemu_log_mask(LOG_GUEST_ERROR, 1211 "stellaris_adc: write at bad offset 0x%x\n", (int)offset); 1212 } 1213 stellaris_adc_update(s); 1214 } 1215 1216 static const MemoryRegionOps stellaris_adc_ops = { 1217 .read = stellaris_adc_read, 1218 .write = stellaris_adc_write, 1219 .endianness = DEVICE_NATIVE_ENDIAN, 1220 }; 1221 1222 static const VMStateDescription vmstate_stellaris_adc = { 1223 .name = "stellaris_adc", 1224 .version_id = 1, 1225 .minimum_version_id = 1, 1226 .fields = (VMStateField[]) { 1227 VMSTATE_UINT32(actss, stellaris_adc_state), 1228 VMSTATE_UINT32(ris, stellaris_adc_state), 1229 VMSTATE_UINT32(im, stellaris_adc_state), 1230 VMSTATE_UINT32(emux, stellaris_adc_state), 1231 VMSTATE_UINT32(ostat, stellaris_adc_state), 1232 VMSTATE_UINT32(ustat, stellaris_adc_state), 1233 VMSTATE_UINT32(sspri, stellaris_adc_state), 1234 VMSTATE_UINT32(sac, stellaris_adc_state), 1235 VMSTATE_UINT32(fifo[0].state, stellaris_adc_state), 1236 VMSTATE_UINT32_ARRAY(fifo[0].data, stellaris_adc_state, 16), 1237 VMSTATE_UINT32(ssmux[0], stellaris_adc_state), 1238 VMSTATE_UINT32(ssctl[0], stellaris_adc_state), 1239 VMSTATE_UINT32(fifo[1].state, stellaris_adc_state), 1240 VMSTATE_UINT32_ARRAY(fifo[1].data, stellaris_adc_state, 16), 1241 VMSTATE_UINT32(ssmux[1], stellaris_adc_state), 1242 VMSTATE_UINT32(ssctl[1], stellaris_adc_state), 1243 VMSTATE_UINT32(fifo[2].state, stellaris_adc_state), 1244 VMSTATE_UINT32_ARRAY(fifo[2].data, stellaris_adc_state, 16), 1245 VMSTATE_UINT32(ssmux[2], stellaris_adc_state), 1246 VMSTATE_UINT32(ssctl[2], stellaris_adc_state), 1247 VMSTATE_UINT32(fifo[3].state, stellaris_adc_state), 1248 VMSTATE_UINT32_ARRAY(fifo[3].data, stellaris_adc_state, 16), 1249 VMSTATE_UINT32(ssmux[3], stellaris_adc_state), 1250 VMSTATE_UINT32(ssctl[3], stellaris_adc_state), 1251 VMSTATE_UINT32(noise, stellaris_adc_state), 1252 VMSTATE_END_OF_LIST() 1253 } 1254 }; 1255 1256 static void stellaris_adc_init(Object *obj) 1257 { 1258 DeviceState *dev = DEVICE(obj); 1259 stellaris_adc_state *s = STELLARIS_ADC(obj); 1260 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 1261 int n; 1262 1263 for (n = 0; n < 4; n++) { 1264 sysbus_init_irq(sbd, &s->irq[n]); 1265 } 1266 1267 memory_region_init_io(&s->iomem, obj, &stellaris_adc_ops, s, 1268 "adc", 0x1000); 1269 sysbus_init_mmio(sbd, &s->iomem); 1270 stellaris_adc_reset(s); 1271 qdev_init_gpio_in(dev, stellaris_adc_trigger, 1); 1272 } 1273 1274 /* Board init. */ 1275 static stellaris_board_info stellaris_boards[] = { 1276 { "LM3S811EVB", 1277 0, 1278 0x0032000e, 1279 0x001f001f, /* dc0 */ 1280 0x001132bf, 1281 0x01071013, 1282 0x3f0f01ff, 1283 0x0000001f, 1284 BP_OLED_I2C 1285 }, 1286 { "LM3S6965EVB", 1287 0x10010002, 1288 0x1073402e, 1289 0x00ff007f, /* dc0 */ 1290 0x001133ff, 1291 0x030f5317, 1292 0x0f0f87ff, 1293 0x5000007f, 1294 BP_OLED_SSI | BP_GAMEPAD 1295 } 1296 }; 1297 1298 static void stellaris_init(MachineState *ms, stellaris_board_info *board) 1299 { 1300 static const int uart_irq[] = {5, 6, 33, 34}; 1301 static const int timer_irq[] = {19, 21, 23, 35}; 1302 static const uint32_t gpio_addr[7] = 1303 { 0x40004000, 0x40005000, 0x40006000, 0x40007000, 1304 0x40024000, 0x40025000, 0x40026000}; 1305 static const int gpio_irq[7] = {0, 1, 2, 3, 4, 30, 31}; 1306 1307 /* Memory map of SoC devices, from 1308 * Stellaris LM3S6965 Microcontroller Data Sheet (rev I) 1309 * http://www.ti.com/lit/ds/symlink/lm3s6965.pdf 1310 * 1311 * 40000000 wdtimer 1312 * 40002000 i2c (unimplemented) 1313 * 40004000 GPIO 1314 * 40005000 GPIO 1315 * 40006000 GPIO 1316 * 40007000 GPIO 1317 * 40008000 SSI 1318 * 4000c000 UART 1319 * 4000d000 UART 1320 * 4000e000 UART 1321 * 40020000 i2c 1322 * 40021000 i2c (unimplemented) 1323 * 40024000 GPIO 1324 * 40025000 GPIO 1325 * 40026000 GPIO 1326 * 40028000 PWM (unimplemented) 1327 * 4002c000 QEI (unimplemented) 1328 * 4002d000 QEI (unimplemented) 1329 * 40030000 gptimer 1330 * 40031000 gptimer 1331 * 40032000 gptimer 1332 * 40033000 gptimer 1333 * 40038000 ADC 1334 * 4003c000 analogue comparator (unimplemented) 1335 * 40048000 ethernet 1336 * 400fc000 hibernation module (unimplemented) 1337 * 400fd000 flash memory control (unimplemented) 1338 * 400fe000 system control 1339 */ 1340 1341 DeviceState *gpio_dev[7], *nvic; 1342 qemu_irq gpio_in[7][8]; 1343 qemu_irq gpio_out[7][8]; 1344 qemu_irq adc; 1345 int sram_size; 1346 int flash_size; 1347 I2CBus *i2c; 1348 DeviceState *dev; 1349 DeviceState *ssys_dev; 1350 int i; 1351 int j; 1352 1353 MemoryRegion *sram = g_new(MemoryRegion, 1); 1354 MemoryRegion *flash = g_new(MemoryRegion, 1); 1355 MemoryRegion *system_memory = get_system_memory(); 1356 1357 flash_size = (((board->dc0 & 0xffff) + 1) << 1) * 1024; 1358 sram_size = ((board->dc0 >> 18) + 1) * 1024; 1359 1360 /* Flash programming is done via the SCU, so pretend it is ROM. */ 1361 memory_region_init_rom(flash, NULL, "stellaris.flash", flash_size, 1362 &error_fatal); 1363 memory_region_add_subregion(system_memory, 0, flash); 1364 1365 memory_region_init_ram(sram, NULL, "stellaris.sram", sram_size, 1366 &error_fatal); 1367 memory_region_add_subregion(system_memory, 0x20000000, sram); 1368 1369 nvic = qdev_new(TYPE_ARMV7M); 1370 qdev_prop_set_uint32(nvic, "num-irq", NUM_IRQ_LINES); 1371 qdev_prop_set_string(nvic, "cpu-type", ms->cpu_type); 1372 qdev_prop_set_bit(nvic, "enable-bitband", true); 1373 object_property_set_link(OBJECT(nvic), "memory", 1374 OBJECT(get_system_memory()), &error_abort); 1375 /* This will exit with an error if the user passed us a bad cpu_type */ 1376 sysbus_realize_and_unref(SYS_BUS_DEVICE(nvic), &error_fatal); 1377 1378 if (board->dc1 & (1 << 16)) { 1379 dev = sysbus_create_varargs(TYPE_STELLARIS_ADC, 0x40038000, 1380 qdev_get_gpio_in(nvic, 14), 1381 qdev_get_gpio_in(nvic, 15), 1382 qdev_get_gpio_in(nvic, 16), 1383 qdev_get_gpio_in(nvic, 17), 1384 NULL); 1385 adc = qdev_get_gpio_in(dev, 0); 1386 } else { 1387 adc = NULL; 1388 } 1389 for (i = 0; i < 4; i++) { 1390 if (board->dc2 & (0x10000 << i)) { 1391 dev = sysbus_create_simple(TYPE_STELLARIS_GPTM, 1392 0x40030000 + i * 0x1000, 1393 qdev_get_gpio_in(nvic, timer_irq[i])); 1394 /* TODO: This is incorrect, but we get away with it because 1395 the ADC output is only ever pulsed. */ 1396 qdev_connect_gpio_out(dev, 0, adc); 1397 } 1398 } 1399 1400 ssys_dev = stellaris_sys_init(0x400fe000, qdev_get_gpio_in(nvic, 28), 1401 board, nd_table[0].macaddr.a); 1402 1403 1404 if (board->dc1 & (1 << 3)) { /* watchdog present */ 1405 dev = qdev_new(TYPE_LUMINARY_WATCHDOG); 1406 1407 qdev_connect_clock_in(dev, "WDOGCLK", 1408 qdev_get_clock_out(ssys_dev, "SYSCLK")); 1409 1410 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1411 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1412 0, 1413 0x40000000u); 1414 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1415 0, 1416 qdev_get_gpio_in(nvic, 18)); 1417 } 1418 1419 1420 for (i = 0; i < 7; i++) { 1421 if (board->dc4 & (1 << i)) { 1422 gpio_dev[i] = sysbus_create_simple("pl061_luminary", gpio_addr[i], 1423 qdev_get_gpio_in(nvic, 1424 gpio_irq[i])); 1425 for (j = 0; j < 8; j++) { 1426 gpio_in[i][j] = qdev_get_gpio_in(gpio_dev[i], j); 1427 gpio_out[i][j] = NULL; 1428 } 1429 } 1430 } 1431 1432 if (board->dc2 & (1 << 12)) { 1433 dev = sysbus_create_simple(TYPE_STELLARIS_I2C, 0x40020000, 1434 qdev_get_gpio_in(nvic, 8)); 1435 i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c"); 1436 if (board->peripherals & BP_OLED_I2C) { 1437 i2c_slave_create_simple(i2c, "ssd0303", 0x3d); 1438 } 1439 } 1440 1441 for (i = 0; i < 4; i++) { 1442 if (board->dc2 & (1 << i)) { 1443 pl011_luminary_create(0x4000c000 + i * 0x1000, 1444 qdev_get_gpio_in(nvic, uart_irq[i]), 1445 serial_hd(i)); 1446 } 1447 } 1448 if (board->dc2 & (1 << 4)) { 1449 dev = sysbus_create_simple("pl022", 0x40008000, 1450 qdev_get_gpio_in(nvic, 7)); 1451 if (board->peripherals & BP_OLED_SSI) { 1452 void *bus; 1453 DeviceState *sddev; 1454 DeviceState *ssddev; 1455 1456 /* 1457 * Some boards have both an OLED controller and SD card connected to 1458 * the same SSI port, with the SD card chip select connected to a 1459 * GPIO pin. Technically the OLED chip select is connected to the 1460 * SSI Fss pin. We do not bother emulating that as both devices 1461 * should never be selected simultaneously, and our OLED controller 1462 * ignores stray 0xff commands that occur when deselecting the SD 1463 * card. 1464 * 1465 * The h/w wiring is: 1466 * - GPIO pin D0 is wired to the active-low SD card chip select 1467 * - GPIO pin A3 is wired to the active-low OLED chip select 1468 * - The SoC wiring of the PL061 "auxiliary function" for A3 is 1469 * SSI0Fss ("frame signal"), which is an output from the SoC's 1470 * SSI controller. The SSI controller takes SSI0Fss low when it 1471 * transmits a frame, so it can work as a chip-select signal. 1472 * - GPIO A4 is aux-function SSI0Rx, and wired to the SD card Tx 1473 * (the OLED never sends data to the CPU, so no wiring needed) 1474 * - GPIO A5 is aux-function SSI0Tx, and wired to the SD card Rx 1475 * and the OLED display-data-in 1476 * - GPIO A2 is aux-function SSI0Clk, wired to SD card and OLED 1477 * serial-clock input 1478 * So a guest that wants to use the OLED can configure the PL061 1479 * to make pins A2, A3, A5 aux-function, so they are connected 1480 * directly to the SSI controller. When the SSI controller sends 1481 * data it asserts SSI0Fss which selects the OLED. 1482 * A guest that wants to use the SD card configures A2, A4 and A5 1483 * as aux-function, but leaves A3 as a software-controlled GPIO 1484 * line. It asserts the SD card chip-select by using the PL061 1485 * to control pin D0, and lets the SSI controller handle Clk, Tx 1486 * and Rx. (The SSI controller asserts Fss during tx cycles as 1487 * usual, but because A3 is not set to aux-function this is not 1488 * forwarded to the OLED, and so the OLED stays unselected.) 1489 * 1490 * The QEMU implementation instead is: 1491 * - GPIO pin D0 is wired to the active-low SD card chip select, 1492 * and also to the OLED chip-select which is implemented 1493 * as *active-high* 1494 * - SSI controller signals go to the devices regardless of 1495 * whether the guest programs A2, A4, A5 as aux-function or not 1496 * 1497 * The problem with this implementation is if the guest doesn't 1498 * care about the SD card and only uses the OLED. In that case it 1499 * may choose never to do anything with D0 (leaving it in its 1500 * default floating state, which reliably leaves the card disabled 1501 * because an SD card has a pullup on CS within the card itself), 1502 * and only set up A2, A3, A5. This for us would mean the OLED 1503 * never gets the chip-select assert it needs. We work around 1504 * this with a manual raise of D0 here (despite board creation 1505 * code being the wrong place to raise IRQ lines) to put the OLED 1506 * into an initially selected state. 1507 * 1508 * In theory the right way to model this would be: 1509 * - Implement aux-function support in the PL061, with an 1510 * extra set of AFIN and AFOUT GPIO lines (set up so that 1511 * if a GPIO line is in auxfn mode the main GPIO in and out 1512 * track the AFIN and AFOUT lines) 1513 * - Wire the AFOUT for D0 up to either a line from the 1514 * SSI controller that's pulled low around every transmit, 1515 * or at least to an always-0 line here on the board 1516 * - Make the ssd0323 OLED controller chipselect active-low 1517 */ 1518 bus = qdev_get_child_bus(dev, "ssi"); 1519 1520 sddev = ssi_create_peripheral(bus, "ssi-sd"); 1521 ssddev = ssi_create_peripheral(bus, "ssd0323"); 1522 gpio_out[GPIO_D][0] = qemu_irq_split( 1523 qdev_get_gpio_in_named(sddev, SSI_GPIO_CS, 0), 1524 qdev_get_gpio_in_named(ssddev, SSI_GPIO_CS, 0)); 1525 gpio_out[GPIO_C][7] = qdev_get_gpio_in(ssddev, 0); 1526 1527 /* Make sure the select pin is high. */ 1528 qemu_irq_raise(gpio_out[GPIO_D][0]); 1529 } 1530 } 1531 if (board->dc4 & (1 << 28)) { 1532 DeviceState *enet; 1533 1534 qemu_check_nic_model(&nd_table[0], "stellaris"); 1535 1536 enet = qdev_new("stellaris_enet"); 1537 qdev_set_nic_properties(enet, &nd_table[0]); 1538 sysbus_realize_and_unref(SYS_BUS_DEVICE(enet), &error_fatal); 1539 sysbus_mmio_map(SYS_BUS_DEVICE(enet), 0, 0x40048000); 1540 sysbus_connect_irq(SYS_BUS_DEVICE(enet), 0, qdev_get_gpio_in(nvic, 42)); 1541 } 1542 if (board->peripherals & BP_GAMEPAD) { 1543 qemu_irq gpad_irq[5]; 1544 static const int gpad_keycode[5] = { 0xc8, 0xd0, 0xcb, 0xcd, 0x1d }; 1545 1546 gpad_irq[0] = qemu_irq_invert(gpio_in[GPIO_E][0]); /* up */ 1547 gpad_irq[1] = qemu_irq_invert(gpio_in[GPIO_E][1]); /* down */ 1548 gpad_irq[2] = qemu_irq_invert(gpio_in[GPIO_E][2]); /* left */ 1549 gpad_irq[3] = qemu_irq_invert(gpio_in[GPIO_E][3]); /* right */ 1550 gpad_irq[4] = qemu_irq_invert(gpio_in[GPIO_F][1]); /* select */ 1551 1552 stellaris_gamepad_init(5, gpad_irq, gpad_keycode); 1553 } 1554 for (i = 0; i < 7; i++) { 1555 if (board->dc4 & (1 << i)) { 1556 for (j = 0; j < 8; j++) { 1557 if (gpio_out[i][j]) { 1558 qdev_connect_gpio_out(gpio_dev[i], j, gpio_out[i][j]); 1559 } 1560 } 1561 } 1562 } 1563 1564 /* Add dummy regions for the devices we don't implement yet, 1565 * so guest accesses don't cause unlogged crashes. 1566 */ 1567 create_unimplemented_device("i2c-0", 0x40002000, 0x1000); 1568 create_unimplemented_device("i2c-2", 0x40021000, 0x1000); 1569 create_unimplemented_device("PWM", 0x40028000, 0x1000); 1570 create_unimplemented_device("QEI-0", 0x4002c000, 0x1000); 1571 create_unimplemented_device("QEI-1", 0x4002d000, 0x1000); 1572 create_unimplemented_device("analogue-comparator", 0x4003c000, 0x1000); 1573 create_unimplemented_device("hibernation", 0x400fc000, 0x1000); 1574 create_unimplemented_device("flash-control", 0x400fd000, 0x1000); 1575 1576 armv7m_load_kernel(ARM_CPU(first_cpu), ms->kernel_filename, flash_size); 1577 } 1578 1579 /* FIXME: Figure out how to generate these from stellaris_boards. */ 1580 static void lm3s811evb_init(MachineState *machine) 1581 { 1582 stellaris_init(machine, &stellaris_boards[0]); 1583 } 1584 1585 static void lm3s6965evb_init(MachineState *machine) 1586 { 1587 stellaris_init(machine, &stellaris_boards[1]); 1588 } 1589 1590 static void lm3s811evb_class_init(ObjectClass *oc, void *data) 1591 { 1592 MachineClass *mc = MACHINE_CLASS(oc); 1593 1594 mc->desc = "Stellaris LM3S811EVB (Cortex-M3)"; 1595 mc->init = lm3s811evb_init; 1596 mc->ignore_memory_transaction_failures = true; 1597 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3"); 1598 } 1599 1600 static const TypeInfo lm3s811evb_type = { 1601 .name = MACHINE_TYPE_NAME("lm3s811evb"), 1602 .parent = TYPE_MACHINE, 1603 .class_init = lm3s811evb_class_init, 1604 }; 1605 1606 static void lm3s6965evb_class_init(ObjectClass *oc, void *data) 1607 { 1608 MachineClass *mc = MACHINE_CLASS(oc); 1609 1610 mc->desc = "Stellaris LM3S6965EVB (Cortex-M3)"; 1611 mc->init = lm3s6965evb_init; 1612 mc->ignore_memory_transaction_failures = true; 1613 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3"); 1614 } 1615 1616 static const TypeInfo lm3s6965evb_type = { 1617 .name = MACHINE_TYPE_NAME("lm3s6965evb"), 1618 .parent = TYPE_MACHINE, 1619 .class_init = lm3s6965evb_class_init, 1620 }; 1621 1622 static void stellaris_machine_init(void) 1623 { 1624 type_register_static(&lm3s811evb_type); 1625 type_register_static(&lm3s6965evb_type); 1626 } 1627 1628 type_init(stellaris_machine_init) 1629 1630 static void stellaris_i2c_class_init(ObjectClass *klass, void *data) 1631 { 1632 DeviceClass *dc = DEVICE_CLASS(klass); 1633 1634 dc->vmsd = &vmstate_stellaris_i2c; 1635 } 1636 1637 static const TypeInfo stellaris_i2c_info = { 1638 .name = TYPE_STELLARIS_I2C, 1639 .parent = TYPE_SYS_BUS_DEVICE, 1640 .instance_size = sizeof(stellaris_i2c_state), 1641 .instance_init = stellaris_i2c_init, 1642 .class_init = stellaris_i2c_class_init, 1643 }; 1644 1645 static void stellaris_gptm_class_init(ObjectClass *klass, void *data) 1646 { 1647 DeviceClass *dc = DEVICE_CLASS(klass); 1648 1649 dc->vmsd = &vmstate_stellaris_gptm; 1650 dc->realize = stellaris_gptm_realize; 1651 } 1652 1653 static const TypeInfo stellaris_gptm_info = { 1654 .name = TYPE_STELLARIS_GPTM, 1655 .parent = TYPE_SYS_BUS_DEVICE, 1656 .instance_size = sizeof(gptm_state), 1657 .instance_init = stellaris_gptm_init, 1658 .class_init = stellaris_gptm_class_init, 1659 }; 1660 1661 static void stellaris_adc_class_init(ObjectClass *klass, void *data) 1662 { 1663 DeviceClass *dc = DEVICE_CLASS(klass); 1664 1665 dc->vmsd = &vmstate_stellaris_adc; 1666 } 1667 1668 static const TypeInfo stellaris_adc_info = { 1669 .name = TYPE_STELLARIS_ADC, 1670 .parent = TYPE_SYS_BUS_DEVICE, 1671 .instance_size = sizeof(stellaris_adc_state), 1672 .instance_init = stellaris_adc_init, 1673 .class_init = stellaris_adc_class_init, 1674 }; 1675 1676 static void stellaris_sys_class_init(ObjectClass *klass, void *data) 1677 { 1678 DeviceClass *dc = DEVICE_CLASS(klass); 1679 ResettableClass *rc = RESETTABLE_CLASS(klass); 1680 1681 dc->vmsd = &vmstate_stellaris_sys; 1682 rc->phases.enter = stellaris_sys_reset_enter; 1683 rc->phases.hold = stellaris_sys_reset_hold; 1684 rc->phases.exit = stellaris_sys_reset_exit; 1685 device_class_set_props(dc, stellaris_sys_properties); 1686 } 1687 1688 static const TypeInfo stellaris_sys_info = { 1689 .name = TYPE_STELLARIS_SYS, 1690 .parent = TYPE_SYS_BUS_DEVICE, 1691 .instance_size = sizeof(ssys_state), 1692 .instance_init = stellaris_sys_instance_init, 1693 .class_init = stellaris_sys_class_init, 1694 }; 1695 1696 static void stellaris_register_types(void) 1697 { 1698 type_register_static(&stellaris_i2c_info); 1699 type_register_static(&stellaris_gptm_info); 1700 type_register_static(&stellaris_adc_info); 1701 type_register_static(&stellaris_sys_info); 1702 } 1703 1704 type_init(stellaris_register_types) 1705