1 /* 2 * Luminary Micro Stellaris peripherals 3 * 4 * Copyright (c) 2006 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "hw/sysbus.h" 11 #include "hw/ssi.h" 12 #include "hw/arm/arm.h" 13 #include "hw/devices.h" 14 #include "qemu/timer.h" 15 #include "hw/i2c/i2c.h" 16 #include "net/net.h" 17 #include "hw/boards.h" 18 #include "exec/address-spaces.h" 19 20 #define GPIO_A 0 21 #define GPIO_B 1 22 #define GPIO_C 2 23 #define GPIO_D 3 24 #define GPIO_E 4 25 #define GPIO_F 5 26 #define GPIO_G 6 27 28 #define BP_OLED_I2C 0x01 29 #define BP_OLED_SSI 0x02 30 #define BP_GAMEPAD 0x04 31 32 typedef const struct { 33 const char *name; 34 uint32_t did0; 35 uint32_t did1; 36 uint32_t dc0; 37 uint32_t dc1; 38 uint32_t dc2; 39 uint32_t dc3; 40 uint32_t dc4; 41 uint32_t peripherals; 42 } stellaris_board_info; 43 44 /* General purpose timer module. */ 45 46 #define TYPE_STELLARIS_GPTM "stellaris-gptm" 47 #define STELLARIS_GPTM(obj) \ 48 OBJECT_CHECK(gptm_state, (obj), TYPE_STELLARIS_GPTM) 49 50 typedef struct gptm_state { 51 SysBusDevice parent_obj; 52 53 MemoryRegion iomem; 54 uint32_t config; 55 uint32_t mode[2]; 56 uint32_t control; 57 uint32_t state; 58 uint32_t mask; 59 uint32_t load[2]; 60 uint32_t match[2]; 61 uint32_t prescale[2]; 62 uint32_t match_prescale[2]; 63 uint32_t rtc; 64 int64_t tick[2]; 65 struct gptm_state *opaque[2]; 66 QEMUTimer *timer[2]; 67 /* The timers have an alternate output used to trigger the ADC. */ 68 qemu_irq trigger; 69 qemu_irq irq; 70 } gptm_state; 71 72 static void gptm_update_irq(gptm_state *s) 73 { 74 int level; 75 level = (s->state & s->mask) != 0; 76 qemu_set_irq(s->irq, level); 77 } 78 79 static void gptm_stop(gptm_state *s, int n) 80 { 81 timer_del(s->timer[n]); 82 } 83 84 static void gptm_reload(gptm_state *s, int n, int reset) 85 { 86 int64_t tick; 87 if (reset) 88 tick = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 89 else 90 tick = s->tick[n]; 91 92 if (s->config == 0) { 93 /* 32-bit CountDown. */ 94 uint32_t count; 95 count = s->load[0] | (s->load[1] << 16); 96 tick += (int64_t)count * system_clock_scale; 97 } else if (s->config == 1) { 98 /* 32-bit RTC. 1Hz tick. */ 99 tick += get_ticks_per_sec(); 100 } else if (s->mode[n] == 0xa) { 101 /* PWM mode. Not implemented. */ 102 } else { 103 hw_error("TODO: 16-bit timer mode 0x%x\n", s->mode[n]); 104 } 105 s->tick[n] = tick; 106 timer_mod(s->timer[n], tick); 107 } 108 109 static void gptm_tick(void *opaque) 110 { 111 gptm_state **p = (gptm_state **)opaque; 112 gptm_state *s; 113 int n; 114 115 s = *p; 116 n = p - s->opaque; 117 if (s->config == 0) { 118 s->state |= 1; 119 if ((s->control & 0x20)) { 120 /* Output trigger. */ 121 qemu_irq_pulse(s->trigger); 122 } 123 if (s->mode[0] & 1) { 124 /* One-shot. */ 125 s->control &= ~1; 126 } else { 127 /* Periodic. */ 128 gptm_reload(s, 0, 0); 129 } 130 } else if (s->config == 1) { 131 /* RTC. */ 132 uint32_t match; 133 s->rtc++; 134 match = s->match[0] | (s->match[1] << 16); 135 if (s->rtc > match) 136 s->rtc = 0; 137 if (s->rtc == 0) { 138 s->state |= 8; 139 } 140 gptm_reload(s, 0, 0); 141 } else if (s->mode[n] == 0xa) { 142 /* PWM mode. Not implemented. */ 143 } else { 144 hw_error("TODO: 16-bit timer mode 0x%x\n", s->mode[n]); 145 } 146 gptm_update_irq(s); 147 } 148 149 static uint64_t gptm_read(void *opaque, hwaddr offset, 150 unsigned size) 151 { 152 gptm_state *s = (gptm_state *)opaque; 153 154 switch (offset) { 155 case 0x00: /* CFG */ 156 return s->config; 157 case 0x04: /* TAMR */ 158 return s->mode[0]; 159 case 0x08: /* TBMR */ 160 return s->mode[1]; 161 case 0x0c: /* CTL */ 162 return s->control; 163 case 0x18: /* IMR */ 164 return s->mask; 165 case 0x1c: /* RIS */ 166 return s->state; 167 case 0x20: /* MIS */ 168 return s->state & s->mask; 169 case 0x24: /* CR */ 170 return 0; 171 case 0x28: /* TAILR */ 172 return s->load[0] | ((s->config < 4) ? (s->load[1] << 16) : 0); 173 case 0x2c: /* TBILR */ 174 return s->load[1]; 175 case 0x30: /* TAMARCHR */ 176 return s->match[0] | ((s->config < 4) ? (s->match[1] << 16) : 0); 177 case 0x34: /* TBMATCHR */ 178 return s->match[1]; 179 case 0x38: /* TAPR */ 180 return s->prescale[0]; 181 case 0x3c: /* TBPR */ 182 return s->prescale[1]; 183 case 0x40: /* TAPMR */ 184 return s->match_prescale[0]; 185 case 0x44: /* TBPMR */ 186 return s->match_prescale[1]; 187 case 0x48: /* TAR */ 188 if (s->control == 1) 189 return s->rtc; 190 case 0x4c: /* TBR */ 191 hw_error("TODO: Timer value read\n"); 192 default: 193 hw_error("gptm_read: Bad offset 0x%x\n", (int)offset); 194 return 0; 195 } 196 } 197 198 static void gptm_write(void *opaque, hwaddr offset, 199 uint64_t value, unsigned size) 200 { 201 gptm_state *s = (gptm_state *)opaque; 202 uint32_t oldval; 203 204 /* The timers should be disabled before changing the configuration. 205 We take advantage of this and defer everything until the timer 206 is enabled. */ 207 switch (offset) { 208 case 0x00: /* CFG */ 209 s->config = value; 210 break; 211 case 0x04: /* TAMR */ 212 s->mode[0] = value; 213 break; 214 case 0x08: /* TBMR */ 215 s->mode[1] = value; 216 break; 217 case 0x0c: /* CTL */ 218 oldval = s->control; 219 s->control = value; 220 /* TODO: Implement pause. */ 221 if ((oldval ^ value) & 1) { 222 if (value & 1) { 223 gptm_reload(s, 0, 1); 224 } else { 225 gptm_stop(s, 0); 226 } 227 } 228 if (((oldval ^ value) & 0x100) && s->config >= 4) { 229 if (value & 0x100) { 230 gptm_reload(s, 1, 1); 231 } else { 232 gptm_stop(s, 1); 233 } 234 } 235 break; 236 case 0x18: /* IMR */ 237 s->mask = value & 0x77; 238 gptm_update_irq(s); 239 break; 240 case 0x24: /* CR */ 241 s->state &= ~value; 242 break; 243 case 0x28: /* TAILR */ 244 s->load[0] = value & 0xffff; 245 if (s->config < 4) { 246 s->load[1] = value >> 16; 247 } 248 break; 249 case 0x2c: /* TBILR */ 250 s->load[1] = value & 0xffff; 251 break; 252 case 0x30: /* TAMARCHR */ 253 s->match[0] = value & 0xffff; 254 if (s->config < 4) { 255 s->match[1] = value >> 16; 256 } 257 break; 258 case 0x34: /* TBMATCHR */ 259 s->match[1] = value >> 16; 260 break; 261 case 0x38: /* TAPR */ 262 s->prescale[0] = value; 263 break; 264 case 0x3c: /* TBPR */ 265 s->prescale[1] = value; 266 break; 267 case 0x40: /* TAPMR */ 268 s->match_prescale[0] = value; 269 break; 270 case 0x44: /* TBPMR */ 271 s->match_prescale[0] = value; 272 break; 273 default: 274 hw_error("gptm_write: Bad offset 0x%x\n", (int)offset); 275 } 276 gptm_update_irq(s); 277 } 278 279 static const MemoryRegionOps gptm_ops = { 280 .read = gptm_read, 281 .write = gptm_write, 282 .endianness = DEVICE_NATIVE_ENDIAN, 283 }; 284 285 static const VMStateDescription vmstate_stellaris_gptm = { 286 .name = "stellaris_gptm", 287 .version_id = 1, 288 .minimum_version_id = 1, 289 .fields = (VMStateField[]) { 290 VMSTATE_UINT32(config, gptm_state), 291 VMSTATE_UINT32_ARRAY(mode, gptm_state, 2), 292 VMSTATE_UINT32(control, gptm_state), 293 VMSTATE_UINT32(state, gptm_state), 294 VMSTATE_UINT32(mask, gptm_state), 295 VMSTATE_UNUSED(8), 296 VMSTATE_UINT32_ARRAY(load, gptm_state, 2), 297 VMSTATE_UINT32_ARRAY(match, gptm_state, 2), 298 VMSTATE_UINT32_ARRAY(prescale, gptm_state, 2), 299 VMSTATE_UINT32_ARRAY(match_prescale, gptm_state, 2), 300 VMSTATE_UINT32(rtc, gptm_state), 301 VMSTATE_INT64_ARRAY(tick, gptm_state, 2), 302 VMSTATE_TIMER_ARRAY(timer, gptm_state, 2), 303 VMSTATE_END_OF_LIST() 304 } 305 }; 306 307 static int stellaris_gptm_init(SysBusDevice *sbd) 308 { 309 DeviceState *dev = DEVICE(sbd); 310 gptm_state *s = STELLARIS_GPTM(dev); 311 312 sysbus_init_irq(sbd, &s->irq); 313 qdev_init_gpio_out(dev, &s->trigger, 1); 314 315 memory_region_init_io(&s->iomem, OBJECT(s), &gptm_ops, s, 316 "gptm", 0x1000); 317 sysbus_init_mmio(sbd, &s->iomem); 318 319 s->opaque[0] = s->opaque[1] = s; 320 s->timer[0] = timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque[0]); 321 s->timer[1] = timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque[1]); 322 vmstate_register(dev, -1, &vmstate_stellaris_gptm, s); 323 return 0; 324 } 325 326 327 /* System controller. */ 328 329 typedef struct { 330 MemoryRegion iomem; 331 uint32_t pborctl; 332 uint32_t ldopctl; 333 uint32_t int_status; 334 uint32_t int_mask; 335 uint32_t resc; 336 uint32_t rcc; 337 uint32_t rcc2; 338 uint32_t rcgc[3]; 339 uint32_t scgc[3]; 340 uint32_t dcgc[3]; 341 uint32_t clkvclr; 342 uint32_t ldoarst; 343 uint32_t user0; 344 uint32_t user1; 345 qemu_irq irq; 346 stellaris_board_info *board; 347 } ssys_state; 348 349 static void ssys_update(ssys_state *s) 350 { 351 qemu_set_irq(s->irq, (s->int_status & s->int_mask) != 0); 352 } 353 354 static uint32_t pllcfg_sandstorm[16] = { 355 0x31c0, /* 1 Mhz */ 356 0x1ae0, /* 1.8432 Mhz */ 357 0x18c0, /* 2 Mhz */ 358 0xd573, /* 2.4576 Mhz */ 359 0x37a6, /* 3.57954 Mhz */ 360 0x1ae2, /* 3.6864 Mhz */ 361 0x0c40, /* 4 Mhz */ 362 0x98bc, /* 4.906 Mhz */ 363 0x935b, /* 4.9152 Mhz */ 364 0x09c0, /* 5 Mhz */ 365 0x4dee, /* 5.12 Mhz */ 366 0x0c41, /* 6 Mhz */ 367 0x75db, /* 6.144 Mhz */ 368 0x1ae6, /* 7.3728 Mhz */ 369 0x0600, /* 8 Mhz */ 370 0x585b /* 8.192 Mhz */ 371 }; 372 373 static uint32_t pllcfg_fury[16] = { 374 0x3200, /* 1 Mhz */ 375 0x1b20, /* 1.8432 Mhz */ 376 0x1900, /* 2 Mhz */ 377 0xf42b, /* 2.4576 Mhz */ 378 0x37e3, /* 3.57954 Mhz */ 379 0x1b21, /* 3.6864 Mhz */ 380 0x0c80, /* 4 Mhz */ 381 0x98ee, /* 4.906 Mhz */ 382 0xd5b4, /* 4.9152 Mhz */ 383 0x0a00, /* 5 Mhz */ 384 0x4e27, /* 5.12 Mhz */ 385 0x1902, /* 6 Mhz */ 386 0xec1c, /* 6.144 Mhz */ 387 0x1b23, /* 7.3728 Mhz */ 388 0x0640, /* 8 Mhz */ 389 0xb11c /* 8.192 Mhz */ 390 }; 391 392 #define DID0_VER_MASK 0x70000000 393 #define DID0_VER_0 0x00000000 394 #define DID0_VER_1 0x10000000 395 396 #define DID0_CLASS_MASK 0x00FF0000 397 #define DID0_CLASS_SANDSTORM 0x00000000 398 #define DID0_CLASS_FURY 0x00010000 399 400 static int ssys_board_class(const ssys_state *s) 401 { 402 uint32_t did0 = s->board->did0; 403 switch (did0 & DID0_VER_MASK) { 404 case DID0_VER_0: 405 return DID0_CLASS_SANDSTORM; 406 case DID0_VER_1: 407 switch (did0 & DID0_CLASS_MASK) { 408 case DID0_CLASS_SANDSTORM: 409 case DID0_CLASS_FURY: 410 return did0 & DID0_CLASS_MASK; 411 } 412 /* for unknown classes, fall through */ 413 default: 414 hw_error("ssys_board_class: Unknown class 0x%08x\n", did0); 415 } 416 } 417 418 static uint64_t ssys_read(void *opaque, hwaddr offset, 419 unsigned size) 420 { 421 ssys_state *s = (ssys_state *)opaque; 422 423 switch (offset) { 424 case 0x000: /* DID0 */ 425 return s->board->did0; 426 case 0x004: /* DID1 */ 427 return s->board->did1; 428 case 0x008: /* DC0 */ 429 return s->board->dc0; 430 case 0x010: /* DC1 */ 431 return s->board->dc1; 432 case 0x014: /* DC2 */ 433 return s->board->dc2; 434 case 0x018: /* DC3 */ 435 return s->board->dc3; 436 case 0x01c: /* DC4 */ 437 return s->board->dc4; 438 case 0x030: /* PBORCTL */ 439 return s->pborctl; 440 case 0x034: /* LDOPCTL */ 441 return s->ldopctl; 442 case 0x040: /* SRCR0 */ 443 return 0; 444 case 0x044: /* SRCR1 */ 445 return 0; 446 case 0x048: /* SRCR2 */ 447 return 0; 448 case 0x050: /* RIS */ 449 return s->int_status; 450 case 0x054: /* IMC */ 451 return s->int_mask; 452 case 0x058: /* MISC */ 453 return s->int_status & s->int_mask; 454 case 0x05c: /* RESC */ 455 return s->resc; 456 case 0x060: /* RCC */ 457 return s->rcc; 458 case 0x064: /* PLLCFG */ 459 { 460 int xtal; 461 xtal = (s->rcc >> 6) & 0xf; 462 switch (ssys_board_class(s)) { 463 case DID0_CLASS_FURY: 464 return pllcfg_fury[xtal]; 465 case DID0_CLASS_SANDSTORM: 466 return pllcfg_sandstorm[xtal]; 467 default: 468 hw_error("ssys_read: Unhandled class for PLLCFG read.\n"); 469 return 0; 470 } 471 } 472 case 0x070: /* RCC2 */ 473 return s->rcc2; 474 case 0x100: /* RCGC0 */ 475 return s->rcgc[0]; 476 case 0x104: /* RCGC1 */ 477 return s->rcgc[1]; 478 case 0x108: /* RCGC2 */ 479 return s->rcgc[2]; 480 case 0x110: /* SCGC0 */ 481 return s->scgc[0]; 482 case 0x114: /* SCGC1 */ 483 return s->scgc[1]; 484 case 0x118: /* SCGC2 */ 485 return s->scgc[2]; 486 case 0x120: /* DCGC0 */ 487 return s->dcgc[0]; 488 case 0x124: /* DCGC1 */ 489 return s->dcgc[1]; 490 case 0x128: /* DCGC2 */ 491 return s->dcgc[2]; 492 case 0x150: /* CLKVCLR */ 493 return s->clkvclr; 494 case 0x160: /* LDOARST */ 495 return s->ldoarst; 496 case 0x1e0: /* USER0 */ 497 return s->user0; 498 case 0x1e4: /* USER1 */ 499 return s->user1; 500 default: 501 hw_error("ssys_read: Bad offset 0x%x\n", (int)offset); 502 return 0; 503 } 504 } 505 506 static bool ssys_use_rcc2(ssys_state *s) 507 { 508 return (s->rcc2 >> 31) & 0x1; 509 } 510 511 /* 512 * Caculate the sys. clock period in ms. 513 */ 514 static void ssys_calculate_system_clock(ssys_state *s) 515 { 516 if (ssys_use_rcc2(s)) { 517 system_clock_scale = 5 * (((s->rcc2 >> 23) & 0x3f) + 1); 518 } else { 519 system_clock_scale = 5 * (((s->rcc >> 23) & 0xf) + 1); 520 } 521 } 522 523 static void ssys_write(void *opaque, hwaddr offset, 524 uint64_t value, unsigned size) 525 { 526 ssys_state *s = (ssys_state *)opaque; 527 528 switch (offset) { 529 case 0x030: /* PBORCTL */ 530 s->pborctl = value & 0xffff; 531 break; 532 case 0x034: /* LDOPCTL */ 533 s->ldopctl = value & 0x1f; 534 break; 535 case 0x040: /* SRCR0 */ 536 case 0x044: /* SRCR1 */ 537 case 0x048: /* SRCR2 */ 538 fprintf(stderr, "Peripheral reset not implemented\n"); 539 break; 540 case 0x054: /* IMC */ 541 s->int_mask = value & 0x7f; 542 break; 543 case 0x058: /* MISC */ 544 s->int_status &= ~value; 545 break; 546 case 0x05c: /* RESC */ 547 s->resc = value & 0x3f; 548 break; 549 case 0x060: /* RCC */ 550 if ((s->rcc & (1 << 13)) != 0 && (value & (1 << 13)) == 0) { 551 /* PLL enable. */ 552 s->int_status |= (1 << 6); 553 } 554 s->rcc = value; 555 ssys_calculate_system_clock(s); 556 break; 557 case 0x070: /* RCC2 */ 558 if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) { 559 break; 560 } 561 562 if ((s->rcc2 & (1 << 13)) != 0 && (value & (1 << 13)) == 0) { 563 /* PLL enable. */ 564 s->int_status |= (1 << 6); 565 } 566 s->rcc2 = value; 567 ssys_calculate_system_clock(s); 568 break; 569 case 0x100: /* RCGC0 */ 570 s->rcgc[0] = value; 571 break; 572 case 0x104: /* RCGC1 */ 573 s->rcgc[1] = value; 574 break; 575 case 0x108: /* RCGC2 */ 576 s->rcgc[2] = value; 577 break; 578 case 0x110: /* SCGC0 */ 579 s->scgc[0] = value; 580 break; 581 case 0x114: /* SCGC1 */ 582 s->scgc[1] = value; 583 break; 584 case 0x118: /* SCGC2 */ 585 s->scgc[2] = value; 586 break; 587 case 0x120: /* DCGC0 */ 588 s->dcgc[0] = value; 589 break; 590 case 0x124: /* DCGC1 */ 591 s->dcgc[1] = value; 592 break; 593 case 0x128: /* DCGC2 */ 594 s->dcgc[2] = value; 595 break; 596 case 0x150: /* CLKVCLR */ 597 s->clkvclr = value; 598 break; 599 case 0x160: /* LDOARST */ 600 s->ldoarst = value; 601 break; 602 default: 603 hw_error("ssys_write: Bad offset 0x%x\n", (int)offset); 604 } 605 ssys_update(s); 606 } 607 608 static const MemoryRegionOps ssys_ops = { 609 .read = ssys_read, 610 .write = ssys_write, 611 .endianness = DEVICE_NATIVE_ENDIAN, 612 }; 613 614 static void ssys_reset(void *opaque) 615 { 616 ssys_state *s = (ssys_state *)opaque; 617 618 s->pborctl = 0x7ffd; 619 s->rcc = 0x078e3ac0; 620 621 if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) { 622 s->rcc2 = 0; 623 } else { 624 s->rcc2 = 0x07802810; 625 } 626 s->rcgc[0] = 1; 627 s->scgc[0] = 1; 628 s->dcgc[0] = 1; 629 ssys_calculate_system_clock(s); 630 } 631 632 static int stellaris_sys_post_load(void *opaque, int version_id) 633 { 634 ssys_state *s = opaque; 635 636 ssys_calculate_system_clock(s); 637 638 return 0; 639 } 640 641 static const VMStateDescription vmstate_stellaris_sys = { 642 .name = "stellaris_sys", 643 .version_id = 2, 644 .minimum_version_id = 1, 645 .post_load = stellaris_sys_post_load, 646 .fields = (VMStateField[]) { 647 VMSTATE_UINT32(pborctl, ssys_state), 648 VMSTATE_UINT32(ldopctl, ssys_state), 649 VMSTATE_UINT32(int_mask, ssys_state), 650 VMSTATE_UINT32(int_status, ssys_state), 651 VMSTATE_UINT32(resc, ssys_state), 652 VMSTATE_UINT32(rcc, ssys_state), 653 VMSTATE_UINT32_V(rcc2, ssys_state, 2), 654 VMSTATE_UINT32_ARRAY(rcgc, ssys_state, 3), 655 VMSTATE_UINT32_ARRAY(scgc, ssys_state, 3), 656 VMSTATE_UINT32_ARRAY(dcgc, ssys_state, 3), 657 VMSTATE_UINT32(clkvclr, ssys_state), 658 VMSTATE_UINT32(ldoarst, ssys_state), 659 VMSTATE_END_OF_LIST() 660 } 661 }; 662 663 static int stellaris_sys_init(uint32_t base, qemu_irq irq, 664 stellaris_board_info * board, 665 uint8_t *macaddr) 666 { 667 ssys_state *s; 668 669 s = (ssys_state *)g_malloc0(sizeof(ssys_state)); 670 s->irq = irq; 671 s->board = board; 672 /* Most devices come preprogrammed with a MAC address in the user data. */ 673 s->user0 = macaddr[0] | (macaddr[1] << 8) | (macaddr[2] << 16); 674 s->user1 = macaddr[3] | (macaddr[4] << 8) | (macaddr[5] << 16); 675 676 memory_region_init_io(&s->iomem, NULL, &ssys_ops, s, "ssys", 0x00001000); 677 memory_region_add_subregion(get_system_memory(), base, &s->iomem); 678 ssys_reset(s); 679 vmstate_register(NULL, -1, &vmstate_stellaris_sys, s); 680 return 0; 681 } 682 683 684 /* I2C controller. */ 685 686 #define TYPE_STELLARIS_I2C "stellaris-i2c" 687 #define STELLARIS_I2C(obj) \ 688 OBJECT_CHECK(stellaris_i2c_state, (obj), TYPE_STELLARIS_I2C) 689 690 typedef struct { 691 SysBusDevice parent_obj; 692 693 I2CBus *bus; 694 qemu_irq irq; 695 MemoryRegion iomem; 696 uint32_t msa; 697 uint32_t mcs; 698 uint32_t mdr; 699 uint32_t mtpr; 700 uint32_t mimr; 701 uint32_t mris; 702 uint32_t mcr; 703 } stellaris_i2c_state; 704 705 #define STELLARIS_I2C_MCS_BUSY 0x01 706 #define STELLARIS_I2C_MCS_ERROR 0x02 707 #define STELLARIS_I2C_MCS_ADRACK 0x04 708 #define STELLARIS_I2C_MCS_DATACK 0x08 709 #define STELLARIS_I2C_MCS_ARBLST 0x10 710 #define STELLARIS_I2C_MCS_IDLE 0x20 711 #define STELLARIS_I2C_MCS_BUSBSY 0x40 712 713 static uint64_t stellaris_i2c_read(void *opaque, hwaddr offset, 714 unsigned size) 715 { 716 stellaris_i2c_state *s = (stellaris_i2c_state *)opaque; 717 718 switch (offset) { 719 case 0x00: /* MSA */ 720 return s->msa; 721 case 0x04: /* MCS */ 722 /* We don't emulate timing, so the controller is never busy. */ 723 return s->mcs | STELLARIS_I2C_MCS_IDLE; 724 case 0x08: /* MDR */ 725 return s->mdr; 726 case 0x0c: /* MTPR */ 727 return s->mtpr; 728 case 0x10: /* MIMR */ 729 return s->mimr; 730 case 0x14: /* MRIS */ 731 return s->mris; 732 case 0x18: /* MMIS */ 733 return s->mris & s->mimr; 734 case 0x20: /* MCR */ 735 return s->mcr; 736 default: 737 hw_error("strllaris_i2c_read: Bad offset 0x%x\n", (int)offset); 738 return 0; 739 } 740 } 741 742 static void stellaris_i2c_update(stellaris_i2c_state *s) 743 { 744 int level; 745 746 level = (s->mris & s->mimr) != 0; 747 qemu_set_irq(s->irq, level); 748 } 749 750 static void stellaris_i2c_write(void *opaque, hwaddr offset, 751 uint64_t value, unsigned size) 752 { 753 stellaris_i2c_state *s = (stellaris_i2c_state *)opaque; 754 755 switch (offset) { 756 case 0x00: /* MSA */ 757 s->msa = value & 0xff; 758 break; 759 case 0x04: /* MCS */ 760 if ((s->mcr & 0x10) == 0) { 761 /* Disabled. Do nothing. */ 762 break; 763 } 764 /* Grab the bus if this is starting a transfer. */ 765 if ((value & 2) && (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) { 766 if (i2c_start_transfer(s->bus, s->msa >> 1, s->msa & 1)) { 767 s->mcs |= STELLARIS_I2C_MCS_ARBLST; 768 } else { 769 s->mcs &= ~STELLARIS_I2C_MCS_ARBLST; 770 s->mcs |= STELLARIS_I2C_MCS_BUSBSY; 771 } 772 } 773 /* If we don't have the bus then indicate an error. */ 774 if (!i2c_bus_busy(s->bus) 775 || (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) { 776 s->mcs |= STELLARIS_I2C_MCS_ERROR; 777 break; 778 } 779 s->mcs &= ~STELLARIS_I2C_MCS_ERROR; 780 if (value & 1) { 781 /* Transfer a byte. */ 782 /* TODO: Handle errors. */ 783 if (s->msa & 1) { 784 /* Recv */ 785 s->mdr = i2c_recv(s->bus) & 0xff; 786 } else { 787 /* Send */ 788 i2c_send(s->bus, s->mdr); 789 } 790 /* Raise an interrupt. */ 791 s->mris |= 1; 792 } 793 if (value & 4) { 794 /* Finish transfer. */ 795 i2c_end_transfer(s->bus); 796 s->mcs &= ~STELLARIS_I2C_MCS_BUSBSY; 797 } 798 break; 799 case 0x08: /* MDR */ 800 s->mdr = value & 0xff; 801 break; 802 case 0x0c: /* MTPR */ 803 s->mtpr = value & 0xff; 804 break; 805 case 0x10: /* MIMR */ 806 s->mimr = 1; 807 break; 808 case 0x1c: /* MICR */ 809 s->mris &= ~value; 810 break; 811 case 0x20: /* MCR */ 812 if (value & 1) 813 hw_error( 814 "stellaris_i2c_write: Loopback not implemented\n"); 815 if (value & 0x20) 816 hw_error( 817 "stellaris_i2c_write: Slave mode not implemented\n"); 818 s->mcr = value & 0x31; 819 break; 820 default: 821 hw_error("stellaris_i2c_write: Bad offset 0x%x\n", 822 (int)offset); 823 } 824 stellaris_i2c_update(s); 825 } 826 827 static void stellaris_i2c_reset(stellaris_i2c_state *s) 828 { 829 if (s->mcs & STELLARIS_I2C_MCS_BUSBSY) 830 i2c_end_transfer(s->bus); 831 832 s->msa = 0; 833 s->mcs = 0; 834 s->mdr = 0; 835 s->mtpr = 1; 836 s->mimr = 0; 837 s->mris = 0; 838 s->mcr = 0; 839 stellaris_i2c_update(s); 840 } 841 842 static const MemoryRegionOps stellaris_i2c_ops = { 843 .read = stellaris_i2c_read, 844 .write = stellaris_i2c_write, 845 .endianness = DEVICE_NATIVE_ENDIAN, 846 }; 847 848 static const VMStateDescription vmstate_stellaris_i2c = { 849 .name = "stellaris_i2c", 850 .version_id = 1, 851 .minimum_version_id = 1, 852 .fields = (VMStateField[]) { 853 VMSTATE_UINT32(msa, stellaris_i2c_state), 854 VMSTATE_UINT32(mcs, stellaris_i2c_state), 855 VMSTATE_UINT32(mdr, stellaris_i2c_state), 856 VMSTATE_UINT32(mtpr, stellaris_i2c_state), 857 VMSTATE_UINT32(mimr, stellaris_i2c_state), 858 VMSTATE_UINT32(mris, stellaris_i2c_state), 859 VMSTATE_UINT32(mcr, stellaris_i2c_state), 860 VMSTATE_END_OF_LIST() 861 } 862 }; 863 864 static int stellaris_i2c_init(SysBusDevice *sbd) 865 { 866 DeviceState *dev = DEVICE(sbd); 867 stellaris_i2c_state *s = STELLARIS_I2C(dev); 868 I2CBus *bus; 869 870 sysbus_init_irq(sbd, &s->irq); 871 bus = i2c_init_bus(dev, "i2c"); 872 s->bus = bus; 873 874 memory_region_init_io(&s->iomem, OBJECT(s), &stellaris_i2c_ops, s, 875 "i2c", 0x1000); 876 sysbus_init_mmio(sbd, &s->iomem); 877 /* ??? For now we only implement the master interface. */ 878 stellaris_i2c_reset(s); 879 vmstate_register(dev, -1, &vmstate_stellaris_i2c, s); 880 return 0; 881 } 882 883 /* Analogue to Digital Converter. This is only partially implemented, 884 enough for applications that use a combined ADC and timer tick. */ 885 886 #define STELLARIS_ADC_EM_CONTROLLER 0 887 #define STELLARIS_ADC_EM_COMP 1 888 #define STELLARIS_ADC_EM_EXTERNAL 4 889 #define STELLARIS_ADC_EM_TIMER 5 890 #define STELLARIS_ADC_EM_PWM0 6 891 #define STELLARIS_ADC_EM_PWM1 7 892 #define STELLARIS_ADC_EM_PWM2 8 893 894 #define STELLARIS_ADC_FIFO_EMPTY 0x0100 895 #define STELLARIS_ADC_FIFO_FULL 0x1000 896 897 #define TYPE_STELLARIS_ADC "stellaris-adc" 898 #define STELLARIS_ADC(obj) \ 899 OBJECT_CHECK(stellaris_adc_state, (obj), TYPE_STELLARIS_ADC) 900 901 typedef struct StellarisADCState { 902 SysBusDevice parent_obj; 903 904 MemoryRegion iomem; 905 uint32_t actss; 906 uint32_t ris; 907 uint32_t im; 908 uint32_t emux; 909 uint32_t ostat; 910 uint32_t ustat; 911 uint32_t sspri; 912 uint32_t sac; 913 struct { 914 uint32_t state; 915 uint32_t data[16]; 916 } fifo[4]; 917 uint32_t ssmux[4]; 918 uint32_t ssctl[4]; 919 uint32_t noise; 920 qemu_irq irq[4]; 921 } stellaris_adc_state; 922 923 static uint32_t stellaris_adc_fifo_read(stellaris_adc_state *s, int n) 924 { 925 int tail; 926 927 tail = s->fifo[n].state & 0xf; 928 if (s->fifo[n].state & STELLARIS_ADC_FIFO_EMPTY) { 929 s->ustat |= 1 << n; 930 } else { 931 s->fifo[n].state = (s->fifo[n].state & ~0xf) | ((tail + 1) & 0xf); 932 s->fifo[n].state &= ~STELLARIS_ADC_FIFO_FULL; 933 if (tail + 1 == ((s->fifo[n].state >> 4) & 0xf)) 934 s->fifo[n].state |= STELLARIS_ADC_FIFO_EMPTY; 935 } 936 return s->fifo[n].data[tail]; 937 } 938 939 static void stellaris_adc_fifo_write(stellaris_adc_state *s, int n, 940 uint32_t value) 941 { 942 int head; 943 944 /* TODO: Real hardware has limited size FIFOs. We have a full 16 entry 945 FIFO fir each sequencer. */ 946 head = (s->fifo[n].state >> 4) & 0xf; 947 if (s->fifo[n].state & STELLARIS_ADC_FIFO_FULL) { 948 s->ostat |= 1 << n; 949 return; 950 } 951 s->fifo[n].data[head] = value; 952 head = (head + 1) & 0xf; 953 s->fifo[n].state &= ~STELLARIS_ADC_FIFO_EMPTY; 954 s->fifo[n].state = (s->fifo[n].state & ~0xf0) | (head << 4); 955 if ((s->fifo[n].state & 0xf) == head) 956 s->fifo[n].state |= STELLARIS_ADC_FIFO_FULL; 957 } 958 959 static void stellaris_adc_update(stellaris_adc_state *s) 960 { 961 int level; 962 int n; 963 964 for (n = 0; n < 4; n++) { 965 level = (s->ris & s->im & (1 << n)) != 0; 966 qemu_set_irq(s->irq[n], level); 967 } 968 } 969 970 static void stellaris_adc_trigger(void *opaque, int irq, int level) 971 { 972 stellaris_adc_state *s = (stellaris_adc_state *)opaque; 973 int n; 974 975 for (n = 0; n < 4; n++) { 976 if ((s->actss & (1 << n)) == 0) { 977 continue; 978 } 979 980 if (((s->emux >> (n * 4)) & 0xff) != 5) { 981 continue; 982 } 983 984 /* Some applications use the ADC as a random number source, so introduce 985 some variation into the signal. */ 986 s->noise = s->noise * 314159 + 1; 987 /* ??? actual inputs not implemented. Return an arbitrary value. */ 988 stellaris_adc_fifo_write(s, n, 0x200 + ((s->noise >> 16) & 7)); 989 s->ris |= (1 << n); 990 stellaris_adc_update(s); 991 } 992 } 993 994 static void stellaris_adc_reset(stellaris_adc_state *s) 995 { 996 int n; 997 998 for (n = 0; n < 4; n++) { 999 s->ssmux[n] = 0; 1000 s->ssctl[n] = 0; 1001 s->fifo[n].state = STELLARIS_ADC_FIFO_EMPTY; 1002 } 1003 } 1004 1005 static uint64_t stellaris_adc_read(void *opaque, hwaddr offset, 1006 unsigned size) 1007 { 1008 stellaris_adc_state *s = (stellaris_adc_state *)opaque; 1009 1010 /* TODO: Implement this. */ 1011 if (offset >= 0x40 && offset < 0xc0) { 1012 int n; 1013 n = (offset - 0x40) >> 5; 1014 switch (offset & 0x1f) { 1015 case 0x00: /* SSMUX */ 1016 return s->ssmux[n]; 1017 case 0x04: /* SSCTL */ 1018 return s->ssctl[n]; 1019 case 0x08: /* SSFIFO */ 1020 return stellaris_adc_fifo_read(s, n); 1021 case 0x0c: /* SSFSTAT */ 1022 return s->fifo[n].state; 1023 default: 1024 break; 1025 } 1026 } 1027 switch (offset) { 1028 case 0x00: /* ACTSS */ 1029 return s->actss; 1030 case 0x04: /* RIS */ 1031 return s->ris; 1032 case 0x08: /* IM */ 1033 return s->im; 1034 case 0x0c: /* ISC */ 1035 return s->ris & s->im; 1036 case 0x10: /* OSTAT */ 1037 return s->ostat; 1038 case 0x14: /* EMUX */ 1039 return s->emux; 1040 case 0x18: /* USTAT */ 1041 return s->ustat; 1042 case 0x20: /* SSPRI */ 1043 return s->sspri; 1044 case 0x30: /* SAC */ 1045 return s->sac; 1046 default: 1047 hw_error("strllaris_adc_read: Bad offset 0x%x\n", 1048 (int)offset); 1049 return 0; 1050 } 1051 } 1052 1053 static void stellaris_adc_write(void *opaque, hwaddr offset, 1054 uint64_t value, unsigned size) 1055 { 1056 stellaris_adc_state *s = (stellaris_adc_state *)opaque; 1057 1058 /* TODO: Implement this. */ 1059 if (offset >= 0x40 && offset < 0xc0) { 1060 int n; 1061 n = (offset - 0x40) >> 5; 1062 switch (offset & 0x1f) { 1063 case 0x00: /* SSMUX */ 1064 s->ssmux[n] = value & 0x33333333; 1065 return; 1066 case 0x04: /* SSCTL */ 1067 if (value != 6) { 1068 hw_error("ADC: Unimplemented sequence %" PRIx64 "\n", 1069 value); 1070 } 1071 s->ssctl[n] = value; 1072 return; 1073 default: 1074 break; 1075 } 1076 } 1077 switch (offset) { 1078 case 0x00: /* ACTSS */ 1079 s->actss = value & 0xf; 1080 break; 1081 case 0x08: /* IM */ 1082 s->im = value; 1083 break; 1084 case 0x0c: /* ISC */ 1085 s->ris &= ~value; 1086 break; 1087 case 0x10: /* OSTAT */ 1088 s->ostat &= ~value; 1089 break; 1090 case 0x14: /* EMUX */ 1091 s->emux = value; 1092 break; 1093 case 0x18: /* USTAT */ 1094 s->ustat &= ~value; 1095 break; 1096 case 0x20: /* SSPRI */ 1097 s->sspri = value; 1098 break; 1099 case 0x28: /* PSSI */ 1100 hw_error("Not implemented: ADC sample initiate\n"); 1101 break; 1102 case 0x30: /* SAC */ 1103 s->sac = value; 1104 break; 1105 default: 1106 hw_error("stellaris_adc_write: Bad offset 0x%x\n", (int)offset); 1107 } 1108 stellaris_adc_update(s); 1109 } 1110 1111 static const MemoryRegionOps stellaris_adc_ops = { 1112 .read = stellaris_adc_read, 1113 .write = stellaris_adc_write, 1114 .endianness = DEVICE_NATIVE_ENDIAN, 1115 }; 1116 1117 static const VMStateDescription vmstate_stellaris_adc = { 1118 .name = "stellaris_adc", 1119 .version_id = 1, 1120 .minimum_version_id = 1, 1121 .fields = (VMStateField[]) { 1122 VMSTATE_UINT32(actss, stellaris_adc_state), 1123 VMSTATE_UINT32(ris, stellaris_adc_state), 1124 VMSTATE_UINT32(im, stellaris_adc_state), 1125 VMSTATE_UINT32(emux, stellaris_adc_state), 1126 VMSTATE_UINT32(ostat, stellaris_adc_state), 1127 VMSTATE_UINT32(ustat, stellaris_adc_state), 1128 VMSTATE_UINT32(sspri, stellaris_adc_state), 1129 VMSTATE_UINT32(sac, stellaris_adc_state), 1130 VMSTATE_UINT32(fifo[0].state, stellaris_adc_state), 1131 VMSTATE_UINT32_ARRAY(fifo[0].data, stellaris_adc_state, 16), 1132 VMSTATE_UINT32(ssmux[0], stellaris_adc_state), 1133 VMSTATE_UINT32(ssctl[0], stellaris_adc_state), 1134 VMSTATE_UINT32(fifo[1].state, stellaris_adc_state), 1135 VMSTATE_UINT32_ARRAY(fifo[1].data, stellaris_adc_state, 16), 1136 VMSTATE_UINT32(ssmux[1], stellaris_adc_state), 1137 VMSTATE_UINT32(ssctl[1], stellaris_adc_state), 1138 VMSTATE_UINT32(fifo[2].state, stellaris_adc_state), 1139 VMSTATE_UINT32_ARRAY(fifo[2].data, stellaris_adc_state, 16), 1140 VMSTATE_UINT32(ssmux[2], stellaris_adc_state), 1141 VMSTATE_UINT32(ssctl[2], stellaris_adc_state), 1142 VMSTATE_UINT32(fifo[3].state, stellaris_adc_state), 1143 VMSTATE_UINT32_ARRAY(fifo[3].data, stellaris_adc_state, 16), 1144 VMSTATE_UINT32(ssmux[3], stellaris_adc_state), 1145 VMSTATE_UINT32(ssctl[3], stellaris_adc_state), 1146 VMSTATE_UINT32(noise, stellaris_adc_state), 1147 VMSTATE_END_OF_LIST() 1148 } 1149 }; 1150 1151 static int stellaris_adc_init(SysBusDevice *sbd) 1152 { 1153 DeviceState *dev = DEVICE(sbd); 1154 stellaris_adc_state *s = STELLARIS_ADC(dev); 1155 int n; 1156 1157 for (n = 0; n < 4; n++) { 1158 sysbus_init_irq(sbd, &s->irq[n]); 1159 } 1160 1161 memory_region_init_io(&s->iomem, OBJECT(s), &stellaris_adc_ops, s, 1162 "adc", 0x1000); 1163 sysbus_init_mmio(sbd, &s->iomem); 1164 stellaris_adc_reset(s); 1165 qdev_init_gpio_in(dev, stellaris_adc_trigger, 1); 1166 vmstate_register(dev, -1, &vmstate_stellaris_adc, s); 1167 return 0; 1168 } 1169 1170 /* Board init. */ 1171 static stellaris_board_info stellaris_boards[] = { 1172 { "LM3S811EVB", 1173 0, 1174 0x0032000e, 1175 0x001f001f, /* dc0 */ 1176 0x001132bf, 1177 0x01071013, 1178 0x3f0f01ff, 1179 0x0000001f, 1180 BP_OLED_I2C 1181 }, 1182 { "LM3S6965EVB", 1183 0x10010002, 1184 0x1073402e, 1185 0x00ff007f, /* dc0 */ 1186 0x001133ff, 1187 0x030f5317, 1188 0x0f0f87ff, 1189 0x5000007f, 1190 BP_OLED_SSI | BP_GAMEPAD 1191 } 1192 }; 1193 1194 static void stellaris_init(const char *kernel_filename, const char *cpu_model, 1195 stellaris_board_info *board) 1196 { 1197 static const int uart_irq[] = {5, 6, 33, 34}; 1198 static const int timer_irq[] = {19, 21, 23, 35}; 1199 static const uint32_t gpio_addr[7] = 1200 { 0x40004000, 0x40005000, 0x40006000, 0x40007000, 1201 0x40024000, 0x40025000, 0x40026000}; 1202 static const int gpio_irq[7] = {0, 1, 2, 3, 4, 30, 31}; 1203 1204 MemoryRegion *address_space_mem = get_system_memory(); 1205 qemu_irq *pic; 1206 DeviceState *gpio_dev[7]; 1207 qemu_irq gpio_in[7][8]; 1208 qemu_irq gpio_out[7][8]; 1209 qemu_irq adc; 1210 int sram_size; 1211 int flash_size; 1212 I2CBus *i2c; 1213 DeviceState *dev; 1214 int i; 1215 int j; 1216 1217 flash_size = ((board->dc0 & 0xffff) + 1) << 1; 1218 sram_size = (board->dc0 >> 18) + 1; 1219 pic = armv7m_init(address_space_mem, 1220 flash_size, sram_size, kernel_filename, cpu_model); 1221 1222 if (board->dc1 & (1 << 16)) { 1223 dev = sysbus_create_varargs(TYPE_STELLARIS_ADC, 0x40038000, 1224 pic[14], pic[15], pic[16], pic[17], NULL); 1225 adc = qdev_get_gpio_in(dev, 0); 1226 } else { 1227 adc = NULL; 1228 } 1229 for (i = 0; i < 4; i++) { 1230 if (board->dc2 & (0x10000 << i)) { 1231 dev = sysbus_create_simple(TYPE_STELLARIS_GPTM, 1232 0x40030000 + i * 0x1000, 1233 pic[timer_irq[i]]); 1234 /* TODO: This is incorrect, but we get away with it because 1235 the ADC output is only ever pulsed. */ 1236 qdev_connect_gpio_out(dev, 0, adc); 1237 } 1238 } 1239 1240 stellaris_sys_init(0x400fe000, pic[28], board, nd_table[0].macaddr.a); 1241 1242 for (i = 0; i < 7; i++) { 1243 if (board->dc4 & (1 << i)) { 1244 gpio_dev[i] = sysbus_create_simple("pl061_luminary", gpio_addr[i], 1245 pic[gpio_irq[i]]); 1246 for (j = 0; j < 8; j++) { 1247 gpio_in[i][j] = qdev_get_gpio_in(gpio_dev[i], j); 1248 gpio_out[i][j] = NULL; 1249 } 1250 } 1251 } 1252 1253 if (board->dc2 & (1 << 12)) { 1254 dev = sysbus_create_simple(TYPE_STELLARIS_I2C, 0x40020000, pic[8]); 1255 i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c"); 1256 if (board->peripherals & BP_OLED_I2C) { 1257 i2c_create_slave(i2c, "ssd0303", 0x3d); 1258 } 1259 } 1260 1261 for (i = 0; i < 4; i++) { 1262 if (board->dc2 & (1 << i)) { 1263 sysbus_create_simple("pl011_luminary", 0x4000c000 + i * 0x1000, 1264 pic[uart_irq[i]]); 1265 } 1266 } 1267 if (board->dc2 & (1 << 4)) { 1268 dev = sysbus_create_simple("pl022", 0x40008000, pic[7]); 1269 if (board->peripherals & BP_OLED_SSI) { 1270 void *bus; 1271 DeviceState *sddev; 1272 DeviceState *ssddev; 1273 1274 /* Some boards have both an OLED controller and SD card connected to 1275 * the same SSI port, with the SD card chip select connected to a 1276 * GPIO pin. Technically the OLED chip select is connected to the 1277 * SSI Fss pin. We do not bother emulating that as both devices 1278 * should never be selected simultaneously, and our OLED controller 1279 * ignores stray 0xff commands that occur when deselecting the SD 1280 * card. 1281 */ 1282 bus = qdev_get_child_bus(dev, "ssi"); 1283 1284 sddev = ssi_create_slave(bus, "ssi-sd"); 1285 ssddev = ssi_create_slave(bus, "ssd0323"); 1286 gpio_out[GPIO_D][0] = qemu_irq_split(qdev_get_gpio_in(sddev, 0), 1287 qdev_get_gpio_in(ssddev, 0)); 1288 gpio_out[GPIO_C][7] = qdev_get_gpio_in(ssddev, 1); 1289 1290 /* Make sure the select pin is high. */ 1291 qemu_irq_raise(gpio_out[GPIO_D][0]); 1292 } 1293 } 1294 if (board->dc4 & (1 << 28)) { 1295 DeviceState *enet; 1296 1297 qemu_check_nic_model(&nd_table[0], "stellaris"); 1298 1299 enet = qdev_create(NULL, "stellaris_enet"); 1300 qdev_set_nic_properties(enet, &nd_table[0]); 1301 qdev_init_nofail(enet); 1302 sysbus_mmio_map(SYS_BUS_DEVICE(enet), 0, 0x40048000); 1303 sysbus_connect_irq(SYS_BUS_DEVICE(enet), 0, pic[42]); 1304 } 1305 if (board->peripherals & BP_GAMEPAD) { 1306 qemu_irq gpad_irq[5]; 1307 static const int gpad_keycode[5] = { 0xc8, 0xd0, 0xcb, 0xcd, 0x1d }; 1308 1309 gpad_irq[0] = qemu_irq_invert(gpio_in[GPIO_E][0]); /* up */ 1310 gpad_irq[1] = qemu_irq_invert(gpio_in[GPIO_E][1]); /* down */ 1311 gpad_irq[2] = qemu_irq_invert(gpio_in[GPIO_E][2]); /* left */ 1312 gpad_irq[3] = qemu_irq_invert(gpio_in[GPIO_E][3]); /* right */ 1313 gpad_irq[4] = qemu_irq_invert(gpio_in[GPIO_F][1]); /* select */ 1314 1315 stellaris_gamepad_init(5, gpad_irq, gpad_keycode); 1316 } 1317 for (i = 0; i < 7; i++) { 1318 if (board->dc4 & (1 << i)) { 1319 for (j = 0; j < 8; j++) { 1320 if (gpio_out[i][j]) { 1321 qdev_connect_gpio_out(gpio_dev[i], j, gpio_out[i][j]); 1322 } 1323 } 1324 } 1325 } 1326 } 1327 1328 /* FIXME: Figure out how to generate these from stellaris_boards. */ 1329 static void lm3s811evb_init(QEMUMachineInitArgs *args) 1330 { 1331 const char *cpu_model = args->cpu_model; 1332 const char *kernel_filename = args->kernel_filename; 1333 stellaris_init(kernel_filename, cpu_model, &stellaris_boards[0]); 1334 } 1335 1336 static void lm3s6965evb_init(QEMUMachineInitArgs *args) 1337 { 1338 const char *cpu_model = args->cpu_model; 1339 const char *kernel_filename = args->kernel_filename; 1340 stellaris_init(kernel_filename, cpu_model, &stellaris_boards[1]); 1341 } 1342 1343 static QEMUMachine lm3s811evb_machine = { 1344 .name = "lm3s811evb", 1345 .desc = "Stellaris LM3S811EVB", 1346 .init = lm3s811evb_init, 1347 }; 1348 1349 static QEMUMachine lm3s6965evb_machine = { 1350 .name = "lm3s6965evb", 1351 .desc = "Stellaris LM3S6965EVB", 1352 .init = lm3s6965evb_init, 1353 }; 1354 1355 static void stellaris_machine_init(void) 1356 { 1357 qemu_register_machine(&lm3s811evb_machine); 1358 qemu_register_machine(&lm3s6965evb_machine); 1359 } 1360 1361 machine_init(stellaris_machine_init); 1362 1363 static void stellaris_i2c_class_init(ObjectClass *klass, void *data) 1364 { 1365 SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); 1366 1367 sdc->init = stellaris_i2c_init; 1368 } 1369 1370 static const TypeInfo stellaris_i2c_info = { 1371 .name = TYPE_STELLARIS_I2C, 1372 .parent = TYPE_SYS_BUS_DEVICE, 1373 .instance_size = sizeof(stellaris_i2c_state), 1374 .class_init = stellaris_i2c_class_init, 1375 }; 1376 1377 static void stellaris_gptm_class_init(ObjectClass *klass, void *data) 1378 { 1379 SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); 1380 1381 sdc->init = stellaris_gptm_init; 1382 } 1383 1384 static const TypeInfo stellaris_gptm_info = { 1385 .name = TYPE_STELLARIS_GPTM, 1386 .parent = TYPE_SYS_BUS_DEVICE, 1387 .instance_size = sizeof(gptm_state), 1388 .class_init = stellaris_gptm_class_init, 1389 }; 1390 1391 static void stellaris_adc_class_init(ObjectClass *klass, void *data) 1392 { 1393 SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); 1394 1395 sdc->init = stellaris_adc_init; 1396 } 1397 1398 static const TypeInfo stellaris_adc_info = { 1399 .name = TYPE_STELLARIS_ADC, 1400 .parent = TYPE_SYS_BUS_DEVICE, 1401 .instance_size = sizeof(stellaris_adc_state), 1402 .class_init = stellaris_adc_class_init, 1403 }; 1404 1405 static void stellaris_register_types(void) 1406 { 1407 type_register_static(&stellaris_i2c_info); 1408 type_register_static(&stellaris_gptm_info); 1409 type_register_static(&stellaris_adc_info); 1410 } 1411 1412 type_init(stellaris_register_types) 1413