1 /* 2 * Luminary Micro Stellaris peripherals 3 * 4 * Copyright (c) 2006 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qapi/error.h" 12 #include "hw/sysbus.h" 13 #include "hw/ssi/ssi.h" 14 #include "hw/arm/boot.h" 15 #include "qemu/timer.h" 16 #include "hw/i2c/i2c.h" 17 #include "net/net.h" 18 #include "hw/boards.h" 19 #include "qemu/log.h" 20 #include "exec/address-spaces.h" 21 #include "sysemu/sysemu.h" 22 #include "hw/arm/armv7m.h" 23 #include "hw/char/pl011.h" 24 #include "hw/input/gamepad.h" 25 #include "hw/irq.h" 26 #include "hw/watchdog/cmsdk-apb-watchdog.h" 27 #include "migration/vmstate.h" 28 #include "hw/misc/unimp.h" 29 #include "cpu.h" 30 31 #define GPIO_A 0 32 #define GPIO_B 1 33 #define GPIO_C 2 34 #define GPIO_D 3 35 #define GPIO_E 4 36 #define GPIO_F 5 37 #define GPIO_G 6 38 39 #define BP_OLED_I2C 0x01 40 #define BP_OLED_SSI 0x02 41 #define BP_GAMEPAD 0x04 42 43 #define NUM_IRQ_LINES 64 44 45 typedef const struct { 46 const char *name; 47 uint32_t did0; 48 uint32_t did1; 49 uint32_t dc0; 50 uint32_t dc1; 51 uint32_t dc2; 52 uint32_t dc3; 53 uint32_t dc4; 54 uint32_t peripherals; 55 } stellaris_board_info; 56 57 /* General purpose timer module. */ 58 59 #define TYPE_STELLARIS_GPTM "stellaris-gptm" 60 #define STELLARIS_GPTM(obj) \ 61 OBJECT_CHECK(gptm_state, (obj), TYPE_STELLARIS_GPTM) 62 63 typedef struct gptm_state { 64 SysBusDevice parent_obj; 65 66 MemoryRegion iomem; 67 uint32_t config; 68 uint32_t mode[2]; 69 uint32_t control; 70 uint32_t state; 71 uint32_t mask; 72 uint32_t load[2]; 73 uint32_t match[2]; 74 uint32_t prescale[2]; 75 uint32_t match_prescale[2]; 76 uint32_t rtc; 77 int64_t tick[2]; 78 struct gptm_state *opaque[2]; 79 QEMUTimer *timer[2]; 80 /* The timers have an alternate output used to trigger the ADC. */ 81 qemu_irq trigger; 82 qemu_irq irq; 83 } gptm_state; 84 85 static void gptm_update_irq(gptm_state *s) 86 { 87 int level; 88 level = (s->state & s->mask) != 0; 89 qemu_set_irq(s->irq, level); 90 } 91 92 static void gptm_stop(gptm_state *s, int n) 93 { 94 timer_del(s->timer[n]); 95 } 96 97 static void gptm_reload(gptm_state *s, int n, int reset) 98 { 99 int64_t tick; 100 if (reset) 101 tick = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 102 else 103 tick = s->tick[n]; 104 105 if (s->config == 0) { 106 /* 32-bit CountDown. */ 107 uint32_t count; 108 count = s->load[0] | (s->load[1] << 16); 109 tick += (int64_t)count * system_clock_scale; 110 } else if (s->config == 1) { 111 /* 32-bit RTC. 1Hz tick. */ 112 tick += NANOSECONDS_PER_SECOND; 113 } else if (s->mode[n] == 0xa) { 114 /* PWM mode. Not implemented. */ 115 } else { 116 qemu_log_mask(LOG_UNIMP, 117 "GPTM: 16-bit timer mode unimplemented: 0x%x\n", 118 s->mode[n]); 119 return; 120 } 121 s->tick[n] = tick; 122 timer_mod(s->timer[n], tick); 123 } 124 125 static void gptm_tick(void *opaque) 126 { 127 gptm_state **p = (gptm_state **)opaque; 128 gptm_state *s; 129 int n; 130 131 s = *p; 132 n = p - s->opaque; 133 if (s->config == 0) { 134 s->state |= 1; 135 if ((s->control & 0x20)) { 136 /* Output trigger. */ 137 qemu_irq_pulse(s->trigger); 138 } 139 if (s->mode[0] & 1) { 140 /* One-shot. */ 141 s->control &= ~1; 142 } else { 143 /* Periodic. */ 144 gptm_reload(s, 0, 0); 145 } 146 } else if (s->config == 1) { 147 /* RTC. */ 148 uint32_t match; 149 s->rtc++; 150 match = s->match[0] | (s->match[1] << 16); 151 if (s->rtc > match) 152 s->rtc = 0; 153 if (s->rtc == 0) { 154 s->state |= 8; 155 } 156 gptm_reload(s, 0, 0); 157 } else if (s->mode[n] == 0xa) { 158 /* PWM mode. Not implemented. */ 159 } else { 160 qemu_log_mask(LOG_UNIMP, 161 "GPTM: 16-bit timer mode unimplemented: 0x%x\n", 162 s->mode[n]); 163 } 164 gptm_update_irq(s); 165 } 166 167 static uint64_t gptm_read(void *opaque, hwaddr offset, 168 unsigned size) 169 { 170 gptm_state *s = (gptm_state *)opaque; 171 172 switch (offset) { 173 case 0x00: /* CFG */ 174 return s->config; 175 case 0x04: /* TAMR */ 176 return s->mode[0]; 177 case 0x08: /* TBMR */ 178 return s->mode[1]; 179 case 0x0c: /* CTL */ 180 return s->control; 181 case 0x18: /* IMR */ 182 return s->mask; 183 case 0x1c: /* RIS */ 184 return s->state; 185 case 0x20: /* MIS */ 186 return s->state & s->mask; 187 case 0x24: /* CR */ 188 return 0; 189 case 0x28: /* TAILR */ 190 return s->load[0] | ((s->config < 4) ? (s->load[1] << 16) : 0); 191 case 0x2c: /* TBILR */ 192 return s->load[1]; 193 case 0x30: /* TAMARCHR */ 194 return s->match[0] | ((s->config < 4) ? (s->match[1] << 16) : 0); 195 case 0x34: /* TBMATCHR */ 196 return s->match[1]; 197 case 0x38: /* TAPR */ 198 return s->prescale[0]; 199 case 0x3c: /* TBPR */ 200 return s->prescale[1]; 201 case 0x40: /* TAPMR */ 202 return s->match_prescale[0]; 203 case 0x44: /* TBPMR */ 204 return s->match_prescale[1]; 205 case 0x48: /* TAR */ 206 if (s->config == 1) { 207 return s->rtc; 208 } 209 qemu_log_mask(LOG_UNIMP, 210 "GPTM: read of TAR but timer read not supported\n"); 211 return 0; 212 case 0x4c: /* TBR */ 213 qemu_log_mask(LOG_UNIMP, 214 "GPTM: read of TBR but timer read not supported\n"); 215 return 0; 216 default: 217 qemu_log_mask(LOG_GUEST_ERROR, 218 "GPTM: read at bad offset 0x02%" HWADDR_PRIx "\n", 219 offset); 220 return 0; 221 } 222 } 223 224 static void gptm_write(void *opaque, hwaddr offset, 225 uint64_t value, unsigned size) 226 { 227 gptm_state *s = (gptm_state *)opaque; 228 uint32_t oldval; 229 230 /* The timers should be disabled before changing the configuration. 231 We take advantage of this and defer everything until the timer 232 is enabled. */ 233 switch (offset) { 234 case 0x00: /* CFG */ 235 s->config = value; 236 break; 237 case 0x04: /* TAMR */ 238 s->mode[0] = value; 239 break; 240 case 0x08: /* TBMR */ 241 s->mode[1] = value; 242 break; 243 case 0x0c: /* CTL */ 244 oldval = s->control; 245 s->control = value; 246 /* TODO: Implement pause. */ 247 if ((oldval ^ value) & 1) { 248 if (value & 1) { 249 gptm_reload(s, 0, 1); 250 } else { 251 gptm_stop(s, 0); 252 } 253 } 254 if (((oldval ^ value) & 0x100) && s->config >= 4) { 255 if (value & 0x100) { 256 gptm_reload(s, 1, 1); 257 } else { 258 gptm_stop(s, 1); 259 } 260 } 261 break; 262 case 0x18: /* IMR */ 263 s->mask = value & 0x77; 264 gptm_update_irq(s); 265 break; 266 case 0x24: /* CR */ 267 s->state &= ~value; 268 break; 269 case 0x28: /* TAILR */ 270 s->load[0] = value & 0xffff; 271 if (s->config < 4) { 272 s->load[1] = value >> 16; 273 } 274 break; 275 case 0x2c: /* TBILR */ 276 s->load[1] = value & 0xffff; 277 break; 278 case 0x30: /* TAMARCHR */ 279 s->match[0] = value & 0xffff; 280 if (s->config < 4) { 281 s->match[1] = value >> 16; 282 } 283 break; 284 case 0x34: /* TBMATCHR */ 285 s->match[1] = value >> 16; 286 break; 287 case 0x38: /* TAPR */ 288 s->prescale[0] = value; 289 break; 290 case 0x3c: /* TBPR */ 291 s->prescale[1] = value; 292 break; 293 case 0x40: /* TAPMR */ 294 s->match_prescale[0] = value; 295 break; 296 case 0x44: /* TBPMR */ 297 s->match_prescale[0] = value; 298 break; 299 default: 300 qemu_log_mask(LOG_GUEST_ERROR, 301 "GPTM: write at bad offset 0x02%" HWADDR_PRIx "\n", 302 offset); 303 } 304 gptm_update_irq(s); 305 } 306 307 static const MemoryRegionOps gptm_ops = { 308 .read = gptm_read, 309 .write = gptm_write, 310 .endianness = DEVICE_NATIVE_ENDIAN, 311 }; 312 313 static const VMStateDescription vmstate_stellaris_gptm = { 314 .name = "stellaris_gptm", 315 .version_id = 1, 316 .minimum_version_id = 1, 317 .fields = (VMStateField[]) { 318 VMSTATE_UINT32(config, gptm_state), 319 VMSTATE_UINT32_ARRAY(mode, gptm_state, 2), 320 VMSTATE_UINT32(control, gptm_state), 321 VMSTATE_UINT32(state, gptm_state), 322 VMSTATE_UINT32(mask, gptm_state), 323 VMSTATE_UNUSED(8), 324 VMSTATE_UINT32_ARRAY(load, gptm_state, 2), 325 VMSTATE_UINT32_ARRAY(match, gptm_state, 2), 326 VMSTATE_UINT32_ARRAY(prescale, gptm_state, 2), 327 VMSTATE_UINT32_ARRAY(match_prescale, gptm_state, 2), 328 VMSTATE_UINT32(rtc, gptm_state), 329 VMSTATE_INT64_ARRAY(tick, gptm_state, 2), 330 VMSTATE_TIMER_PTR_ARRAY(timer, gptm_state, 2), 331 VMSTATE_END_OF_LIST() 332 } 333 }; 334 335 static void stellaris_gptm_init(Object *obj) 336 { 337 DeviceState *dev = DEVICE(obj); 338 gptm_state *s = STELLARIS_GPTM(obj); 339 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 340 341 sysbus_init_irq(sbd, &s->irq); 342 qdev_init_gpio_out(dev, &s->trigger, 1); 343 344 memory_region_init_io(&s->iomem, obj, &gptm_ops, s, 345 "gptm", 0x1000); 346 sysbus_init_mmio(sbd, &s->iomem); 347 348 s->opaque[0] = s->opaque[1] = s; 349 s->timer[0] = timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque[0]); 350 s->timer[1] = timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque[1]); 351 } 352 353 354 /* System controller. */ 355 356 typedef struct { 357 MemoryRegion iomem; 358 uint32_t pborctl; 359 uint32_t ldopctl; 360 uint32_t int_status; 361 uint32_t int_mask; 362 uint32_t resc; 363 uint32_t rcc; 364 uint32_t rcc2; 365 uint32_t rcgc[3]; 366 uint32_t scgc[3]; 367 uint32_t dcgc[3]; 368 uint32_t clkvclr; 369 uint32_t ldoarst; 370 uint32_t user0; 371 uint32_t user1; 372 qemu_irq irq; 373 stellaris_board_info *board; 374 } ssys_state; 375 376 static void ssys_update(ssys_state *s) 377 { 378 qemu_set_irq(s->irq, (s->int_status & s->int_mask) != 0); 379 } 380 381 static uint32_t pllcfg_sandstorm[16] = { 382 0x31c0, /* 1 Mhz */ 383 0x1ae0, /* 1.8432 Mhz */ 384 0x18c0, /* 2 Mhz */ 385 0xd573, /* 2.4576 Mhz */ 386 0x37a6, /* 3.57954 Mhz */ 387 0x1ae2, /* 3.6864 Mhz */ 388 0x0c40, /* 4 Mhz */ 389 0x98bc, /* 4.906 Mhz */ 390 0x935b, /* 4.9152 Mhz */ 391 0x09c0, /* 5 Mhz */ 392 0x4dee, /* 5.12 Mhz */ 393 0x0c41, /* 6 Mhz */ 394 0x75db, /* 6.144 Mhz */ 395 0x1ae6, /* 7.3728 Mhz */ 396 0x0600, /* 8 Mhz */ 397 0x585b /* 8.192 Mhz */ 398 }; 399 400 static uint32_t pllcfg_fury[16] = { 401 0x3200, /* 1 Mhz */ 402 0x1b20, /* 1.8432 Mhz */ 403 0x1900, /* 2 Mhz */ 404 0xf42b, /* 2.4576 Mhz */ 405 0x37e3, /* 3.57954 Mhz */ 406 0x1b21, /* 3.6864 Mhz */ 407 0x0c80, /* 4 Mhz */ 408 0x98ee, /* 4.906 Mhz */ 409 0xd5b4, /* 4.9152 Mhz */ 410 0x0a00, /* 5 Mhz */ 411 0x4e27, /* 5.12 Mhz */ 412 0x1902, /* 6 Mhz */ 413 0xec1c, /* 6.144 Mhz */ 414 0x1b23, /* 7.3728 Mhz */ 415 0x0640, /* 8 Mhz */ 416 0xb11c /* 8.192 Mhz */ 417 }; 418 419 #define DID0_VER_MASK 0x70000000 420 #define DID0_VER_0 0x00000000 421 #define DID0_VER_1 0x10000000 422 423 #define DID0_CLASS_MASK 0x00FF0000 424 #define DID0_CLASS_SANDSTORM 0x00000000 425 #define DID0_CLASS_FURY 0x00010000 426 427 static int ssys_board_class(const ssys_state *s) 428 { 429 uint32_t did0 = s->board->did0; 430 switch (did0 & DID0_VER_MASK) { 431 case DID0_VER_0: 432 return DID0_CLASS_SANDSTORM; 433 case DID0_VER_1: 434 switch (did0 & DID0_CLASS_MASK) { 435 case DID0_CLASS_SANDSTORM: 436 case DID0_CLASS_FURY: 437 return did0 & DID0_CLASS_MASK; 438 } 439 /* for unknown classes, fall through */ 440 default: 441 /* This can only happen if the hardwired constant did0 value 442 * in this board's stellaris_board_info struct is wrong. 443 */ 444 g_assert_not_reached(); 445 } 446 } 447 448 static uint64_t ssys_read(void *opaque, hwaddr offset, 449 unsigned size) 450 { 451 ssys_state *s = (ssys_state *)opaque; 452 453 switch (offset) { 454 case 0x000: /* DID0 */ 455 return s->board->did0; 456 case 0x004: /* DID1 */ 457 return s->board->did1; 458 case 0x008: /* DC0 */ 459 return s->board->dc0; 460 case 0x010: /* DC1 */ 461 return s->board->dc1; 462 case 0x014: /* DC2 */ 463 return s->board->dc2; 464 case 0x018: /* DC3 */ 465 return s->board->dc3; 466 case 0x01c: /* DC4 */ 467 return s->board->dc4; 468 case 0x030: /* PBORCTL */ 469 return s->pborctl; 470 case 0x034: /* LDOPCTL */ 471 return s->ldopctl; 472 case 0x040: /* SRCR0 */ 473 return 0; 474 case 0x044: /* SRCR1 */ 475 return 0; 476 case 0x048: /* SRCR2 */ 477 return 0; 478 case 0x050: /* RIS */ 479 return s->int_status; 480 case 0x054: /* IMC */ 481 return s->int_mask; 482 case 0x058: /* MISC */ 483 return s->int_status & s->int_mask; 484 case 0x05c: /* RESC */ 485 return s->resc; 486 case 0x060: /* RCC */ 487 return s->rcc; 488 case 0x064: /* PLLCFG */ 489 { 490 int xtal; 491 xtal = (s->rcc >> 6) & 0xf; 492 switch (ssys_board_class(s)) { 493 case DID0_CLASS_FURY: 494 return pllcfg_fury[xtal]; 495 case DID0_CLASS_SANDSTORM: 496 return pllcfg_sandstorm[xtal]; 497 default: 498 g_assert_not_reached(); 499 } 500 } 501 case 0x070: /* RCC2 */ 502 return s->rcc2; 503 case 0x100: /* RCGC0 */ 504 return s->rcgc[0]; 505 case 0x104: /* RCGC1 */ 506 return s->rcgc[1]; 507 case 0x108: /* RCGC2 */ 508 return s->rcgc[2]; 509 case 0x110: /* SCGC0 */ 510 return s->scgc[0]; 511 case 0x114: /* SCGC1 */ 512 return s->scgc[1]; 513 case 0x118: /* SCGC2 */ 514 return s->scgc[2]; 515 case 0x120: /* DCGC0 */ 516 return s->dcgc[0]; 517 case 0x124: /* DCGC1 */ 518 return s->dcgc[1]; 519 case 0x128: /* DCGC2 */ 520 return s->dcgc[2]; 521 case 0x150: /* CLKVCLR */ 522 return s->clkvclr; 523 case 0x160: /* LDOARST */ 524 return s->ldoarst; 525 case 0x1e0: /* USER0 */ 526 return s->user0; 527 case 0x1e4: /* USER1 */ 528 return s->user1; 529 default: 530 qemu_log_mask(LOG_GUEST_ERROR, 531 "SSYS: read at bad offset 0x%x\n", (int)offset); 532 return 0; 533 } 534 } 535 536 static bool ssys_use_rcc2(ssys_state *s) 537 { 538 return (s->rcc2 >> 31) & 0x1; 539 } 540 541 /* 542 * Caculate the sys. clock period in ms. 543 */ 544 static void ssys_calculate_system_clock(ssys_state *s) 545 { 546 if (ssys_use_rcc2(s)) { 547 system_clock_scale = 5 * (((s->rcc2 >> 23) & 0x3f) + 1); 548 } else { 549 system_clock_scale = 5 * (((s->rcc >> 23) & 0xf) + 1); 550 } 551 } 552 553 static void ssys_write(void *opaque, hwaddr offset, 554 uint64_t value, unsigned size) 555 { 556 ssys_state *s = (ssys_state *)opaque; 557 558 switch (offset) { 559 case 0x030: /* PBORCTL */ 560 s->pborctl = value & 0xffff; 561 break; 562 case 0x034: /* LDOPCTL */ 563 s->ldopctl = value & 0x1f; 564 break; 565 case 0x040: /* SRCR0 */ 566 case 0x044: /* SRCR1 */ 567 case 0x048: /* SRCR2 */ 568 qemu_log_mask(LOG_UNIMP, "Peripheral reset not implemented\n"); 569 break; 570 case 0x054: /* IMC */ 571 s->int_mask = value & 0x7f; 572 break; 573 case 0x058: /* MISC */ 574 s->int_status &= ~value; 575 break; 576 case 0x05c: /* RESC */ 577 s->resc = value & 0x3f; 578 break; 579 case 0x060: /* RCC */ 580 if ((s->rcc & (1 << 13)) != 0 && (value & (1 << 13)) == 0) { 581 /* PLL enable. */ 582 s->int_status |= (1 << 6); 583 } 584 s->rcc = value; 585 ssys_calculate_system_clock(s); 586 break; 587 case 0x070: /* RCC2 */ 588 if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) { 589 break; 590 } 591 592 if ((s->rcc2 & (1 << 13)) != 0 && (value & (1 << 13)) == 0) { 593 /* PLL enable. */ 594 s->int_status |= (1 << 6); 595 } 596 s->rcc2 = value; 597 ssys_calculate_system_clock(s); 598 break; 599 case 0x100: /* RCGC0 */ 600 s->rcgc[0] = value; 601 break; 602 case 0x104: /* RCGC1 */ 603 s->rcgc[1] = value; 604 break; 605 case 0x108: /* RCGC2 */ 606 s->rcgc[2] = value; 607 break; 608 case 0x110: /* SCGC0 */ 609 s->scgc[0] = value; 610 break; 611 case 0x114: /* SCGC1 */ 612 s->scgc[1] = value; 613 break; 614 case 0x118: /* SCGC2 */ 615 s->scgc[2] = value; 616 break; 617 case 0x120: /* DCGC0 */ 618 s->dcgc[0] = value; 619 break; 620 case 0x124: /* DCGC1 */ 621 s->dcgc[1] = value; 622 break; 623 case 0x128: /* DCGC2 */ 624 s->dcgc[2] = value; 625 break; 626 case 0x150: /* CLKVCLR */ 627 s->clkvclr = value; 628 break; 629 case 0x160: /* LDOARST */ 630 s->ldoarst = value; 631 break; 632 default: 633 qemu_log_mask(LOG_GUEST_ERROR, 634 "SSYS: write at bad offset 0x%x\n", (int)offset); 635 } 636 ssys_update(s); 637 } 638 639 static const MemoryRegionOps ssys_ops = { 640 .read = ssys_read, 641 .write = ssys_write, 642 .endianness = DEVICE_NATIVE_ENDIAN, 643 }; 644 645 static void ssys_reset(void *opaque) 646 { 647 ssys_state *s = (ssys_state *)opaque; 648 649 s->pborctl = 0x7ffd; 650 s->rcc = 0x078e3ac0; 651 652 if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) { 653 s->rcc2 = 0; 654 } else { 655 s->rcc2 = 0x07802810; 656 } 657 s->rcgc[0] = 1; 658 s->scgc[0] = 1; 659 s->dcgc[0] = 1; 660 ssys_calculate_system_clock(s); 661 } 662 663 static int stellaris_sys_post_load(void *opaque, int version_id) 664 { 665 ssys_state *s = opaque; 666 667 ssys_calculate_system_clock(s); 668 669 return 0; 670 } 671 672 static const VMStateDescription vmstate_stellaris_sys = { 673 .name = "stellaris_sys", 674 .version_id = 2, 675 .minimum_version_id = 1, 676 .post_load = stellaris_sys_post_load, 677 .fields = (VMStateField[]) { 678 VMSTATE_UINT32(pborctl, ssys_state), 679 VMSTATE_UINT32(ldopctl, ssys_state), 680 VMSTATE_UINT32(int_mask, ssys_state), 681 VMSTATE_UINT32(int_status, ssys_state), 682 VMSTATE_UINT32(resc, ssys_state), 683 VMSTATE_UINT32(rcc, ssys_state), 684 VMSTATE_UINT32_V(rcc2, ssys_state, 2), 685 VMSTATE_UINT32_ARRAY(rcgc, ssys_state, 3), 686 VMSTATE_UINT32_ARRAY(scgc, ssys_state, 3), 687 VMSTATE_UINT32_ARRAY(dcgc, ssys_state, 3), 688 VMSTATE_UINT32(clkvclr, ssys_state), 689 VMSTATE_UINT32(ldoarst, ssys_state), 690 VMSTATE_END_OF_LIST() 691 } 692 }; 693 694 static int stellaris_sys_init(uint32_t base, qemu_irq irq, 695 stellaris_board_info * board, 696 uint8_t *macaddr) 697 { 698 ssys_state *s; 699 700 s = g_new0(ssys_state, 1); 701 s->irq = irq; 702 s->board = board; 703 /* Most devices come preprogrammed with a MAC address in the user data. */ 704 s->user0 = macaddr[0] | (macaddr[1] << 8) | (macaddr[2] << 16); 705 s->user1 = macaddr[3] | (macaddr[4] << 8) | (macaddr[5] << 16); 706 707 memory_region_init_io(&s->iomem, NULL, &ssys_ops, s, "ssys", 0x00001000); 708 memory_region_add_subregion(get_system_memory(), base, &s->iomem); 709 ssys_reset(s); 710 vmstate_register(NULL, -1, &vmstate_stellaris_sys, s); 711 return 0; 712 } 713 714 715 /* I2C controller. */ 716 717 #define TYPE_STELLARIS_I2C "stellaris-i2c" 718 #define STELLARIS_I2C(obj) \ 719 OBJECT_CHECK(stellaris_i2c_state, (obj), TYPE_STELLARIS_I2C) 720 721 typedef struct { 722 SysBusDevice parent_obj; 723 724 I2CBus *bus; 725 qemu_irq irq; 726 MemoryRegion iomem; 727 uint32_t msa; 728 uint32_t mcs; 729 uint32_t mdr; 730 uint32_t mtpr; 731 uint32_t mimr; 732 uint32_t mris; 733 uint32_t mcr; 734 } stellaris_i2c_state; 735 736 #define STELLARIS_I2C_MCS_BUSY 0x01 737 #define STELLARIS_I2C_MCS_ERROR 0x02 738 #define STELLARIS_I2C_MCS_ADRACK 0x04 739 #define STELLARIS_I2C_MCS_DATACK 0x08 740 #define STELLARIS_I2C_MCS_ARBLST 0x10 741 #define STELLARIS_I2C_MCS_IDLE 0x20 742 #define STELLARIS_I2C_MCS_BUSBSY 0x40 743 744 static uint64_t stellaris_i2c_read(void *opaque, hwaddr offset, 745 unsigned size) 746 { 747 stellaris_i2c_state *s = (stellaris_i2c_state *)opaque; 748 749 switch (offset) { 750 case 0x00: /* MSA */ 751 return s->msa; 752 case 0x04: /* MCS */ 753 /* We don't emulate timing, so the controller is never busy. */ 754 return s->mcs | STELLARIS_I2C_MCS_IDLE; 755 case 0x08: /* MDR */ 756 return s->mdr; 757 case 0x0c: /* MTPR */ 758 return s->mtpr; 759 case 0x10: /* MIMR */ 760 return s->mimr; 761 case 0x14: /* MRIS */ 762 return s->mris; 763 case 0x18: /* MMIS */ 764 return s->mris & s->mimr; 765 case 0x20: /* MCR */ 766 return s->mcr; 767 default: 768 qemu_log_mask(LOG_GUEST_ERROR, 769 "stellaris_i2c: read at bad offset 0x%x\n", (int)offset); 770 return 0; 771 } 772 } 773 774 static void stellaris_i2c_update(stellaris_i2c_state *s) 775 { 776 int level; 777 778 level = (s->mris & s->mimr) != 0; 779 qemu_set_irq(s->irq, level); 780 } 781 782 static void stellaris_i2c_write(void *opaque, hwaddr offset, 783 uint64_t value, unsigned size) 784 { 785 stellaris_i2c_state *s = (stellaris_i2c_state *)opaque; 786 787 switch (offset) { 788 case 0x00: /* MSA */ 789 s->msa = value & 0xff; 790 break; 791 case 0x04: /* MCS */ 792 if ((s->mcr & 0x10) == 0) { 793 /* Disabled. Do nothing. */ 794 break; 795 } 796 /* Grab the bus if this is starting a transfer. */ 797 if ((value & 2) && (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) { 798 if (i2c_start_transfer(s->bus, s->msa >> 1, s->msa & 1)) { 799 s->mcs |= STELLARIS_I2C_MCS_ARBLST; 800 } else { 801 s->mcs &= ~STELLARIS_I2C_MCS_ARBLST; 802 s->mcs |= STELLARIS_I2C_MCS_BUSBSY; 803 } 804 } 805 /* If we don't have the bus then indicate an error. */ 806 if (!i2c_bus_busy(s->bus) 807 || (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) { 808 s->mcs |= STELLARIS_I2C_MCS_ERROR; 809 break; 810 } 811 s->mcs &= ~STELLARIS_I2C_MCS_ERROR; 812 if (value & 1) { 813 /* Transfer a byte. */ 814 /* TODO: Handle errors. */ 815 if (s->msa & 1) { 816 /* Recv */ 817 s->mdr = i2c_recv(s->bus); 818 } else { 819 /* Send */ 820 i2c_send(s->bus, s->mdr); 821 } 822 /* Raise an interrupt. */ 823 s->mris |= 1; 824 } 825 if (value & 4) { 826 /* Finish transfer. */ 827 i2c_end_transfer(s->bus); 828 s->mcs &= ~STELLARIS_I2C_MCS_BUSBSY; 829 } 830 break; 831 case 0x08: /* MDR */ 832 s->mdr = value & 0xff; 833 break; 834 case 0x0c: /* MTPR */ 835 s->mtpr = value & 0xff; 836 break; 837 case 0x10: /* MIMR */ 838 s->mimr = 1; 839 break; 840 case 0x1c: /* MICR */ 841 s->mris &= ~value; 842 break; 843 case 0x20: /* MCR */ 844 if (value & 1) { 845 qemu_log_mask(LOG_UNIMP, 846 "stellaris_i2c: Loopback not implemented\n"); 847 } 848 if (value & 0x20) { 849 qemu_log_mask(LOG_UNIMP, 850 "stellaris_i2c: Slave mode not implemented\n"); 851 } 852 s->mcr = value & 0x31; 853 break; 854 default: 855 qemu_log_mask(LOG_GUEST_ERROR, 856 "stellaris_i2c: write at bad offset 0x%x\n", (int)offset); 857 } 858 stellaris_i2c_update(s); 859 } 860 861 static void stellaris_i2c_reset(stellaris_i2c_state *s) 862 { 863 if (s->mcs & STELLARIS_I2C_MCS_BUSBSY) 864 i2c_end_transfer(s->bus); 865 866 s->msa = 0; 867 s->mcs = 0; 868 s->mdr = 0; 869 s->mtpr = 1; 870 s->mimr = 0; 871 s->mris = 0; 872 s->mcr = 0; 873 stellaris_i2c_update(s); 874 } 875 876 static const MemoryRegionOps stellaris_i2c_ops = { 877 .read = stellaris_i2c_read, 878 .write = stellaris_i2c_write, 879 .endianness = DEVICE_NATIVE_ENDIAN, 880 }; 881 882 static const VMStateDescription vmstate_stellaris_i2c = { 883 .name = "stellaris_i2c", 884 .version_id = 1, 885 .minimum_version_id = 1, 886 .fields = (VMStateField[]) { 887 VMSTATE_UINT32(msa, stellaris_i2c_state), 888 VMSTATE_UINT32(mcs, stellaris_i2c_state), 889 VMSTATE_UINT32(mdr, stellaris_i2c_state), 890 VMSTATE_UINT32(mtpr, stellaris_i2c_state), 891 VMSTATE_UINT32(mimr, stellaris_i2c_state), 892 VMSTATE_UINT32(mris, stellaris_i2c_state), 893 VMSTATE_UINT32(mcr, stellaris_i2c_state), 894 VMSTATE_END_OF_LIST() 895 } 896 }; 897 898 static void stellaris_i2c_init(Object *obj) 899 { 900 DeviceState *dev = DEVICE(obj); 901 stellaris_i2c_state *s = STELLARIS_I2C(obj); 902 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 903 I2CBus *bus; 904 905 sysbus_init_irq(sbd, &s->irq); 906 bus = i2c_init_bus(dev, "i2c"); 907 s->bus = bus; 908 909 memory_region_init_io(&s->iomem, obj, &stellaris_i2c_ops, s, 910 "i2c", 0x1000); 911 sysbus_init_mmio(sbd, &s->iomem); 912 /* ??? For now we only implement the master interface. */ 913 stellaris_i2c_reset(s); 914 } 915 916 /* Analogue to Digital Converter. This is only partially implemented, 917 enough for applications that use a combined ADC and timer tick. */ 918 919 #define STELLARIS_ADC_EM_CONTROLLER 0 920 #define STELLARIS_ADC_EM_COMP 1 921 #define STELLARIS_ADC_EM_EXTERNAL 4 922 #define STELLARIS_ADC_EM_TIMER 5 923 #define STELLARIS_ADC_EM_PWM0 6 924 #define STELLARIS_ADC_EM_PWM1 7 925 #define STELLARIS_ADC_EM_PWM2 8 926 927 #define STELLARIS_ADC_FIFO_EMPTY 0x0100 928 #define STELLARIS_ADC_FIFO_FULL 0x1000 929 930 #define TYPE_STELLARIS_ADC "stellaris-adc" 931 #define STELLARIS_ADC(obj) \ 932 OBJECT_CHECK(stellaris_adc_state, (obj), TYPE_STELLARIS_ADC) 933 934 typedef struct StellarisADCState { 935 SysBusDevice parent_obj; 936 937 MemoryRegion iomem; 938 uint32_t actss; 939 uint32_t ris; 940 uint32_t im; 941 uint32_t emux; 942 uint32_t ostat; 943 uint32_t ustat; 944 uint32_t sspri; 945 uint32_t sac; 946 struct { 947 uint32_t state; 948 uint32_t data[16]; 949 } fifo[4]; 950 uint32_t ssmux[4]; 951 uint32_t ssctl[4]; 952 uint32_t noise; 953 qemu_irq irq[4]; 954 } stellaris_adc_state; 955 956 static uint32_t stellaris_adc_fifo_read(stellaris_adc_state *s, int n) 957 { 958 int tail; 959 960 tail = s->fifo[n].state & 0xf; 961 if (s->fifo[n].state & STELLARIS_ADC_FIFO_EMPTY) { 962 s->ustat |= 1 << n; 963 } else { 964 s->fifo[n].state = (s->fifo[n].state & ~0xf) | ((tail + 1) & 0xf); 965 s->fifo[n].state &= ~STELLARIS_ADC_FIFO_FULL; 966 if (tail + 1 == ((s->fifo[n].state >> 4) & 0xf)) 967 s->fifo[n].state |= STELLARIS_ADC_FIFO_EMPTY; 968 } 969 return s->fifo[n].data[tail]; 970 } 971 972 static void stellaris_adc_fifo_write(stellaris_adc_state *s, int n, 973 uint32_t value) 974 { 975 int head; 976 977 /* TODO: Real hardware has limited size FIFOs. We have a full 16 entry 978 FIFO fir each sequencer. */ 979 head = (s->fifo[n].state >> 4) & 0xf; 980 if (s->fifo[n].state & STELLARIS_ADC_FIFO_FULL) { 981 s->ostat |= 1 << n; 982 return; 983 } 984 s->fifo[n].data[head] = value; 985 head = (head + 1) & 0xf; 986 s->fifo[n].state &= ~STELLARIS_ADC_FIFO_EMPTY; 987 s->fifo[n].state = (s->fifo[n].state & ~0xf0) | (head << 4); 988 if ((s->fifo[n].state & 0xf) == head) 989 s->fifo[n].state |= STELLARIS_ADC_FIFO_FULL; 990 } 991 992 static void stellaris_adc_update(stellaris_adc_state *s) 993 { 994 int level; 995 int n; 996 997 for (n = 0; n < 4; n++) { 998 level = (s->ris & s->im & (1 << n)) != 0; 999 qemu_set_irq(s->irq[n], level); 1000 } 1001 } 1002 1003 static void stellaris_adc_trigger(void *opaque, int irq, int level) 1004 { 1005 stellaris_adc_state *s = (stellaris_adc_state *)opaque; 1006 int n; 1007 1008 for (n = 0; n < 4; n++) { 1009 if ((s->actss & (1 << n)) == 0) { 1010 continue; 1011 } 1012 1013 if (((s->emux >> (n * 4)) & 0xff) != 5) { 1014 continue; 1015 } 1016 1017 /* Some applications use the ADC as a random number source, so introduce 1018 some variation into the signal. */ 1019 s->noise = s->noise * 314159 + 1; 1020 /* ??? actual inputs not implemented. Return an arbitrary value. */ 1021 stellaris_adc_fifo_write(s, n, 0x200 + ((s->noise >> 16) & 7)); 1022 s->ris |= (1 << n); 1023 stellaris_adc_update(s); 1024 } 1025 } 1026 1027 static void stellaris_adc_reset(stellaris_adc_state *s) 1028 { 1029 int n; 1030 1031 for (n = 0; n < 4; n++) { 1032 s->ssmux[n] = 0; 1033 s->ssctl[n] = 0; 1034 s->fifo[n].state = STELLARIS_ADC_FIFO_EMPTY; 1035 } 1036 } 1037 1038 static uint64_t stellaris_adc_read(void *opaque, hwaddr offset, 1039 unsigned size) 1040 { 1041 stellaris_adc_state *s = (stellaris_adc_state *)opaque; 1042 1043 /* TODO: Implement this. */ 1044 if (offset >= 0x40 && offset < 0xc0) { 1045 int n; 1046 n = (offset - 0x40) >> 5; 1047 switch (offset & 0x1f) { 1048 case 0x00: /* SSMUX */ 1049 return s->ssmux[n]; 1050 case 0x04: /* SSCTL */ 1051 return s->ssctl[n]; 1052 case 0x08: /* SSFIFO */ 1053 return stellaris_adc_fifo_read(s, n); 1054 case 0x0c: /* SSFSTAT */ 1055 return s->fifo[n].state; 1056 default: 1057 break; 1058 } 1059 } 1060 switch (offset) { 1061 case 0x00: /* ACTSS */ 1062 return s->actss; 1063 case 0x04: /* RIS */ 1064 return s->ris; 1065 case 0x08: /* IM */ 1066 return s->im; 1067 case 0x0c: /* ISC */ 1068 return s->ris & s->im; 1069 case 0x10: /* OSTAT */ 1070 return s->ostat; 1071 case 0x14: /* EMUX */ 1072 return s->emux; 1073 case 0x18: /* USTAT */ 1074 return s->ustat; 1075 case 0x20: /* SSPRI */ 1076 return s->sspri; 1077 case 0x30: /* SAC */ 1078 return s->sac; 1079 default: 1080 qemu_log_mask(LOG_GUEST_ERROR, 1081 "stellaris_adc: read at bad offset 0x%x\n", (int)offset); 1082 return 0; 1083 } 1084 } 1085 1086 static void stellaris_adc_write(void *opaque, hwaddr offset, 1087 uint64_t value, unsigned size) 1088 { 1089 stellaris_adc_state *s = (stellaris_adc_state *)opaque; 1090 1091 /* TODO: Implement this. */ 1092 if (offset >= 0x40 && offset < 0xc0) { 1093 int n; 1094 n = (offset - 0x40) >> 5; 1095 switch (offset & 0x1f) { 1096 case 0x00: /* SSMUX */ 1097 s->ssmux[n] = value & 0x33333333; 1098 return; 1099 case 0x04: /* SSCTL */ 1100 if (value != 6) { 1101 qemu_log_mask(LOG_UNIMP, 1102 "ADC: Unimplemented sequence %" PRIx64 "\n", 1103 value); 1104 } 1105 s->ssctl[n] = value; 1106 return; 1107 default: 1108 break; 1109 } 1110 } 1111 switch (offset) { 1112 case 0x00: /* ACTSS */ 1113 s->actss = value & 0xf; 1114 break; 1115 case 0x08: /* IM */ 1116 s->im = value; 1117 break; 1118 case 0x0c: /* ISC */ 1119 s->ris &= ~value; 1120 break; 1121 case 0x10: /* OSTAT */ 1122 s->ostat &= ~value; 1123 break; 1124 case 0x14: /* EMUX */ 1125 s->emux = value; 1126 break; 1127 case 0x18: /* USTAT */ 1128 s->ustat &= ~value; 1129 break; 1130 case 0x20: /* SSPRI */ 1131 s->sspri = value; 1132 break; 1133 case 0x28: /* PSSI */ 1134 qemu_log_mask(LOG_UNIMP, "ADC: sample initiate unimplemented\n"); 1135 break; 1136 case 0x30: /* SAC */ 1137 s->sac = value; 1138 break; 1139 default: 1140 qemu_log_mask(LOG_GUEST_ERROR, 1141 "stellaris_adc: write at bad offset 0x%x\n", (int)offset); 1142 } 1143 stellaris_adc_update(s); 1144 } 1145 1146 static const MemoryRegionOps stellaris_adc_ops = { 1147 .read = stellaris_adc_read, 1148 .write = stellaris_adc_write, 1149 .endianness = DEVICE_NATIVE_ENDIAN, 1150 }; 1151 1152 static const VMStateDescription vmstate_stellaris_adc = { 1153 .name = "stellaris_adc", 1154 .version_id = 1, 1155 .minimum_version_id = 1, 1156 .fields = (VMStateField[]) { 1157 VMSTATE_UINT32(actss, stellaris_adc_state), 1158 VMSTATE_UINT32(ris, stellaris_adc_state), 1159 VMSTATE_UINT32(im, stellaris_adc_state), 1160 VMSTATE_UINT32(emux, stellaris_adc_state), 1161 VMSTATE_UINT32(ostat, stellaris_adc_state), 1162 VMSTATE_UINT32(ustat, stellaris_adc_state), 1163 VMSTATE_UINT32(sspri, stellaris_adc_state), 1164 VMSTATE_UINT32(sac, stellaris_adc_state), 1165 VMSTATE_UINT32(fifo[0].state, stellaris_adc_state), 1166 VMSTATE_UINT32_ARRAY(fifo[0].data, stellaris_adc_state, 16), 1167 VMSTATE_UINT32(ssmux[0], stellaris_adc_state), 1168 VMSTATE_UINT32(ssctl[0], stellaris_adc_state), 1169 VMSTATE_UINT32(fifo[1].state, stellaris_adc_state), 1170 VMSTATE_UINT32_ARRAY(fifo[1].data, stellaris_adc_state, 16), 1171 VMSTATE_UINT32(ssmux[1], stellaris_adc_state), 1172 VMSTATE_UINT32(ssctl[1], stellaris_adc_state), 1173 VMSTATE_UINT32(fifo[2].state, stellaris_adc_state), 1174 VMSTATE_UINT32_ARRAY(fifo[2].data, stellaris_adc_state, 16), 1175 VMSTATE_UINT32(ssmux[2], stellaris_adc_state), 1176 VMSTATE_UINT32(ssctl[2], stellaris_adc_state), 1177 VMSTATE_UINT32(fifo[3].state, stellaris_adc_state), 1178 VMSTATE_UINT32_ARRAY(fifo[3].data, stellaris_adc_state, 16), 1179 VMSTATE_UINT32(ssmux[3], stellaris_adc_state), 1180 VMSTATE_UINT32(ssctl[3], stellaris_adc_state), 1181 VMSTATE_UINT32(noise, stellaris_adc_state), 1182 VMSTATE_END_OF_LIST() 1183 } 1184 }; 1185 1186 static void stellaris_adc_init(Object *obj) 1187 { 1188 DeviceState *dev = DEVICE(obj); 1189 stellaris_adc_state *s = STELLARIS_ADC(obj); 1190 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 1191 int n; 1192 1193 for (n = 0; n < 4; n++) { 1194 sysbus_init_irq(sbd, &s->irq[n]); 1195 } 1196 1197 memory_region_init_io(&s->iomem, obj, &stellaris_adc_ops, s, 1198 "adc", 0x1000); 1199 sysbus_init_mmio(sbd, &s->iomem); 1200 stellaris_adc_reset(s); 1201 qdev_init_gpio_in(dev, stellaris_adc_trigger, 1); 1202 } 1203 1204 static 1205 void do_sys_reset(void *opaque, int n, int level) 1206 { 1207 if (level) { 1208 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 1209 } 1210 } 1211 1212 /* Board init. */ 1213 static stellaris_board_info stellaris_boards[] = { 1214 { "LM3S811EVB", 1215 0, 1216 0x0032000e, 1217 0x001f001f, /* dc0 */ 1218 0x001132bf, 1219 0x01071013, 1220 0x3f0f01ff, 1221 0x0000001f, 1222 BP_OLED_I2C 1223 }, 1224 { "LM3S6965EVB", 1225 0x10010002, 1226 0x1073402e, 1227 0x00ff007f, /* dc0 */ 1228 0x001133ff, 1229 0x030f5317, 1230 0x0f0f87ff, 1231 0x5000007f, 1232 BP_OLED_SSI | BP_GAMEPAD 1233 } 1234 }; 1235 1236 static void stellaris_init(MachineState *ms, stellaris_board_info *board) 1237 { 1238 static const int uart_irq[] = {5, 6, 33, 34}; 1239 static const int timer_irq[] = {19, 21, 23, 35}; 1240 static const uint32_t gpio_addr[7] = 1241 { 0x40004000, 0x40005000, 0x40006000, 0x40007000, 1242 0x40024000, 0x40025000, 0x40026000}; 1243 static const int gpio_irq[7] = {0, 1, 2, 3, 4, 30, 31}; 1244 1245 /* Memory map of SoC devices, from 1246 * Stellaris LM3S6965 Microcontroller Data Sheet (rev I) 1247 * http://www.ti.com/lit/ds/symlink/lm3s6965.pdf 1248 * 1249 * 40000000 wdtimer 1250 * 40002000 i2c (unimplemented) 1251 * 40004000 GPIO 1252 * 40005000 GPIO 1253 * 40006000 GPIO 1254 * 40007000 GPIO 1255 * 40008000 SSI 1256 * 4000c000 UART 1257 * 4000d000 UART 1258 * 4000e000 UART 1259 * 40020000 i2c 1260 * 40021000 i2c (unimplemented) 1261 * 40024000 GPIO 1262 * 40025000 GPIO 1263 * 40026000 GPIO 1264 * 40028000 PWM (unimplemented) 1265 * 4002c000 QEI (unimplemented) 1266 * 4002d000 QEI (unimplemented) 1267 * 40030000 gptimer 1268 * 40031000 gptimer 1269 * 40032000 gptimer 1270 * 40033000 gptimer 1271 * 40038000 ADC 1272 * 4003c000 analogue comparator (unimplemented) 1273 * 40048000 ethernet 1274 * 400fc000 hibernation module (unimplemented) 1275 * 400fd000 flash memory control (unimplemented) 1276 * 400fe000 system control 1277 */ 1278 1279 DeviceState *gpio_dev[7], *nvic; 1280 qemu_irq gpio_in[7][8]; 1281 qemu_irq gpio_out[7][8]; 1282 qemu_irq adc; 1283 int sram_size; 1284 int flash_size; 1285 I2CBus *i2c; 1286 DeviceState *dev; 1287 int i; 1288 int j; 1289 1290 MemoryRegion *sram = g_new(MemoryRegion, 1); 1291 MemoryRegion *flash = g_new(MemoryRegion, 1); 1292 MemoryRegion *system_memory = get_system_memory(); 1293 1294 flash_size = (((board->dc0 & 0xffff) + 1) << 1) * 1024; 1295 sram_size = ((board->dc0 >> 18) + 1) * 1024; 1296 1297 /* Flash programming is done via the SCU, so pretend it is ROM. */ 1298 memory_region_init_ram(flash, NULL, "stellaris.flash", flash_size, 1299 &error_fatal); 1300 memory_region_set_readonly(flash, true); 1301 memory_region_add_subregion(system_memory, 0, flash); 1302 1303 memory_region_init_ram(sram, NULL, "stellaris.sram", sram_size, 1304 &error_fatal); 1305 memory_region_add_subregion(system_memory, 0x20000000, sram); 1306 1307 nvic = qdev_create(NULL, TYPE_ARMV7M); 1308 qdev_prop_set_uint32(nvic, "num-irq", NUM_IRQ_LINES); 1309 qdev_prop_set_string(nvic, "cpu-type", ms->cpu_type); 1310 qdev_prop_set_bit(nvic, "enable-bitband", true); 1311 object_property_set_link(OBJECT(nvic), OBJECT(get_system_memory()), 1312 "memory", &error_abort); 1313 /* This will exit with an error if the user passed us a bad cpu_type */ 1314 qdev_init_nofail(nvic); 1315 1316 qdev_connect_gpio_out_named(nvic, "SYSRESETREQ", 0, 1317 qemu_allocate_irq(&do_sys_reset, NULL, 0)); 1318 1319 if (board->dc1 & (1 << 16)) { 1320 dev = sysbus_create_varargs(TYPE_STELLARIS_ADC, 0x40038000, 1321 qdev_get_gpio_in(nvic, 14), 1322 qdev_get_gpio_in(nvic, 15), 1323 qdev_get_gpio_in(nvic, 16), 1324 qdev_get_gpio_in(nvic, 17), 1325 NULL); 1326 adc = qdev_get_gpio_in(dev, 0); 1327 } else { 1328 adc = NULL; 1329 } 1330 for (i = 0; i < 4; i++) { 1331 if (board->dc2 & (0x10000 << i)) { 1332 dev = sysbus_create_simple(TYPE_STELLARIS_GPTM, 1333 0x40030000 + i * 0x1000, 1334 qdev_get_gpio_in(nvic, timer_irq[i])); 1335 /* TODO: This is incorrect, but we get away with it because 1336 the ADC output is only ever pulsed. */ 1337 qdev_connect_gpio_out(dev, 0, adc); 1338 } 1339 } 1340 1341 stellaris_sys_init(0x400fe000, qdev_get_gpio_in(nvic, 28), 1342 board, nd_table[0].macaddr.a); 1343 1344 1345 if (board->dc1 & (1 << 3)) { /* watchdog present */ 1346 dev = qdev_create(NULL, TYPE_LUMINARY_WATCHDOG); 1347 1348 /* system_clock_scale is valid now */ 1349 uint32_t mainclk = NANOSECONDS_PER_SECOND / system_clock_scale; 1350 qdev_prop_set_uint32(dev, "wdogclk-frq", mainclk); 1351 1352 qdev_init_nofail(dev); 1353 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1354 0, 1355 0x40000000u); 1356 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1357 0, 1358 qdev_get_gpio_in(nvic, 18)); 1359 } 1360 1361 1362 for (i = 0; i < 7; i++) { 1363 if (board->dc4 & (1 << i)) { 1364 gpio_dev[i] = sysbus_create_simple("pl061_luminary", gpio_addr[i], 1365 qdev_get_gpio_in(nvic, 1366 gpio_irq[i])); 1367 for (j = 0; j < 8; j++) { 1368 gpio_in[i][j] = qdev_get_gpio_in(gpio_dev[i], j); 1369 gpio_out[i][j] = NULL; 1370 } 1371 } 1372 } 1373 1374 if (board->dc2 & (1 << 12)) { 1375 dev = sysbus_create_simple(TYPE_STELLARIS_I2C, 0x40020000, 1376 qdev_get_gpio_in(nvic, 8)); 1377 i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c"); 1378 if (board->peripherals & BP_OLED_I2C) { 1379 i2c_create_slave(i2c, "ssd0303", 0x3d); 1380 } 1381 } 1382 1383 for (i = 0; i < 4; i++) { 1384 if (board->dc2 & (1 << i)) { 1385 pl011_luminary_create(0x4000c000 + i * 0x1000, 1386 qdev_get_gpio_in(nvic, uart_irq[i]), 1387 serial_hd(i)); 1388 } 1389 } 1390 if (board->dc2 & (1 << 4)) { 1391 dev = sysbus_create_simple("pl022", 0x40008000, 1392 qdev_get_gpio_in(nvic, 7)); 1393 if (board->peripherals & BP_OLED_SSI) { 1394 void *bus; 1395 DeviceState *sddev; 1396 DeviceState *ssddev; 1397 1398 /* Some boards have both an OLED controller and SD card connected to 1399 * the same SSI port, with the SD card chip select connected to a 1400 * GPIO pin. Technically the OLED chip select is connected to the 1401 * SSI Fss pin. We do not bother emulating that as both devices 1402 * should never be selected simultaneously, and our OLED controller 1403 * ignores stray 0xff commands that occur when deselecting the SD 1404 * card. 1405 */ 1406 bus = qdev_get_child_bus(dev, "ssi"); 1407 1408 sddev = ssi_create_slave(bus, "ssi-sd"); 1409 ssddev = ssi_create_slave(bus, "ssd0323"); 1410 gpio_out[GPIO_D][0] = qemu_irq_split( 1411 qdev_get_gpio_in_named(sddev, SSI_GPIO_CS, 0), 1412 qdev_get_gpio_in_named(ssddev, SSI_GPIO_CS, 0)); 1413 gpio_out[GPIO_C][7] = qdev_get_gpio_in(ssddev, 0); 1414 1415 /* Make sure the select pin is high. */ 1416 qemu_irq_raise(gpio_out[GPIO_D][0]); 1417 } 1418 } 1419 if (board->dc4 & (1 << 28)) { 1420 DeviceState *enet; 1421 1422 qemu_check_nic_model(&nd_table[0], "stellaris"); 1423 1424 enet = qdev_create(NULL, "stellaris_enet"); 1425 qdev_set_nic_properties(enet, &nd_table[0]); 1426 qdev_init_nofail(enet); 1427 sysbus_mmio_map(SYS_BUS_DEVICE(enet), 0, 0x40048000); 1428 sysbus_connect_irq(SYS_BUS_DEVICE(enet), 0, qdev_get_gpio_in(nvic, 42)); 1429 } 1430 if (board->peripherals & BP_GAMEPAD) { 1431 qemu_irq gpad_irq[5]; 1432 static const int gpad_keycode[5] = { 0xc8, 0xd0, 0xcb, 0xcd, 0x1d }; 1433 1434 gpad_irq[0] = qemu_irq_invert(gpio_in[GPIO_E][0]); /* up */ 1435 gpad_irq[1] = qemu_irq_invert(gpio_in[GPIO_E][1]); /* down */ 1436 gpad_irq[2] = qemu_irq_invert(gpio_in[GPIO_E][2]); /* left */ 1437 gpad_irq[3] = qemu_irq_invert(gpio_in[GPIO_E][3]); /* right */ 1438 gpad_irq[4] = qemu_irq_invert(gpio_in[GPIO_F][1]); /* select */ 1439 1440 stellaris_gamepad_init(5, gpad_irq, gpad_keycode); 1441 } 1442 for (i = 0; i < 7; i++) { 1443 if (board->dc4 & (1 << i)) { 1444 for (j = 0; j < 8; j++) { 1445 if (gpio_out[i][j]) { 1446 qdev_connect_gpio_out(gpio_dev[i], j, gpio_out[i][j]); 1447 } 1448 } 1449 } 1450 } 1451 1452 /* Add dummy regions for the devices we don't implement yet, 1453 * so guest accesses don't cause unlogged crashes. 1454 */ 1455 create_unimplemented_device("i2c-0", 0x40002000, 0x1000); 1456 create_unimplemented_device("i2c-2", 0x40021000, 0x1000); 1457 create_unimplemented_device("PWM", 0x40028000, 0x1000); 1458 create_unimplemented_device("QEI-0", 0x4002c000, 0x1000); 1459 create_unimplemented_device("QEI-1", 0x4002d000, 0x1000); 1460 create_unimplemented_device("analogue-comparator", 0x4003c000, 0x1000); 1461 create_unimplemented_device("hibernation", 0x400fc000, 0x1000); 1462 create_unimplemented_device("flash-control", 0x400fd000, 0x1000); 1463 1464 armv7m_load_kernel(ARM_CPU(first_cpu), ms->kernel_filename, flash_size); 1465 } 1466 1467 /* FIXME: Figure out how to generate these from stellaris_boards. */ 1468 static void lm3s811evb_init(MachineState *machine) 1469 { 1470 stellaris_init(machine, &stellaris_boards[0]); 1471 } 1472 1473 static void lm3s6965evb_init(MachineState *machine) 1474 { 1475 stellaris_init(machine, &stellaris_boards[1]); 1476 } 1477 1478 static void lm3s811evb_class_init(ObjectClass *oc, void *data) 1479 { 1480 MachineClass *mc = MACHINE_CLASS(oc); 1481 1482 mc->desc = "Stellaris LM3S811EVB"; 1483 mc->init = lm3s811evb_init; 1484 mc->ignore_memory_transaction_failures = true; 1485 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3"); 1486 } 1487 1488 static const TypeInfo lm3s811evb_type = { 1489 .name = MACHINE_TYPE_NAME("lm3s811evb"), 1490 .parent = TYPE_MACHINE, 1491 .class_init = lm3s811evb_class_init, 1492 }; 1493 1494 static void lm3s6965evb_class_init(ObjectClass *oc, void *data) 1495 { 1496 MachineClass *mc = MACHINE_CLASS(oc); 1497 1498 mc->desc = "Stellaris LM3S6965EVB"; 1499 mc->init = lm3s6965evb_init; 1500 mc->ignore_memory_transaction_failures = true; 1501 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3"); 1502 } 1503 1504 static const TypeInfo lm3s6965evb_type = { 1505 .name = MACHINE_TYPE_NAME("lm3s6965evb"), 1506 .parent = TYPE_MACHINE, 1507 .class_init = lm3s6965evb_class_init, 1508 }; 1509 1510 static void stellaris_machine_init(void) 1511 { 1512 type_register_static(&lm3s811evb_type); 1513 type_register_static(&lm3s6965evb_type); 1514 } 1515 1516 type_init(stellaris_machine_init) 1517 1518 static void stellaris_i2c_class_init(ObjectClass *klass, void *data) 1519 { 1520 DeviceClass *dc = DEVICE_CLASS(klass); 1521 1522 dc->vmsd = &vmstate_stellaris_i2c; 1523 } 1524 1525 static const TypeInfo stellaris_i2c_info = { 1526 .name = TYPE_STELLARIS_I2C, 1527 .parent = TYPE_SYS_BUS_DEVICE, 1528 .instance_size = sizeof(stellaris_i2c_state), 1529 .instance_init = stellaris_i2c_init, 1530 .class_init = stellaris_i2c_class_init, 1531 }; 1532 1533 static void stellaris_gptm_class_init(ObjectClass *klass, void *data) 1534 { 1535 DeviceClass *dc = DEVICE_CLASS(klass); 1536 1537 dc->vmsd = &vmstate_stellaris_gptm; 1538 } 1539 1540 static const TypeInfo stellaris_gptm_info = { 1541 .name = TYPE_STELLARIS_GPTM, 1542 .parent = TYPE_SYS_BUS_DEVICE, 1543 .instance_size = sizeof(gptm_state), 1544 .instance_init = stellaris_gptm_init, 1545 .class_init = stellaris_gptm_class_init, 1546 }; 1547 1548 static void stellaris_adc_class_init(ObjectClass *klass, void *data) 1549 { 1550 DeviceClass *dc = DEVICE_CLASS(klass); 1551 1552 dc->vmsd = &vmstate_stellaris_adc; 1553 } 1554 1555 static const TypeInfo stellaris_adc_info = { 1556 .name = TYPE_STELLARIS_ADC, 1557 .parent = TYPE_SYS_BUS_DEVICE, 1558 .instance_size = sizeof(stellaris_adc_state), 1559 .instance_init = stellaris_adc_init, 1560 .class_init = stellaris_adc_class_init, 1561 }; 1562 1563 static void stellaris_register_types(void) 1564 { 1565 type_register_static(&stellaris_i2c_info); 1566 type_register_static(&stellaris_gptm_info); 1567 type_register_static(&stellaris_adc_info); 1568 } 1569 1570 type_init(stellaris_register_types) 1571