1 /* 2 * Luminary Micro Stellaris peripherals 3 * 4 * Copyright (c) 2006 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qapi/error.h" 12 #include "hw/sysbus.h" 13 #include "hw/ssi/ssi.h" 14 #include "hw/arm/boot.h" 15 #include "qemu/timer.h" 16 #include "hw/i2c/i2c.h" 17 #include "net/net.h" 18 #include "hw/boards.h" 19 #include "qemu/log.h" 20 #include "exec/address-spaces.h" 21 #include "sysemu/sysemu.h" 22 #include "hw/arm/armv7m.h" 23 #include "hw/char/pl011.h" 24 #include "hw/input/gamepad.h" 25 #include "hw/irq.h" 26 #include "hw/watchdog/cmsdk-apb-watchdog.h" 27 #include "hw/misc/unimp.h" 28 #include "cpu.h" 29 30 #define GPIO_A 0 31 #define GPIO_B 1 32 #define GPIO_C 2 33 #define GPIO_D 3 34 #define GPIO_E 4 35 #define GPIO_F 5 36 #define GPIO_G 6 37 38 #define BP_OLED_I2C 0x01 39 #define BP_OLED_SSI 0x02 40 #define BP_GAMEPAD 0x04 41 42 #define NUM_IRQ_LINES 64 43 44 typedef const struct { 45 const char *name; 46 uint32_t did0; 47 uint32_t did1; 48 uint32_t dc0; 49 uint32_t dc1; 50 uint32_t dc2; 51 uint32_t dc3; 52 uint32_t dc4; 53 uint32_t peripherals; 54 } stellaris_board_info; 55 56 /* General purpose timer module. */ 57 58 #define TYPE_STELLARIS_GPTM "stellaris-gptm" 59 #define STELLARIS_GPTM(obj) \ 60 OBJECT_CHECK(gptm_state, (obj), TYPE_STELLARIS_GPTM) 61 62 typedef struct gptm_state { 63 SysBusDevice parent_obj; 64 65 MemoryRegion iomem; 66 uint32_t config; 67 uint32_t mode[2]; 68 uint32_t control; 69 uint32_t state; 70 uint32_t mask; 71 uint32_t load[2]; 72 uint32_t match[2]; 73 uint32_t prescale[2]; 74 uint32_t match_prescale[2]; 75 uint32_t rtc; 76 int64_t tick[2]; 77 struct gptm_state *opaque[2]; 78 QEMUTimer *timer[2]; 79 /* The timers have an alternate output used to trigger the ADC. */ 80 qemu_irq trigger; 81 qemu_irq irq; 82 } gptm_state; 83 84 static void gptm_update_irq(gptm_state *s) 85 { 86 int level; 87 level = (s->state & s->mask) != 0; 88 qemu_set_irq(s->irq, level); 89 } 90 91 static void gptm_stop(gptm_state *s, int n) 92 { 93 timer_del(s->timer[n]); 94 } 95 96 static void gptm_reload(gptm_state *s, int n, int reset) 97 { 98 int64_t tick; 99 if (reset) 100 tick = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 101 else 102 tick = s->tick[n]; 103 104 if (s->config == 0) { 105 /* 32-bit CountDown. */ 106 uint32_t count; 107 count = s->load[0] | (s->load[1] << 16); 108 tick += (int64_t)count * system_clock_scale; 109 } else if (s->config == 1) { 110 /* 32-bit RTC. 1Hz tick. */ 111 tick += NANOSECONDS_PER_SECOND; 112 } else if (s->mode[n] == 0xa) { 113 /* PWM mode. Not implemented. */ 114 } else { 115 qemu_log_mask(LOG_UNIMP, 116 "GPTM: 16-bit timer mode unimplemented: 0x%x\n", 117 s->mode[n]); 118 return; 119 } 120 s->tick[n] = tick; 121 timer_mod(s->timer[n], tick); 122 } 123 124 static void gptm_tick(void *opaque) 125 { 126 gptm_state **p = (gptm_state **)opaque; 127 gptm_state *s; 128 int n; 129 130 s = *p; 131 n = p - s->opaque; 132 if (s->config == 0) { 133 s->state |= 1; 134 if ((s->control & 0x20)) { 135 /* Output trigger. */ 136 qemu_irq_pulse(s->trigger); 137 } 138 if (s->mode[0] & 1) { 139 /* One-shot. */ 140 s->control &= ~1; 141 } else { 142 /* Periodic. */ 143 gptm_reload(s, 0, 0); 144 } 145 } else if (s->config == 1) { 146 /* RTC. */ 147 uint32_t match; 148 s->rtc++; 149 match = s->match[0] | (s->match[1] << 16); 150 if (s->rtc > match) 151 s->rtc = 0; 152 if (s->rtc == 0) { 153 s->state |= 8; 154 } 155 gptm_reload(s, 0, 0); 156 } else if (s->mode[n] == 0xa) { 157 /* PWM mode. Not implemented. */ 158 } else { 159 qemu_log_mask(LOG_UNIMP, 160 "GPTM: 16-bit timer mode unimplemented: 0x%x\n", 161 s->mode[n]); 162 } 163 gptm_update_irq(s); 164 } 165 166 static uint64_t gptm_read(void *opaque, hwaddr offset, 167 unsigned size) 168 { 169 gptm_state *s = (gptm_state *)opaque; 170 171 switch (offset) { 172 case 0x00: /* CFG */ 173 return s->config; 174 case 0x04: /* TAMR */ 175 return s->mode[0]; 176 case 0x08: /* TBMR */ 177 return s->mode[1]; 178 case 0x0c: /* CTL */ 179 return s->control; 180 case 0x18: /* IMR */ 181 return s->mask; 182 case 0x1c: /* RIS */ 183 return s->state; 184 case 0x20: /* MIS */ 185 return s->state & s->mask; 186 case 0x24: /* CR */ 187 return 0; 188 case 0x28: /* TAILR */ 189 return s->load[0] | ((s->config < 4) ? (s->load[1] << 16) : 0); 190 case 0x2c: /* TBILR */ 191 return s->load[1]; 192 case 0x30: /* TAMARCHR */ 193 return s->match[0] | ((s->config < 4) ? (s->match[1] << 16) : 0); 194 case 0x34: /* TBMATCHR */ 195 return s->match[1]; 196 case 0x38: /* TAPR */ 197 return s->prescale[0]; 198 case 0x3c: /* TBPR */ 199 return s->prescale[1]; 200 case 0x40: /* TAPMR */ 201 return s->match_prescale[0]; 202 case 0x44: /* TBPMR */ 203 return s->match_prescale[1]; 204 case 0x48: /* TAR */ 205 if (s->config == 1) { 206 return s->rtc; 207 } 208 qemu_log_mask(LOG_UNIMP, 209 "GPTM: read of TAR but timer read not supported\n"); 210 return 0; 211 case 0x4c: /* TBR */ 212 qemu_log_mask(LOG_UNIMP, 213 "GPTM: read of TBR but timer read not supported\n"); 214 return 0; 215 default: 216 qemu_log_mask(LOG_GUEST_ERROR, 217 "GPTM: read at bad offset 0x02%" HWADDR_PRIx "\n", 218 offset); 219 return 0; 220 } 221 } 222 223 static void gptm_write(void *opaque, hwaddr offset, 224 uint64_t value, unsigned size) 225 { 226 gptm_state *s = (gptm_state *)opaque; 227 uint32_t oldval; 228 229 /* The timers should be disabled before changing the configuration. 230 We take advantage of this and defer everything until the timer 231 is enabled. */ 232 switch (offset) { 233 case 0x00: /* CFG */ 234 s->config = value; 235 break; 236 case 0x04: /* TAMR */ 237 s->mode[0] = value; 238 break; 239 case 0x08: /* TBMR */ 240 s->mode[1] = value; 241 break; 242 case 0x0c: /* CTL */ 243 oldval = s->control; 244 s->control = value; 245 /* TODO: Implement pause. */ 246 if ((oldval ^ value) & 1) { 247 if (value & 1) { 248 gptm_reload(s, 0, 1); 249 } else { 250 gptm_stop(s, 0); 251 } 252 } 253 if (((oldval ^ value) & 0x100) && s->config >= 4) { 254 if (value & 0x100) { 255 gptm_reload(s, 1, 1); 256 } else { 257 gptm_stop(s, 1); 258 } 259 } 260 break; 261 case 0x18: /* IMR */ 262 s->mask = value & 0x77; 263 gptm_update_irq(s); 264 break; 265 case 0x24: /* CR */ 266 s->state &= ~value; 267 break; 268 case 0x28: /* TAILR */ 269 s->load[0] = value & 0xffff; 270 if (s->config < 4) { 271 s->load[1] = value >> 16; 272 } 273 break; 274 case 0x2c: /* TBILR */ 275 s->load[1] = value & 0xffff; 276 break; 277 case 0x30: /* TAMARCHR */ 278 s->match[0] = value & 0xffff; 279 if (s->config < 4) { 280 s->match[1] = value >> 16; 281 } 282 break; 283 case 0x34: /* TBMATCHR */ 284 s->match[1] = value >> 16; 285 break; 286 case 0x38: /* TAPR */ 287 s->prescale[0] = value; 288 break; 289 case 0x3c: /* TBPR */ 290 s->prescale[1] = value; 291 break; 292 case 0x40: /* TAPMR */ 293 s->match_prescale[0] = value; 294 break; 295 case 0x44: /* TBPMR */ 296 s->match_prescale[0] = value; 297 break; 298 default: 299 qemu_log_mask(LOG_GUEST_ERROR, 300 "GPTM: write at bad offset 0x02%" HWADDR_PRIx "\n", 301 offset); 302 } 303 gptm_update_irq(s); 304 } 305 306 static const MemoryRegionOps gptm_ops = { 307 .read = gptm_read, 308 .write = gptm_write, 309 .endianness = DEVICE_NATIVE_ENDIAN, 310 }; 311 312 static const VMStateDescription vmstate_stellaris_gptm = { 313 .name = "stellaris_gptm", 314 .version_id = 1, 315 .minimum_version_id = 1, 316 .fields = (VMStateField[]) { 317 VMSTATE_UINT32(config, gptm_state), 318 VMSTATE_UINT32_ARRAY(mode, gptm_state, 2), 319 VMSTATE_UINT32(control, gptm_state), 320 VMSTATE_UINT32(state, gptm_state), 321 VMSTATE_UINT32(mask, gptm_state), 322 VMSTATE_UNUSED(8), 323 VMSTATE_UINT32_ARRAY(load, gptm_state, 2), 324 VMSTATE_UINT32_ARRAY(match, gptm_state, 2), 325 VMSTATE_UINT32_ARRAY(prescale, gptm_state, 2), 326 VMSTATE_UINT32_ARRAY(match_prescale, gptm_state, 2), 327 VMSTATE_UINT32(rtc, gptm_state), 328 VMSTATE_INT64_ARRAY(tick, gptm_state, 2), 329 VMSTATE_TIMER_PTR_ARRAY(timer, gptm_state, 2), 330 VMSTATE_END_OF_LIST() 331 } 332 }; 333 334 static void stellaris_gptm_init(Object *obj) 335 { 336 DeviceState *dev = DEVICE(obj); 337 gptm_state *s = STELLARIS_GPTM(obj); 338 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 339 340 sysbus_init_irq(sbd, &s->irq); 341 qdev_init_gpio_out(dev, &s->trigger, 1); 342 343 memory_region_init_io(&s->iomem, obj, &gptm_ops, s, 344 "gptm", 0x1000); 345 sysbus_init_mmio(sbd, &s->iomem); 346 347 s->opaque[0] = s->opaque[1] = s; 348 s->timer[0] = timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque[0]); 349 s->timer[1] = timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque[1]); 350 } 351 352 353 /* System controller. */ 354 355 typedef struct { 356 MemoryRegion iomem; 357 uint32_t pborctl; 358 uint32_t ldopctl; 359 uint32_t int_status; 360 uint32_t int_mask; 361 uint32_t resc; 362 uint32_t rcc; 363 uint32_t rcc2; 364 uint32_t rcgc[3]; 365 uint32_t scgc[3]; 366 uint32_t dcgc[3]; 367 uint32_t clkvclr; 368 uint32_t ldoarst; 369 uint32_t user0; 370 uint32_t user1; 371 qemu_irq irq; 372 stellaris_board_info *board; 373 } ssys_state; 374 375 static void ssys_update(ssys_state *s) 376 { 377 qemu_set_irq(s->irq, (s->int_status & s->int_mask) != 0); 378 } 379 380 static uint32_t pllcfg_sandstorm[16] = { 381 0x31c0, /* 1 Mhz */ 382 0x1ae0, /* 1.8432 Mhz */ 383 0x18c0, /* 2 Mhz */ 384 0xd573, /* 2.4576 Mhz */ 385 0x37a6, /* 3.57954 Mhz */ 386 0x1ae2, /* 3.6864 Mhz */ 387 0x0c40, /* 4 Mhz */ 388 0x98bc, /* 4.906 Mhz */ 389 0x935b, /* 4.9152 Mhz */ 390 0x09c0, /* 5 Mhz */ 391 0x4dee, /* 5.12 Mhz */ 392 0x0c41, /* 6 Mhz */ 393 0x75db, /* 6.144 Mhz */ 394 0x1ae6, /* 7.3728 Mhz */ 395 0x0600, /* 8 Mhz */ 396 0x585b /* 8.192 Mhz */ 397 }; 398 399 static uint32_t pllcfg_fury[16] = { 400 0x3200, /* 1 Mhz */ 401 0x1b20, /* 1.8432 Mhz */ 402 0x1900, /* 2 Mhz */ 403 0xf42b, /* 2.4576 Mhz */ 404 0x37e3, /* 3.57954 Mhz */ 405 0x1b21, /* 3.6864 Mhz */ 406 0x0c80, /* 4 Mhz */ 407 0x98ee, /* 4.906 Mhz */ 408 0xd5b4, /* 4.9152 Mhz */ 409 0x0a00, /* 5 Mhz */ 410 0x4e27, /* 5.12 Mhz */ 411 0x1902, /* 6 Mhz */ 412 0xec1c, /* 6.144 Mhz */ 413 0x1b23, /* 7.3728 Mhz */ 414 0x0640, /* 8 Mhz */ 415 0xb11c /* 8.192 Mhz */ 416 }; 417 418 #define DID0_VER_MASK 0x70000000 419 #define DID0_VER_0 0x00000000 420 #define DID0_VER_1 0x10000000 421 422 #define DID0_CLASS_MASK 0x00FF0000 423 #define DID0_CLASS_SANDSTORM 0x00000000 424 #define DID0_CLASS_FURY 0x00010000 425 426 static int ssys_board_class(const ssys_state *s) 427 { 428 uint32_t did0 = s->board->did0; 429 switch (did0 & DID0_VER_MASK) { 430 case DID0_VER_0: 431 return DID0_CLASS_SANDSTORM; 432 case DID0_VER_1: 433 switch (did0 & DID0_CLASS_MASK) { 434 case DID0_CLASS_SANDSTORM: 435 case DID0_CLASS_FURY: 436 return did0 & DID0_CLASS_MASK; 437 } 438 /* for unknown classes, fall through */ 439 default: 440 /* This can only happen if the hardwired constant did0 value 441 * in this board's stellaris_board_info struct is wrong. 442 */ 443 g_assert_not_reached(); 444 } 445 } 446 447 static uint64_t ssys_read(void *opaque, hwaddr offset, 448 unsigned size) 449 { 450 ssys_state *s = (ssys_state *)opaque; 451 452 switch (offset) { 453 case 0x000: /* DID0 */ 454 return s->board->did0; 455 case 0x004: /* DID1 */ 456 return s->board->did1; 457 case 0x008: /* DC0 */ 458 return s->board->dc0; 459 case 0x010: /* DC1 */ 460 return s->board->dc1; 461 case 0x014: /* DC2 */ 462 return s->board->dc2; 463 case 0x018: /* DC3 */ 464 return s->board->dc3; 465 case 0x01c: /* DC4 */ 466 return s->board->dc4; 467 case 0x030: /* PBORCTL */ 468 return s->pborctl; 469 case 0x034: /* LDOPCTL */ 470 return s->ldopctl; 471 case 0x040: /* SRCR0 */ 472 return 0; 473 case 0x044: /* SRCR1 */ 474 return 0; 475 case 0x048: /* SRCR2 */ 476 return 0; 477 case 0x050: /* RIS */ 478 return s->int_status; 479 case 0x054: /* IMC */ 480 return s->int_mask; 481 case 0x058: /* MISC */ 482 return s->int_status & s->int_mask; 483 case 0x05c: /* RESC */ 484 return s->resc; 485 case 0x060: /* RCC */ 486 return s->rcc; 487 case 0x064: /* PLLCFG */ 488 { 489 int xtal; 490 xtal = (s->rcc >> 6) & 0xf; 491 switch (ssys_board_class(s)) { 492 case DID0_CLASS_FURY: 493 return pllcfg_fury[xtal]; 494 case DID0_CLASS_SANDSTORM: 495 return pllcfg_sandstorm[xtal]; 496 default: 497 g_assert_not_reached(); 498 } 499 } 500 case 0x070: /* RCC2 */ 501 return s->rcc2; 502 case 0x100: /* RCGC0 */ 503 return s->rcgc[0]; 504 case 0x104: /* RCGC1 */ 505 return s->rcgc[1]; 506 case 0x108: /* RCGC2 */ 507 return s->rcgc[2]; 508 case 0x110: /* SCGC0 */ 509 return s->scgc[0]; 510 case 0x114: /* SCGC1 */ 511 return s->scgc[1]; 512 case 0x118: /* SCGC2 */ 513 return s->scgc[2]; 514 case 0x120: /* DCGC0 */ 515 return s->dcgc[0]; 516 case 0x124: /* DCGC1 */ 517 return s->dcgc[1]; 518 case 0x128: /* DCGC2 */ 519 return s->dcgc[2]; 520 case 0x150: /* CLKVCLR */ 521 return s->clkvclr; 522 case 0x160: /* LDOARST */ 523 return s->ldoarst; 524 case 0x1e0: /* USER0 */ 525 return s->user0; 526 case 0x1e4: /* USER1 */ 527 return s->user1; 528 default: 529 qemu_log_mask(LOG_GUEST_ERROR, 530 "SSYS: read at bad offset 0x%x\n", (int)offset); 531 return 0; 532 } 533 } 534 535 static bool ssys_use_rcc2(ssys_state *s) 536 { 537 return (s->rcc2 >> 31) & 0x1; 538 } 539 540 /* 541 * Caculate the sys. clock period in ms. 542 */ 543 static void ssys_calculate_system_clock(ssys_state *s) 544 { 545 if (ssys_use_rcc2(s)) { 546 system_clock_scale = 5 * (((s->rcc2 >> 23) & 0x3f) + 1); 547 } else { 548 system_clock_scale = 5 * (((s->rcc >> 23) & 0xf) + 1); 549 } 550 } 551 552 static void ssys_write(void *opaque, hwaddr offset, 553 uint64_t value, unsigned size) 554 { 555 ssys_state *s = (ssys_state *)opaque; 556 557 switch (offset) { 558 case 0x030: /* PBORCTL */ 559 s->pborctl = value & 0xffff; 560 break; 561 case 0x034: /* LDOPCTL */ 562 s->ldopctl = value & 0x1f; 563 break; 564 case 0x040: /* SRCR0 */ 565 case 0x044: /* SRCR1 */ 566 case 0x048: /* SRCR2 */ 567 qemu_log_mask(LOG_UNIMP, "Peripheral reset not implemented\n"); 568 break; 569 case 0x054: /* IMC */ 570 s->int_mask = value & 0x7f; 571 break; 572 case 0x058: /* MISC */ 573 s->int_status &= ~value; 574 break; 575 case 0x05c: /* RESC */ 576 s->resc = value & 0x3f; 577 break; 578 case 0x060: /* RCC */ 579 if ((s->rcc & (1 << 13)) != 0 && (value & (1 << 13)) == 0) { 580 /* PLL enable. */ 581 s->int_status |= (1 << 6); 582 } 583 s->rcc = value; 584 ssys_calculate_system_clock(s); 585 break; 586 case 0x070: /* RCC2 */ 587 if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) { 588 break; 589 } 590 591 if ((s->rcc2 & (1 << 13)) != 0 && (value & (1 << 13)) == 0) { 592 /* PLL enable. */ 593 s->int_status |= (1 << 6); 594 } 595 s->rcc2 = value; 596 ssys_calculate_system_clock(s); 597 break; 598 case 0x100: /* RCGC0 */ 599 s->rcgc[0] = value; 600 break; 601 case 0x104: /* RCGC1 */ 602 s->rcgc[1] = value; 603 break; 604 case 0x108: /* RCGC2 */ 605 s->rcgc[2] = value; 606 break; 607 case 0x110: /* SCGC0 */ 608 s->scgc[0] = value; 609 break; 610 case 0x114: /* SCGC1 */ 611 s->scgc[1] = value; 612 break; 613 case 0x118: /* SCGC2 */ 614 s->scgc[2] = value; 615 break; 616 case 0x120: /* DCGC0 */ 617 s->dcgc[0] = value; 618 break; 619 case 0x124: /* DCGC1 */ 620 s->dcgc[1] = value; 621 break; 622 case 0x128: /* DCGC2 */ 623 s->dcgc[2] = value; 624 break; 625 case 0x150: /* CLKVCLR */ 626 s->clkvclr = value; 627 break; 628 case 0x160: /* LDOARST */ 629 s->ldoarst = value; 630 break; 631 default: 632 qemu_log_mask(LOG_GUEST_ERROR, 633 "SSYS: write at bad offset 0x%x\n", (int)offset); 634 } 635 ssys_update(s); 636 } 637 638 static const MemoryRegionOps ssys_ops = { 639 .read = ssys_read, 640 .write = ssys_write, 641 .endianness = DEVICE_NATIVE_ENDIAN, 642 }; 643 644 static void ssys_reset(void *opaque) 645 { 646 ssys_state *s = (ssys_state *)opaque; 647 648 s->pborctl = 0x7ffd; 649 s->rcc = 0x078e3ac0; 650 651 if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) { 652 s->rcc2 = 0; 653 } else { 654 s->rcc2 = 0x07802810; 655 } 656 s->rcgc[0] = 1; 657 s->scgc[0] = 1; 658 s->dcgc[0] = 1; 659 ssys_calculate_system_clock(s); 660 } 661 662 static int stellaris_sys_post_load(void *opaque, int version_id) 663 { 664 ssys_state *s = opaque; 665 666 ssys_calculate_system_clock(s); 667 668 return 0; 669 } 670 671 static const VMStateDescription vmstate_stellaris_sys = { 672 .name = "stellaris_sys", 673 .version_id = 2, 674 .minimum_version_id = 1, 675 .post_load = stellaris_sys_post_load, 676 .fields = (VMStateField[]) { 677 VMSTATE_UINT32(pborctl, ssys_state), 678 VMSTATE_UINT32(ldopctl, ssys_state), 679 VMSTATE_UINT32(int_mask, ssys_state), 680 VMSTATE_UINT32(int_status, ssys_state), 681 VMSTATE_UINT32(resc, ssys_state), 682 VMSTATE_UINT32(rcc, ssys_state), 683 VMSTATE_UINT32_V(rcc2, ssys_state, 2), 684 VMSTATE_UINT32_ARRAY(rcgc, ssys_state, 3), 685 VMSTATE_UINT32_ARRAY(scgc, ssys_state, 3), 686 VMSTATE_UINT32_ARRAY(dcgc, ssys_state, 3), 687 VMSTATE_UINT32(clkvclr, ssys_state), 688 VMSTATE_UINT32(ldoarst, ssys_state), 689 VMSTATE_END_OF_LIST() 690 } 691 }; 692 693 static int stellaris_sys_init(uint32_t base, qemu_irq irq, 694 stellaris_board_info * board, 695 uint8_t *macaddr) 696 { 697 ssys_state *s; 698 699 s = g_new0(ssys_state, 1); 700 s->irq = irq; 701 s->board = board; 702 /* Most devices come preprogrammed with a MAC address in the user data. */ 703 s->user0 = macaddr[0] | (macaddr[1] << 8) | (macaddr[2] << 16); 704 s->user1 = macaddr[3] | (macaddr[4] << 8) | (macaddr[5] << 16); 705 706 memory_region_init_io(&s->iomem, NULL, &ssys_ops, s, "ssys", 0x00001000); 707 memory_region_add_subregion(get_system_memory(), base, &s->iomem); 708 ssys_reset(s); 709 vmstate_register(NULL, -1, &vmstate_stellaris_sys, s); 710 return 0; 711 } 712 713 714 /* I2C controller. */ 715 716 #define TYPE_STELLARIS_I2C "stellaris-i2c" 717 #define STELLARIS_I2C(obj) \ 718 OBJECT_CHECK(stellaris_i2c_state, (obj), TYPE_STELLARIS_I2C) 719 720 typedef struct { 721 SysBusDevice parent_obj; 722 723 I2CBus *bus; 724 qemu_irq irq; 725 MemoryRegion iomem; 726 uint32_t msa; 727 uint32_t mcs; 728 uint32_t mdr; 729 uint32_t mtpr; 730 uint32_t mimr; 731 uint32_t mris; 732 uint32_t mcr; 733 } stellaris_i2c_state; 734 735 #define STELLARIS_I2C_MCS_BUSY 0x01 736 #define STELLARIS_I2C_MCS_ERROR 0x02 737 #define STELLARIS_I2C_MCS_ADRACK 0x04 738 #define STELLARIS_I2C_MCS_DATACK 0x08 739 #define STELLARIS_I2C_MCS_ARBLST 0x10 740 #define STELLARIS_I2C_MCS_IDLE 0x20 741 #define STELLARIS_I2C_MCS_BUSBSY 0x40 742 743 static uint64_t stellaris_i2c_read(void *opaque, hwaddr offset, 744 unsigned size) 745 { 746 stellaris_i2c_state *s = (stellaris_i2c_state *)opaque; 747 748 switch (offset) { 749 case 0x00: /* MSA */ 750 return s->msa; 751 case 0x04: /* MCS */ 752 /* We don't emulate timing, so the controller is never busy. */ 753 return s->mcs | STELLARIS_I2C_MCS_IDLE; 754 case 0x08: /* MDR */ 755 return s->mdr; 756 case 0x0c: /* MTPR */ 757 return s->mtpr; 758 case 0x10: /* MIMR */ 759 return s->mimr; 760 case 0x14: /* MRIS */ 761 return s->mris; 762 case 0x18: /* MMIS */ 763 return s->mris & s->mimr; 764 case 0x20: /* MCR */ 765 return s->mcr; 766 default: 767 qemu_log_mask(LOG_GUEST_ERROR, 768 "stellaris_i2c: read at bad offset 0x%x\n", (int)offset); 769 return 0; 770 } 771 } 772 773 static void stellaris_i2c_update(stellaris_i2c_state *s) 774 { 775 int level; 776 777 level = (s->mris & s->mimr) != 0; 778 qemu_set_irq(s->irq, level); 779 } 780 781 static void stellaris_i2c_write(void *opaque, hwaddr offset, 782 uint64_t value, unsigned size) 783 { 784 stellaris_i2c_state *s = (stellaris_i2c_state *)opaque; 785 786 switch (offset) { 787 case 0x00: /* MSA */ 788 s->msa = value & 0xff; 789 break; 790 case 0x04: /* MCS */ 791 if ((s->mcr & 0x10) == 0) { 792 /* Disabled. Do nothing. */ 793 break; 794 } 795 /* Grab the bus if this is starting a transfer. */ 796 if ((value & 2) && (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) { 797 if (i2c_start_transfer(s->bus, s->msa >> 1, s->msa & 1)) { 798 s->mcs |= STELLARIS_I2C_MCS_ARBLST; 799 } else { 800 s->mcs &= ~STELLARIS_I2C_MCS_ARBLST; 801 s->mcs |= STELLARIS_I2C_MCS_BUSBSY; 802 } 803 } 804 /* If we don't have the bus then indicate an error. */ 805 if (!i2c_bus_busy(s->bus) 806 || (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) { 807 s->mcs |= STELLARIS_I2C_MCS_ERROR; 808 break; 809 } 810 s->mcs &= ~STELLARIS_I2C_MCS_ERROR; 811 if (value & 1) { 812 /* Transfer a byte. */ 813 /* TODO: Handle errors. */ 814 if (s->msa & 1) { 815 /* Recv */ 816 s->mdr = i2c_recv(s->bus); 817 } else { 818 /* Send */ 819 i2c_send(s->bus, s->mdr); 820 } 821 /* Raise an interrupt. */ 822 s->mris |= 1; 823 } 824 if (value & 4) { 825 /* Finish transfer. */ 826 i2c_end_transfer(s->bus); 827 s->mcs &= ~STELLARIS_I2C_MCS_BUSBSY; 828 } 829 break; 830 case 0x08: /* MDR */ 831 s->mdr = value & 0xff; 832 break; 833 case 0x0c: /* MTPR */ 834 s->mtpr = value & 0xff; 835 break; 836 case 0x10: /* MIMR */ 837 s->mimr = 1; 838 break; 839 case 0x1c: /* MICR */ 840 s->mris &= ~value; 841 break; 842 case 0x20: /* MCR */ 843 if (value & 1) { 844 qemu_log_mask(LOG_UNIMP, 845 "stellaris_i2c: Loopback not implemented\n"); 846 } 847 if (value & 0x20) { 848 qemu_log_mask(LOG_UNIMP, 849 "stellaris_i2c: Slave mode not implemented\n"); 850 } 851 s->mcr = value & 0x31; 852 break; 853 default: 854 qemu_log_mask(LOG_GUEST_ERROR, 855 "stellaris_i2c: write at bad offset 0x%x\n", (int)offset); 856 } 857 stellaris_i2c_update(s); 858 } 859 860 static void stellaris_i2c_reset(stellaris_i2c_state *s) 861 { 862 if (s->mcs & STELLARIS_I2C_MCS_BUSBSY) 863 i2c_end_transfer(s->bus); 864 865 s->msa = 0; 866 s->mcs = 0; 867 s->mdr = 0; 868 s->mtpr = 1; 869 s->mimr = 0; 870 s->mris = 0; 871 s->mcr = 0; 872 stellaris_i2c_update(s); 873 } 874 875 static const MemoryRegionOps stellaris_i2c_ops = { 876 .read = stellaris_i2c_read, 877 .write = stellaris_i2c_write, 878 .endianness = DEVICE_NATIVE_ENDIAN, 879 }; 880 881 static const VMStateDescription vmstate_stellaris_i2c = { 882 .name = "stellaris_i2c", 883 .version_id = 1, 884 .minimum_version_id = 1, 885 .fields = (VMStateField[]) { 886 VMSTATE_UINT32(msa, stellaris_i2c_state), 887 VMSTATE_UINT32(mcs, stellaris_i2c_state), 888 VMSTATE_UINT32(mdr, stellaris_i2c_state), 889 VMSTATE_UINT32(mtpr, stellaris_i2c_state), 890 VMSTATE_UINT32(mimr, stellaris_i2c_state), 891 VMSTATE_UINT32(mris, stellaris_i2c_state), 892 VMSTATE_UINT32(mcr, stellaris_i2c_state), 893 VMSTATE_END_OF_LIST() 894 } 895 }; 896 897 static void stellaris_i2c_init(Object *obj) 898 { 899 DeviceState *dev = DEVICE(obj); 900 stellaris_i2c_state *s = STELLARIS_I2C(obj); 901 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 902 I2CBus *bus; 903 904 sysbus_init_irq(sbd, &s->irq); 905 bus = i2c_init_bus(dev, "i2c"); 906 s->bus = bus; 907 908 memory_region_init_io(&s->iomem, obj, &stellaris_i2c_ops, s, 909 "i2c", 0x1000); 910 sysbus_init_mmio(sbd, &s->iomem); 911 /* ??? For now we only implement the master interface. */ 912 stellaris_i2c_reset(s); 913 } 914 915 /* Analogue to Digital Converter. This is only partially implemented, 916 enough for applications that use a combined ADC and timer tick. */ 917 918 #define STELLARIS_ADC_EM_CONTROLLER 0 919 #define STELLARIS_ADC_EM_COMP 1 920 #define STELLARIS_ADC_EM_EXTERNAL 4 921 #define STELLARIS_ADC_EM_TIMER 5 922 #define STELLARIS_ADC_EM_PWM0 6 923 #define STELLARIS_ADC_EM_PWM1 7 924 #define STELLARIS_ADC_EM_PWM2 8 925 926 #define STELLARIS_ADC_FIFO_EMPTY 0x0100 927 #define STELLARIS_ADC_FIFO_FULL 0x1000 928 929 #define TYPE_STELLARIS_ADC "stellaris-adc" 930 #define STELLARIS_ADC(obj) \ 931 OBJECT_CHECK(stellaris_adc_state, (obj), TYPE_STELLARIS_ADC) 932 933 typedef struct StellarisADCState { 934 SysBusDevice parent_obj; 935 936 MemoryRegion iomem; 937 uint32_t actss; 938 uint32_t ris; 939 uint32_t im; 940 uint32_t emux; 941 uint32_t ostat; 942 uint32_t ustat; 943 uint32_t sspri; 944 uint32_t sac; 945 struct { 946 uint32_t state; 947 uint32_t data[16]; 948 } fifo[4]; 949 uint32_t ssmux[4]; 950 uint32_t ssctl[4]; 951 uint32_t noise; 952 qemu_irq irq[4]; 953 } stellaris_adc_state; 954 955 static uint32_t stellaris_adc_fifo_read(stellaris_adc_state *s, int n) 956 { 957 int tail; 958 959 tail = s->fifo[n].state & 0xf; 960 if (s->fifo[n].state & STELLARIS_ADC_FIFO_EMPTY) { 961 s->ustat |= 1 << n; 962 } else { 963 s->fifo[n].state = (s->fifo[n].state & ~0xf) | ((tail + 1) & 0xf); 964 s->fifo[n].state &= ~STELLARIS_ADC_FIFO_FULL; 965 if (tail + 1 == ((s->fifo[n].state >> 4) & 0xf)) 966 s->fifo[n].state |= STELLARIS_ADC_FIFO_EMPTY; 967 } 968 return s->fifo[n].data[tail]; 969 } 970 971 static void stellaris_adc_fifo_write(stellaris_adc_state *s, int n, 972 uint32_t value) 973 { 974 int head; 975 976 /* TODO: Real hardware has limited size FIFOs. We have a full 16 entry 977 FIFO fir each sequencer. */ 978 head = (s->fifo[n].state >> 4) & 0xf; 979 if (s->fifo[n].state & STELLARIS_ADC_FIFO_FULL) { 980 s->ostat |= 1 << n; 981 return; 982 } 983 s->fifo[n].data[head] = value; 984 head = (head + 1) & 0xf; 985 s->fifo[n].state &= ~STELLARIS_ADC_FIFO_EMPTY; 986 s->fifo[n].state = (s->fifo[n].state & ~0xf0) | (head << 4); 987 if ((s->fifo[n].state & 0xf) == head) 988 s->fifo[n].state |= STELLARIS_ADC_FIFO_FULL; 989 } 990 991 static void stellaris_adc_update(stellaris_adc_state *s) 992 { 993 int level; 994 int n; 995 996 for (n = 0; n < 4; n++) { 997 level = (s->ris & s->im & (1 << n)) != 0; 998 qemu_set_irq(s->irq[n], level); 999 } 1000 } 1001 1002 static void stellaris_adc_trigger(void *opaque, int irq, int level) 1003 { 1004 stellaris_adc_state *s = (stellaris_adc_state *)opaque; 1005 int n; 1006 1007 for (n = 0; n < 4; n++) { 1008 if ((s->actss & (1 << n)) == 0) { 1009 continue; 1010 } 1011 1012 if (((s->emux >> (n * 4)) & 0xff) != 5) { 1013 continue; 1014 } 1015 1016 /* Some applications use the ADC as a random number source, so introduce 1017 some variation into the signal. */ 1018 s->noise = s->noise * 314159 + 1; 1019 /* ??? actual inputs not implemented. Return an arbitrary value. */ 1020 stellaris_adc_fifo_write(s, n, 0x200 + ((s->noise >> 16) & 7)); 1021 s->ris |= (1 << n); 1022 stellaris_adc_update(s); 1023 } 1024 } 1025 1026 static void stellaris_adc_reset(stellaris_adc_state *s) 1027 { 1028 int n; 1029 1030 for (n = 0; n < 4; n++) { 1031 s->ssmux[n] = 0; 1032 s->ssctl[n] = 0; 1033 s->fifo[n].state = STELLARIS_ADC_FIFO_EMPTY; 1034 } 1035 } 1036 1037 static uint64_t stellaris_adc_read(void *opaque, hwaddr offset, 1038 unsigned size) 1039 { 1040 stellaris_adc_state *s = (stellaris_adc_state *)opaque; 1041 1042 /* TODO: Implement this. */ 1043 if (offset >= 0x40 && offset < 0xc0) { 1044 int n; 1045 n = (offset - 0x40) >> 5; 1046 switch (offset & 0x1f) { 1047 case 0x00: /* SSMUX */ 1048 return s->ssmux[n]; 1049 case 0x04: /* SSCTL */ 1050 return s->ssctl[n]; 1051 case 0x08: /* SSFIFO */ 1052 return stellaris_adc_fifo_read(s, n); 1053 case 0x0c: /* SSFSTAT */ 1054 return s->fifo[n].state; 1055 default: 1056 break; 1057 } 1058 } 1059 switch (offset) { 1060 case 0x00: /* ACTSS */ 1061 return s->actss; 1062 case 0x04: /* RIS */ 1063 return s->ris; 1064 case 0x08: /* IM */ 1065 return s->im; 1066 case 0x0c: /* ISC */ 1067 return s->ris & s->im; 1068 case 0x10: /* OSTAT */ 1069 return s->ostat; 1070 case 0x14: /* EMUX */ 1071 return s->emux; 1072 case 0x18: /* USTAT */ 1073 return s->ustat; 1074 case 0x20: /* SSPRI */ 1075 return s->sspri; 1076 case 0x30: /* SAC */ 1077 return s->sac; 1078 default: 1079 qemu_log_mask(LOG_GUEST_ERROR, 1080 "stellaris_adc: read at bad offset 0x%x\n", (int)offset); 1081 return 0; 1082 } 1083 } 1084 1085 static void stellaris_adc_write(void *opaque, hwaddr offset, 1086 uint64_t value, unsigned size) 1087 { 1088 stellaris_adc_state *s = (stellaris_adc_state *)opaque; 1089 1090 /* TODO: Implement this. */ 1091 if (offset >= 0x40 && offset < 0xc0) { 1092 int n; 1093 n = (offset - 0x40) >> 5; 1094 switch (offset & 0x1f) { 1095 case 0x00: /* SSMUX */ 1096 s->ssmux[n] = value & 0x33333333; 1097 return; 1098 case 0x04: /* SSCTL */ 1099 if (value != 6) { 1100 qemu_log_mask(LOG_UNIMP, 1101 "ADC: Unimplemented sequence %" PRIx64 "\n", 1102 value); 1103 } 1104 s->ssctl[n] = value; 1105 return; 1106 default: 1107 break; 1108 } 1109 } 1110 switch (offset) { 1111 case 0x00: /* ACTSS */ 1112 s->actss = value & 0xf; 1113 break; 1114 case 0x08: /* IM */ 1115 s->im = value; 1116 break; 1117 case 0x0c: /* ISC */ 1118 s->ris &= ~value; 1119 break; 1120 case 0x10: /* OSTAT */ 1121 s->ostat &= ~value; 1122 break; 1123 case 0x14: /* EMUX */ 1124 s->emux = value; 1125 break; 1126 case 0x18: /* USTAT */ 1127 s->ustat &= ~value; 1128 break; 1129 case 0x20: /* SSPRI */ 1130 s->sspri = value; 1131 break; 1132 case 0x28: /* PSSI */ 1133 qemu_log_mask(LOG_UNIMP, "ADC: sample initiate unimplemented\n"); 1134 break; 1135 case 0x30: /* SAC */ 1136 s->sac = value; 1137 break; 1138 default: 1139 qemu_log_mask(LOG_GUEST_ERROR, 1140 "stellaris_adc: write at bad offset 0x%x\n", (int)offset); 1141 } 1142 stellaris_adc_update(s); 1143 } 1144 1145 static const MemoryRegionOps stellaris_adc_ops = { 1146 .read = stellaris_adc_read, 1147 .write = stellaris_adc_write, 1148 .endianness = DEVICE_NATIVE_ENDIAN, 1149 }; 1150 1151 static const VMStateDescription vmstate_stellaris_adc = { 1152 .name = "stellaris_adc", 1153 .version_id = 1, 1154 .minimum_version_id = 1, 1155 .fields = (VMStateField[]) { 1156 VMSTATE_UINT32(actss, stellaris_adc_state), 1157 VMSTATE_UINT32(ris, stellaris_adc_state), 1158 VMSTATE_UINT32(im, stellaris_adc_state), 1159 VMSTATE_UINT32(emux, stellaris_adc_state), 1160 VMSTATE_UINT32(ostat, stellaris_adc_state), 1161 VMSTATE_UINT32(ustat, stellaris_adc_state), 1162 VMSTATE_UINT32(sspri, stellaris_adc_state), 1163 VMSTATE_UINT32(sac, stellaris_adc_state), 1164 VMSTATE_UINT32(fifo[0].state, stellaris_adc_state), 1165 VMSTATE_UINT32_ARRAY(fifo[0].data, stellaris_adc_state, 16), 1166 VMSTATE_UINT32(ssmux[0], stellaris_adc_state), 1167 VMSTATE_UINT32(ssctl[0], stellaris_adc_state), 1168 VMSTATE_UINT32(fifo[1].state, stellaris_adc_state), 1169 VMSTATE_UINT32_ARRAY(fifo[1].data, stellaris_adc_state, 16), 1170 VMSTATE_UINT32(ssmux[1], stellaris_adc_state), 1171 VMSTATE_UINT32(ssctl[1], stellaris_adc_state), 1172 VMSTATE_UINT32(fifo[2].state, stellaris_adc_state), 1173 VMSTATE_UINT32_ARRAY(fifo[2].data, stellaris_adc_state, 16), 1174 VMSTATE_UINT32(ssmux[2], stellaris_adc_state), 1175 VMSTATE_UINT32(ssctl[2], stellaris_adc_state), 1176 VMSTATE_UINT32(fifo[3].state, stellaris_adc_state), 1177 VMSTATE_UINT32_ARRAY(fifo[3].data, stellaris_adc_state, 16), 1178 VMSTATE_UINT32(ssmux[3], stellaris_adc_state), 1179 VMSTATE_UINT32(ssctl[3], stellaris_adc_state), 1180 VMSTATE_UINT32(noise, stellaris_adc_state), 1181 VMSTATE_END_OF_LIST() 1182 } 1183 }; 1184 1185 static void stellaris_adc_init(Object *obj) 1186 { 1187 DeviceState *dev = DEVICE(obj); 1188 stellaris_adc_state *s = STELLARIS_ADC(obj); 1189 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 1190 int n; 1191 1192 for (n = 0; n < 4; n++) { 1193 sysbus_init_irq(sbd, &s->irq[n]); 1194 } 1195 1196 memory_region_init_io(&s->iomem, obj, &stellaris_adc_ops, s, 1197 "adc", 0x1000); 1198 sysbus_init_mmio(sbd, &s->iomem); 1199 stellaris_adc_reset(s); 1200 qdev_init_gpio_in(dev, stellaris_adc_trigger, 1); 1201 } 1202 1203 static 1204 void do_sys_reset(void *opaque, int n, int level) 1205 { 1206 if (level) { 1207 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 1208 } 1209 } 1210 1211 /* Board init. */ 1212 static stellaris_board_info stellaris_boards[] = { 1213 { "LM3S811EVB", 1214 0, 1215 0x0032000e, 1216 0x001f001f, /* dc0 */ 1217 0x001132bf, 1218 0x01071013, 1219 0x3f0f01ff, 1220 0x0000001f, 1221 BP_OLED_I2C 1222 }, 1223 { "LM3S6965EVB", 1224 0x10010002, 1225 0x1073402e, 1226 0x00ff007f, /* dc0 */ 1227 0x001133ff, 1228 0x030f5317, 1229 0x0f0f87ff, 1230 0x5000007f, 1231 BP_OLED_SSI | BP_GAMEPAD 1232 } 1233 }; 1234 1235 static void stellaris_init(MachineState *ms, stellaris_board_info *board) 1236 { 1237 static const int uart_irq[] = {5, 6, 33, 34}; 1238 static const int timer_irq[] = {19, 21, 23, 35}; 1239 static const uint32_t gpio_addr[7] = 1240 { 0x40004000, 0x40005000, 0x40006000, 0x40007000, 1241 0x40024000, 0x40025000, 0x40026000}; 1242 static const int gpio_irq[7] = {0, 1, 2, 3, 4, 30, 31}; 1243 1244 /* Memory map of SoC devices, from 1245 * Stellaris LM3S6965 Microcontroller Data Sheet (rev I) 1246 * http://www.ti.com/lit/ds/symlink/lm3s6965.pdf 1247 * 1248 * 40000000 wdtimer 1249 * 40002000 i2c (unimplemented) 1250 * 40004000 GPIO 1251 * 40005000 GPIO 1252 * 40006000 GPIO 1253 * 40007000 GPIO 1254 * 40008000 SSI 1255 * 4000c000 UART 1256 * 4000d000 UART 1257 * 4000e000 UART 1258 * 40020000 i2c 1259 * 40021000 i2c (unimplemented) 1260 * 40024000 GPIO 1261 * 40025000 GPIO 1262 * 40026000 GPIO 1263 * 40028000 PWM (unimplemented) 1264 * 4002c000 QEI (unimplemented) 1265 * 4002d000 QEI (unimplemented) 1266 * 40030000 gptimer 1267 * 40031000 gptimer 1268 * 40032000 gptimer 1269 * 40033000 gptimer 1270 * 40038000 ADC 1271 * 4003c000 analogue comparator (unimplemented) 1272 * 40048000 ethernet 1273 * 400fc000 hibernation module (unimplemented) 1274 * 400fd000 flash memory control (unimplemented) 1275 * 400fe000 system control 1276 */ 1277 1278 DeviceState *gpio_dev[7], *nvic; 1279 qemu_irq gpio_in[7][8]; 1280 qemu_irq gpio_out[7][8]; 1281 qemu_irq adc; 1282 int sram_size; 1283 int flash_size; 1284 I2CBus *i2c; 1285 DeviceState *dev; 1286 int i; 1287 int j; 1288 1289 MemoryRegion *sram = g_new(MemoryRegion, 1); 1290 MemoryRegion *flash = g_new(MemoryRegion, 1); 1291 MemoryRegion *system_memory = get_system_memory(); 1292 1293 flash_size = (((board->dc0 & 0xffff) + 1) << 1) * 1024; 1294 sram_size = ((board->dc0 >> 18) + 1) * 1024; 1295 1296 /* Flash programming is done via the SCU, so pretend it is ROM. */ 1297 memory_region_init_ram(flash, NULL, "stellaris.flash", flash_size, 1298 &error_fatal); 1299 memory_region_set_readonly(flash, true); 1300 memory_region_add_subregion(system_memory, 0, flash); 1301 1302 memory_region_init_ram(sram, NULL, "stellaris.sram", sram_size, 1303 &error_fatal); 1304 memory_region_add_subregion(system_memory, 0x20000000, sram); 1305 1306 nvic = qdev_create(NULL, TYPE_ARMV7M); 1307 qdev_prop_set_uint32(nvic, "num-irq", NUM_IRQ_LINES); 1308 qdev_prop_set_string(nvic, "cpu-type", ms->cpu_type); 1309 qdev_prop_set_bit(nvic, "enable-bitband", true); 1310 object_property_set_link(OBJECT(nvic), OBJECT(get_system_memory()), 1311 "memory", &error_abort); 1312 /* This will exit with an error if the user passed us a bad cpu_type */ 1313 qdev_init_nofail(nvic); 1314 1315 qdev_connect_gpio_out_named(nvic, "SYSRESETREQ", 0, 1316 qemu_allocate_irq(&do_sys_reset, NULL, 0)); 1317 1318 if (board->dc1 & (1 << 16)) { 1319 dev = sysbus_create_varargs(TYPE_STELLARIS_ADC, 0x40038000, 1320 qdev_get_gpio_in(nvic, 14), 1321 qdev_get_gpio_in(nvic, 15), 1322 qdev_get_gpio_in(nvic, 16), 1323 qdev_get_gpio_in(nvic, 17), 1324 NULL); 1325 adc = qdev_get_gpio_in(dev, 0); 1326 } else { 1327 adc = NULL; 1328 } 1329 for (i = 0; i < 4; i++) { 1330 if (board->dc2 & (0x10000 << i)) { 1331 dev = sysbus_create_simple(TYPE_STELLARIS_GPTM, 1332 0x40030000 + i * 0x1000, 1333 qdev_get_gpio_in(nvic, timer_irq[i])); 1334 /* TODO: This is incorrect, but we get away with it because 1335 the ADC output is only ever pulsed. */ 1336 qdev_connect_gpio_out(dev, 0, adc); 1337 } 1338 } 1339 1340 stellaris_sys_init(0x400fe000, qdev_get_gpio_in(nvic, 28), 1341 board, nd_table[0].macaddr.a); 1342 1343 1344 if (board->dc1 & (1 << 3)) { /* watchdog present */ 1345 dev = qdev_create(NULL, TYPE_LUMINARY_WATCHDOG); 1346 1347 /* system_clock_scale is valid now */ 1348 uint32_t mainclk = NANOSECONDS_PER_SECOND / system_clock_scale; 1349 qdev_prop_set_uint32(dev, "wdogclk-frq", mainclk); 1350 1351 qdev_init_nofail(dev); 1352 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1353 0, 1354 0x40000000u); 1355 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1356 0, 1357 qdev_get_gpio_in(nvic, 18)); 1358 } 1359 1360 1361 for (i = 0; i < 7; i++) { 1362 if (board->dc4 & (1 << i)) { 1363 gpio_dev[i] = sysbus_create_simple("pl061_luminary", gpio_addr[i], 1364 qdev_get_gpio_in(nvic, 1365 gpio_irq[i])); 1366 for (j = 0; j < 8; j++) { 1367 gpio_in[i][j] = qdev_get_gpio_in(gpio_dev[i], j); 1368 gpio_out[i][j] = NULL; 1369 } 1370 } 1371 } 1372 1373 if (board->dc2 & (1 << 12)) { 1374 dev = sysbus_create_simple(TYPE_STELLARIS_I2C, 0x40020000, 1375 qdev_get_gpio_in(nvic, 8)); 1376 i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c"); 1377 if (board->peripherals & BP_OLED_I2C) { 1378 i2c_create_slave(i2c, "ssd0303", 0x3d); 1379 } 1380 } 1381 1382 for (i = 0; i < 4; i++) { 1383 if (board->dc2 & (1 << i)) { 1384 pl011_luminary_create(0x4000c000 + i * 0x1000, 1385 qdev_get_gpio_in(nvic, uart_irq[i]), 1386 serial_hd(i)); 1387 } 1388 } 1389 if (board->dc2 & (1 << 4)) { 1390 dev = sysbus_create_simple("pl022", 0x40008000, 1391 qdev_get_gpio_in(nvic, 7)); 1392 if (board->peripherals & BP_OLED_SSI) { 1393 void *bus; 1394 DeviceState *sddev; 1395 DeviceState *ssddev; 1396 1397 /* Some boards have both an OLED controller and SD card connected to 1398 * the same SSI port, with the SD card chip select connected to a 1399 * GPIO pin. Technically the OLED chip select is connected to the 1400 * SSI Fss pin. We do not bother emulating that as both devices 1401 * should never be selected simultaneously, and our OLED controller 1402 * ignores stray 0xff commands that occur when deselecting the SD 1403 * card. 1404 */ 1405 bus = qdev_get_child_bus(dev, "ssi"); 1406 1407 sddev = ssi_create_slave(bus, "ssi-sd"); 1408 ssddev = ssi_create_slave(bus, "ssd0323"); 1409 gpio_out[GPIO_D][0] = qemu_irq_split( 1410 qdev_get_gpio_in_named(sddev, SSI_GPIO_CS, 0), 1411 qdev_get_gpio_in_named(ssddev, SSI_GPIO_CS, 0)); 1412 gpio_out[GPIO_C][7] = qdev_get_gpio_in(ssddev, 0); 1413 1414 /* Make sure the select pin is high. */ 1415 qemu_irq_raise(gpio_out[GPIO_D][0]); 1416 } 1417 } 1418 if (board->dc4 & (1 << 28)) { 1419 DeviceState *enet; 1420 1421 qemu_check_nic_model(&nd_table[0], "stellaris"); 1422 1423 enet = qdev_create(NULL, "stellaris_enet"); 1424 qdev_set_nic_properties(enet, &nd_table[0]); 1425 qdev_init_nofail(enet); 1426 sysbus_mmio_map(SYS_BUS_DEVICE(enet), 0, 0x40048000); 1427 sysbus_connect_irq(SYS_BUS_DEVICE(enet), 0, qdev_get_gpio_in(nvic, 42)); 1428 } 1429 if (board->peripherals & BP_GAMEPAD) { 1430 qemu_irq gpad_irq[5]; 1431 static const int gpad_keycode[5] = { 0xc8, 0xd0, 0xcb, 0xcd, 0x1d }; 1432 1433 gpad_irq[0] = qemu_irq_invert(gpio_in[GPIO_E][0]); /* up */ 1434 gpad_irq[1] = qemu_irq_invert(gpio_in[GPIO_E][1]); /* down */ 1435 gpad_irq[2] = qemu_irq_invert(gpio_in[GPIO_E][2]); /* left */ 1436 gpad_irq[3] = qemu_irq_invert(gpio_in[GPIO_E][3]); /* right */ 1437 gpad_irq[4] = qemu_irq_invert(gpio_in[GPIO_F][1]); /* select */ 1438 1439 stellaris_gamepad_init(5, gpad_irq, gpad_keycode); 1440 } 1441 for (i = 0; i < 7; i++) { 1442 if (board->dc4 & (1 << i)) { 1443 for (j = 0; j < 8; j++) { 1444 if (gpio_out[i][j]) { 1445 qdev_connect_gpio_out(gpio_dev[i], j, gpio_out[i][j]); 1446 } 1447 } 1448 } 1449 } 1450 1451 /* Add dummy regions for the devices we don't implement yet, 1452 * so guest accesses don't cause unlogged crashes. 1453 */ 1454 create_unimplemented_device("i2c-0", 0x40002000, 0x1000); 1455 create_unimplemented_device("i2c-2", 0x40021000, 0x1000); 1456 create_unimplemented_device("PWM", 0x40028000, 0x1000); 1457 create_unimplemented_device("QEI-0", 0x4002c000, 0x1000); 1458 create_unimplemented_device("QEI-1", 0x4002d000, 0x1000); 1459 create_unimplemented_device("analogue-comparator", 0x4003c000, 0x1000); 1460 create_unimplemented_device("hibernation", 0x400fc000, 0x1000); 1461 create_unimplemented_device("flash-control", 0x400fd000, 0x1000); 1462 1463 armv7m_load_kernel(ARM_CPU(first_cpu), ms->kernel_filename, flash_size); 1464 } 1465 1466 /* FIXME: Figure out how to generate these from stellaris_boards. */ 1467 static void lm3s811evb_init(MachineState *machine) 1468 { 1469 stellaris_init(machine, &stellaris_boards[0]); 1470 } 1471 1472 static void lm3s6965evb_init(MachineState *machine) 1473 { 1474 stellaris_init(machine, &stellaris_boards[1]); 1475 } 1476 1477 static void lm3s811evb_class_init(ObjectClass *oc, void *data) 1478 { 1479 MachineClass *mc = MACHINE_CLASS(oc); 1480 1481 mc->desc = "Stellaris LM3S811EVB"; 1482 mc->init = lm3s811evb_init; 1483 mc->ignore_memory_transaction_failures = true; 1484 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3"); 1485 } 1486 1487 static const TypeInfo lm3s811evb_type = { 1488 .name = MACHINE_TYPE_NAME("lm3s811evb"), 1489 .parent = TYPE_MACHINE, 1490 .class_init = lm3s811evb_class_init, 1491 }; 1492 1493 static void lm3s6965evb_class_init(ObjectClass *oc, void *data) 1494 { 1495 MachineClass *mc = MACHINE_CLASS(oc); 1496 1497 mc->desc = "Stellaris LM3S6965EVB"; 1498 mc->init = lm3s6965evb_init; 1499 mc->ignore_memory_transaction_failures = true; 1500 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3"); 1501 } 1502 1503 static const TypeInfo lm3s6965evb_type = { 1504 .name = MACHINE_TYPE_NAME("lm3s6965evb"), 1505 .parent = TYPE_MACHINE, 1506 .class_init = lm3s6965evb_class_init, 1507 }; 1508 1509 static void stellaris_machine_init(void) 1510 { 1511 type_register_static(&lm3s811evb_type); 1512 type_register_static(&lm3s6965evb_type); 1513 } 1514 1515 type_init(stellaris_machine_init) 1516 1517 static void stellaris_i2c_class_init(ObjectClass *klass, void *data) 1518 { 1519 DeviceClass *dc = DEVICE_CLASS(klass); 1520 1521 dc->vmsd = &vmstate_stellaris_i2c; 1522 } 1523 1524 static const TypeInfo stellaris_i2c_info = { 1525 .name = TYPE_STELLARIS_I2C, 1526 .parent = TYPE_SYS_BUS_DEVICE, 1527 .instance_size = sizeof(stellaris_i2c_state), 1528 .instance_init = stellaris_i2c_init, 1529 .class_init = stellaris_i2c_class_init, 1530 }; 1531 1532 static void stellaris_gptm_class_init(ObjectClass *klass, void *data) 1533 { 1534 DeviceClass *dc = DEVICE_CLASS(klass); 1535 1536 dc->vmsd = &vmstate_stellaris_gptm; 1537 } 1538 1539 static const TypeInfo stellaris_gptm_info = { 1540 .name = TYPE_STELLARIS_GPTM, 1541 .parent = TYPE_SYS_BUS_DEVICE, 1542 .instance_size = sizeof(gptm_state), 1543 .instance_init = stellaris_gptm_init, 1544 .class_init = stellaris_gptm_class_init, 1545 }; 1546 1547 static void stellaris_adc_class_init(ObjectClass *klass, void *data) 1548 { 1549 DeviceClass *dc = DEVICE_CLASS(klass); 1550 1551 dc->vmsd = &vmstate_stellaris_adc; 1552 } 1553 1554 static const TypeInfo stellaris_adc_info = { 1555 .name = TYPE_STELLARIS_ADC, 1556 .parent = TYPE_SYS_BUS_DEVICE, 1557 .instance_size = sizeof(stellaris_adc_state), 1558 .instance_init = stellaris_adc_init, 1559 .class_init = stellaris_adc_class_init, 1560 }; 1561 1562 static void stellaris_register_types(void) 1563 { 1564 type_register_static(&stellaris_i2c_info); 1565 type_register_static(&stellaris_gptm_info); 1566 type_register_static(&stellaris_adc_info); 1567 } 1568 1569 type_init(stellaris_register_types) 1570