1 /* 2 * Luminary Micro Stellaris peripherals 3 * 4 * Copyright (c) 2006 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qapi/error.h" 12 #include "hw/core/split-irq.h" 13 #include "hw/sysbus.h" 14 #include "hw/sd/sd.h" 15 #include "hw/ssi/ssi.h" 16 #include "hw/arm/boot.h" 17 #include "qemu/timer.h" 18 #include "hw/i2c/i2c.h" 19 #include "net/net.h" 20 #include "hw/boards.h" 21 #include "qemu/log.h" 22 #include "exec/address-spaces.h" 23 #include "sysemu/sysemu.h" 24 #include "hw/arm/armv7m.h" 25 #include "hw/char/pl011.h" 26 #include "hw/input/stellaris_gamepad.h" 27 #include "hw/irq.h" 28 #include "hw/watchdog/cmsdk-apb-watchdog.h" 29 #include "migration/vmstate.h" 30 #include "hw/misc/unimp.h" 31 #include "hw/timer/stellaris-gptm.h" 32 #include "hw/qdev-clock.h" 33 #include "qom/object.h" 34 #include "qapi/qmp/qlist.h" 35 #include "ui/input.h" 36 37 #define GPIO_A 0 38 #define GPIO_B 1 39 #define GPIO_C 2 40 #define GPIO_D 3 41 #define GPIO_E 4 42 #define GPIO_F 5 43 #define GPIO_G 6 44 45 #define BP_OLED_I2C 0x01 46 #define BP_OLED_SSI 0x02 47 #define BP_GAMEPAD 0x04 48 49 #define NUM_IRQ_LINES 64 50 51 typedef const struct { 52 const char *name; 53 uint32_t did0; 54 uint32_t did1; 55 uint32_t dc0; 56 uint32_t dc1; 57 uint32_t dc2; 58 uint32_t dc3; 59 uint32_t dc4; 60 uint32_t peripherals; 61 } stellaris_board_info; 62 63 /* System controller. */ 64 65 #define TYPE_STELLARIS_SYS "stellaris-sys" 66 OBJECT_DECLARE_SIMPLE_TYPE(ssys_state, STELLARIS_SYS) 67 68 struct ssys_state { 69 SysBusDevice parent_obj; 70 71 MemoryRegion iomem; 72 uint32_t pborctl; 73 uint32_t ldopctl; 74 uint32_t int_status; 75 uint32_t int_mask; 76 uint32_t resc; 77 uint32_t rcc; 78 uint32_t rcc2; 79 uint32_t rcgc[3]; 80 uint32_t scgc[3]; 81 uint32_t dcgc[3]; 82 uint32_t clkvclr; 83 uint32_t ldoarst; 84 qemu_irq irq; 85 Clock *sysclk; 86 /* Properties (all read-only registers) */ 87 uint32_t user0; 88 uint32_t user1; 89 uint32_t did0; 90 uint32_t did1; 91 uint32_t dc0; 92 uint32_t dc1; 93 uint32_t dc2; 94 uint32_t dc3; 95 uint32_t dc4; 96 }; 97 98 static void ssys_update(ssys_state *s) 99 { 100 qemu_set_irq(s->irq, (s->int_status & s->int_mask) != 0); 101 } 102 103 static uint32_t pllcfg_sandstorm[16] = { 104 0x31c0, /* 1 Mhz */ 105 0x1ae0, /* 1.8432 Mhz */ 106 0x18c0, /* 2 Mhz */ 107 0xd573, /* 2.4576 Mhz */ 108 0x37a6, /* 3.57954 Mhz */ 109 0x1ae2, /* 3.6864 Mhz */ 110 0x0c40, /* 4 Mhz */ 111 0x98bc, /* 4.906 Mhz */ 112 0x935b, /* 4.9152 Mhz */ 113 0x09c0, /* 5 Mhz */ 114 0x4dee, /* 5.12 Mhz */ 115 0x0c41, /* 6 Mhz */ 116 0x75db, /* 6.144 Mhz */ 117 0x1ae6, /* 7.3728 Mhz */ 118 0x0600, /* 8 Mhz */ 119 0x585b /* 8.192 Mhz */ 120 }; 121 122 static uint32_t pllcfg_fury[16] = { 123 0x3200, /* 1 Mhz */ 124 0x1b20, /* 1.8432 Mhz */ 125 0x1900, /* 2 Mhz */ 126 0xf42b, /* 2.4576 Mhz */ 127 0x37e3, /* 3.57954 Mhz */ 128 0x1b21, /* 3.6864 Mhz */ 129 0x0c80, /* 4 Mhz */ 130 0x98ee, /* 4.906 Mhz */ 131 0xd5b4, /* 4.9152 Mhz */ 132 0x0a00, /* 5 Mhz */ 133 0x4e27, /* 5.12 Mhz */ 134 0x1902, /* 6 Mhz */ 135 0xec1c, /* 6.144 Mhz */ 136 0x1b23, /* 7.3728 Mhz */ 137 0x0640, /* 8 Mhz */ 138 0xb11c /* 8.192 Mhz */ 139 }; 140 141 #define DID0_VER_MASK 0x70000000 142 #define DID0_VER_0 0x00000000 143 #define DID0_VER_1 0x10000000 144 145 #define DID0_CLASS_MASK 0x00FF0000 146 #define DID0_CLASS_SANDSTORM 0x00000000 147 #define DID0_CLASS_FURY 0x00010000 148 149 static int ssys_board_class(const ssys_state *s) 150 { 151 uint32_t did0 = s->did0; 152 switch (did0 & DID0_VER_MASK) { 153 case DID0_VER_0: 154 return DID0_CLASS_SANDSTORM; 155 case DID0_VER_1: 156 switch (did0 & DID0_CLASS_MASK) { 157 case DID0_CLASS_SANDSTORM: 158 case DID0_CLASS_FURY: 159 return did0 & DID0_CLASS_MASK; 160 } 161 /* for unknown classes, fall through */ 162 default: 163 /* This can only happen if the hardwired constant did0 value 164 * in this board's stellaris_board_info struct is wrong. 165 */ 166 g_assert_not_reached(); 167 } 168 } 169 170 static uint64_t ssys_read(void *opaque, hwaddr offset, 171 unsigned size) 172 { 173 ssys_state *s = (ssys_state *)opaque; 174 175 switch (offset) { 176 case 0x000: /* DID0 */ 177 return s->did0; 178 case 0x004: /* DID1 */ 179 return s->did1; 180 case 0x008: /* DC0 */ 181 return s->dc0; 182 case 0x010: /* DC1 */ 183 return s->dc1; 184 case 0x014: /* DC2 */ 185 return s->dc2; 186 case 0x018: /* DC3 */ 187 return s->dc3; 188 case 0x01c: /* DC4 */ 189 return s->dc4; 190 case 0x030: /* PBORCTL */ 191 return s->pborctl; 192 case 0x034: /* LDOPCTL */ 193 return s->ldopctl; 194 case 0x040: /* SRCR0 */ 195 return 0; 196 case 0x044: /* SRCR1 */ 197 return 0; 198 case 0x048: /* SRCR2 */ 199 return 0; 200 case 0x050: /* RIS */ 201 return s->int_status; 202 case 0x054: /* IMC */ 203 return s->int_mask; 204 case 0x058: /* MISC */ 205 return s->int_status & s->int_mask; 206 case 0x05c: /* RESC */ 207 return s->resc; 208 case 0x060: /* RCC */ 209 return s->rcc; 210 case 0x064: /* PLLCFG */ 211 { 212 int xtal; 213 xtal = (s->rcc >> 6) & 0xf; 214 switch (ssys_board_class(s)) { 215 case DID0_CLASS_FURY: 216 return pllcfg_fury[xtal]; 217 case DID0_CLASS_SANDSTORM: 218 return pllcfg_sandstorm[xtal]; 219 default: 220 g_assert_not_reached(); 221 } 222 } 223 case 0x070: /* RCC2 */ 224 return s->rcc2; 225 case 0x100: /* RCGC0 */ 226 return s->rcgc[0]; 227 case 0x104: /* RCGC1 */ 228 return s->rcgc[1]; 229 case 0x108: /* RCGC2 */ 230 return s->rcgc[2]; 231 case 0x110: /* SCGC0 */ 232 return s->scgc[0]; 233 case 0x114: /* SCGC1 */ 234 return s->scgc[1]; 235 case 0x118: /* SCGC2 */ 236 return s->scgc[2]; 237 case 0x120: /* DCGC0 */ 238 return s->dcgc[0]; 239 case 0x124: /* DCGC1 */ 240 return s->dcgc[1]; 241 case 0x128: /* DCGC2 */ 242 return s->dcgc[2]; 243 case 0x150: /* CLKVCLR */ 244 return s->clkvclr; 245 case 0x160: /* LDOARST */ 246 return s->ldoarst; 247 case 0x1e0: /* USER0 */ 248 return s->user0; 249 case 0x1e4: /* USER1 */ 250 return s->user1; 251 default: 252 qemu_log_mask(LOG_GUEST_ERROR, 253 "SSYS: read at bad offset 0x%x\n", (int)offset); 254 return 0; 255 } 256 } 257 258 static bool ssys_use_rcc2(ssys_state *s) 259 { 260 return (s->rcc2 >> 31) & 0x1; 261 } 262 263 /* 264 * Calculate the system clock period. We only want to propagate 265 * this change to the rest of the system if we're not being called 266 * from migration post-load. 267 */ 268 static void ssys_calculate_system_clock(ssys_state *s, bool propagate_clock) 269 { 270 int period_ns; 271 /* 272 * SYSDIV field specifies divisor: 0 == /1, 1 == /2, etc. Input 273 * clock is 200MHz, which is a period of 5 ns. Dividing the clock 274 * frequency by X is the same as multiplying the period by X. 275 */ 276 if (ssys_use_rcc2(s)) { 277 period_ns = 5 * (((s->rcc2 >> 23) & 0x3f) + 1); 278 } else { 279 period_ns = 5 * (((s->rcc >> 23) & 0xf) + 1); 280 } 281 clock_set_ns(s->sysclk, period_ns); 282 if (propagate_clock) { 283 clock_propagate(s->sysclk); 284 } 285 } 286 287 static void ssys_write(void *opaque, hwaddr offset, 288 uint64_t value, unsigned size) 289 { 290 ssys_state *s = (ssys_state *)opaque; 291 292 switch (offset) { 293 case 0x030: /* PBORCTL */ 294 s->pborctl = value & 0xffff; 295 break; 296 case 0x034: /* LDOPCTL */ 297 s->ldopctl = value & 0x1f; 298 break; 299 case 0x040: /* SRCR0 */ 300 case 0x044: /* SRCR1 */ 301 case 0x048: /* SRCR2 */ 302 qemu_log_mask(LOG_UNIMP, "Peripheral reset not implemented\n"); 303 break; 304 case 0x054: /* IMC */ 305 s->int_mask = value & 0x7f; 306 break; 307 case 0x058: /* MISC */ 308 s->int_status &= ~value; 309 break; 310 case 0x05c: /* RESC */ 311 s->resc = value & 0x3f; 312 break; 313 case 0x060: /* RCC */ 314 if ((s->rcc & (1 << 13)) != 0 && (value & (1 << 13)) == 0) { 315 /* PLL enable. */ 316 s->int_status |= (1 << 6); 317 } 318 s->rcc = value; 319 ssys_calculate_system_clock(s, true); 320 break; 321 case 0x070: /* RCC2 */ 322 if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) { 323 break; 324 } 325 326 if ((s->rcc2 & (1 << 13)) != 0 && (value & (1 << 13)) == 0) { 327 /* PLL enable. */ 328 s->int_status |= (1 << 6); 329 } 330 s->rcc2 = value; 331 ssys_calculate_system_clock(s, true); 332 break; 333 case 0x100: /* RCGC0 */ 334 s->rcgc[0] = value; 335 break; 336 case 0x104: /* RCGC1 */ 337 s->rcgc[1] = value; 338 break; 339 case 0x108: /* RCGC2 */ 340 s->rcgc[2] = value; 341 break; 342 case 0x110: /* SCGC0 */ 343 s->scgc[0] = value; 344 break; 345 case 0x114: /* SCGC1 */ 346 s->scgc[1] = value; 347 break; 348 case 0x118: /* SCGC2 */ 349 s->scgc[2] = value; 350 break; 351 case 0x120: /* DCGC0 */ 352 s->dcgc[0] = value; 353 break; 354 case 0x124: /* DCGC1 */ 355 s->dcgc[1] = value; 356 break; 357 case 0x128: /* DCGC2 */ 358 s->dcgc[2] = value; 359 break; 360 case 0x150: /* CLKVCLR */ 361 s->clkvclr = value; 362 break; 363 case 0x160: /* LDOARST */ 364 s->ldoarst = value; 365 break; 366 default: 367 qemu_log_mask(LOG_GUEST_ERROR, 368 "SSYS: write at bad offset 0x%x\n", (int)offset); 369 } 370 ssys_update(s); 371 } 372 373 static const MemoryRegionOps ssys_ops = { 374 .read = ssys_read, 375 .write = ssys_write, 376 .endianness = DEVICE_NATIVE_ENDIAN, 377 }; 378 379 static void stellaris_sys_reset_enter(Object *obj, ResetType type) 380 { 381 ssys_state *s = STELLARIS_SYS(obj); 382 383 s->pborctl = 0x7ffd; 384 s->rcc = 0x078e3ac0; 385 386 if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) { 387 s->rcc2 = 0; 388 } else { 389 s->rcc2 = 0x07802810; 390 } 391 s->rcgc[0] = 1; 392 s->scgc[0] = 1; 393 s->dcgc[0] = 1; 394 } 395 396 static void stellaris_sys_reset_hold(Object *obj) 397 { 398 ssys_state *s = STELLARIS_SYS(obj); 399 400 /* OK to propagate clocks from the hold phase */ 401 ssys_calculate_system_clock(s, true); 402 } 403 404 static void stellaris_sys_reset_exit(Object *obj) 405 { 406 } 407 408 static int stellaris_sys_post_load(void *opaque, int version_id) 409 { 410 ssys_state *s = opaque; 411 412 ssys_calculate_system_clock(s, false); 413 414 return 0; 415 } 416 417 static const VMStateDescription vmstate_stellaris_sys = { 418 .name = "stellaris_sys", 419 .version_id = 2, 420 .minimum_version_id = 1, 421 .post_load = stellaris_sys_post_load, 422 .fields = (VMStateField[]) { 423 VMSTATE_UINT32(pborctl, ssys_state), 424 VMSTATE_UINT32(ldopctl, ssys_state), 425 VMSTATE_UINT32(int_mask, ssys_state), 426 VMSTATE_UINT32(int_status, ssys_state), 427 VMSTATE_UINT32(resc, ssys_state), 428 VMSTATE_UINT32(rcc, ssys_state), 429 VMSTATE_UINT32_V(rcc2, ssys_state, 2), 430 VMSTATE_UINT32_ARRAY(rcgc, ssys_state, 3), 431 VMSTATE_UINT32_ARRAY(scgc, ssys_state, 3), 432 VMSTATE_UINT32_ARRAY(dcgc, ssys_state, 3), 433 VMSTATE_UINT32(clkvclr, ssys_state), 434 VMSTATE_UINT32(ldoarst, ssys_state), 435 /* No field for sysclk -- handled in post-load instead */ 436 VMSTATE_END_OF_LIST() 437 } 438 }; 439 440 static Property stellaris_sys_properties[] = { 441 DEFINE_PROP_UINT32("user0", ssys_state, user0, 0), 442 DEFINE_PROP_UINT32("user1", ssys_state, user1, 0), 443 DEFINE_PROP_UINT32("did0", ssys_state, did0, 0), 444 DEFINE_PROP_UINT32("did1", ssys_state, did1, 0), 445 DEFINE_PROP_UINT32("dc0", ssys_state, dc0, 0), 446 DEFINE_PROP_UINT32("dc1", ssys_state, dc1, 0), 447 DEFINE_PROP_UINT32("dc2", ssys_state, dc2, 0), 448 DEFINE_PROP_UINT32("dc3", ssys_state, dc3, 0), 449 DEFINE_PROP_UINT32("dc4", ssys_state, dc4, 0), 450 DEFINE_PROP_END_OF_LIST() 451 }; 452 453 static void stellaris_sys_instance_init(Object *obj) 454 { 455 ssys_state *s = STELLARIS_SYS(obj); 456 SysBusDevice *sbd = SYS_BUS_DEVICE(s); 457 458 memory_region_init_io(&s->iomem, obj, &ssys_ops, s, "ssys", 0x00001000); 459 sysbus_init_mmio(sbd, &s->iomem); 460 sysbus_init_irq(sbd, &s->irq); 461 s->sysclk = qdev_init_clock_out(DEVICE(s), "SYSCLK"); 462 } 463 464 /* I2C controller. */ 465 466 #define TYPE_STELLARIS_I2C "stellaris-i2c" 467 OBJECT_DECLARE_SIMPLE_TYPE(stellaris_i2c_state, STELLARIS_I2C) 468 469 struct stellaris_i2c_state { 470 SysBusDevice parent_obj; 471 472 I2CBus *bus; 473 qemu_irq irq; 474 MemoryRegion iomem; 475 uint32_t msa; 476 uint32_t mcs; 477 uint32_t mdr; 478 uint32_t mtpr; 479 uint32_t mimr; 480 uint32_t mris; 481 uint32_t mcr; 482 }; 483 484 #define STELLARIS_I2C_MCS_BUSY 0x01 485 #define STELLARIS_I2C_MCS_ERROR 0x02 486 #define STELLARIS_I2C_MCS_ADRACK 0x04 487 #define STELLARIS_I2C_MCS_DATACK 0x08 488 #define STELLARIS_I2C_MCS_ARBLST 0x10 489 #define STELLARIS_I2C_MCS_IDLE 0x20 490 #define STELLARIS_I2C_MCS_BUSBSY 0x40 491 492 static uint64_t stellaris_i2c_read(void *opaque, hwaddr offset, 493 unsigned size) 494 { 495 stellaris_i2c_state *s = (stellaris_i2c_state *)opaque; 496 497 switch (offset) { 498 case 0x00: /* MSA */ 499 return s->msa; 500 case 0x04: /* MCS */ 501 /* We don't emulate timing, so the controller is never busy. */ 502 return s->mcs | STELLARIS_I2C_MCS_IDLE; 503 case 0x08: /* MDR */ 504 return s->mdr; 505 case 0x0c: /* MTPR */ 506 return s->mtpr; 507 case 0x10: /* MIMR */ 508 return s->mimr; 509 case 0x14: /* MRIS */ 510 return s->mris; 511 case 0x18: /* MMIS */ 512 return s->mris & s->mimr; 513 case 0x20: /* MCR */ 514 return s->mcr; 515 default: 516 qemu_log_mask(LOG_GUEST_ERROR, 517 "stellaris_i2c: read at bad offset 0x%x\n", (int)offset); 518 return 0; 519 } 520 } 521 522 static void stellaris_i2c_update(stellaris_i2c_state *s) 523 { 524 int level; 525 526 level = (s->mris & s->mimr) != 0; 527 qemu_set_irq(s->irq, level); 528 } 529 530 static void stellaris_i2c_write(void *opaque, hwaddr offset, 531 uint64_t value, unsigned size) 532 { 533 stellaris_i2c_state *s = (stellaris_i2c_state *)opaque; 534 535 switch (offset) { 536 case 0x00: /* MSA */ 537 s->msa = value & 0xff; 538 break; 539 case 0x04: /* MCS */ 540 if ((s->mcr & 0x10) == 0) { 541 /* Disabled. Do nothing. */ 542 break; 543 } 544 /* Grab the bus if this is starting a transfer. */ 545 if ((value & 2) && (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) { 546 if (i2c_start_transfer(s->bus, s->msa >> 1, s->msa & 1)) { 547 s->mcs |= STELLARIS_I2C_MCS_ARBLST; 548 } else { 549 s->mcs &= ~STELLARIS_I2C_MCS_ARBLST; 550 s->mcs |= STELLARIS_I2C_MCS_BUSBSY; 551 } 552 } 553 /* If we don't have the bus then indicate an error. */ 554 if (!i2c_bus_busy(s->bus) 555 || (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) { 556 s->mcs |= STELLARIS_I2C_MCS_ERROR; 557 break; 558 } 559 s->mcs &= ~STELLARIS_I2C_MCS_ERROR; 560 if (value & 1) { 561 /* Transfer a byte. */ 562 /* TODO: Handle errors. */ 563 if (s->msa & 1) { 564 /* Recv */ 565 s->mdr = i2c_recv(s->bus); 566 } else { 567 /* Send */ 568 i2c_send(s->bus, s->mdr); 569 } 570 /* Raise an interrupt. */ 571 s->mris |= 1; 572 } 573 if (value & 4) { 574 /* Finish transfer. */ 575 i2c_end_transfer(s->bus); 576 s->mcs &= ~STELLARIS_I2C_MCS_BUSBSY; 577 } 578 break; 579 case 0x08: /* MDR */ 580 s->mdr = value & 0xff; 581 break; 582 case 0x0c: /* MTPR */ 583 s->mtpr = value & 0xff; 584 break; 585 case 0x10: /* MIMR */ 586 s->mimr = 1; 587 break; 588 case 0x1c: /* MICR */ 589 s->mris &= ~value; 590 break; 591 case 0x20: /* MCR */ 592 if (value & 1) { 593 qemu_log_mask(LOG_UNIMP, 594 "stellaris_i2c: Loopback not implemented\n"); 595 } 596 if (value & 0x20) { 597 qemu_log_mask(LOG_UNIMP, 598 "stellaris_i2c: Slave mode not implemented\n"); 599 } 600 s->mcr = value & 0x31; 601 break; 602 default: 603 qemu_log_mask(LOG_GUEST_ERROR, 604 "stellaris_i2c: write at bad offset 0x%x\n", (int)offset); 605 } 606 stellaris_i2c_update(s); 607 } 608 609 static void stellaris_i2c_reset(stellaris_i2c_state *s) 610 { 611 if (s->mcs & STELLARIS_I2C_MCS_BUSBSY) 612 i2c_end_transfer(s->bus); 613 614 s->msa = 0; 615 s->mcs = 0; 616 s->mdr = 0; 617 s->mtpr = 1; 618 s->mimr = 0; 619 s->mris = 0; 620 s->mcr = 0; 621 stellaris_i2c_update(s); 622 } 623 624 static const MemoryRegionOps stellaris_i2c_ops = { 625 .read = stellaris_i2c_read, 626 .write = stellaris_i2c_write, 627 .endianness = DEVICE_NATIVE_ENDIAN, 628 }; 629 630 static const VMStateDescription vmstate_stellaris_i2c = { 631 .name = "stellaris_i2c", 632 .version_id = 1, 633 .minimum_version_id = 1, 634 .fields = (VMStateField[]) { 635 VMSTATE_UINT32(msa, stellaris_i2c_state), 636 VMSTATE_UINT32(mcs, stellaris_i2c_state), 637 VMSTATE_UINT32(mdr, stellaris_i2c_state), 638 VMSTATE_UINT32(mtpr, stellaris_i2c_state), 639 VMSTATE_UINT32(mimr, stellaris_i2c_state), 640 VMSTATE_UINT32(mris, stellaris_i2c_state), 641 VMSTATE_UINT32(mcr, stellaris_i2c_state), 642 VMSTATE_END_OF_LIST() 643 } 644 }; 645 646 static void stellaris_i2c_init(Object *obj) 647 { 648 DeviceState *dev = DEVICE(obj); 649 stellaris_i2c_state *s = STELLARIS_I2C(obj); 650 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 651 I2CBus *bus; 652 653 sysbus_init_irq(sbd, &s->irq); 654 bus = i2c_init_bus(dev, "i2c"); 655 s->bus = bus; 656 657 memory_region_init_io(&s->iomem, obj, &stellaris_i2c_ops, s, 658 "i2c", 0x1000); 659 sysbus_init_mmio(sbd, &s->iomem); 660 /* ??? For now we only implement the master interface. */ 661 stellaris_i2c_reset(s); 662 } 663 664 /* Analogue to Digital Converter. This is only partially implemented, 665 enough for applications that use a combined ADC and timer tick. */ 666 667 #define STELLARIS_ADC_EM_CONTROLLER 0 668 #define STELLARIS_ADC_EM_COMP 1 669 #define STELLARIS_ADC_EM_EXTERNAL 4 670 #define STELLARIS_ADC_EM_TIMER 5 671 #define STELLARIS_ADC_EM_PWM0 6 672 #define STELLARIS_ADC_EM_PWM1 7 673 #define STELLARIS_ADC_EM_PWM2 8 674 675 #define STELLARIS_ADC_FIFO_EMPTY 0x0100 676 #define STELLARIS_ADC_FIFO_FULL 0x1000 677 678 #define TYPE_STELLARIS_ADC "stellaris-adc" 679 typedef struct StellarisADCState StellarisADCState; 680 DECLARE_INSTANCE_CHECKER(StellarisADCState, STELLARIS_ADC, TYPE_STELLARIS_ADC) 681 682 struct StellarisADCState { 683 SysBusDevice parent_obj; 684 685 MemoryRegion iomem; 686 uint32_t actss; 687 uint32_t ris; 688 uint32_t im; 689 uint32_t emux; 690 uint32_t ostat; 691 uint32_t ustat; 692 uint32_t sspri; 693 uint32_t sac; 694 struct { 695 uint32_t state; 696 uint32_t data[16]; 697 } fifo[4]; 698 uint32_t ssmux[4]; 699 uint32_t ssctl[4]; 700 uint32_t noise; 701 qemu_irq irq[4]; 702 }; 703 704 static uint32_t stellaris_adc_fifo_read(StellarisADCState *s, int n) 705 { 706 int tail; 707 708 tail = s->fifo[n].state & 0xf; 709 if (s->fifo[n].state & STELLARIS_ADC_FIFO_EMPTY) { 710 s->ustat |= 1 << n; 711 } else { 712 s->fifo[n].state = (s->fifo[n].state & ~0xf) | ((tail + 1) & 0xf); 713 s->fifo[n].state &= ~STELLARIS_ADC_FIFO_FULL; 714 if (tail + 1 == ((s->fifo[n].state >> 4) & 0xf)) 715 s->fifo[n].state |= STELLARIS_ADC_FIFO_EMPTY; 716 } 717 return s->fifo[n].data[tail]; 718 } 719 720 static void stellaris_adc_fifo_write(StellarisADCState *s, int n, 721 uint32_t value) 722 { 723 int head; 724 725 /* TODO: Real hardware has limited size FIFOs. We have a full 16 entry 726 FIFO fir each sequencer. */ 727 head = (s->fifo[n].state >> 4) & 0xf; 728 if (s->fifo[n].state & STELLARIS_ADC_FIFO_FULL) { 729 s->ostat |= 1 << n; 730 return; 731 } 732 s->fifo[n].data[head] = value; 733 head = (head + 1) & 0xf; 734 s->fifo[n].state &= ~STELLARIS_ADC_FIFO_EMPTY; 735 s->fifo[n].state = (s->fifo[n].state & ~0xf0) | (head << 4); 736 if ((s->fifo[n].state & 0xf) == head) 737 s->fifo[n].state |= STELLARIS_ADC_FIFO_FULL; 738 } 739 740 static void stellaris_adc_update(StellarisADCState *s) 741 { 742 int level; 743 int n; 744 745 for (n = 0; n < 4; n++) { 746 level = (s->ris & s->im & (1 << n)) != 0; 747 qemu_set_irq(s->irq[n], level); 748 } 749 } 750 751 static void stellaris_adc_trigger(void *opaque, int irq, int level) 752 { 753 StellarisADCState *s = opaque; 754 int n; 755 756 for (n = 0; n < 4; n++) { 757 if ((s->actss & (1 << n)) == 0) { 758 continue; 759 } 760 761 if (((s->emux >> (n * 4)) & 0xff) != 5) { 762 continue; 763 } 764 765 /* Some applications use the ADC as a random number source, so introduce 766 some variation into the signal. */ 767 s->noise = s->noise * 314159 + 1; 768 /* ??? actual inputs not implemented. Return an arbitrary value. */ 769 stellaris_adc_fifo_write(s, n, 0x200 + ((s->noise >> 16) & 7)); 770 s->ris |= (1 << n); 771 stellaris_adc_update(s); 772 } 773 } 774 775 static void stellaris_adc_reset(StellarisADCState *s) 776 { 777 int n; 778 779 for (n = 0; n < 4; n++) { 780 s->ssmux[n] = 0; 781 s->ssctl[n] = 0; 782 s->fifo[n].state = STELLARIS_ADC_FIFO_EMPTY; 783 } 784 } 785 786 static uint64_t stellaris_adc_read(void *opaque, hwaddr offset, 787 unsigned size) 788 { 789 StellarisADCState *s = opaque; 790 791 /* TODO: Implement this. */ 792 if (offset >= 0x40 && offset < 0xc0) { 793 int n; 794 n = (offset - 0x40) >> 5; 795 switch (offset & 0x1f) { 796 case 0x00: /* SSMUX */ 797 return s->ssmux[n]; 798 case 0x04: /* SSCTL */ 799 return s->ssctl[n]; 800 case 0x08: /* SSFIFO */ 801 return stellaris_adc_fifo_read(s, n); 802 case 0x0c: /* SSFSTAT */ 803 return s->fifo[n].state; 804 default: 805 break; 806 } 807 } 808 switch (offset) { 809 case 0x00: /* ACTSS */ 810 return s->actss; 811 case 0x04: /* RIS */ 812 return s->ris; 813 case 0x08: /* IM */ 814 return s->im; 815 case 0x0c: /* ISC */ 816 return s->ris & s->im; 817 case 0x10: /* OSTAT */ 818 return s->ostat; 819 case 0x14: /* EMUX */ 820 return s->emux; 821 case 0x18: /* USTAT */ 822 return s->ustat; 823 case 0x20: /* SSPRI */ 824 return s->sspri; 825 case 0x30: /* SAC */ 826 return s->sac; 827 default: 828 qemu_log_mask(LOG_GUEST_ERROR, 829 "stellaris_adc: read at bad offset 0x%x\n", (int)offset); 830 return 0; 831 } 832 } 833 834 static void stellaris_adc_write(void *opaque, hwaddr offset, 835 uint64_t value, unsigned size) 836 { 837 StellarisADCState *s = opaque; 838 839 /* TODO: Implement this. */ 840 if (offset >= 0x40 && offset < 0xc0) { 841 int n; 842 n = (offset - 0x40) >> 5; 843 switch (offset & 0x1f) { 844 case 0x00: /* SSMUX */ 845 s->ssmux[n] = value & 0x33333333; 846 return; 847 case 0x04: /* SSCTL */ 848 if (value != 6) { 849 qemu_log_mask(LOG_UNIMP, 850 "ADC: Unimplemented sequence %" PRIx64 "\n", 851 value); 852 } 853 s->ssctl[n] = value; 854 return; 855 default: 856 break; 857 } 858 } 859 switch (offset) { 860 case 0x00: /* ACTSS */ 861 s->actss = value & 0xf; 862 break; 863 case 0x08: /* IM */ 864 s->im = value; 865 break; 866 case 0x0c: /* ISC */ 867 s->ris &= ~value; 868 break; 869 case 0x10: /* OSTAT */ 870 s->ostat &= ~value; 871 break; 872 case 0x14: /* EMUX */ 873 s->emux = value; 874 break; 875 case 0x18: /* USTAT */ 876 s->ustat &= ~value; 877 break; 878 case 0x20: /* SSPRI */ 879 s->sspri = value; 880 break; 881 case 0x28: /* PSSI */ 882 qemu_log_mask(LOG_UNIMP, "ADC: sample initiate unimplemented\n"); 883 break; 884 case 0x30: /* SAC */ 885 s->sac = value; 886 break; 887 default: 888 qemu_log_mask(LOG_GUEST_ERROR, 889 "stellaris_adc: write at bad offset 0x%x\n", (int)offset); 890 } 891 stellaris_adc_update(s); 892 } 893 894 static const MemoryRegionOps stellaris_adc_ops = { 895 .read = stellaris_adc_read, 896 .write = stellaris_adc_write, 897 .endianness = DEVICE_NATIVE_ENDIAN, 898 }; 899 900 static const VMStateDescription vmstate_stellaris_adc = { 901 .name = "stellaris_adc", 902 .version_id = 1, 903 .minimum_version_id = 1, 904 .fields = (VMStateField[]) { 905 VMSTATE_UINT32(actss, StellarisADCState), 906 VMSTATE_UINT32(ris, StellarisADCState), 907 VMSTATE_UINT32(im, StellarisADCState), 908 VMSTATE_UINT32(emux, StellarisADCState), 909 VMSTATE_UINT32(ostat, StellarisADCState), 910 VMSTATE_UINT32(ustat, StellarisADCState), 911 VMSTATE_UINT32(sspri, StellarisADCState), 912 VMSTATE_UINT32(sac, StellarisADCState), 913 VMSTATE_UINT32(fifo[0].state, StellarisADCState), 914 VMSTATE_UINT32_ARRAY(fifo[0].data, StellarisADCState, 16), 915 VMSTATE_UINT32(ssmux[0], StellarisADCState), 916 VMSTATE_UINT32(ssctl[0], StellarisADCState), 917 VMSTATE_UINT32(fifo[1].state, StellarisADCState), 918 VMSTATE_UINT32_ARRAY(fifo[1].data, StellarisADCState, 16), 919 VMSTATE_UINT32(ssmux[1], StellarisADCState), 920 VMSTATE_UINT32(ssctl[1], StellarisADCState), 921 VMSTATE_UINT32(fifo[2].state, StellarisADCState), 922 VMSTATE_UINT32_ARRAY(fifo[2].data, StellarisADCState, 16), 923 VMSTATE_UINT32(ssmux[2], StellarisADCState), 924 VMSTATE_UINT32(ssctl[2], StellarisADCState), 925 VMSTATE_UINT32(fifo[3].state, StellarisADCState), 926 VMSTATE_UINT32_ARRAY(fifo[3].data, StellarisADCState, 16), 927 VMSTATE_UINT32(ssmux[3], StellarisADCState), 928 VMSTATE_UINT32(ssctl[3], StellarisADCState), 929 VMSTATE_UINT32(noise, StellarisADCState), 930 VMSTATE_END_OF_LIST() 931 } 932 }; 933 934 static void stellaris_adc_init(Object *obj) 935 { 936 DeviceState *dev = DEVICE(obj); 937 StellarisADCState *s = STELLARIS_ADC(obj); 938 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 939 int n; 940 941 for (n = 0; n < 4; n++) { 942 sysbus_init_irq(sbd, &s->irq[n]); 943 } 944 945 memory_region_init_io(&s->iomem, obj, &stellaris_adc_ops, s, 946 "adc", 0x1000); 947 sysbus_init_mmio(sbd, &s->iomem); 948 stellaris_adc_reset(s); 949 qdev_init_gpio_in(dev, stellaris_adc_trigger, 1); 950 } 951 952 /* Board init. */ 953 static stellaris_board_info stellaris_boards[] = { 954 { "LM3S811EVB", 955 0, 956 0x0032000e, 957 0x001f001f, /* dc0 */ 958 0x001132bf, 959 0x01071013, 960 0x3f0f01ff, 961 0x0000001f, 962 BP_OLED_I2C 963 }, 964 { "LM3S6965EVB", 965 0x10010002, 966 0x1073402e, 967 0x00ff007f, /* dc0 */ 968 0x001133ff, 969 0x030f5317, 970 0x0f0f87ff, 971 0x5000007f, 972 BP_OLED_SSI | BP_GAMEPAD 973 } 974 }; 975 976 static void stellaris_init(MachineState *ms, stellaris_board_info *board) 977 { 978 static const int uart_irq[] = {5, 6, 33, 34}; 979 static const int timer_irq[] = {19, 21, 23, 35}; 980 static const uint32_t gpio_addr[7] = 981 { 0x40004000, 0x40005000, 0x40006000, 0x40007000, 982 0x40024000, 0x40025000, 0x40026000}; 983 static const int gpio_irq[7] = {0, 1, 2, 3, 4, 30, 31}; 984 985 /* Memory map of SoC devices, from 986 * Stellaris LM3S6965 Microcontroller Data Sheet (rev I) 987 * http://www.ti.com/lit/ds/symlink/lm3s6965.pdf 988 * 989 * 40000000 wdtimer 990 * 40002000 i2c (unimplemented) 991 * 40004000 GPIO 992 * 40005000 GPIO 993 * 40006000 GPIO 994 * 40007000 GPIO 995 * 40008000 SSI 996 * 4000c000 UART 997 * 4000d000 UART 998 * 4000e000 UART 999 * 40020000 i2c 1000 * 40021000 i2c (unimplemented) 1001 * 40024000 GPIO 1002 * 40025000 GPIO 1003 * 40026000 GPIO 1004 * 40028000 PWM (unimplemented) 1005 * 4002c000 QEI (unimplemented) 1006 * 4002d000 QEI (unimplemented) 1007 * 40030000 gptimer 1008 * 40031000 gptimer 1009 * 40032000 gptimer 1010 * 40033000 gptimer 1011 * 40038000 ADC 1012 * 4003c000 analogue comparator (unimplemented) 1013 * 40048000 ethernet 1014 * 400fc000 hibernation module (unimplemented) 1015 * 400fd000 flash memory control (unimplemented) 1016 * 400fe000 system control 1017 */ 1018 1019 DeviceState *gpio_dev[7], *nvic; 1020 qemu_irq gpio_in[7][8]; 1021 qemu_irq gpio_out[7][8]; 1022 qemu_irq adc; 1023 int sram_size; 1024 int flash_size; 1025 I2CBus *i2c; 1026 DeviceState *dev; 1027 DeviceState *ssys_dev; 1028 int i; 1029 int j; 1030 const uint8_t *macaddr; 1031 1032 MemoryRegion *sram = g_new(MemoryRegion, 1); 1033 MemoryRegion *flash = g_new(MemoryRegion, 1); 1034 MemoryRegion *system_memory = get_system_memory(); 1035 1036 flash_size = (((board->dc0 & 0xffff) + 1) << 1) * 1024; 1037 sram_size = ((board->dc0 >> 18) + 1) * 1024; 1038 1039 /* Flash programming is done via the SCU, so pretend it is ROM. */ 1040 memory_region_init_rom(flash, NULL, "stellaris.flash", flash_size, 1041 &error_fatal); 1042 memory_region_add_subregion(system_memory, 0, flash); 1043 1044 memory_region_init_ram(sram, NULL, "stellaris.sram", sram_size, 1045 &error_fatal); 1046 memory_region_add_subregion(system_memory, 0x20000000, sram); 1047 1048 /* 1049 * Create the system-registers object early, because we will 1050 * need its sysclk output. 1051 */ 1052 ssys_dev = qdev_new(TYPE_STELLARIS_SYS); 1053 /* Most devices come preprogrammed with a MAC address in the user data. */ 1054 macaddr = nd_table[0].macaddr.a; 1055 qdev_prop_set_uint32(ssys_dev, "user0", 1056 macaddr[0] | (macaddr[1] << 8) | (macaddr[2] << 16)); 1057 qdev_prop_set_uint32(ssys_dev, "user1", 1058 macaddr[3] | (macaddr[4] << 8) | (macaddr[5] << 16)); 1059 qdev_prop_set_uint32(ssys_dev, "did0", board->did0); 1060 qdev_prop_set_uint32(ssys_dev, "did1", board->did1); 1061 qdev_prop_set_uint32(ssys_dev, "dc0", board->dc0); 1062 qdev_prop_set_uint32(ssys_dev, "dc1", board->dc1); 1063 qdev_prop_set_uint32(ssys_dev, "dc2", board->dc2); 1064 qdev_prop_set_uint32(ssys_dev, "dc3", board->dc3); 1065 qdev_prop_set_uint32(ssys_dev, "dc4", board->dc4); 1066 sysbus_realize_and_unref(SYS_BUS_DEVICE(ssys_dev), &error_fatal); 1067 1068 nvic = qdev_new(TYPE_ARMV7M); 1069 qdev_prop_set_uint32(nvic, "num-irq", NUM_IRQ_LINES); 1070 qdev_prop_set_string(nvic, "cpu-type", ms->cpu_type); 1071 qdev_prop_set_bit(nvic, "enable-bitband", true); 1072 qdev_connect_clock_in(nvic, "cpuclk", 1073 qdev_get_clock_out(ssys_dev, "SYSCLK")); 1074 /* This SoC does not connect the systick reference clock */ 1075 object_property_set_link(OBJECT(nvic), "memory", 1076 OBJECT(get_system_memory()), &error_abort); 1077 /* This will exit with an error if the user passed us a bad cpu_type */ 1078 sysbus_realize_and_unref(SYS_BUS_DEVICE(nvic), &error_fatal); 1079 1080 /* Now we can wire up the IRQ and MMIO of the system registers */ 1081 sysbus_mmio_map(SYS_BUS_DEVICE(ssys_dev), 0, 0x400fe000); 1082 sysbus_connect_irq(SYS_BUS_DEVICE(ssys_dev), 0, qdev_get_gpio_in(nvic, 28)); 1083 1084 if (board->dc1 & (1 << 16)) { 1085 dev = sysbus_create_varargs(TYPE_STELLARIS_ADC, 0x40038000, 1086 qdev_get_gpio_in(nvic, 14), 1087 qdev_get_gpio_in(nvic, 15), 1088 qdev_get_gpio_in(nvic, 16), 1089 qdev_get_gpio_in(nvic, 17), 1090 NULL); 1091 adc = qdev_get_gpio_in(dev, 0); 1092 } else { 1093 adc = NULL; 1094 } 1095 for (i = 0; i < 4; i++) { 1096 if (board->dc2 & (0x10000 << i)) { 1097 SysBusDevice *sbd; 1098 1099 dev = qdev_new(TYPE_STELLARIS_GPTM); 1100 sbd = SYS_BUS_DEVICE(dev); 1101 qdev_connect_clock_in(dev, "clk", 1102 qdev_get_clock_out(ssys_dev, "SYSCLK")); 1103 sysbus_realize_and_unref(sbd, &error_fatal); 1104 sysbus_mmio_map(sbd, 0, 0x40030000 + i * 0x1000); 1105 sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(nvic, timer_irq[i])); 1106 /* TODO: This is incorrect, but we get away with it because 1107 the ADC output is only ever pulsed. */ 1108 qdev_connect_gpio_out(dev, 0, adc); 1109 } 1110 } 1111 1112 if (board->dc1 & (1 << 3)) { /* watchdog present */ 1113 dev = qdev_new(TYPE_LUMINARY_WATCHDOG); 1114 1115 qdev_connect_clock_in(dev, "WDOGCLK", 1116 qdev_get_clock_out(ssys_dev, "SYSCLK")); 1117 1118 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1119 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1120 0, 1121 0x40000000u); 1122 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1123 0, 1124 qdev_get_gpio_in(nvic, 18)); 1125 } 1126 1127 1128 for (i = 0; i < 7; i++) { 1129 if (board->dc4 & (1 << i)) { 1130 gpio_dev[i] = sysbus_create_simple("pl061_luminary", gpio_addr[i], 1131 qdev_get_gpio_in(nvic, 1132 gpio_irq[i])); 1133 for (j = 0; j < 8; j++) { 1134 gpio_in[i][j] = qdev_get_gpio_in(gpio_dev[i], j); 1135 gpio_out[i][j] = NULL; 1136 } 1137 } 1138 } 1139 1140 if (board->dc2 & (1 << 12)) { 1141 dev = sysbus_create_simple(TYPE_STELLARIS_I2C, 0x40020000, 1142 qdev_get_gpio_in(nvic, 8)); 1143 i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c"); 1144 if (board->peripherals & BP_OLED_I2C) { 1145 i2c_slave_create_simple(i2c, "ssd0303", 0x3d); 1146 } 1147 } 1148 1149 for (i = 0; i < 4; i++) { 1150 if (board->dc2 & (1 << i)) { 1151 SysBusDevice *sbd; 1152 1153 dev = qdev_new("pl011_luminary"); 1154 sbd = SYS_BUS_DEVICE(dev); 1155 qdev_prop_set_chr(dev, "chardev", serial_hd(i)); 1156 sysbus_realize_and_unref(sbd, &error_fatal); 1157 sysbus_mmio_map(sbd, 0, 0x4000c000 + i * 0x1000); 1158 sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(nvic, uart_irq[i])); 1159 } 1160 } 1161 if (board->dc2 & (1 << 4)) { 1162 dev = sysbus_create_simple("pl022", 0x40008000, 1163 qdev_get_gpio_in(nvic, 7)); 1164 if (board->peripherals & BP_OLED_SSI) { 1165 void *bus; 1166 DeviceState *sddev; 1167 DeviceState *ssddev; 1168 DriveInfo *dinfo; 1169 DeviceState *carddev; 1170 DeviceState *gpio_d_splitter; 1171 BlockBackend *blk; 1172 1173 /* 1174 * Some boards have both an OLED controller and SD card connected to 1175 * the same SSI port, with the SD card chip select connected to a 1176 * GPIO pin. Technically the OLED chip select is connected to the 1177 * SSI Fss pin. We do not bother emulating that as both devices 1178 * should never be selected simultaneously, and our OLED controller 1179 * ignores stray 0xff commands that occur when deselecting the SD 1180 * card. 1181 * 1182 * The h/w wiring is: 1183 * - GPIO pin D0 is wired to the active-low SD card chip select 1184 * - GPIO pin A3 is wired to the active-low OLED chip select 1185 * - The SoC wiring of the PL061 "auxiliary function" for A3 is 1186 * SSI0Fss ("frame signal"), which is an output from the SoC's 1187 * SSI controller. The SSI controller takes SSI0Fss low when it 1188 * transmits a frame, so it can work as a chip-select signal. 1189 * - GPIO A4 is aux-function SSI0Rx, and wired to the SD card Tx 1190 * (the OLED never sends data to the CPU, so no wiring needed) 1191 * - GPIO A5 is aux-function SSI0Tx, and wired to the SD card Rx 1192 * and the OLED display-data-in 1193 * - GPIO A2 is aux-function SSI0Clk, wired to SD card and OLED 1194 * serial-clock input 1195 * So a guest that wants to use the OLED can configure the PL061 1196 * to make pins A2, A3, A5 aux-function, so they are connected 1197 * directly to the SSI controller. When the SSI controller sends 1198 * data it asserts SSI0Fss which selects the OLED. 1199 * A guest that wants to use the SD card configures A2, A4 and A5 1200 * as aux-function, but leaves A3 as a software-controlled GPIO 1201 * line. It asserts the SD card chip-select by using the PL061 1202 * to control pin D0, and lets the SSI controller handle Clk, Tx 1203 * and Rx. (The SSI controller asserts Fss during tx cycles as 1204 * usual, but because A3 is not set to aux-function this is not 1205 * forwarded to the OLED, and so the OLED stays unselected.) 1206 * 1207 * The QEMU implementation instead is: 1208 * - GPIO pin D0 is wired to the active-low SD card chip select, 1209 * and also to the OLED chip-select which is implemented 1210 * as *active-high* 1211 * - SSI controller signals go to the devices regardless of 1212 * whether the guest programs A2, A4, A5 as aux-function or not 1213 * 1214 * The problem with this implementation is if the guest doesn't 1215 * care about the SD card and only uses the OLED. In that case it 1216 * may choose never to do anything with D0 (leaving it in its 1217 * default floating state, which reliably leaves the card disabled 1218 * because an SD card has a pullup on CS within the card itself), 1219 * and only set up A2, A3, A5. This for us would mean the OLED 1220 * never gets the chip-select assert it needs. We work around 1221 * this with a manual raise of D0 here (despite board creation 1222 * code being the wrong place to raise IRQ lines) to put the OLED 1223 * into an initially selected state. 1224 * 1225 * In theory the right way to model this would be: 1226 * - Implement aux-function support in the PL061, with an 1227 * extra set of AFIN and AFOUT GPIO lines (set up so that 1228 * if a GPIO line is in auxfn mode the main GPIO in and out 1229 * track the AFIN and AFOUT lines) 1230 * - Wire the AFOUT for D0 up to either a line from the 1231 * SSI controller that's pulled low around every transmit, 1232 * or at least to an always-0 line here on the board 1233 * - Make the ssd0323 OLED controller chipselect active-low 1234 */ 1235 bus = qdev_get_child_bus(dev, "ssi"); 1236 sddev = ssi_create_peripheral(bus, "ssi-sd"); 1237 1238 dinfo = drive_get(IF_SD, 0, 0); 1239 blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL; 1240 carddev = qdev_new(TYPE_SD_CARD_SPI); 1241 qdev_prop_set_drive_err(carddev, "drive", blk, &error_fatal); 1242 qdev_realize_and_unref(carddev, 1243 qdev_get_child_bus(sddev, "sd-bus"), 1244 &error_fatal); 1245 1246 ssddev = qdev_new("ssd0323"); 1247 qdev_prop_set_uint8(ssddev, "cs", 1); 1248 qdev_realize_and_unref(ssddev, bus, &error_fatal); 1249 1250 gpio_d_splitter = qdev_new(TYPE_SPLIT_IRQ); 1251 qdev_prop_set_uint32(gpio_d_splitter, "num-lines", 2); 1252 qdev_realize_and_unref(gpio_d_splitter, NULL, &error_fatal); 1253 qdev_connect_gpio_out( 1254 gpio_d_splitter, 0, 1255 qdev_get_gpio_in_named(sddev, SSI_GPIO_CS, 0)); 1256 qdev_connect_gpio_out( 1257 gpio_d_splitter, 1, 1258 qdev_get_gpio_in_named(ssddev, SSI_GPIO_CS, 0)); 1259 gpio_out[GPIO_D][0] = qdev_get_gpio_in(gpio_d_splitter, 0); 1260 1261 gpio_out[GPIO_C][7] = qdev_get_gpio_in(ssddev, 0); 1262 1263 /* Make sure the select pin is high. */ 1264 qemu_irq_raise(gpio_out[GPIO_D][0]); 1265 } 1266 } 1267 if (board->dc4 & (1 << 28)) { 1268 DeviceState *enet; 1269 1270 qemu_check_nic_model(&nd_table[0], "stellaris"); 1271 1272 enet = qdev_new("stellaris_enet"); 1273 qdev_set_nic_properties(enet, &nd_table[0]); 1274 sysbus_realize_and_unref(SYS_BUS_DEVICE(enet), &error_fatal); 1275 sysbus_mmio_map(SYS_BUS_DEVICE(enet), 0, 0x40048000); 1276 sysbus_connect_irq(SYS_BUS_DEVICE(enet), 0, qdev_get_gpio_in(nvic, 42)); 1277 } 1278 if (board->peripherals & BP_GAMEPAD) { 1279 QList *gpad_keycode_list = qlist_new(); 1280 static const int gpad_keycode[5] = { 1281 Q_KEY_CODE_UP, Q_KEY_CODE_DOWN, Q_KEY_CODE_LEFT, 1282 Q_KEY_CODE_RIGHT, Q_KEY_CODE_CTRL, 1283 }; 1284 DeviceState *gpad; 1285 1286 gpad = qdev_new(TYPE_STELLARIS_GAMEPAD); 1287 for (i = 0; i < ARRAY_SIZE(gpad_keycode); i++) { 1288 qlist_append_int(gpad_keycode_list, gpad_keycode[i]); 1289 } 1290 qdev_prop_set_array(gpad, "keycodes", gpad_keycode_list); 1291 sysbus_realize_and_unref(SYS_BUS_DEVICE(gpad), &error_fatal); 1292 1293 qdev_connect_gpio_out(gpad, 0, 1294 qemu_irq_invert(gpio_in[GPIO_E][0])); /* up */ 1295 qdev_connect_gpio_out(gpad, 1, 1296 qemu_irq_invert(gpio_in[GPIO_E][1])); /* down */ 1297 qdev_connect_gpio_out(gpad, 2, 1298 qemu_irq_invert(gpio_in[GPIO_E][2])); /* left */ 1299 qdev_connect_gpio_out(gpad, 3, 1300 qemu_irq_invert(gpio_in[GPIO_E][3])); /* right */ 1301 qdev_connect_gpio_out(gpad, 4, 1302 qemu_irq_invert(gpio_in[GPIO_F][1])); /* select */ 1303 } 1304 for (i = 0; i < 7; i++) { 1305 if (board->dc4 & (1 << i)) { 1306 for (j = 0; j < 8; j++) { 1307 if (gpio_out[i][j]) { 1308 qdev_connect_gpio_out(gpio_dev[i], j, gpio_out[i][j]); 1309 } 1310 } 1311 } 1312 } 1313 1314 /* Add dummy regions for the devices we don't implement yet, 1315 * so guest accesses don't cause unlogged crashes. 1316 */ 1317 create_unimplemented_device("i2c-0", 0x40002000, 0x1000); 1318 create_unimplemented_device("i2c-2", 0x40021000, 0x1000); 1319 create_unimplemented_device("PWM", 0x40028000, 0x1000); 1320 create_unimplemented_device("QEI-0", 0x4002c000, 0x1000); 1321 create_unimplemented_device("QEI-1", 0x4002d000, 0x1000); 1322 create_unimplemented_device("analogue-comparator", 0x4003c000, 0x1000); 1323 create_unimplemented_device("hibernation", 0x400fc000, 0x1000); 1324 create_unimplemented_device("flash-control", 0x400fd000, 0x1000); 1325 1326 armv7m_load_kernel(ARM_CPU(first_cpu), ms->kernel_filename, 0, flash_size); 1327 } 1328 1329 /* FIXME: Figure out how to generate these from stellaris_boards. */ 1330 static void lm3s811evb_init(MachineState *machine) 1331 { 1332 stellaris_init(machine, &stellaris_boards[0]); 1333 } 1334 1335 static void lm3s6965evb_init(MachineState *machine) 1336 { 1337 stellaris_init(machine, &stellaris_boards[1]); 1338 } 1339 1340 static void lm3s811evb_class_init(ObjectClass *oc, void *data) 1341 { 1342 MachineClass *mc = MACHINE_CLASS(oc); 1343 1344 mc->desc = "Stellaris LM3S811EVB (Cortex-M3)"; 1345 mc->init = lm3s811evb_init; 1346 mc->ignore_memory_transaction_failures = true; 1347 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3"); 1348 } 1349 1350 static const TypeInfo lm3s811evb_type = { 1351 .name = MACHINE_TYPE_NAME("lm3s811evb"), 1352 .parent = TYPE_MACHINE, 1353 .class_init = lm3s811evb_class_init, 1354 }; 1355 1356 static void lm3s6965evb_class_init(ObjectClass *oc, void *data) 1357 { 1358 MachineClass *mc = MACHINE_CLASS(oc); 1359 1360 mc->desc = "Stellaris LM3S6965EVB (Cortex-M3)"; 1361 mc->init = lm3s6965evb_init; 1362 mc->ignore_memory_transaction_failures = true; 1363 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3"); 1364 } 1365 1366 static const TypeInfo lm3s6965evb_type = { 1367 .name = MACHINE_TYPE_NAME("lm3s6965evb"), 1368 .parent = TYPE_MACHINE, 1369 .class_init = lm3s6965evb_class_init, 1370 }; 1371 1372 static void stellaris_machine_init(void) 1373 { 1374 type_register_static(&lm3s811evb_type); 1375 type_register_static(&lm3s6965evb_type); 1376 } 1377 1378 type_init(stellaris_machine_init) 1379 1380 static void stellaris_i2c_class_init(ObjectClass *klass, void *data) 1381 { 1382 DeviceClass *dc = DEVICE_CLASS(klass); 1383 1384 dc->vmsd = &vmstate_stellaris_i2c; 1385 } 1386 1387 static const TypeInfo stellaris_i2c_info = { 1388 .name = TYPE_STELLARIS_I2C, 1389 .parent = TYPE_SYS_BUS_DEVICE, 1390 .instance_size = sizeof(stellaris_i2c_state), 1391 .instance_init = stellaris_i2c_init, 1392 .class_init = stellaris_i2c_class_init, 1393 }; 1394 1395 static void stellaris_adc_class_init(ObjectClass *klass, void *data) 1396 { 1397 DeviceClass *dc = DEVICE_CLASS(klass); 1398 1399 dc->vmsd = &vmstate_stellaris_adc; 1400 } 1401 1402 static const TypeInfo stellaris_adc_info = { 1403 .name = TYPE_STELLARIS_ADC, 1404 .parent = TYPE_SYS_BUS_DEVICE, 1405 .instance_size = sizeof(StellarisADCState), 1406 .instance_init = stellaris_adc_init, 1407 .class_init = stellaris_adc_class_init, 1408 }; 1409 1410 static void stellaris_sys_class_init(ObjectClass *klass, void *data) 1411 { 1412 DeviceClass *dc = DEVICE_CLASS(klass); 1413 ResettableClass *rc = RESETTABLE_CLASS(klass); 1414 1415 dc->vmsd = &vmstate_stellaris_sys; 1416 rc->phases.enter = stellaris_sys_reset_enter; 1417 rc->phases.hold = stellaris_sys_reset_hold; 1418 rc->phases.exit = stellaris_sys_reset_exit; 1419 device_class_set_props(dc, stellaris_sys_properties); 1420 } 1421 1422 static const TypeInfo stellaris_sys_info = { 1423 .name = TYPE_STELLARIS_SYS, 1424 .parent = TYPE_SYS_BUS_DEVICE, 1425 .instance_size = sizeof(ssys_state), 1426 .instance_init = stellaris_sys_instance_init, 1427 .class_init = stellaris_sys_class_init, 1428 }; 1429 1430 static void stellaris_register_types(void) 1431 { 1432 type_register_static(&stellaris_i2c_info); 1433 type_register_static(&stellaris_adc_info); 1434 type_register_static(&stellaris_sys_info); 1435 } 1436 1437 type_init(stellaris_register_types) 1438