1 /* 2 * Luminary Micro Stellaris peripherals 3 * 4 * Copyright (c) 2006 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qapi/error.h" 12 #include "hw/sysbus.h" 13 #include "hw/ssi/ssi.h" 14 #include "hw/arm/arm.h" 15 #include "hw/devices.h" 16 #include "qemu/timer.h" 17 #include "hw/i2c/i2c.h" 18 #include "net/net.h" 19 #include "hw/boards.h" 20 #include "qemu/log.h" 21 #include "exec/address-spaces.h" 22 #include "sysemu/sysemu.h" 23 #include "hw/char/pl011.h" 24 #include "hw/misc/unimp.h" 25 #include "cpu.h" 26 27 #define GPIO_A 0 28 #define GPIO_B 1 29 #define GPIO_C 2 30 #define GPIO_D 3 31 #define GPIO_E 4 32 #define GPIO_F 5 33 #define GPIO_G 6 34 35 #define BP_OLED_I2C 0x01 36 #define BP_OLED_SSI 0x02 37 #define BP_GAMEPAD 0x04 38 39 #define NUM_IRQ_LINES 64 40 41 typedef const struct { 42 const char *name; 43 uint32_t did0; 44 uint32_t did1; 45 uint32_t dc0; 46 uint32_t dc1; 47 uint32_t dc2; 48 uint32_t dc3; 49 uint32_t dc4; 50 uint32_t peripherals; 51 } stellaris_board_info; 52 53 /* General purpose timer module. */ 54 55 #define TYPE_STELLARIS_GPTM "stellaris-gptm" 56 #define STELLARIS_GPTM(obj) \ 57 OBJECT_CHECK(gptm_state, (obj), TYPE_STELLARIS_GPTM) 58 59 typedef struct gptm_state { 60 SysBusDevice parent_obj; 61 62 MemoryRegion iomem; 63 uint32_t config; 64 uint32_t mode[2]; 65 uint32_t control; 66 uint32_t state; 67 uint32_t mask; 68 uint32_t load[2]; 69 uint32_t match[2]; 70 uint32_t prescale[2]; 71 uint32_t match_prescale[2]; 72 uint32_t rtc; 73 int64_t tick[2]; 74 struct gptm_state *opaque[2]; 75 QEMUTimer *timer[2]; 76 /* The timers have an alternate output used to trigger the ADC. */ 77 qemu_irq trigger; 78 qemu_irq irq; 79 } gptm_state; 80 81 static void gptm_update_irq(gptm_state *s) 82 { 83 int level; 84 level = (s->state & s->mask) != 0; 85 qemu_set_irq(s->irq, level); 86 } 87 88 static void gptm_stop(gptm_state *s, int n) 89 { 90 timer_del(s->timer[n]); 91 } 92 93 static void gptm_reload(gptm_state *s, int n, int reset) 94 { 95 int64_t tick; 96 if (reset) 97 tick = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 98 else 99 tick = s->tick[n]; 100 101 if (s->config == 0) { 102 /* 32-bit CountDown. */ 103 uint32_t count; 104 count = s->load[0] | (s->load[1] << 16); 105 tick += (int64_t)count * system_clock_scale; 106 } else if (s->config == 1) { 107 /* 32-bit RTC. 1Hz tick. */ 108 tick += NANOSECONDS_PER_SECOND; 109 } else if (s->mode[n] == 0xa) { 110 /* PWM mode. Not implemented. */ 111 } else { 112 qemu_log_mask(LOG_UNIMP, 113 "GPTM: 16-bit timer mode unimplemented: 0x%x\n", 114 s->mode[n]); 115 return; 116 } 117 s->tick[n] = tick; 118 timer_mod(s->timer[n], tick); 119 } 120 121 static void gptm_tick(void *opaque) 122 { 123 gptm_state **p = (gptm_state **)opaque; 124 gptm_state *s; 125 int n; 126 127 s = *p; 128 n = p - s->opaque; 129 if (s->config == 0) { 130 s->state |= 1; 131 if ((s->control & 0x20)) { 132 /* Output trigger. */ 133 qemu_irq_pulse(s->trigger); 134 } 135 if (s->mode[0] & 1) { 136 /* One-shot. */ 137 s->control &= ~1; 138 } else { 139 /* Periodic. */ 140 gptm_reload(s, 0, 0); 141 } 142 } else if (s->config == 1) { 143 /* RTC. */ 144 uint32_t match; 145 s->rtc++; 146 match = s->match[0] | (s->match[1] << 16); 147 if (s->rtc > match) 148 s->rtc = 0; 149 if (s->rtc == 0) { 150 s->state |= 8; 151 } 152 gptm_reload(s, 0, 0); 153 } else if (s->mode[n] == 0xa) { 154 /* PWM mode. Not implemented. */ 155 } else { 156 qemu_log_mask(LOG_UNIMP, 157 "GPTM: 16-bit timer mode unimplemented: 0x%x\n", 158 s->mode[n]); 159 } 160 gptm_update_irq(s); 161 } 162 163 static uint64_t gptm_read(void *opaque, hwaddr offset, 164 unsigned size) 165 { 166 gptm_state *s = (gptm_state *)opaque; 167 168 switch (offset) { 169 case 0x00: /* CFG */ 170 return s->config; 171 case 0x04: /* TAMR */ 172 return s->mode[0]; 173 case 0x08: /* TBMR */ 174 return s->mode[1]; 175 case 0x0c: /* CTL */ 176 return s->control; 177 case 0x18: /* IMR */ 178 return s->mask; 179 case 0x1c: /* RIS */ 180 return s->state; 181 case 0x20: /* MIS */ 182 return s->state & s->mask; 183 case 0x24: /* CR */ 184 return 0; 185 case 0x28: /* TAILR */ 186 return s->load[0] | ((s->config < 4) ? (s->load[1] << 16) : 0); 187 case 0x2c: /* TBILR */ 188 return s->load[1]; 189 case 0x30: /* TAMARCHR */ 190 return s->match[0] | ((s->config < 4) ? (s->match[1] << 16) : 0); 191 case 0x34: /* TBMATCHR */ 192 return s->match[1]; 193 case 0x38: /* TAPR */ 194 return s->prescale[0]; 195 case 0x3c: /* TBPR */ 196 return s->prescale[1]; 197 case 0x40: /* TAPMR */ 198 return s->match_prescale[0]; 199 case 0x44: /* TBPMR */ 200 return s->match_prescale[1]; 201 case 0x48: /* TAR */ 202 if (s->config == 1) { 203 return s->rtc; 204 } 205 qemu_log_mask(LOG_UNIMP, 206 "GPTM: read of TAR but timer read not supported"); 207 return 0; 208 case 0x4c: /* TBR */ 209 qemu_log_mask(LOG_UNIMP, 210 "GPTM: read of TBR but timer read not supported"); 211 return 0; 212 default: 213 qemu_log_mask(LOG_GUEST_ERROR, 214 "GPTM: read at bad offset 0x%x\n", (int)offset); 215 return 0; 216 } 217 } 218 219 static void gptm_write(void *opaque, hwaddr offset, 220 uint64_t value, unsigned size) 221 { 222 gptm_state *s = (gptm_state *)opaque; 223 uint32_t oldval; 224 225 /* The timers should be disabled before changing the configuration. 226 We take advantage of this and defer everything until the timer 227 is enabled. */ 228 switch (offset) { 229 case 0x00: /* CFG */ 230 s->config = value; 231 break; 232 case 0x04: /* TAMR */ 233 s->mode[0] = value; 234 break; 235 case 0x08: /* TBMR */ 236 s->mode[1] = value; 237 break; 238 case 0x0c: /* CTL */ 239 oldval = s->control; 240 s->control = value; 241 /* TODO: Implement pause. */ 242 if ((oldval ^ value) & 1) { 243 if (value & 1) { 244 gptm_reload(s, 0, 1); 245 } else { 246 gptm_stop(s, 0); 247 } 248 } 249 if (((oldval ^ value) & 0x100) && s->config >= 4) { 250 if (value & 0x100) { 251 gptm_reload(s, 1, 1); 252 } else { 253 gptm_stop(s, 1); 254 } 255 } 256 break; 257 case 0x18: /* IMR */ 258 s->mask = value & 0x77; 259 gptm_update_irq(s); 260 break; 261 case 0x24: /* CR */ 262 s->state &= ~value; 263 break; 264 case 0x28: /* TAILR */ 265 s->load[0] = value & 0xffff; 266 if (s->config < 4) { 267 s->load[1] = value >> 16; 268 } 269 break; 270 case 0x2c: /* TBILR */ 271 s->load[1] = value & 0xffff; 272 break; 273 case 0x30: /* TAMARCHR */ 274 s->match[0] = value & 0xffff; 275 if (s->config < 4) { 276 s->match[1] = value >> 16; 277 } 278 break; 279 case 0x34: /* TBMATCHR */ 280 s->match[1] = value >> 16; 281 break; 282 case 0x38: /* TAPR */ 283 s->prescale[0] = value; 284 break; 285 case 0x3c: /* TBPR */ 286 s->prescale[1] = value; 287 break; 288 case 0x40: /* TAPMR */ 289 s->match_prescale[0] = value; 290 break; 291 case 0x44: /* TBPMR */ 292 s->match_prescale[0] = value; 293 break; 294 default: 295 qemu_log_mask(LOG_GUEST_ERROR, 296 "GPTM: read at bad offset 0x%x\n", (int)offset); 297 } 298 gptm_update_irq(s); 299 } 300 301 static const MemoryRegionOps gptm_ops = { 302 .read = gptm_read, 303 .write = gptm_write, 304 .endianness = DEVICE_NATIVE_ENDIAN, 305 }; 306 307 static const VMStateDescription vmstate_stellaris_gptm = { 308 .name = "stellaris_gptm", 309 .version_id = 1, 310 .minimum_version_id = 1, 311 .fields = (VMStateField[]) { 312 VMSTATE_UINT32(config, gptm_state), 313 VMSTATE_UINT32_ARRAY(mode, gptm_state, 2), 314 VMSTATE_UINT32(control, gptm_state), 315 VMSTATE_UINT32(state, gptm_state), 316 VMSTATE_UINT32(mask, gptm_state), 317 VMSTATE_UNUSED(8), 318 VMSTATE_UINT32_ARRAY(load, gptm_state, 2), 319 VMSTATE_UINT32_ARRAY(match, gptm_state, 2), 320 VMSTATE_UINT32_ARRAY(prescale, gptm_state, 2), 321 VMSTATE_UINT32_ARRAY(match_prescale, gptm_state, 2), 322 VMSTATE_UINT32(rtc, gptm_state), 323 VMSTATE_INT64_ARRAY(tick, gptm_state, 2), 324 VMSTATE_TIMER_PTR_ARRAY(timer, gptm_state, 2), 325 VMSTATE_END_OF_LIST() 326 } 327 }; 328 329 static void stellaris_gptm_init(Object *obj) 330 { 331 DeviceState *dev = DEVICE(obj); 332 gptm_state *s = STELLARIS_GPTM(obj); 333 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 334 335 sysbus_init_irq(sbd, &s->irq); 336 qdev_init_gpio_out(dev, &s->trigger, 1); 337 338 memory_region_init_io(&s->iomem, obj, &gptm_ops, s, 339 "gptm", 0x1000); 340 sysbus_init_mmio(sbd, &s->iomem); 341 342 s->opaque[0] = s->opaque[1] = s; 343 s->timer[0] = timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque[0]); 344 s->timer[1] = timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque[1]); 345 } 346 347 348 /* System controller. */ 349 350 typedef struct { 351 MemoryRegion iomem; 352 uint32_t pborctl; 353 uint32_t ldopctl; 354 uint32_t int_status; 355 uint32_t int_mask; 356 uint32_t resc; 357 uint32_t rcc; 358 uint32_t rcc2; 359 uint32_t rcgc[3]; 360 uint32_t scgc[3]; 361 uint32_t dcgc[3]; 362 uint32_t clkvclr; 363 uint32_t ldoarst; 364 uint32_t user0; 365 uint32_t user1; 366 qemu_irq irq; 367 stellaris_board_info *board; 368 } ssys_state; 369 370 static void ssys_update(ssys_state *s) 371 { 372 qemu_set_irq(s->irq, (s->int_status & s->int_mask) != 0); 373 } 374 375 static uint32_t pllcfg_sandstorm[16] = { 376 0x31c0, /* 1 Mhz */ 377 0x1ae0, /* 1.8432 Mhz */ 378 0x18c0, /* 2 Mhz */ 379 0xd573, /* 2.4576 Mhz */ 380 0x37a6, /* 3.57954 Mhz */ 381 0x1ae2, /* 3.6864 Mhz */ 382 0x0c40, /* 4 Mhz */ 383 0x98bc, /* 4.906 Mhz */ 384 0x935b, /* 4.9152 Mhz */ 385 0x09c0, /* 5 Mhz */ 386 0x4dee, /* 5.12 Mhz */ 387 0x0c41, /* 6 Mhz */ 388 0x75db, /* 6.144 Mhz */ 389 0x1ae6, /* 7.3728 Mhz */ 390 0x0600, /* 8 Mhz */ 391 0x585b /* 8.192 Mhz */ 392 }; 393 394 static uint32_t pllcfg_fury[16] = { 395 0x3200, /* 1 Mhz */ 396 0x1b20, /* 1.8432 Mhz */ 397 0x1900, /* 2 Mhz */ 398 0xf42b, /* 2.4576 Mhz */ 399 0x37e3, /* 3.57954 Mhz */ 400 0x1b21, /* 3.6864 Mhz */ 401 0x0c80, /* 4 Mhz */ 402 0x98ee, /* 4.906 Mhz */ 403 0xd5b4, /* 4.9152 Mhz */ 404 0x0a00, /* 5 Mhz */ 405 0x4e27, /* 5.12 Mhz */ 406 0x1902, /* 6 Mhz */ 407 0xec1c, /* 6.144 Mhz */ 408 0x1b23, /* 7.3728 Mhz */ 409 0x0640, /* 8 Mhz */ 410 0xb11c /* 8.192 Mhz */ 411 }; 412 413 #define DID0_VER_MASK 0x70000000 414 #define DID0_VER_0 0x00000000 415 #define DID0_VER_1 0x10000000 416 417 #define DID0_CLASS_MASK 0x00FF0000 418 #define DID0_CLASS_SANDSTORM 0x00000000 419 #define DID0_CLASS_FURY 0x00010000 420 421 static int ssys_board_class(const ssys_state *s) 422 { 423 uint32_t did0 = s->board->did0; 424 switch (did0 & DID0_VER_MASK) { 425 case DID0_VER_0: 426 return DID0_CLASS_SANDSTORM; 427 case DID0_VER_1: 428 switch (did0 & DID0_CLASS_MASK) { 429 case DID0_CLASS_SANDSTORM: 430 case DID0_CLASS_FURY: 431 return did0 & DID0_CLASS_MASK; 432 } 433 /* for unknown classes, fall through */ 434 default: 435 /* This can only happen if the hardwired constant did0 value 436 * in this board's stellaris_board_info struct is wrong. 437 */ 438 g_assert_not_reached(); 439 } 440 } 441 442 static uint64_t ssys_read(void *opaque, hwaddr offset, 443 unsigned size) 444 { 445 ssys_state *s = (ssys_state *)opaque; 446 447 switch (offset) { 448 case 0x000: /* DID0 */ 449 return s->board->did0; 450 case 0x004: /* DID1 */ 451 return s->board->did1; 452 case 0x008: /* DC0 */ 453 return s->board->dc0; 454 case 0x010: /* DC1 */ 455 return s->board->dc1; 456 case 0x014: /* DC2 */ 457 return s->board->dc2; 458 case 0x018: /* DC3 */ 459 return s->board->dc3; 460 case 0x01c: /* DC4 */ 461 return s->board->dc4; 462 case 0x030: /* PBORCTL */ 463 return s->pborctl; 464 case 0x034: /* LDOPCTL */ 465 return s->ldopctl; 466 case 0x040: /* SRCR0 */ 467 return 0; 468 case 0x044: /* SRCR1 */ 469 return 0; 470 case 0x048: /* SRCR2 */ 471 return 0; 472 case 0x050: /* RIS */ 473 return s->int_status; 474 case 0x054: /* IMC */ 475 return s->int_mask; 476 case 0x058: /* MISC */ 477 return s->int_status & s->int_mask; 478 case 0x05c: /* RESC */ 479 return s->resc; 480 case 0x060: /* RCC */ 481 return s->rcc; 482 case 0x064: /* PLLCFG */ 483 { 484 int xtal; 485 xtal = (s->rcc >> 6) & 0xf; 486 switch (ssys_board_class(s)) { 487 case DID0_CLASS_FURY: 488 return pllcfg_fury[xtal]; 489 case DID0_CLASS_SANDSTORM: 490 return pllcfg_sandstorm[xtal]; 491 default: 492 g_assert_not_reached(); 493 } 494 } 495 case 0x070: /* RCC2 */ 496 return s->rcc2; 497 case 0x100: /* RCGC0 */ 498 return s->rcgc[0]; 499 case 0x104: /* RCGC1 */ 500 return s->rcgc[1]; 501 case 0x108: /* RCGC2 */ 502 return s->rcgc[2]; 503 case 0x110: /* SCGC0 */ 504 return s->scgc[0]; 505 case 0x114: /* SCGC1 */ 506 return s->scgc[1]; 507 case 0x118: /* SCGC2 */ 508 return s->scgc[2]; 509 case 0x120: /* DCGC0 */ 510 return s->dcgc[0]; 511 case 0x124: /* DCGC1 */ 512 return s->dcgc[1]; 513 case 0x128: /* DCGC2 */ 514 return s->dcgc[2]; 515 case 0x150: /* CLKVCLR */ 516 return s->clkvclr; 517 case 0x160: /* LDOARST */ 518 return s->ldoarst; 519 case 0x1e0: /* USER0 */ 520 return s->user0; 521 case 0x1e4: /* USER1 */ 522 return s->user1; 523 default: 524 qemu_log_mask(LOG_GUEST_ERROR, 525 "SSYS: read at bad offset 0x%x\n", (int)offset); 526 return 0; 527 } 528 } 529 530 static bool ssys_use_rcc2(ssys_state *s) 531 { 532 return (s->rcc2 >> 31) & 0x1; 533 } 534 535 /* 536 * Caculate the sys. clock period in ms. 537 */ 538 static void ssys_calculate_system_clock(ssys_state *s) 539 { 540 if (ssys_use_rcc2(s)) { 541 system_clock_scale = 5 * (((s->rcc2 >> 23) & 0x3f) + 1); 542 } else { 543 system_clock_scale = 5 * (((s->rcc >> 23) & 0xf) + 1); 544 } 545 } 546 547 static void ssys_write(void *opaque, hwaddr offset, 548 uint64_t value, unsigned size) 549 { 550 ssys_state *s = (ssys_state *)opaque; 551 552 switch (offset) { 553 case 0x030: /* PBORCTL */ 554 s->pborctl = value & 0xffff; 555 break; 556 case 0x034: /* LDOPCTL */ 557 s->ldopctl = value & 0x1f; 558 break; 559 case 0x040: /* SRCR0 */ 560 case 0x044: /* SRCR1 */ 561 case 0x048: /* SRCR2 */ 562 fprintf(stderr, "Peripheral reset not implemented\n"); 563 break; 564 case 0x054: /* IMC */ 565 s->int_mask = value & 0x7f; 566 break; 567 case 0x058: /* MISC */ 568 s->int_status &= ~value; 569 break; 570 case 0x05c: /* RESC */ 571 s->resc = value & 0x3f; 572 break; 573 case 0x060: /* RCC */ 574 if ((s->rcc & (1 << 13)) != 0 && (value & (1 << 13)) == 0) { 575 /* PLL enable. */ 576 s->int_status |= (1 << 6); 577 } 578 s->rcc = value; 579 ssys_calculate_system_clock(s); 580 break; 581 case 0x070: /* RCC2 */ 582 if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) { 583 break; 584 } 585 586 if ((s->rcc2 & (1 << 13)) != 0 && (value & (1 << 13)) == 0) { 587 /* PLL enable. */ 588 s->int_status |= (1 << 6); 589 } 590 s->rcc2 = value; 591 ssys_calculate_system_clock(s); 592 break; 593 case 0x100: /* RCGC0 */ 594 s->rcgc[0] = value; 595 break; 596 case 0x104: /* RCGC1 */ 597 s->rcgc[1] = value; 598 break; 599 case 0x108: /* RCGC2 */ 600 s->rcgc[2] = value; 601 break; 602 case 0x110: /* SCGC0 */ 603 s->scgc[0] = value; 604 break; 605 case 0x114: /* SCGC1 */ 606 s->scgc[1] = value; 607 break; 608 case 0x118: /* SCGC2 */ 609 s->scgc[2] = value; 610 break; 611 case 0x120: /* DCGC0 */ 612 s->dcgc[0] = value; 613 break; 614 case 0x124: /* DCGC1 */ 615 s->dcgc[1] = value; 616 break; 617 case 0x128: /* DCGC2 */ 618 s->dcgc[2] = value; 619 break; 620 case 0x150: /* CLKVCLR */ 621 s->clkvclr = value; 622 break; 623 case 0x160: /* LDOARST */ 624 s->ldoarst = value; 625 break; 626 default: 627 qemu_log_mask(LOG_GUEST_ERROR, 628 "SSYS: write at bad offset 0x%x\n", (int)offset); 629 } 630 ssys_update(s); 631 } 632 633 static const MemoryRegionOps ssys_ops = { 634 .read = ssys_read, 635 .write = ssys_write, 636 .endianness = DEVICE_NATIVE_ENDIAN, 637 }; 638 639 static void ssys_reset(void *opaque) 640 { 641 ssys_state *s = (ssys_state *)opaque; 642 643 s->pborctl = 0x7ffd; 644 s->rcc = 0x078e3ac0; 645 646 if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) { 647 s->rcc2 = 0; 648 } else { 649 s->rcc2 = 0x07802810; 650 } 651 s->rcgc[0] = 1; 652 s->scgc[0] = 1; 653 s->dcgc[0] = 1; 654 ssys_calculate_system_clock(s); 655 } 656 657 static int stellaris_sys_post_load(void *opaque, int version_id) 658 { 659 ssys_state *s = opaque; 660 661 ssys_calculate_system_clock(s); 662 663 return 0; 664 } 665 666 static const VMStateDescription vmstate_stellaris_sys = { 667 .name = "stellaris_sys", 668 .version_id = 2, 669 .minimum_version_id = 1, 670 .post_load = stellaris_sys_post_load, 671 .fields = (VMStateField[]) { 672 VMSTATE_UINT32(pborctl, ssys_state), 673 VMSTATE_UINT32(ldopctl, ssys_state), 674 VMSTATE_UINT32(int_mask, ssys_state), 675 VMSTATE_UINT32(int_status, ssys_state), 676 VMSTATE_UINT32(resc, ssys_state), 677 VMSTATE_UINT32(rcc, ssys_state), 678 VMSTATE_UINT32_V(rcc2, ssys_state, 2), 679 VMSTATE_UINT32_ARRAY(rcgc, ssys_state, 3), 680 VMSTATE_UINT32_ARRAY(scgc, ssys_state, 3), 681 VMSTATE_UINT32_ARRAY(dcgc, ssys_state, 3), 682 VMSTATE_UINT32(clkvclr, ssys_state), 683 VMSTATE_UINT32(ldoarst, ssys_state), 684 VMSTATE_END_OF_LIST() 685 } 686 }; 687 688 static int stellaris_sys_init(uint32_t base, qemu_irq irq, 689 stellaris_board_info * board, 690 uint8_t *macaddr) 691 { 692 ssys_state *s; 693 694 s = g_new0(ssys_state, 1); 695 s->irq = irq; 696 s->board = board; 697 /* Most devices come preprogrammed with a MAC address in the user data. */ 698 s->user0 = macaddr[0] | (macaddr[1] << 8) | (macaddr[2] << 16); 699 s->user1 = macaddr[3] | (macaddr[4] << 8) | (macaddr[5] << 16); 700 701 memory_region_init_io(&s->iomem, NULL, &ssys_ops, s, "ssys", 0x00001000); 702 memory_region_add_subregion(get_system_memory(), base, &s->iomem); 703 ssys_reset(s); 704 vmstate_register(NULL, -1, &vmstate_stellaris_sys, s); 705 return 0; 706 } 707 708 709 /* I2C controller. */ 710 711 #define TYPE_STELLARIS_I2C "stellaris-i2c" 712 #define STELLARIS_I2C(obj) \ 713 OBJECT_CHECK(stellaris_i2c_state, (obj), TYPE_STELLARIS_I2C) 714 715 typedef struct { 716 SysBusDevice parent_obj; 717 718 I2CBus *bus; 719 qemu_irq irq; 720 MemoryRegion iomem; 721 uint32_t msa; 722 uint32_t mcs; 723 uint32_t mdr; 724 uint32_t mtpr; 725 uint32_t mimr; 726 uint32_t mris; 727 uint32_t mcr; 728 } stellaris_i2c_state; 729 730 #define STELLARIS_I2C_MCS_BUSY 0x01 731 #define STELLARIS_I2C_MCS_ERROR 0x02 732 #define STELLARIS_I2C_MCS_ADRACK 0x04 733 #define STELLARIS_I2C_MCS_DATACK 0x08 734 #define STELLARIS_I2C_MCS_ARBLST 0x10 735 #define STELLARIS_I2C_MCS_IDLE 0x20 736 #define STELLARIS_I2C_MCS_BUSBSY 0x40 737 738 static uint64_t stellaris_i2c_read(void *opaque, hwaddr offset, 739 unsigned size) 740 { 741 stellaris_i2c_state *s = (stellaris_i2c_state *)opaque; 742 743 switch (offset) { 744 case 0x00: /* MSA */ 745 return s->msa; 746 case 0x04: /* MCS */ 747 /* We don't emulate timing, so the controller is never busy. */ 748 return s->mcs | STELLARIS_I2C_MCS_IDLE; 749 case 0x08: /* MDR */ 750 return s->mdr; 751 case 0x0c: /* MTPR */ 752 return s->mtpr; 753 case 0x10: /* MIMR */ 754 return s->mimr; 755 case 0x14: /* MRIS */ 756 return s->mris; 757 case 0x18: /* MMIS */ 758 return s->mris & s->mimr; 759 case 0x20: /* MCR */ 760 return s->mcr; 761 default: 762 qemu_log_mask(LOG_GUEST_ERROR, 763 "stellaris_i2c: read at bad offset 0x%x\n", (int)offset); 764 return 0; 765 } 766 } 767 768 static void stellaris_i2c_update(stellaris_i2c_state *s) 769 { 770 int level; 771 772 level = (s->mris & s->mimr) != 0; 773 qemu_set_irq(s->irq, level); 774 } 775 776 static void stellaris_i2c_write(void *opaque, hwaddr offset, 777 uint64_t value, unsigned size) 778 { 779 stellaris_i2c_state *s = (stellaris_i2c_state *)opaque; 780 781 switch (offset) { 782 case 0x00: /* MSA */ 783 s->msa = value & 0xff; 784 break; 785 case 0x04: /* MCS */ 786 if ((s->mcr & 0x10) == 0) { 787 /* Disabled. Do nothing. */ 788 break; 789 } 790 /* Grab the bus if this is starting a transfer. */ 791 if ((value & 2) && (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) { 792 if (i2c_start_transfer(s->bus, s->msa >> 1, s->msa & 1)) { 793 s->mcs |= STELLARIS_I2C_MCS_ARBLST; 794 } else { 795 s->mcs &= ~STELLARIS_I2C_MCS_ARBLST; 796 s->mcs |= STELLARIS_I2C_MCS_BUSBSY; 797 } 798 } 799 /* If we don't have the bus then indicate an error. */ 800 if (!i2c_bus_busy(s->bus) 801 || (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) { 802 s->mcs |= STELLARIS_I2C_MCS_ERROR; 803 break; 804 } 805 s->mcs &= ~STELLARIS_I2C_MCS_ERROR; 806 if (value & 1) { 807 /* Transfer a byte. */ 808 /* TODO: Handle errors. */ 809 if (s->msa & 1) { 810 /* Recv */ 811 s->mdr = i2c_recv(s->bus) & 0xff; 812 } else { 813 /* Send */ 814 i2c_send(s->bus, s->mdr); 815 } 816 /* Raise an interrupt. */ 817 s->mris |= 1; 818 } 819 if (value & 4) { 820 /* Finish transfer. */ 821 i2c_end_transfer(s->bus); 822 s->mcs &= ~STELLARIS_I2C_MCS_BUSBSY; 823 } 824 break; 825 case 0x08: /* MDR */ 826 s->mdr = value & 0xff; 827 break; 828 case 0x0c: /* MTPR */ 829 s->mtpr = value & 0xff; 830 break; 831 case 0x10: /* MIMR */ 832 s->mimr = 1; 833 break; 834 case 0x1c: /* MICR */ 835 s->mris &= ~value; 836 break; 837 case 0x20: /* MCR */ 838 if (value & 1) { 839 qemu_log_mask(LOG_UNIMP, "stellaris_i2c: Loopback not implemented"); 840 } 841 if (value & 0x20) { 842 qemu_log_mask(LOG_UNIMP, 843 "stellaris_i2c: Slave mode not implemented"); 844 } 845 s->mcr = value & 0x31; 846 break; 847 default: 848 qemu_log_mask(LOG_GUEST_ERROR, 849 "stellaris_i2c: write at bad offset 0x%x\n", (int)offset); 850 } 851 stellaris_i2c_update(s); 852 } 853 854 static void stellaris_i2c_reset(stellaris_i2c_state *s) 855 { 856 if (s->mcs & STELLARIS_I2C_MCS_BUSBSY) 857 i2c_end_transfer(s->bus); 858 859 s->msa = 0; 860 s->mcs = 0; 861 s->mdr = 0; 862 s->mtpr = 1; 863 s->mimr = 0; 864 s->mris = 0; 865 s->mcr = 0; 866 stellaris_i2c_update(s); 867 } 868 869 static const MemoryRegionOps stellaris_i2c_ops = { 870 .read = stellaris_i2c_read, 871 .write = stellaris_i2c_write, 872 .endianness = DEVICE_NATIVE_ENDIAN, 873 }; 874 875 static const VMStateDescription vmstate_stellaris_i2c = { 876 .name = "stellaris_i2c", 877 .version_id = 1, 878 .minimum_version_id = 1, 879 .fields = (VMStateField[]) { 880 VMSTATE_UINT32(msa, stellaris_i2c_state), 881 VMSTATE_UINT32(mcs, stellaris_i2c_state), 882 VMSTATE_UINT32(mdr, stellaris_i2c_state), 883 VMSTATE_UINT32(mtpr, stellaris_i2c_state), 884 VMSTATE_UINT32(mimr, stellaris_i2c_state), 885 VMSTATE_UINT32(mris, stellaris_i2c_state), 886 VMSTATE_UINT32(mcr, stellaris_i2c_state), 887 VMSTATE_END_OF_LIST() 888 } 889 }; 890 891 static void stellaris_i2c_init(Object *obj) 892 { 893 DeviceState *dev = DEVICE(obj); 894 stellaris_i2c_state *s = STELLARIS_I2C(obj); 895 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 896 I2CBus *bus; 897 898 sysbus_init_irq(sbd, &s->irq); 899 bus = i2c_init_bus(dev, "i2c"); 900 s->bus = bus; 901 902 memory_region_init_io(&s->iomem, obj, &stellaris_i2c_ops, s, 903 "i2c", 0x1000); 904 sysbus_init_mmio(sbd, &s->iomem); 905 /* ??? For now we only implement the master interface. */ 906 stellaris_i2c_reset(s); 907 } 908 909 /* Analogue to Digital Converter. This is only partially implemented, 910 enough for applications that use a combined ADC and timer tick. */ 911 912 #define STELLARIS_ADC_EM_CONTROLLER 0 913 #define STELLARIS_ADC_EM_COMP 1 914 #define STELLARIS_ADC_EM_EXTERNAL 4 915 #define STELLARIS_ADC_EM_TIMER 5 916 #define STELLARIS_ADC_EM_PWM0 6 917 #define STELLARIS_ADC_EM_PWM1 7 918 #define STELLARIS_ADC_EM_PWM2 8 919 920 #define STELLARIS_ADC_FIFO_EMPTY 0x0100 921 #define STELLARIS_ADC_FIFO_FULL 0x1000 922 923 #define TYPE_STELLARIS_ADC "stellaris-adc" 924 #define STELLARIS_ADC(obj) \ 925 OBJECT_CHECK(stellaris_adc_state, (obj), TYPE_STELLARIS_ADC) 926 927 typedef struct StellarisADCState { 928 SysBusDevice parent_obj; 929 930 MemoryRegion iomem; 931 uint32_t actss; 932 uint32_t ris; 933 uint32_t im; 934 uint32_t emux; 935 uint32_t ostat; 936 uint32_t ustat; 937 uint32_t sspri; 938 uint32_t sac; 939 struct { 940 uint32_t state; 941 uint32_t data[16]; 942 } fifo[4]; 943 uint32_t ssmux[4]; 944 uint32_t ssctl[4]; 945 uint32_t noise; 946 qemu_irq irq[4]; 947 } stellaris_adc_state; 948 949 static uint32_t stellaris_adc_fifo_read(stellaris_adc_state *s, int n) 950 { 951 int tail; 952 953 tail = s->fifo[n].state & 0xf; 954 if (s->fifo[n].state & STELLARIS_ADC_FIFO_EMPTY) { 955 s->ustat |= 1 << n; 956 } else { 957 s->fifo[n].state = (s->fifo[n].state & ~0xf) | ((tail + 1) & 0xf); 958 s->fifo[n].state &= ~STELLARIS_ADC_FIFO_FULL; 959 if (tail + 1 == ((s->fifo[n].state >> 4) & 0xf)) 960 s->fifo[n].state |= STELLARIS_ADC_FIFO_EMPTY; 961 } 962 return s->fifo[n].data[tail]; 963 } 964 965 static void stellaris_adc_fifo_write(stellaris_adc_state *s, int n, 966 uint32_t value) 967 { 968 int head; 969 970 /* TODO: Real hardware has limited size FIFOs. We have a full 16 entry 971 FIFO fir each sequencer. */ 972 head = (s->fifo[n].state >> 4) & 0xf; 973 if (s->fifo[n].state & STELLARIS_ADC_FIFO_FULL) { 974 s->ostat |= 1 << n; 975 return; 976 } 977 s->fifo[n].data[head] = value; 978 head = (head + 1) & 0xf; 979 s->fifo[n].state &= ~STELLARIS_ADC_FIFO_EMPTY; 980 s->fifo[n].state = (s->fifo[n].state & ~0xf0) | (head << 4); 981 if ((s->fifo[n].state & 0xf) == head) 982 s->fifo[n].state |= STELLARIS_ADC_FIFO_FULL; 983 } 984 985 static void stellaris_adc_update(stellaris_adc_state *s) 986 { 987 int level; 988 int n; 989 990 for (n = 0; n < 4; n++) { 991 level = (s->ris & s->im & (1 << n)) != 0; 992 qemu_set_irq(s->irq[n], level); 993 } 994 } 995 996 static void stellaris_adc_trigger(void *opaque, int irq, int level) 997 { 998 stellaris_adc_state *s = (stellaris_adc_state *)opaque; 999 int n; 1000 1001 for (n = 0; n < 4; n++) { 1002 if ((s->actss & (1 << n)) == 0) { 1003 continue; 1004 } 1005 1006 if (((s->emux >> (n * 4)) & 0xff) != 5) { 1007 continue; 1008 } 1009 1010 /* Some applications use the ADC as a random number source, so introduce 1011 some variation into the signal. */ 1012 s->noise = s->noise * 314159 + 1; 1013 /* ??? actual inputs not implemented. Return an arbitrary value. */ 1014 stellaris_adc_fifo_write(s, n, 0x200 + ((s->noise >> 16) & 7)); 1015 s->ris |= (1 << n); 1016 stellaris_adc_update(s); 1017 } 1018 } 1019 1020 static void stellaris_adc_reset(stellaris_adc_state *s) 1021 { 1022 int n; 1023 1024 for (n = 0; n < 4; n++) { 1025 s->ssmux[n] = 0; 1026 s->ssctl[n] = 0; 1027 s->fifo[n].state = STELLARIS_ADC_FIFO_EMPTY; 1028 } 1029 } 1030 1031 static uint64_t stellaris_adc_read(void *opaque, hwaddr offset, 1032 unsigned size) 1033 { 1034 stellaris_adc_state *s = (stellaris_adc_state *)opaque; 1035 1036 /* TODO: Implement this. */ 1037 if (offset >= 0x40 && offset < 0xc0) { 1038 int n; 1039 n = (offset - 0x40) >> 5; 1040 switch (offset & 0x1f) { 1041 case 0x00: /* SSMUX */ 1042 return s->ssmux[n]; 1043 case 0x04: /* SSCTL */ 1044 return s->ssctl[n]; 1045 case 0x08: /* SSFIFO */ 1046 return stellaris_adc_fifo_read(s, n); 1047 case 0x0c: /* SSFSTAT */ 1048 return s->fifo[n].state; 1049 default: 1050 break; 1051 } 1052 } 1053 switch (offset) { 1054 case 0x00: /* ACTSS */ 1055 return s->actss; 1056 case 0x04: /* RIS */ 1057 return s->ris; 1058 case 0x08: /* IM */ 1059 return s->im; 1060 case 0x0c: /* ISC */ 1061 return s->ris & s->im; 1062 case 0x10: /* OSTAT */ 1063 return s->ostat; 1064 case 0x14: /* EMUX */ 1065 return s->emux; 1066 case 0x18: /* USTAT */ 1067 return s->ustat; 1068 case 0x20: /* SSPRI */ 1069 return s->sspri; 1070 case 0x30: /* SAC */ 1071 return s->sac; 1072 default: 1073 qemu_log_mask(LOG_GUEST_ERROR, 1074 "stellaris_adc: read at bad offset 0x%x\n", (int)offset); 1075 return 0; 1076 } 1077 } 1078 1079 static void stellaris_adc_write(void *opaque, hwaddr offset, 1080 uint64_t value, unsigned size) 1081 { 1082 stellaris_adc_state *s = (stellaris_adc_state *)opaque; 1083 1084 /* TODO: Implement this. */ 1085 if (offset >= 0x40 && offset < 0xc0) { 1086 int n; 1087 n = (offset - 0x40) >> 5; 1088 switch (offset & 0x1f) { 1089 case 0x00: /* SSMUX */ 1090 s->ssmux[n] = value & 0x33333333; 1091 return; 1092 case 0x04: /* SSCTL */ 1093 if (value != 6) { 1094 qemu_log_mask(LOG_UNIMP, 1095 "ADC: Unimplemented sequence %" PRIx64 "\n", 1096 value); 1097 } 1098 s->ssctl[n] = value; 1099 return; 1100 default: 1101 break; 1102 } 1103 } 1104 switch (offset) { 1105 case 0x00: /* ACTSS */ 1106 s->actss = value & 0xf; 1107 break; 1108 case 0x08: /* IM */ 1109 s->im = value; 1110 break; 1111 case 0x0c: /* ISC */ 1112 s->ris &= ~value; 1113 break; 1114 case 0x10: /* OSTAT */ 1115 s->ostat &= ~value; 1116 break; 1117 case 0x14: /* EMUX */ 1118 s->emux = value; 1119 break; 1120 case 0x18: /* USTAT */ 1121 s->ustat &= ~value; 1122 break; 1123 case 0x20: /* SSPRI */ 1124 s->sspri = value; 1125 break; 1126 case 0x28: /* PSSI */ 1127 qemu_log_mask(LOG_UNIMP, "ADC: sample initiate unimplemented"); 1128 break; 1129 case 0x30: /* SAC */ 1130 s->sac = value; 1131 break; 1132 default: 1133 qemu_log_mask(LOG_GUEST_ERROR, 1134 "stellaris_adc: write at bad offset 0x%x\n", (int)offset); 1135 } 1136 stellaris_adc_update(s); 1137 } 1138 1139 static const MemoryRegionOps stellaris_adc_ops = { 1140 .read = stellaris_adc_read, 1141 .write = stellaris_adc_write, 1142 .endianness = DEVICE_NATIVE_ENDIAN, 1143 }; 1144 1145 static const VMStateDescription vmstate_stellaris_adc = { 1146 .name = "stellaris_adc", 1147 .version_id = 1, 1148 .minimum_version_id = 1, 1149 .fields = (VMStateField[]) { 1150 VMSTATE_UINT32(actss, stellaris_adc_state), 1151 VMSTATE_UINT32(ris, stellaris_adc_state), 1152 VMSTATE_UINT32(im, stellaris_adc_state), 1153 VMSTATE_UINT32(emux, stellaris_adc_state), 1154 VMSTATE_UINT32(ostat, stellaris_adc_state), 1155 VMSTATE_UINT32(ustat, stellaris_adc_state), 1156 VMSTATE_UINT32(sspri, stellaris_adc_state), 1157 VMSTATE_UINT32(sac, stellaris_adc_state), 1158 VMSTATE_UINT32(fifo[0].state, stellaris_adc_state), 1159 VMSTATE_UINT32_ARRAY(fifo[0].data, stellaris_adc_state, 16), 1160 VMSTATE_UINT32(ssmux[0], stellaris_adc_state), 1161 VMSTATE_UINT32(ssctl[0], stellaris_adc_state), 1162 VMSTATE_UINT32(fifo[1].state, stellaris_adc_state), 1163 VMSTATE_UINT32_ARRAY(fifo[1].data, stellaris_adc_state, 16), 1164 VMSTATE_UINT32(ssmux[1], stellaris_adc_state), 1165 VMSTATE_UINT32(ssctl[1], stellaris_adc_state), 1166 VMSTATE_UINT32(fifo[2].state, stellaris_adc_state), 1167 VMSTATE_UINT32_ARRAY(fifo[2].data, stellaris_adc_state, 16), 1168 VMSTATE_UINT32(ssmux[2], stellaris_adc_state), 1169 VMSTATE_UINT32(ssctl[2], stellaris_adc_state), 1170 VMSTATE_UINT32(fifo[3].state, stellaris_adc_state), 1171 VMSTATE_UINT32_ARRAY(fifo[3].data, stellaris_adc_state, 16), 1172 VMSTATE_UINT32(ssmux[3], stellaris_adc_state), 1173 VMSTATE_UINT32(ssctl[3], stellaris_adc_state), 1174 VMSTATE_UINT32(noise, stellaris_adc_state), 1175 VMSTATE_END_OF_LIST() 1176 } 1177 }; 1178 1179 static void stellaris_adc_init(Object *obj) 1180 { 1181 DeviceState *dev = DEVICE(obj); 1182 stellaris_adc_state *s = STELLARIS_ADC(obj); 1183 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 1184 int n; 1185 1186 for (n = 0; n < 4; n++) { 1187 sysbus_init_irq(sbd, &s->irq[n]); 1188 } 1189 1190 memory_region_init_io(&s->iomem, obj, &stellaris_adc_ops, s, 1191 "adc", 0x1000); 1192 sysbus_init_mmio(sbd, &s->iomem); 1193 stellaris_adc_reset(s); 1194 qdev_init_gpio_in(dev, stellaris_adc_trigger, 1); 1195 } 1196 1197 static 1198 void do_sys_reset(void *opaque, int n, int level) 1199 { 1200 if (level) { 1201 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 1202 } 1203 } 1204 1205 /* Board init. */ 1206 static stellaris_board_info stellaris_boards[] = { 1207 { "LM3S811EVB", 1208 0, 1209 0x0032000e, 1210 0x001f001f, /* dc0 */ 1211 0x001132bf, 1212 0x01071013, 1213 0x3f0f01ff, 1214 0x0000001f, 1215 BP_OLED_I2C 1216 }, 1217 { "LM3S6965EVB", 1218 0x10010002, 1219 0x1073402e, 1220 0x00ff007f, /* dc0 */ 1221 0x001133ff, 1222 0x030f5317, 1223 0x0f0f87ff, 1224 0x5000007f, 1225 BP_OLED_SSI | BP_GAMEPAD 1226 } 1227 }; 1228 1229 static void stellaris_init(MachineState *ms, stellaris_board_info *board) 1230 { 1231 static const int uart_irq[] = {5, 6, 33, 34}; 1232 static const int timer_irq[] = {19, 21, 23, 35}; 1233 static const uint32_t gpio_addr[7] = 1234 { 0x40004000, 0x40005000, 0x40006000, 0x40007000, 1235 0x40024000, 0x40025000, 0x40026000}; 1236 static const int gpio_irq[7] = {0, 1, 2, 3, 4, 30, 31}; 1237 1238 /* Memory map of SoC devices, from 1239 * Stellaris LM3S6965 Microcontroller Data Sheet (rev I) 1240 * http://www.ti.com/lit/ds/symlink/lm3s6965.pdf 1241 * 1242 * 40000000 wdtimer (unimplemented) 1243 * 40002000 i2c (unimplemented) 1244 * 40004000 GPIO 1245 * 40005000 GPIO 1246 * 40006000 GPIO 1247 * 40007000 GPIO 1248 * 40008000 SSI 1249 * 4000c000 UART 1250 * 4000d000 UART 1251 * 4000e000 UART 1252 * 40020000 i2c 1253 * 40021000 i2c (unimplemented) 1254 * 40024000 GPIO 1255 * 40025000 GPIO 1256 * 40026000 GPIO 1257 * 40028000 PWM (unimplemented) 1258 * 4002c000 QEI (unimplemented) 1259 * 4002d000 QEI (unimplemented) 1260 * 40030000 gptimer 1261 * 40031000 gptimer 1262 * 40032000 gptimer 1263 * 40033000 gptimer 1264 * 40038000 ADC 1265 * 4003c000 analogue comparator (unimplemented) 1266 * 40048000 ethernet 1267 * 400fc000 hibernation module (unimplemented) 1268 * 400fd000 flash memory control (unimplemented) 1269 * 400fe000 system control 1270 */ 1271 1272 DeviceState *gpio_dev[7], *nvic; 1273 qemu_irq gpio_in[7][8]; 1274 qemu_irq gpio_out[7][8]; 1275 qemu_irq adc; 1276 int sram_size; 1277 int flash_size; 1278 I2CBus *i2c; 1279 DeviceState *dev; 1280 int i; 1281 int j; 1282 1283 MemoryRegion *sram = g_new(MemoryRegion, 1); 1284 MemoryRegion *flash = g_new(MemoryRegion, 1); 1285 MemoryRegion *system_memory = get_system_memory(); 1286 1287 flash_size = (((board->dc0 & 0xffff) + 1) << 1) * 1024; 1288 sram_size = ((board->dc0 >> 18) + 1) * 1024; 1289 1290 /* Flash programming is done via the SCU, so pretend it is ROM. */ 1291 memory_region_init_ram(flash, NULL, "stellaris.flash", flash_size, 1292 &error_fatal); 1293 memory_region_set_readonly(flash, true); 1294 memory_region_add_subregion(system_memory, 0, flash); 1295 1296 memory_region_init_ram(sram, NULL, "stellaris.sram", sram_size, 1297 &error_fatal); 1298 memory_region_add_subregion(system_memory, 0x20000000, sram); 1299 1300 nvic = armv7m_init(system_memory, flash_size, NUM_IRQ_LINES, 1301 ms->kernel_filename, ms->cpu_type); 1302 1303 qdev_connect_gpio_out_named(nvic, "SYSRESETREQ", 0, 1304 qemu_allocate_irq(&do_sys_reset, NULL, 0)); 1305 1306 if (board->dc1 & (1 << 16)) { 1307 dev = sysbus_create_varargs(TYPE_STELLARIS_ADC, 0x40038000, 1308 qdev_get_gpio_in(nvic, 14), 1309 qdev_get_gpio_in(nvic, 15), 1310 qdev_get_gpio_in(nvic, 16), 1311 qdev_get_gpio_in(nvic, 17), 1312 NULL); 1313 adc = qdev_get_gpio_in(dev, 0); 1314 } else { 1315 adc = NULL; 1316 } 1317 for (i = 0; i < 4; i++) { 1318 if (board->dc2 & (0x10000 << i)) { 1319 dev = sysbus_create_simple(TYPE_STELLARIS_GPTM, 1320 0x40030000 + i * 0x1000, 1321 qdev_get_gpio_in(nvic, timer_irq[i])); 1322 /* TODO: This is incorrect, but we get away with it because 1323 the ADC output is only ever pulsed. */ 1324 qdev_connect_gpio_out(dev, 0, adc); 1325 } 1326 } 1327 1328 stellaris_sys_init(0x400fe000, qdev_get_gpio_in(nvic, 28), 1329 board, nd_table[0].macaddr.a); 1330 1331 for (i = 0; i < 7; i++) { 1332 if (board->dc4 & (1 << i)) { 1333 gpio_dev[i] = sysbus_create_simple("pl061_luminary", gpio_addr[i], 1334 qdev_get_gpio_in(nvic, 1335 gpio_irq[i])); 1336 for (j = 0; j < 8; j++) { 1337 gpio_in[i][j] = qdev_get_gpio_in(gpio_dev[i], j); 1338 gpio_out[i][j] = NULL; 1339 } 1340 } 1341 } 1342 1343 if (board->dc2 & (1 << 12)) { 1344 dev = sysbus_create_simple(TYPE_STELLARIS_I2C, 0x40020000, 1345 qdev_get_gpio_in(nvic, 8)); 1346 i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c"); 1347 if (board->peripherals & BP_OLED_I2C) { 1348 i2c_create_slave(i2c, "ssd0303", 0x3d); 1349 } 1350 } 1351 1352 for (i = 0; i < 4; i++) { 1353 if (board->dc2 & (1 << i)) { 1354 pl011_luminary_create(0x4000c000 + i * 0x1000, 1355 qdev_get_gpio_in(nvic, uart_irq[i]), 1356 serial_hds[i]); 1357 } 1358 } 1359 if (board->dc2 & (1 << 4)) { 1360 dev = sysbus_create_simple("pl022", 0x40008000, 1361 qdev_get_gpio_in(nvic, 7)); 1362 if (board->peripherals & BP_OLED_SSI) { 1363 void *bus; 1364 DeviceState *sddev; 1365 DeviceState *ssddev; 1366 1367 /* Some boards have both an OLED controller and SD card connected to 1368 * the same SSI port, with the SD card chip select connected to a 1369 * GPIO pin. Technically the OLED chip select is connected to the 1370 * SSI Fss pin. We do not bother emulating that as both devices 1371 * should never be selected simultaneously, and our OLED controller 1372 * ignores stray 0xff commands that occur when deselecting the SD 1373 * card. 1374 */ 1375 bus = qdev_get_child_bus(dev, "ssi"); 1376 1377 sddev = ssi_create_slave(bus, "ssi-sd"); 1378 ssddev = ssi_create_slave(bus, "ssd0323"); 1379 gpio_out[GPIO_D][0] = qemu_irq_split( 1380 qdev_get_gpio_in_named(sddev, SSI_GPIO_CS, 0), 1381 qdev_get_gpio_in_named(ssddev, SSI_GPIO_CS, 0)); 1382 gpio_out[GPIO_C][7] = qdev_get_gpio_in(ssddev, 0); 1383 1384 /* Make sure the select pin is high. */ 1385 qemu_irq_raise(gpio_out[GPIO_D][0]); 1386 } 1387 } 1388 if (board->dc4 & (1 << 28)) { 1389 DeviceState *enet; 1390 1391 qemu_check_nic_model(&nd_table[0], "stellaris"); 1392 1393 enet = qdev_create(NULL, "stellaris_enet"); 1394 qdev_set_nic_properties(enet, &nd_table[0]); 1395 qdev_init_nofail(enet); 1396 sysbus_mmio_map(SYS_BUS_DEVICE(enet), 0, 0x40048000); 1397 sysbus_connect_irq(SYS_BUS_DEVICE(enet), 0, qdev_get_gpio_in(nvic, 42)); 1398 } 1399 if (board->peripherals & BP_GAMEPAD) { 1400 qemu_irq gpad_irq[5]; 1401 static const int gpad_keycode[5] = { 0xc8, 0xd0, 0xcb, 0xcd, 0x1d }; 1402 1403 gpad_irq[0] = qemu_irq_invert(gpio_in[GPIO_E][0]); /* up */ 1404 gpad_irq[1] = qemu_irq_invert(gpio_in[GPIO_E][1]); /* down */ 1405 gpad_irq[2] = qemu_irq_invert(gpio_in[GPIO_E][2]); /* left */ 1406 gpad_irq[3] = qemu_irq_invert(gpio_in[GPIO_E][3]); /* right */ 1407 gpad_irq[4] = qemu_irq_invert(gpio_in[GPIO_F][1]); /* select */ 1408 1409 stellaris_gamepad_init(5, gpad_irq, gpad_keycode); 1410 } 1411 for (i = 0; i < 7; i++) { 1412 if (board->dc4 & (1 << i)) { 1413 for (j = 0; j < 8; j++) { 1414 if (gpio_out[i][j]) { 1415 qdev_connect_gpio_out(gpio_dev[i], j, gpio_out[i][j]); 1416 } 1417 } 1418 } 1419 } 1420 1421 /* Add dummy regions for the devices we don't implement yet, 1422 * so guest accesses don't cause unlogged crashes. 1423 */ 1424 create_unimplemented_device("wdtimer", 0x40000000, 0x1000); 1425 create_unimplemented_device("i2c-0", 0x40002000, 0x1000); 1426 create_unimplemented_device("i2c-2", 0x40021000, 0x1000); 1427 create_unimplemented_device("PWM", 0x40028000, 0x1000); 1428 create_unimplemented_device("QEI-0", 0x4002c000, 0x1000); 1429 create_unimplemented_device("QEI-1", 0x4002d000, 0x1000); 1430 create_unimplemented_device("analogue-comparator", 0x4003c000, 0x1000); 1431 create_unimplemented_device("hibernation", 0x400fc000, 0x1000); 1432 create_unimplemented_device("flash-control", 0x400fd000, 0x1000); 1433 } 1434 1435 /* FIXME: Figure out how to generate these from stellaris_boards. */ 1436 static void lm3s811evb_init(MachineState *machine) 1437 { 1438 stellaris_init(machine, &stellaris_boards[0]); 1439 } 1440 1441 static void lm3s6965evb_init(MachineState *machine) 1442 { 1443 stellaris_init(machine, &stellaris_boards[1]); 1444 } 1445 1446 static void lm3s811evb_class_init(ObjectClass *oc, void *data) 1447 { 1448 MachineClass *mc = MACHINE_CLASS(oc); 1449 1450 mc->desc = "Stellaris LM3S811EVB"; 1451 mc->init = lm3s811evb_init; 1452 mc->ignore_memory_transaction_failures = true; 1453 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3"); 1454 } 1455 1456 static const TypeInfo lm3s811evb_type = { 1457 .name = MACHINE_TYPE_NAME("lm3s811evb"), 1458 .parent = TYPE_MACHINE, 1459 .class_init = lm3s811evb_class_init, 1460 }; 1461 1462 static void lm3s6965evb_class_init(ObjectClass *oc, void *data) 1463 { 1464 MachineClass *mc = MACHINE_CLASS(oc); 1465 1466 mc->desc = "Stellaris LM3S6965EVB"; 1467 mc->init = lm3s6965evb_init; 1468 mc->ignore_memory_transaction_failures = true; 1469 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3"); 1470 } 1471 1472 static const TypeInfo lm3s6965evb_type = { 1473 .name = MACHINE_TYPE_NAME("lm3s6965evb"), 1474 .parent = TYPE_MACHINE, 1475 .class_init = lm3s6965evb_class_init, 1476 }; 1477 1478 static void stellaris_machine_init(void) 1479 { 1480 type_register_static(&lm3s811evb_type); 1481 type_register_static(&lm3s6965evb_type); 1482 } 1483 1484 type_init(stellaris_machine_init) 1485 1486 static void stellaris_i2c_class_init(ObjectClass *klass, void *data) 1487 { 1488 DeviceClass *dc = DEVICE_CLASS(klass); 1489 1490 dc->vmsd = &vmstate_stellaris_i2c; 1491 } 1492 1493 static const TypeInfo stellaris_i2c_info = { 1494 .name = TYPE_STELLARIS_I2C, 1495 .parent = TYPE_SYS_BUS_DEVICE, 1496 .instance_size = sizeof(stellaris_i2c_state), 1497 .instance_init = stellaris_i2c_init, 1498 .class_init = stellaris_i2c_class_init, 1499 }; 1500 1501 static void stellaris_gptm_class_init(ObjectClass *klass, void *data) 1502 { 1503 DeviceClass *dc = DEVICE_CLASS(klass); 1504 1505 dc->vmsd = &vmstate_stellaris_gptm; 1506 } 1507 1508 static const TypeInfo stellaris_gptm_info = { 1509 .name = TYPE_STELLARIS_GPTM, 1510 .parent = TYPE_SYS_BUS_DEVICE, 1511 .instance_size = sizeof(gptm_state), 1512 .instance_init = stellaris_gptm_init, 1513 .class_init = stellaris_gptm_class_init, 1514 }; 1515 1516 static void stellaris_adc_class_init(ObjectClass *klass, void *data) 1517 { 1518 DeviceClass *dc = DEVICE_CLASS(klass); 1519 1520 dc->vmsd = &vmstate_stellaris_adc; 1521 } 1522 1523 static const TypeInfo stellaris_adc_info = { 1524 .name = TYPE_STELLARIS_ADC, 1525 .parent = TYPE_SYS_BUS_DEVICE, 1526 .instance_size = sizeof(stellaris_adc_state), 1527 .instance_init = stellaris_adc_init, 1528 .class_init = stellaris_adc_class_init, 1529 }; 1530 1531 static void stellaris_register_types(void) 1532 { 1533 type_register_static(&stellaris_i2c_info); 1534 type_register_static(&stellaris_gptm_info); 1535 type_register_static(&stellaris_adc_info); 1536 } 1537 1538 type_init(stellaris_register_types) 1539