1 /* 2 * Luminary Micro Stellaris peripherals 3 * 4 * Copyright (c) 2006 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qapi/error.h" 12 #include "hw/sysbus.h" 13 #include "hw/ssi/ssi.h" 14 #include "hw/arm/arm.h" 15 #include "hw/devices.h" 16 #include "qemu/timer.h" 17 #include "hw/i2c/i2c.h" 18 #include "net/net.h" 19 #include "hw/boards.h" 20 #include "exec/address-spaces.h" 21 #include "sysemu/sysemu.h" 22 23 #define GPIO_A 0 24 #define GPIO_B 1 25 #define GPIO_C 2 26 #define GPIO_D 3 27 #define GPIO_E 4 28 #define GPIO_F 5 29 #define GPIO_G 6 30 31 #define BP_OLED_I2C 0x01 32 #define BP_OLED_SSI 0x02 33 #define BP_GAMEPAD 0x04 34 35 #define NUM_IRQ_LINES 64 36 37 typedef const struct { 38 const char *name; 39 uint32_t did0; 40 uint32_t did1; 41 uint32_t dc0; 42 uint32_t dc1; 43 uint32_t dc2; 44 uint32_t dc3; 45 uint32_t dc4; 46 uint32_t peripherals; 47 } stellaris_board_info; 48 49 /* General purpose timer module. */ 50 51 #define TYPE_STELLARIS_GPTM "stellaris-gptm" 52 #define STELLARIS_GPTM(obj) \ 53 OBJECT_CHECK(gptm_state, (obj), TYPE_STELLARIS_GPTM) 54 55 typedef struct gptm_state { 56 SysBusDevice parent_obj; 57 58 MemoryRegion iomem; 59 uint32_t config; 60 uint32_t mode[2]; 61 uint32_t control; 62 uint32_t state; 63 uint32_t mask; 64 uint32_t load[2]; 65 uint32_t match[2]; 66 uint32_t prescale[2]; 67 uint32_t match_prescale[2]; 68 uint32_t rtc; 69 int64_t tick[2]; 70 struct gptm_state *opaque[2]; 71 QEMUTimer *timer[2]; 72 /* The timers have an alternate output used to trigger the ADC. */ 73 qemu_irq trigger; 74 qemu_irq irq; 75 } gptm_state; 76 77 static void gptm_update_irq(gptm_state *s) 78 { 79 int level; 80 level = (s->state & s->mask) != 0; 81 qemu_set_irq(s->irq, level); 82 } 83 84 static void gptm_stop(gptm_state *s, int n) 85 { 86 timer_del(s->timer[n]); 87 } 88 89 static void gptm_reload(gptm_state *s, int n, int reset) 90 { 91 int64_t tick; 92 if (reset) 93 tick = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 94 else 95 tick = s->tick[n]; 96 97 if (s->config == 0) { 98 /* 32-bit CountDown. */ 99 uint32_t count; 100 count = s->load[0] | (s->load[1] << 16); 101 tick += (int64_t)count * system_clock_scale; 102 } else if (s->config == 1) { 103 /* 32-bit RTC. 1Hz tick. */ 104 tick += NANOSECONDS_PER_SECOND; 105 } else if (s->mode[n] == 0xa) { 106 /* PWM mode. Not implemented. */ 107 } else { 108 hw_error("TODO: 16-bit timer mode 0x%x\n", s->mode[n]); 109 } 110 s->tick[n] = tick; 111 timer_mod(s->timer[n], tick); 112 } 113 114 static void gptm_tick(void *opaque) 115 { 116 gptm_state **p = (gptm_state **)opaque; 117 gptm_state *s; 118 int n; 119 120 s = *p; 121 n = p - s->opaque; 122 if (s->config == 0) { 123 s->state |= 1; 124 if ((s->control & 0x20)) { 125 /* Output trigger. */ 126 qemu_irq_pulse(s->trigger); 127 } 128 if (s->mode[0] & 1) { 129 /* One-shot. */ 130 s->control &= ~1; 131 } else { 132 /* Periodic. */ 133 gptm_reload(s, 0, 0); 134 } 135 } else if (s->config == 1) { 136 /* RTC. */ 137 uint32_t match; 138 s->rtc++; 139 match = s->match[0] | (s->match[1] << 16); 140 if (s->rtc > match) 141 s->rtc = 0; 142 if (s->rtc == 0) { 143 s->state |= 8; 144 } 145 gptm_reload(s, 0, 0); 146 } else if (s->mode[n] == 0xa) { 147 /* PWM mode. Not implemented. */ 148 } else { 149 hw_error("TODO: 16-bit timer mode 0x%x\n", s->mode[n]); 150 } 151 gptm_update_irq(s); 152 } 153 154 static uint64_t gptm_read(void *opaque, hwaddr offset, 155 unsigned size) 156 { 157 gptm_state *s = (gptm_state *)opaque; 158 159 switch (offset) { 160 case 0x00: /* CFG */ 161 return s->config; 162 case 0x04: /* TAMR */ 163 return s->mode[0]; 164 case 0x08: /* TBMR */ 165 return s->mode[1]; 166 case 0x0c: /* CTL */ 167 return s->control; 168 case 0x18: /* IMR */ 169 return s->mask; 170 case 0x1c: /* RIS */ 171 return s->state; 172 case 0x20: /* MIS */ 173 return s->state & s->mask; 174 case 0x24: /* CR */ 175 return 0; 176 case 0x28: /* TAILR */ 177 return s->load[0] | ((s->config < 4) ? (s->load[1] << 16) : 0); 178 case 0x2c: /* TBILR */ 179 return s->load[1]; 180 case 0x30: /* TAMARCHR */ 181 return s->match[0] | ((s->config < 4) ? (s->match[1] << 16) : 0); 182 case 0x34: /* TBMATCHR */ 183 return s->match[1]; 184 case 0x38: /* TAPR */ 185 return s->prescale[0]; 186 case 0x3c: /* TBPR */ 187 return s->prescale[1]; 188 case 0x40: /* TAPMR */ 189 return s->match_prescale[0]; 190 case 0x44: /* TBPMR */ 191 return s->match_prescale[1]; 192 case 0x48: /* TAR */ 193 if (s->config == 1) { 194 return s->rtc; 195 } 196 qemu_log_mask(LOG_UNIMP, 197 "GPTM: read of TAR but timer read not supported"); 198 return 0; 199 case 0x4c: /* TBR */ 200 qemu_log_mask(LOG_UNIMP, 201 "GPTM: read of TBR but timer read not supported"); 202 return 0; 203 default: 204 qemu_log_mask(LOG_GUEST_ERROR, 205 "GPTM: read at bad offset 0x%x\n", (int)offset); 206 return 0; 207 } 208 } 209 210 static void gptm_write(void *opaque, hwaddr offset, 211 uint64_t value, unsigned size) 212 { 213 gptm_state *s = (gptm_state *)opaque; 214 uint32_t oldval; 215 216 /* The timers should be disabled before changing the configuration. 217 We take advantage of this and defer everything until the timer 218 is enabled. */ 219 switch (offset) { 220 case 0x00: /* CFG */ 221 s->config = value; 222 break; 223 case 0x04: /* TAMR */ 224 s->mode[0] = value; 225 break; 226 case 0x08: /* TBMR */ 227 s->mode[1] = value; 228 break; 229 case 0x0c: /* CTL */ 230 oldval = s->control; 231 s->control = value; 232 /* TODO: Implement pause. */ 233 if ((oldval ^ value) & 1) { 234 if (value & 1) { 235 gptm_reload(s, 0, 1); 236 } else { 237 gptm_stop(s, 0); 238 } 239 } 240 if (((oldval ^ value) & 0x100) && s->config >= 4) { 241 if (value & 0x100) { 242 gptm_reload(s, 1, 1); 243 } else { 244 gptm_stop(s, 1); 245 } 246 } 247 break; 248 case 0x18: /* IMR */ 249 s->mask = value & 0x77; 250 gptm_update_irq(s); 251 break; 252 case 0x24: /* CR */ 253 s->state &= ~value; 254 break; 255 case 0x28: /* TAILR */ 256 s->load[0] = value & 0xffff; 257 if (s->config < 4) { 258 s->load[1] = value >> 16; 259 } 260 break; 261 case 0x2c: /* TBILR */ 262 s->load[1] = value & 0xffff; 263 break; 264 case 0x30: /* TAMARCHR */ 265 s->match[0] = value & 0xffff; 266 if (s->config < 4) { 267 s->match[1] = value >> 16; 268 } 269 break; 270 case 0x34: /* TBMATCHR */ 271 s->match[1] = value >> 16; 272 break; 273 case 0x38: /* TAPR */ 274 s->prescale[0] = value; 275 break; 276 case 0x3c: /* TBPR */ 277 s->prescale[1] = value; 278 break; 279 case 0x40: /* TAPMR */ 280 s->match_prescale[0] = value; 281 break; 282 case 0x44: /* TBPMR */ 283 s->match_prescale[0] = value; 284 break; 285 default: 286 hw_error("gptm_write: Bad offset 0x%x\n", (int)offset); 287 } 288 gptm_update_irq(s); 289 } 290 291 static const MemoryRegionOps gptm_ops = { 292 .read = gptm_read, 293 .write = gptm_write, 294 .endianness = DEVICE_NATIVE_ENDIAN, 295 }; 296 297 static const VMStateDescription vmstate_stellaris_gptm = { 298 .name = "stellaris_gptm", 299 .version_id = 1, 300 .minimum_version_id = 1, 301 .fields = (VMStateField[]) { 302 VMSTATE_UINT32(config, gptm_state), 303 VMSTATE_UINT32_ARRAY(mode, gptm_state, 2), 304 VMSTATE_UINT32(control, gptm_state), 305 VMSTATE_UINT32(state, gptm_state), 306 VMSTATE_UINT32(mask, gptm_state), 307 VMSTATE_UNUSED(8), 308 VMSTATE_UINT32_ARRAY(load, gptm_state, 2), 309 VMSTATE_UINT32_ARRAY(match, gptm_state, 2), 310 VMSTATE_UINT32_ARRAY(prescale, gptm_state, 2), 311 VMSTATE_UINT32_ARRAY(match_prescale, gptm_state, 2), 312 VMSTATE_UINT32(rtc, gptm_state), 313 VMSTATE_INT64_ARRAY(tick, gptm_state, 2), 314 VMSTATE_TIMER_PTR_ARRAY(timer, gptm_state, 2), 315 VMSTATE_END_OF_LIST() 316 } 317 }; 318 319 static void stellaris_gptm_init(Object *obj) 320 { 321 DeviceState *dev = DEVICE(obj); 322 gptm_state *s = STELLARIS_GPTM(obj); 323 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 324 325 sysbus_init_irq(sbd, &s->irq); 326 qdev_init_gpio_out(dev, &s->trigger, 1); 327 328 memory_region_init_io(&s->iomem, obj, &gptm_ops, s, 329 "gptm", 0x1000); 330 sysbus_init_mmio(sbd, &s->iomem); 331 332 s->opaque[0] = s->opaque[1] = s; 333 s->timer[0] = timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque[0]); 334 s->timer[1] = timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque[1]); 335 } 336 337 338 /* System controller. */ 339 340 typedef struct { 341 MemoryRegion iomem; 342 uint32_t pborctl; 343 uint32_t ldopctl; 344 uint32_t int_status; 345 uint32_t int_mask; 346 uint32_t resc; 347 uint32_t rcc; 348 uint32_t rcc2; 349 uint32_t rcgc[3]; 350 uint32_t scgc[3]; 351 uint32_t dcgc[3]; 352 uint32_t clkvclr; 353 uint32_t ldoarst; 354 uint32_t user0; 355 uint32_t user1; 356 qemu_irq irq; 357 stellaris_board_info *board; 358 } ssys_state; 359 360 static void ssys_update(ssys_state *s) 361 { 362 qemu_set_irq(s->irq, (s->int_status & s->int_mask) != 0); 363 } 364 365 static uint32_t pllcfg_sandstorm[16] = { 366 0x31c0, /* 1 Mhz */ 367 0x1ae0, /* 1.8432 Mhz */ 368 0x18c0, /* 2 Mhz */ 369 0xd573, /* 2.4576 Mhz */ 370 0x37a6, /* 3.57954 Mhz */ 371 0x1ae2, /* 3.6864 Mhz */ 372 0x0c40, /* 4 Mhz */ 373 0x98bc, /* 4.906 Mhz */ 374 0x935b, /* 4.9152 Mhz */ 375 0x09c0, /* 5 Mhz */ 376 0x4dee, /* 5.12 Mhz */ 377 0x0c41, /* 6 Mhz */ 378 0x75db, /* 6.144 Mhz */ 379 0x1ae6, /* 7.3728 Mhz */ 380 0x0600, /* 8 Mhz */ 381 0x585b /* 8.192 Mhz */ 382 }; 383 384 static uint32_t pllcfg_fury[16] = { 385 0x3200, /* 1 Mhz */ 386 0x1b20, /* 1.8432 Mhz */ 387 0x1900, /* 2 Mhz */ 388 0xf42b, /* 2.4576 Mhz */ 389 0x37e3, /* 3.57954 Mhz */ 390 0x1b21, /* 3.6864 Mhz */ 391 0x0c80, /* 4 Mhz */ 392 0x98ee, /* 4.906 Mhz */ 393 0xd5b4, /* 4.9152 Mhz */ 394 0x0a00, /* 5 Mhz */ 395 0x4e27, /* 5.12 Mhz */ 396 0x1902, /* 6 Mhz */ 397 0xec1c, /* 6.144 Mhz */ 398 0x1b23, /* 7.3728 Mhz */ 399 0x0640, /* 8 Mhz */ 400 0xb11c /* 8.192 Mhz */ 401 }; 402 403 #define DID0_VER_MASK 0x70000000 404 #define DID0_VER_0 0x00000000 405 #define DID0_VER_1 0x10000000 406 407 #define DID0_CLASS_MASK 0x00FF0000 408 #define DID0_CLASS_SANDSTORM 0x00000000 409 #define DID0_CLASS_FURY 0x00010000 410 411 static int ssys_board_class(const ssys_state *s) 412 { 413 uint32_t did0 = s->board->did0; 414 switch (did0 & DID0_VER_MASK) { 415 case DID0_VER_0: 416 return DID0_CLASS_SANDSTORM; 417 case DID0_VER_1: 418 switch (did0 & DID0_CLASS_MASK) { 419 case DID0_CLASS_SANDSTORM: 420 case DID0_CLASS_FURY: 421 return did0 & DID0_CLASS_MASK; 422 } 423 /* for unknown classes, fall through */ 424 default: 425 hw_error("ssys_board_class: Unknown class 0x%08x\n", did0); 426 } 427 } 428 429 static uint64_t ssys_read(void *opaque, hwaddr offset, 430 unsigned size) 431 { 432 ssys_state *s = (ssys_state *)opaque; 433 434 switch (offset) { 435 case 0x000: /* DID0 */ 436 return s->board->did0; 437 case 0x004: /* DID1 */ 438 return s->board->did1; 439 case 0x008: /* DC0 */ 440 return s->board->dc0; 441 case 0x010: /* DC1 */ 442 return s->board->dc1; 443 case 0x014: /* DC2 */ 444 return s->board->dc2; 445 case 0x018: /* DC3 */ 446 return s->board->dc3; 447 case 0x01c: /* DC4 */ 448 return s->board->dc4; 449 case 0x030: /* PBORCTL */ 450 return s->pborctl; 451 case 0x034: /* LDOPCTL */ 452 return s->ldopctl; 453 case 0x040: /* SRCR0 */ 454 return 0; 455 case 0x044: /* SRCR1 */ 456 return 0; 457 case 0x048: /* SRCR2 */ 458 return 0; 459 case 0x050: /* RIS */ 460 return s->int_status; 461 case 0x054: /* IMC */ 462 return s->int_mask; 463 case 0x058: /* MISC */ 464 return s->int_status & s->int_mask; 465 case 0x05c: /* RESC */ 466 return s->resc; 467 case 0x060: /* RCC */ 468 return s->rcc; 469 case 0x064: /* PLLCFG */ 470 { 471 int xtal; 472 xtal = (s->rcc >> 6) & 0xf; 473 switch (ssys_board_class(s)) { 474 case DID0_CLASS_FURY: 475 return pllcfg_fury[xtal]; 476 case DID0_CLASS_SANDSTORM: 477 return pllcfg_sandstorm[xtal]; 478 default: 479 hw_error("ssys_read: Unhandled class for PLLCFG read.\n"); 480 return 0; 481 } 482 } 483 case 0x070: /* RCC2 */ 484 return s->rcc2; 485 case 0x100: /* RCGC0 */ 486 return s->rcgc[0]; 487 case 0x104: /* RCGC1 */ 488 return s->rcgc[1]; 489 case 0x108: /* RCGC2 */ 490 return s->rcgc[2]; 491 case 0x110: /* SCGC0 */ 492 return s->scgc[0]; 493 case 0x114: /* SCGC1 */ 494 return s->scgc[1]; 495 case 0x118: /* SCGC2 */ 496 return s->scgc[2]; 497 case 0x120: /* DCGC0 */ 498 return s->dcgc[0]; 499 case 0x124: /* DCGC1 */ 500 return s->dcgc[1]; 501 case 0x128: /* DCGC2 */ 502 return s->dcgc[2]; 503 case 0x150: /* CLKVCLR */ 504 return s->clkvclr; 505 case 0x160: /* LDOARST */ 506 return s->ldoarst; 507 case 0x1e0: /* USER0 */ 508 return s->user0; 509 case 0x1e4: /* USER1 */ 510 return s->user1; 511 default: 512 hw_error("ssys_read: Bad offset 0x%x\n", (int)offset); 513 return 0; 514 } 515 } 516 517 static bool ssys_use_rcc2(ssys_state *s) 518 { 519 return (s->rcc2 >> 31) & 0x1; 520 } 521 522 /* 523 * Caculate the sys. clock period in ms. 524 */ 525 static void ssys_calculate_system_clock(ssys_state *s) 526 { 527 if (ssys_use_rcc2(s)) { 528 system_clock_scale = 5 * (((s->rcc2 >> 23) & 0x3f) + 1); 529 } else { 530 system_clock_scale = 5 * (((s->rcc >> 23) & 0xf) + 1); 531 } 532 } 533 534 static void ssys_write(void *opaque, hwaddr offset, 535 uint64_t value, unsigned size) 536 { 537 ssys_state *s = (ssys_state *)opaque; 538 539 switch (offset) { 540 case 0x030: /* PBORCTL */ 541 s->pborctl = value & 0xffff; 542 break; 543 case 0x034: /* LDOPCTL */ 544 s->ldopctl = value & 0x1f; 545 break; 546 case 0x040: /* SRCR0 */ 547 case 0x044: /* SRCR1 */ 548 case 0x048: /* SRCR2 */ 549 fprintf(stderr, "Peripheral reset not implemented\n"); 550 break; 551 case 0x054: /* IMC */ 552 s->int_mask = value & 0x7f; 553 break; 554 case 0x058: /* MISC */ 555 s->int_status &= ~value; 556 break; 557 case 0x05c: /* RESC */ 558 s->resc = value & 0x3f; 559 break; 560 case 0x060: /* RCC */ 561 if ((s->rcc & (1 << 13)) != 0 && (value & (1 << 13)) == 0) { 562 /* PLL enable. */ 563 s->int_status |= (1 << 6); 564 } 565 s->rcc = value; 566 ssys_calculate_system_clock(s); 567 break; 568 case 0x070: /* RCC2 */ 569 if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) { 570 break; 571 } 572 573 if ((s->rcc2 & (1 << 13)) != 0 && (value & (1 << 13)) == 0) { 574 /* PLL enable. */ 575 s->int_status |= (1 << 6); 576 } 577 s->rcc2 = value; 578 ssys_calculate_system_clock(s); 579 break; 580 case 0x100: /* RCGC0 */ 581 s->rcgc[0] = value; 582 break; 583 case 0x104: /* RCGC1 */ 584 s->rcgc[1] = value; 585 break; 586 case 0x108: /* RCGC2 */ 587 s->rcgc[2] = value; 588 break; 589 case 0x110: /* SCGC0 */ 590 s->scgc[0] = value; 591 break; 592 case 0x114: /* SCGC1 */ 593 s->scgc[1] = value; 594 break; 595 case 0x118: /* SCGC2 */ 596 s->scgc[2] = value; 597 break; 598 case 0x120: /* DCGC0 */ 599 s->dcgc[0] = value; 600 break; 601 case 0x124: /* DCGC1 */ 602 s->dcgc[1] = value; 603 break; 604 case 0x128: /* DCGC2 */ 605 s->dcgc[2] = value; 606 break; 607 case 0x150: /* CLKVCLR */ 608 s->clkvclr = value; 609 break; 610 case 0x160: /* LDOARST */ 611 s->ldoarst = value; 612 break; 613 default: 614 hw_error("ssys_write: Bad offset 0x%x\n", (int)offset); 615 } 616 ssys_update(s); 617 } 618 619 static const MemoryRegionOps ssys_ops = { 620 .read = ssys_read, 621 .write = ssys_write, 622 .endianness = DEVICE_NATIVE_ENDIAN, 623 }; 624 625 static void ssys_reset(void *opaque) 626 { 627 ssys_state *s = (ssys_state *)opaque; 628 629 s->pborctl = 0x7ffd; 630 s->rcc = 0x078e3ac0; 631 632 if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) { 633 s->rcc2 = 0; 634 } else { 635 s->rcc2 = 0x07802810; 636 } 637 s->rcgc[0] = 1; 638 s->scgc[0] = 1; 639 s->dcgc[0] = 1; 640 ssys_calculate_system_clock(s); 641 } 642 643 static int stellaris_sys_post_load(void *opaque, int version_id) 644 { 645 ssys_state *s = opaque; 646 647 ssys_calculate_system_clock(s); 648 649 return 0; 650 } 651 652 static const VMStateDescription vmstate_stellaris_sys = { 653 .name = "stellaris_sys", 654 .version_id = 2, 655 .minimum_version_id = 1, 656 .post_load = stellaris_sys_post_load, 657 .fields = (VMStateField[]) { 658 VMSTATE_UINT32(pborctl, ssys_state), 659 VMSTATE_UINT32(ldopctl, ssys_state), 660 VMSTATE_UINT32(int_mask, ssys_state), 661 VMSTATE_UINT32(int_status, ssys_state), 662 VMSTATE_UINT32(resc, ssys_state), 663 VMSTATE_UINT32(rcc, ssys_state), 664 VMSTATE_UINT32_V(rcc2, ssys_state, 2), 665 VMSTATE_UINT32_ARRAY(rcgc, ssys_state, 3), 666 VMSTATE_UINT32_ARRAY(scgc, ssys_state, 3), 667 VMSTATE_UINT32_ARRAY(dcgc, ssys_state, 3), 668 VMSTATE_UINT32(clkvclr, ssys_state), 669 VMSTATE_UINT32(ldoarst, ssys_state), 670 VMSTATE_END_OF_LIST() 671 } 672 }; 673 674 static int stellaris_sys_init(uint32_t base, qemu_irq irq, 675 stellaris_board_info * board, 676 uint8_t *macaddr) 677 { 678 ssys_state *s; 679 680 s = g_new0(ssys_state, 1); 681 s->irq = irq; 682 s->board = board; 683 /* Most devices come preprogrammed with a MAC address in the user data. */ 684 s->user0 = macaddr[0] | (macaddr[1] << 8) | (macaddr[2] << 16); 685 s->user1 = macaddr[3] | (macaddr[4] << 8) | (macaddr[5] << 16); 686 687 memory_region_init_io(&s->iomem, NULL, &ssys_ops, s, "ssys", 0x00001000); 688 memory_region_add_subregion(get_system_memory(), base, &s->iomem); 689 ssys_reset(s); 690 vmstate_register(NULL, -1, &vmstate_stellaris_sys, s); 691 return 0; 692 } 693 694 695 /* I2C controller. */ 696 697 #define TYPE_STELLARIS_I2C "stellaris-i2c" 698 #define STELLARIS_I2C(obj) \ 699 OBJECT_CHECK(stellaris_i2c_state, (obj), TYPE_STELLARIS_I2C) 700 701 typedef struct { 702 SysBusDevice parent_obj; 703 704 I2CBus *bus; 705 qemu_irq irq; 706 MemoryRegion iomem; 707 uint32_t msa; 708 uint32_t mcs; 709 uint32_t mdr; 710 uint32_t mtpr; 711 uint32_t mimr; 712 uint32_t mris; 713 uint32_t mcr; 714 } stellaris_i2c_state; 715 716 #define STELLARIS_I2C_MCS_BUSY 0x01 717 #define STELLARIS_I2C_MCS_ERROR 0x02 718 #define STELLARIS_I2C_MCS_ADRACK 0x04 719 #define STELLARIS_I2C_MCS_DATACK 0x08 720 #define STELLARIS_I2C_MCS_ARBLST 0x10 721 #define STELLARIS_I2C_MCS_IDLE 0x20 722 #define STELLARIS_I2C_MCS_BUSBSY 0x40 723 724 static uint64_t stellaris_i2c_read(void *opaque, hwaddr offset, 725 unsigned size) 726 { 727 stellaris_i2c_state *s = (stellaris_i2c_state *)opaque; 728 729 switch (offset) { 730 case 0x00: /* MSA */ 731 return s->msa; 732 case 0x04: /* MCS */ 733 /* We don't emulate timing, so the controller is never busy. */ 734 return s->mcs | STELLARIS_I2C_MCS_IDLE; 735 case 0x08: /* MDR */ 736 return s->mdr; 737 case 0x0c: /* MTPR */ 738 return s->mtpr; 739 case 0x10: /* MIMR */ 740 return s->mimr; 741 case 0x14: /* MRIS */ 742 return s->mris; 743 case 0x18: /* MMIS */ 744 return s->mris & s->mimr; 745 case 0x20: /* MCR */ 746 return s->mcr; 747 default: 748 hw_error("strllaris_i2c_read: Bad offset 0x%x\n", (int)offset); 749 return 0; 750 } 751 } 752 753 static void stellaris_i2c_update(stellaris_i2c_state *s) 754 { 755 int level; 756 757 level = (s->mris & s->mimr) != 0; 758 qemu_set_irq(s->irq, level); 759 } 760 761 static void stellaris_i2c_write(void *opaque, hwaddr offset, 762 uint64_t value, unsigned size) 763 { 764 stellaris_i2c_state *s = (stellaris_i2c_state *)opaque; 765 766 switch (offset) { 767 case 0x00: /* MSA */ 768 s->msa = value & 0xff; 769 break; 770 case 0x04: /* MCS */ 771 if ((s->mcr & 0x10) == 0) { 772 /* Disabled. Do nothing. */ 773 break; 774 } 775 /* Grab the bus if this is starting a transfer. */ 776 if ((value & 2) && (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) { 777 if (i2c_start_transfer(s->bus, s->msa >> 1, s->msa & 1)) { 778 s->mcs |= STELLARIS_I2C_MCS_ARBLST; 779 } else { 780 s->mcs &= ~STELLARIS_I2C_MCS_ARBLST; 781 s->mcs |= STELLARIS_I2C_MCS_BUSBSY; 782 } 783 } 784 /* If we don't have the bus then indicate an error. */ 785 if (!i2c_bus_busy(s->bus) 786 || (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) { 787 s->mcs |= STELLARIS_I2C_MCS_ERROR; 788 break; 789 } 790 s->mcs &= ~STELLARIS_I2C_MCS_ERROR; 791 if (value & 1) { 792 /* Transfer a byte. */ 793 /* TODO: Handle errors. */ 794 if (s->msa & 1) { 795 /* Recv */ 796 s->mdr = i2c_recv(s->bus) & 0xff; 797 } else { 798 /* Send */ 799 i2c_send(s->bus, s->mdr); 800 } 801 /* Raise an interrupt. */ 802 s->mris |= 1; 803 } 804 if (value & 4) { 805 /* Finish transfer. */ 806 i2c_end_transfer(s->bus); 807 s->mcs &= ~STELLARIS_I2C_MCS_BUSBSY; 808 } 809 break; 810 case 0x08: /* MDR */ 811 s->mdr = value & 0xff; 812 break; 813 case 0x0c: /* MTPR */ 814 s->mtpr = value & 0xff; 815 break; 816 case 0x10: /* MIMR */ 817 s->mimr = 1; 818 break; 819 case 0x1c: /* MICR */ 820 s->mris &= ~value; 821 break; 822 case 0x20: /* MCR */ 823 if (value & 1) 824 hw_error( 825 "stellaris_i2c_write: Loopback not implemented\n"); 826 if (value & 0x20) 827 hw_error( 828 "stellaris_i2c_write: Slave mode not implemented\n"); 829 s->mcr = value & 0x31; 830 break; 831 default: 832 hw_error("stellaris_i2c_write: Bad offset 0x%x\n", 833 (int)offset); 834 } 835 stellaris_i2c_update(s); 836 } 837 838 static void stellaris_i2c_reset(stellaris_i2c_state *s) 839 { 840 if (s->mcs & STELLARIS_I2C_MCS_BUSBSY) 841 i2c_end_transfer(s->bus); 842 843 s->msa = 0; 844 s->mcs = 0; 845 s->mdr = 0; 846 s->mtpr = 1; 847 s->mimr = 0; 848 s->mris = 0; 849 s->mcr = 0; 850 stellaris_i2c_update(s); 851 } 852 853 static const MemoryRegionOps stellaris_i2c_ops = { 854 .read = stellaris_i2c_read, 855 .write = stellaris_i2c_write, 856 .endianness = DEVICE_NATIVE_ENDIAN, 857 }; 858 859 static const VMStateDescription vmstate_stellaris_i2c = { 860 .name = "stellaris_i2c", 861 .version_id = 1, 862 .minimum_version_id = 1, 863 .fields = (VMStateField[]) { 864 VMSTATE_UINT32(msa, stellaris_i2c_state), 865 VMSTATE_UINT32(mcs, stellaris_i2c_state), 866 VMSTATE_UINT32(mdr, stellaris_i2c_state), 867 VMSTATE_UINT32(mtpr, stellaris_i2c_state), 868 VMSTATE_UINT32(mimr, stellaris_i2c_state), 869 VMSTATE_UINT32(mris, stellaris_i2c_state), 870 VMSTATE_UINT32(mcr, stellaris_i2c_state), 871 VMSTATE_END_OF_LIST() 872 } 873 }; 874 875 static void stellaris_i2c_init(Object *obj) 876 { 877 DeviceState *dev = DEVICE(obj); 878 stellaris_i2c_state *s = STELLARIS_I2C(obj); 879 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 880 I2CBus *bus; 881 882 sysbus_init_irq(sbd, &s->irq); 883 bus = i2c_init_bus(dev, "i2c"); 884 s->bus = bus; 885 886 memory_region_init_io(&s->iomem, obj, &stellaris_i2c_ops, s, 887 "i2c", 0x1000); 888 sysbus_init_mmio(sbd, &s->iomem); 889 /* ??? For now we only implement the master interface. */ 890 stellaris_i2c_reset(s); 891 } 892 893 /* Analogue to Digital Converter. This is only partially implemented, 894 enough for applications that use a combined ADC and timer tick. */ 895 896 #define STELLARIS_ADC_EM_CONTROLLER 0 897 #define STELLARIS_ADC_EM_COMP 1 898 #define STELLARIS_ADC_EM_EXTERNAL 4 899 #define STELLARIS_ADC_EM_TIMER 5 900 #define STELLARIS_ADC_EM_PWM0 6 901 #define STELLARIS_ADC_EM_PWM1 7 902 #define STELLARIS_ADC_EM_PWM2 8 903 904 #define STELLARIS_ADC_FIFO_EMPTY 0x0100 905 #define STELLARIS_ADC_FIFO_FULL 0x1000 906 907 #define TYPE_STELLARIS_ADC "stellaris-adc" 908 #define STELLARIS_ADC(obj) \ 909 OBJECT_CHECK(stellaris_adc_state, (obj), TYPE_STELLARIS_ADC) 910 911 typedef struct StellarisADCState { 912 SysBusDevice parent_obj; 913 914 MemoryRegion iomem; 915 uint32_t actss; 916 uint32_t ris; 917 uint32_t im; 918 uint32_t emux; 919 uint32_t ostat; 920 uint32_t ustat; 921 uint32_t sspri; 922 uint32_t sac; 923 struct { 924 uint32_t state; 925 uint32_t data[16]; 926 } fifo[4]; 927 uint32_t ssmux[4]; 928 uint32_t ssctl[4]; 929 uint32_t noise; 930 qemu_irq irq[4]; 931 } stellaris_adc_state; 932 933 static uint32_t stellaris_adc_fifo_read(stellaris_adc_state *s, int n) 934 { 935 int tail; 936 937 tail = s->fifo[n].state & 0xf; 938 if (s->fifo[n].state & STELLARIS_ADC_FIFO_EMPTY) { 939 s->ustat |= 1 << n; 940 } else { 941 s->fifo[n].state = (s->fifo[n].state & ~0xf) | ((tail + 1) & 0xf); 942 s->fifo[n].state &= ~STELLARIS_ADC_FIFO_FULL; 943 if (tail + 1 == ((s->fifo[n].state >> 4) & 0xf)) 944 s->fifo[n].state |= STELLARIS_ADC_FIFO_EMPTY; 945 } 946 return s->fifo[n].data[tail]; 947 } 948 949 static void stellaris_adc_fifo_write(stellaris_adc_state *s, int n, 950 uint32_t value) 951 { 952 int head; 953 954 /* TODO: Real hardware has limited size FIFOs. We have a full 16 entry 955 FIFO fir each sequencer. */ 956 head = (s->fifo[n].state >> 4) & 0xf; 957 if (s->fifo[n].state & STELLARIS_ADC_FIFO_FULL) { 958 s->ostat |= 1 << n; 959 return; 960 } 961 s->fifo[n].data[head] = value; 962 head = (head + 1) & 0xf; 963 s->fifo[n].state &= ~STELLARIS_ADC_FIFO_EMPTY; 964 s->fifo[n].state = (s->fifo[n].state & ~0xf0) | (head << 4); 965 if ((s->fifo[n].state & 0xf) == head) 966 s->fifo[n].state |= STELLARIS_ADC_FIFO_FULL; 967 } 968 969 static void stellaris_adc_update(stellaris_adc_state *s) 970 { 971 int level; 972 int n; 973 974 for (n = 0; n < 4; n++) { 975 level = (s->ris & s->im & (1 << n)) != 0; 976 qemu_set_irq(s->irq[n], level); 977 } 978 } 979 980 static void stellaris_adc_trigger(void *opaque, int irq, int level) 981 { 982 stellaris_adc_state *s = (stellaris_adc_state *)opaque; 983 int n; 984 985 for (n = 0; n < 4; n++) { 986 if ((s->actss & (1 << n)) == 0) { 987 continue; 988 } 989 990 if (((s->emux >> (n * 4)) & 0xff) != 5) { 991 continue; 992 } 993 994 /* Some applications use the ADC as a random number source, so introduce 995 some variation into the signal. */ 996 s->noise = s->noise * 314159 + 1; 997 /* ??? actual inputs not implemented. Return an arbitrary value. */ 998 stellaris_adc_fifo_write(s, n, 0x200 + ((s->noise >> 16) & 7)); 999 s->ris |= (1 << n); 1000 stellaris_adc_update(s); 1001 } 1002 } 1003 1004 static void stellaris_adc_reset(stellaris_adc_state *s) 1005 { 1006 int n; 1007 1008 for (n = 0; n < 4; n++) { 1009 s->ssmux[n] = 0; 1010 s->ssctl[n] = 0; 1011 s->fifo[n].state = STELLARIS_ADC_FIFO_EMPTY; 1012 } 1013 } 1014 1015 static uint64_t stellaris_adc_read(void *opaque, hwaddr offset, 1016 unsigned size) 1017 { 1018 stellaris_adc_state *s = (stellaris_adc_state *)opaque; 1019 1020 /* TODO: Implement this. */ 1021 if (offset >= 0x40 && offset < 0xc0) { 1022 int n; 1023 n = (offset - 0x40) >> 5; 1024 switch (offset & 0x1f) { 1025 case 0x00: /* SSMUX */ 1026 return s->ssmux[n]; 1027 case 0x04: /* SSCTL */ 1028 return s->ssctl[n]; 1029 case 0x08: /* SSFIFO */ 1030 return stellaris_adc_fifo_read(s, n); 1031 case 0x0c: /* SSFSTAT */ 1032 return s->fifo[n].state; 1033 default: 1034 break; 1035 } 1036 } 1037 switch (offset) { 1038 case 0x00: /* ACTSS */ 1039 return s->actss; 1040 case 0x04: /* RIS */ 1041 return s->ris; 1042 case 0x08: /* IM */ 1043 return s->im; 1044 case 0x0c: /* ISC */ 1045 return s->ris & s->im; 1046 case 0x10: /* OSTAT */ 1047 return s->ostat; 1048 case 0x14: /* EMUX */ 1049 return s->emux; 1050 case 0x18: /* USTAT */ 1051 return s->ustat; 1052 case 0x20: /* SSPRI */ 1053 return s->sspri; 1054 case 0x30: /* SAC */ 1055 return s->sac; 1056 default: 1057 hw_error("strllaris_adc_read: Bad offset 0x%x\n", 1058 (int)offset); 1059 return 0; 1060 } 1061 } 1062 1063 static void stellaris_adc_write(void *opaque, hwaddr offset, 1064 uint64_t value, unsigned size) 1065 { 1066 stellaris_adc_state *s = (stellaris_adc_state *)opaque; 1067 1068 /* TODO: Implement this. */ 1069 if (offset >= 0x40 && offset < 0xc0) { 1070 int n; 1071 n = (offset - 0x40) >> 5; 1072 switch (offset & 0x1f) { 1073 case 0x00: /* SSMUX */ 1074 s->ssmux[n] = value & 0x33333333; 1075 return; 1076 case 0x04: /* SSCTL */ 1077 if (value != 6) { 1078 hw_error("ADC: Unimplemented sequence %" PRIx64 "\n", 1079 value); 1080 } 1081 s->ssctl[n] = value; 1082 return; 1083 default: 1084 break; 1085 } 1086 } 1087 switch (offset) { 1088 case 0x00: /* ACTSS */ 1089 s->actss = value & 0xf; 1090 break; 1091 case 0x08: /* IM */ 1092 s->im = value; 1093 break; 1094 case 0x0c: /* ISC */ 1095 s->ris &= ~value; 1096 break; 1097 case 0x10: /* OSTAT */ 1098 s->ostat &= ~value; 1099 break; 1100 case 0x14: /* EMUX */ 1101 s->emux = value; 1102 break; 1103 case 0x18: /* USTAT */ 1104 s->ustat &= ~value; 1105 break; 1106 case 0x20: /* SSPRI */ 1107 s->sspri = value; 1108 break; 1109 case 0x28: /* PSSI */ 1110 hw_error("Not implemented: ADC sample initiate\n"); 1111 break; 1112 case 0x30: /* SAC */ 1113 s->sac = value; 1114 break; 1115 default: 1116 hw_error("stellaris_adc_write: Bad offset 0x%x\n", (int)offset); 1117 } 1118 stellaris_adc_update(s); 1119 } 1120 1121 static const MemoryRegionOps stellaris_adc_ops = { 1122 .read = stellaris_adc_read, 1123 .write = stellaris_adc_write, 1124 .endianness = DEVICE_NATIVE_ENDIAN, 1125 }; 1126 1127 static const VMStateDescription vmstate_stellaris_adc = { 1128 .name = "stellaris_adc", 1129 .version_id = 1, 1130 .minimum_version_id = 1, 1131 .fields = (VMStateField[]) { 1132 VMSTATE_UINT32(actss, stellaris_adc_state), 1133 VMSTATE_UINT32(ris, stellaris_adc_state), 1134 VMSTATE_UINT32(im, stellaris_adc_state), 1135 VMSTATE_UINT32(emux, stellaris_adc_state), 1136 VMSTATE_UINT32(ostat, stellaris_adc_state), 1137 VMSTATE_UINT32(ustat, stellaris_adc_state), 1138 VMSTATE_UINT32(sspri, stellaris_adc_state), 1139 VMSTATE_UINT32(sac, stellaris_adc_state), 1140 VMSTATE_UINT32(fifo[0].state, stellaris_adc_state), 1141 VMSTATE_UINT32_ARRAY(fifo[0].data, stellaris_adc_state, 16), 1142 VMSTATE_UINT32(ssmux[0], stellaris_adc_state), 1143 VMSTATE_UINT32(ssctl[0], stellaris_adc_state), 1144 VMSTATE_UINT32(fifo[1].state, stellaris_adc_state), 1145 VMSTATE_UINT32_ARRAY(fifo[1].data, stellaris_adc_state, 16), 1146 VMSTATE_UINT32(ssmux[1], stellaris_adc_state), 1147 VMSTATE_UINT32(ssctl[1], stellaris_adc_state), 1148 VMSTATE_UINT32(fifo[2].state, stellaris_adc_state), 1149 VMSTATE_UINT32_ARRAY(fifo[2].data, stellaris_adc_state, 16), 1150 VMSTATE_UINT32(ssmux[2], stellaris_adc_state), 1151 VMSTATE_UINT32(ssctl[2], stellaris_adc_state), 1152 VMSTATE_UINT32(fifo[3].state, stellaris_adc_state), 1153 VMSTATE_UINT32_ARRAY(fifo[3].data, stellaris_adc_state, 16), 1154 VMSTATE_UINT32(ssmux[3], stellaris_adc_state), 1155 VMSTATE_UINT32(ssctl[3], stellaris_adc_state), 1156 VMSTATE_UINT32(noise, stellaris_adc_state), 1157 VMSTATE_END_OF_LIST() 1158 } 1159 }; 1160 1161 static void stellaris_adc_init(Object *obj) 1162 { 1163 DeviceState *dev = DEVICE(obj); 1164 stellaris_adc_state *s = STELLARIS_ADC(obj); 1165 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 1166 int n; 1167 1168 for (n = 0; n < 4; n++) { 1169 sysbus_init_irq(sbd, &s->irq[n]); 1170 } 1171 1172 memory_region_init_io(&s->iomem, obj, &stellaris_adc_ops, s, 1173 "adc", 0x1000); 1174 sysbus_init_mmio(sbd, &s->iomem); 1175 stellaris_adc_reset(s); 1176 qdev_init_gpio_in(dev, stellaris_adc_trigger, 1); 1177 } 1178 1179 static 1180 void do_sys_reset(void *opaque, int n, int level) 1181 { 1182 if (level) { 1183 qemu_system_reset_request(); 1184 } 1185 } 1186 1187 /* Board init. */ 1188 static stellaris_board_info stellaris_boards[] = { 1189 { "LM3S811EVB", 1190 0, 1191 0x0032000e, 1192 0x001f001f, /* dc0 */ 1193 0x001132bf, 1194 0x01071013, 1195 0x3f0f01ff, 1196 0x0000001f, 1197 BP_OLED_I2C 1198 }, 1199 { "LM3S6965EVB", 1200 0x10010002, 1201 0x1073402e, 1202 0x00ff007f, /* dc0 */ 1203 0x001133ff, 1204 0x030f5317, 1205 0x0f0f87ff, 1206 0x5000007f, 1207 BP_OLED_SSI | BP_GAMEPAD 1208 } 1209 }; 1210 1211 static void stellaris_init(const char *kernel_filename, const char *cpu_model, 1212 stellaris_board_info *board) 1213 { 1214 static const int uart_irq[] = {5, 6, 33, 34}; 1215 static const int timer_irq[] = {19, 21, 23, 35}; 1216 static const uint32_t gpio_addr[7] = 1217 { 0x40004000, 0x40005000, 0x40006000, 0x40007000, 1218 0x40024000, 0x40025000, 0x40026000}; 1219 static const int gpio_irq[7] = {0, 1, 2, 3, 4, 30, 31}; 1220 1221 DeviceState *gpio_dev[7], *nvic; 1222 qemu_irq gpio_in[7][8]; 1223 qemu_irq gpio_out[7][8]; 1224 qemu_irq adc; 1225 int sram_size; 1226 int flash_size; 1227 I2CBus *i2c; 1228 DeviceState *dev; 1229 int i; 1230 int j; 1231 1232 MemoryRegion *sram = g_new(MemoryRegion, 1); 1233 MemoryRegion *flash = g_new(MemoryRegion, 1); 1234 MemoryRegion *system_memory = get_system_memory(); 1235 1236 flash_size = (((board->dc0 & 0xffff) + 1) << 1) * 1024; 1237 sram_size = ((board->dc0 >> 18) + 1) * 1024; 1238 1239 /* Flash programming is done via the SCU, so pretend it is ROM. */ 1240 memory_region_init_ram(flash, NULL, "stellaris.flash", flash_size, 1241 &error_fatal); 1242 vmstate_register_ram_global(flash); 1243 memory_region_set_readonly(flash, true); 1244 memory_region_add_subregion(system_memory, 0, flash); 1245 1246 memory_region_init_ram(sram, NULL, "stellaris.sram", sram_size, 1247 &error_fatal); 1248 vmstate_register_ram_global(sram); 1249 memory_region_add_subregion(system_memory, 0x20000000, sram); 1250 1251 nvic = armv7m_init(system_memory, flash_size, NUM_IRQ_LINES, 1252 kernel_filename, cpu_model); 1253 1254 qdev_connect_gpio_out_named(nvic, "SYSRESETREQ", 0, 1255 qemu_allocate_irq(&do_sys_reset, NULL, 0)); 1256 1257 if (board->dc1 & (1 << 16)) { 1258 dev = sysbus_create_varargs(TYPE_STELLARIS_ADC, 0x40038000, 1259 qdev_get_gpio_in(nvic, 14), 1260 qdev_get_gpio_in(nvic, 15), 1261 qdev_get_gpio_in(nvic, 16), 1262 qdev_get_gpio_in(nvic, 17), 1263 NULL); 1264 adc = qdev_get_gpio_in(dev, 0); 1265 } else { 1266 adc = NULL; 1267 } 1268 for (i = 0; i < 4; i++) { 1269 if (board->dc2 & (0x10000 << i)) { 1270 dev = sysbus_create_simple(TYPE_STELLARIS_GPTM, 1271 0x40030000 + i * 0x1000, 1272 qdev_get_gpio_in(nvic, timer_irq[i])); 1273 /* TODO: This is incorrect, but we get away with it because 1274 the ADC output is only ever pulsed. */ 1275 qdev_connect_gpio_out(dev, 0, adc); 1276 } 1277 } 1278 1279 stellaris_sys_init(0x400fe000, qdev_get_gpio_in(nvic, 28), 1280 board, nd_table[0].macaddr.a); 1281 1282 for (i = 0; i < 7; i++) { 1283 if (board->dc4 & (1 << i)) { 1284 gpio_dev[i] = sysbus_create_simple("pl061_luminary", gpio_addr[i], 1285 qdev_get_gpio_in(nvic, 1286 gpio_irq[i])); 1287 for (j = 0; j < 8; j++) { 1288 gpio_in[i][j] = qdev_get_gpio_in(gpio_dev[i], j); 1289 gpio_out[i][j] = NULL; 1290 } 1291 } 1292 } 1293 1294 if (board->dc2 & (1 << 12)) { 1295 dev = sysbus_create_simple(TYPE_STELLARIS_I2C, 0x40020000, 1296 qdev_get_gpio_in(nvic, 8)); 1297 i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c"); 1298 if (board->peripherals & BP_OLED_I2C) { 1299 i2c_create_slave(i2c, "ssd0303", 0x3d); 1300 } 1301 } 1302 1303 for (i = 0; i < 4; i++) { 1304 if (board->dc2 & (1 << i)) { 1305 sysbus_create_simple("pl011_luminary", 0x4000c000 + i * 0x1000, 1306 qdev_get_gpio_in(nvic, uart_irq[i])); 1307 } 1308 } 1309 if (board->dc2 & (1 << 4)) { 1310 dev = sysbus_create_simple("pl022", 0x40008000, 1311 qdev_get_gpio_in(nvic, 7)); 1312 if (board->peripherals & BP_OLED_SSI) { 1313 void *bus; 1314 DeviceState *sddev; 1315 DeviceState *ssddev; 1316 1317 /* Some boards have both an OLED controller and SD card connected to 1318 * the same SSI port, with the SD card chip select connected to a 1319 * GPIO pin. Technically the OLED chip select is connected to the 1320 * SSI Fss pin. We do not bother emulating that as both devices 1321 * should never be selected simultaneously, and our OLED controller 1322 * ignores stray 0xff commands that occur when deselecting the SD 1323 * card. 1324 */ 1325 bus = qdev_get_child_bus(dev, "ssi"); 1326 1327 sddev = ssi_create_slave(bus, "ssi-sd"); 1328 ssddev = ssi_create_slave(bus, "ssd0323"); 1329 gpio_out[GPIO_D][0] = qemu_irq_split( 1330 qdev_get_gpio_in_named(sddev, SSI_GPIO_CS, 0), 1331 qdev_get_gpio_in_named(ssddev, SSI_GPIO_CS, 0)); 1332 gpio_out[GPIO_C][7] = qdev_get_gpio_in(ssddev, 0); 1333 1334 /* Make sure the select pin is high. */ 1335 qemu_irq_raise(gpio_out[GPIO_D][0]); 1336 } 1337 } 1338 if (board->dc4 & (1 << 28)) { 1339 DeviceState *enet; 1340 1341 qemu_check_nic_model(&nd_table[0], "stellaris"); 1342 1343 enet = qdev_create(NULL, "stellaris_enet"); 1344 qdev_set_nic_properties(enet, &nd_table[0]); 1345 qdev_init_nofail(enet); 1346 sysbus_mmio_map(SYS_BUS_DEVICE(enet), 0, 0x40048000); 1347 sysbus_connect_irq(SYS_BUS_DEVICE(enet), 0, qdev_get_gpio_in(nvic, 42)); 1348 } 1349 if (board->peripherals & BP_GAMEPAD) { 1350 qemu_irq gpad_irq[5]; 1351 static const int gpad_keycode[5] = { 0xc8, 0xd0, 0xcb, 0xcd, 0x1d }; 1352 1353 gpad_irq[0] = qemu_irq_invert(gpio_in[GPIO_E][0]); /* up */ 1354 gpad_irq[1] = qemu_irq_invert(gpio_in[GPIO_E][1]); /* down */ 1355 gpad_irq[2] = qemu_irq_invert(gpio_in[GPIO_E][2]); /* left */ 1356 gpad_irq[3] = qemu_irq_invert(gpio_in[GPIO_E][3]); /* right */ 1357 gpad_irq[4] = qemu_irq_invert(gpio_in[GPIO_F][1]); /* select */ 1358 1359 stellaris_gamepad_init(5, gpad_irq, gpad_keycode); 1360 } 1361 for (i = 0; i < 7; i++) { 1362 if (board->dc4 & (1 << i)) { 1363 for (j = 0; j < 8; j++) { 1364 if (gpio_out[i][j]) { 1365 qdev_connect_gpio_out(gpio_dev[i], j, gpio_out[i][j]); 1366 } 1367 } 1368 } 1369 } 1370 } 1371 1372 /* FIXME: Figure out how to generate these from stellaris_boards. */ 1373 static void lm3s811evb_init(MachineState *machine) 1374 { 1375 const char *cpu_model = machine->cpu_model; 1376 const char *kernel_filename = machine->kernel_filename; 1377 stellaris_init(kernel_filename, cpu_model, &stellaris_boards[0]); 1378 } 1379 1380 static void lm3s6965evb_init(MachineState *machine) 1381 { 1382 const char *cpu_model = machine->cpu_model; 1383 const char *kernel_filename = machine->kernel_filename; 1384 stellaris_init(kernel_filename, cpu_model, &stellaris_boards[1]); 1385 } 1386 1387 static void lm3s811evb_class_init(ObjectClass *oc, void *data) 1388 { 1389 MachineClass *mc = MACHINE_CLASS(oc); 1390 1391 mc->desc = "Stellaris LM3S811EVB"; 1392 mc->init = lm3s811evb_init; 1393 } 1394 1395 static const TypeInfo lm3s811evb_type = { 1396 .name = MACHINE_TYPE_NAME("lm3s811evb"), 1397 .parent = TYPE_MACHINE, 1398 .class_init = lm3s811evb_class_init, 1399 }; 1400 1401 static void lm3s6965evb_class_init(ObjectClass *oc, void *data) 1402 { 1403 MachineClass *mc = MACHINE_CLASS(oc); 1404 1405 mc->desc = "Stellaris LM3S6965EVB"; 1406 mc->init = lm3s6965evb_init; 1407 } 1408 1409 static const TypeInfo lm3s6965evb_type = { 1410 .name = MACHINE_TYPE_NAME("lm3s6965evb"), 1411 .parent = TYPE_MACHINE, 1412 .class_init = lm3s6965evb_class_init, 1413 }; 1414 1415 static void stellaris_machine_init(void) 1416 { 1417 type_register_static(&lm3s811evb_type); 1418 type_register_static(&lm3s6965evb_type); 1419 } 1420 1421 type_init(stellaris_machine_init) 1422 1423 static void stellaris_i2c_class_init(ObjectClass *klass, void *data) 1424 { 1425 DeviceClass *dc = DEVICE_CLASS(klass); 1426 1427 dc->vmsd = &vmstate_stellaris_i2c; 1428 } 1429 1430 static const TypeInfo stellaris_i2c_info = { 1431 .name = TYPE_STELLARIS_I2C, 1432 .parent = TYPE_SYS_BUS_DEVICE, 1433 .instance_size = sizeof(stellaris_i2c_state), 1434 .instance_init = stellaris_i2c_init, 1435 .class_init = stellaris_i2c_class_init, 1436 }; 1437 1438 static void stellaris_gptm_class_init(ObjectClass *klass, void *data) 1439 { 1440 DeviceClass *dc = DEVICE_CLASS(klass); 1441 1442 dc->vmsd = &vmstate_stellaris_gptm; 1443 } 1444 1445 static const TypeInfo stellaris_gptm_info = { 1446 .name = TYPE_STELLARIS_GPTM, 1447 .parent = TYPE_SYS_BUS_DEVICE, 1448 .instance_size = sizeof(gptm_state), 1449 .instance_init = stellaris_gptm_init, 1450 .class_init = stellaris_gptm_class_init, 1451 }; 1452 1453 static void stellaris_adc_class_init(ObjectClass *klass, void *data) 1454 { 1455 DeviceClass *dc = DEVICE_CLASS(klass); 1456 1457 dc->vmsd = &vmstate_stellaris_adc; 1458 } 1459 1460 static const TypeInfo stellaris_adc_info = { 1461 .name = TYPE_STELLARIS_ADC, 1462 .parent = TYPE_SYS_BUS_DEVICE, 1463 .instance_size = sizeof(stellaris_adc_state), 1464 .instance_init = stellaris_adc_init, 1465 .class_init = stellaris_adc_class_init, 1466 }; 1467 1468 static void stellaris_register_types(void) 1469 { 1470 type_register_static(&stellaris_i2c_info); 1471 type_register_static(&stellaris_gptm_info); 1472 type_register_static(&stellaris_adc_info); 1473 } 1474 1475 type_init(stellaris_register_types) 1476