1 /* 2 * Luminary Micro Stellaris peripherals 3 * 4 * Copyright (c) 2006 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qapi/error.h" 12 #include "hw/core/split-irq.h" 13 #include "hw/sysbus.h" 14 #include "hw/sd/sd.h" 15 #include "hw/ssi/ssi.h" 16 #include "hw/arm/boot.h" 17 #include "qemu/timer.h" 18 #include "hw/i2c/i2c.h" 19 #include "net/net.h" 20 #include "hw/boards.h" 21 #include "qemu/log.h" 22 #include "exec/address-spaces.h" 23 #include "sysemu/sysemu.h" 24 #include "hw/arm/armv7m.h" 25 #include "hw/char/pl011.h" 26 #include "hw/input/gamepad.h" 27 #include "hw/irq.h" 28 #include "hw/watchdog/cmsdk-apb-watchdog.h" 29 #include "migration/vmstate.h" 30 #include "hw/misc/unimp.h" 31 #include "hw/timer/stellaris-gptm.h" 32 #include "hw/qdev-clock.h" 33 #include "qom/object.h" 34 35 #define GPIO_A 0 36 #define GPIO_B 1 37 #define GPIO_C 2 38 #define GPIO_D 3 39 #define GPIO_E 4 40 #define GPIO_F 5 41 #define GPIO_G 6 42 43 #define BP_OLED_I2C 0x01 44 #define BP_OLED_SSI 0x02 45 #define BP_GAMEPAD 0x04 46 47 #define NUM_IRQ_LINES 64 48 49 typedef const struct { 50 const char *name; 51 uint32_t did0; 52 uint32_t did1; 53 uint32_t dc0; 54 uint32_t dc1; 55 uint32_t dc2; 56 uint32_t dc3; 57 uint32_t dc4; 58 uint32_t peripherals; 59 } stellaris_board_info; 60 61 /* System controller. */ 62 63 #define TYPE_STELLARIS_SYS "stellaris-sys" 64 OBJECT_DECLARE_SIMPLE_TYPE(ssys_state, STELLARIS_SYS) 65 66 struct ssys_state { 67 SysBusDevice parent_obj; 68 69 MemoryRegion iomem; 70 uint32_t pborctl; 71 uint32_t ldopctl; 72 uint32_t int_status; 73 uint32_t int_mask; 74 uint32_t resc; 75 uint32_t rcc; 76 uint32_t rcc2; 77 uint32_t rcgc[3]; 78 uint32_t scgc[3]; 79 uint32_t dcgc[3]; 80 uint32_t clkvclr; 81 uint32_t ldoarst; 82 qemu_irq irq; 83 Clock *sysclk; 84 /* Properties (all read-only registers) */ 85 uint32_t user0; 86 uint32_t user1; 87 uint32_t did0; 88 uint32_t did1; 89 uint32_t dc0; 90 uint32_t dc1; 91 uint32_t dc2; 92 uint32_t dc3; 93 uint32_t dc4; 94 }; 95 96 static void ssys_update(ssys_state *s) 97 { 98 qemu_set_irq(s->irq, (s->int_status & s->int_mask) != 0); 99 } 100 101 static uint32_t pllcfg_sandstorm[16] = { 102 0x31c0, /* 1 Mhz */ 103 0x1ae0, /* 1.8432 Mhz */ 104 0x18c0, /* 2 Mhz */ 105 0xd573, /* 2.4576 Mhz */ 106 0x37a6, /* 3.57954 Mhz */ 107 0x1ae2, /* 3.6864 Mhz */ 108 0x0c40, /* 4 Mhz */ 109 0x98bc, /* 4.906 Mhz */ 110 0x935b, /* 4.9152 Mhz */ 111 0x09c0, /* 5 Mhz */ 112 0x4dee, /* 5.12 Mhz */ 113 0x0c41, /* 6 Mhz */ 114 0x75db, /* 6.144 Mhz */ 115 0x1ae6, /* 7.3728 Mhz */ 116 0x0600, /* 8 Mhz */ 117 0x585b /* 8.192 Mhz */ 118 }; 119 120 static uint32_t pllcfg_fury[16] = { 121 0x3200, /* 1 Mhz */ 122 0x1b20, /* 1.8432 Mhz */ 123 0x1900, /* 2 Mhz */ 124 0xf42b, /* 2.4576 Mhz */ 125 0x37e3, /* 3.57954 Mhz */ 126 0x1b21, /* 3.6864 Mhz */ 127 0x0c80, /* 4 Mhz */ 128 0x98ee, /* 4.906 Mhz */ 129 0xd5b4, /* 4.9152 Mhz */ 130 0x0a00, /* 5 Mhz */ 131 0x4e27, /* 5.12 Mhz */ 132 0x1902, /* 6 Mhz */ 133 0xec1c, /* 6.144 Mhz */ 134 0x1b23, /* 7.3728 Mhz */ 135 0x0640, /* 8 Mhz */ 136 0xb11c /* 8.192 Mhz */ 137 }; 138 139 #define DID0_VER_MASK 0x70000000 140 #define DID0_VER_0 0x00000000 141 #define DID0_VER_1 0x10000000 142 143 #define DID0_CLASS_MASK 0x00FF0000 144 #define DID0_CLASS_SANDSTORM 0x00000000 145 #define DID0_CLASS_FURY 0x00010000 146 147 static int ssys_board_class(const ssys_state *s) 148 { 149 uint32_t did0 = s->did0; 150 switch (did0 & DID0_VER_MASK) { 151 case DID0_VER_0: 152 return DID0_CLASS_SANDSTORM; 153 case DID0_VER_1: 154 switch (did0 & DID0_CLASS_MASK) { 155 case DID0_CLASS_SANDSTORM: 156 case DID0_CLASS_FURY: 157 return did0 & DID0_CLASS_MASK; 158 } 159 /* for unknown classes, fall through */ 160 default: 161 /* This can only happen if the hardwired constant did0 value 162 * in this board's stellaris_board_info struct is wrong. 163 */ 164 g_assert_not_reached(); 165 } 166 } 167 168 static uint64_t ssys_read(void *opaque, hwaddr offset, 169 unsigned size) 170 { 171 ssys_state *s = (ssys_state *)opaque; 172 173 switch (offset) { 174 case 0x000: /* DID0 */ 175 return s->did0; 176 case 0x004: /* DID1 */ 177 return s->did1; 178 case 0x008: /* DC0 */ 179 return s->dc0; 180 case 0x010: /* DC1 */ 181 return s->dc1; 182 case 0x014: /* DC2 */ 183 return s->dc2; 184 case 0x018: /* DC3 */ 185 return s->dc3; 186 case 0x01c: /* DC4 */ 187 return s->dc4; 188 case 0x030: /* PBORCTL */ 189 return s->pborctl; 190 case 0x034: /* LDOPCTL */ 191 return s->ldopctl; 192 case 0x040: /* SRCR0 */ 193 return 0; 194 case 0x044: /* SRCR1 */ 195 return 0; 196 case 0x048: /* SRCR2 */ 197 return 0; 198 case 0x050: /* RIS */ 199 return s->int_status; 200 case 0x054: /* IMC */ 201 return s->int_mask; 202 case 0x058: /* MISC */ 203 return s->int_status & s->int_mask; 204 case 0x05c: /* RESC */ 205 return s->resc; 206 case 0x060: /* RCC */ 207 return s->rcc; 208 case 0x064: /* PLLCFG */ 209 { 210 int xtal; 211 xtal = (s->rcc >> 6) & 0xf; 212 switch (ssys_board_class(s)) { 213 case DID0_CLASS_FURY: 214 return pllcfg_fury[xtal]; 215 case DID0_CLASS_SANDSTORM: 216 return pllcfg_sandstorm[xtal]; 217 default: 218 g_assert_not_reached(); 219 } 220 } 221 case 0x070: /* RCC2 */ 222 return s->rcc2; 223 case 0x100: /* RCGC0 */ 224 return s->rcgc[0]; 225 case 0x104: /* RCGC1 */ 226 return s->rcgc[1]; 227 case 0x108: /* RCGC2 */ 228 return s->rcgc[2]; 229 case 0x110: /* SCGC0 */ 230 return s->scgc[0]; 231 case 0x114: /* SCGC1 */ 232 return s->scgc[1]; 233 case 0x118: /* SCGC2 */ 234 return s->scgc[2]; 235 case 0x120: /* DCGC0 */ 236 return s->dcgc[0]; 237 case 0x124: /* DCGC1 */ 238 return s->dcgc[1]; 239 case 0x128: /* DCGC2 */ 240 return s->dcgc[2]; 241 case 0x150: /* CLKVCLR */ 242 return s->clkvclr; 243 case 0x160: /* LDOARST */ 244 return s->ldoarst; 245 case 0x1e0: /* USER0 */ 246 return s->user0; 247 case 0x1e4: /* USER1 */ 248 return s->user1; 249 default: 250 qemu_log_mask(LOG_GUEST_ERROR, 251 "SSYS: read at bad offset 0x%x\n", (int)offset); 252 return 0; 253 } 254 } 255 256 static bool ssys_use_rcc2(ssys_state *s) 257 { 258 return (s->rcc2 >> 31) & 0x1; 259 } 260 261 /* 262 * Calculate the system clock period. We only want to propagate 263 * this change to the rest of the system if we're not being called 264 * from migration post-load. 265 */ 266 static void ssys_calculate_system_clock(ssys_state *s, bool propagate_clock) 267 { 268 int period_ns; 269 /* 270 * SYSDIV field specifies divisor: 0 == /1, 1 == /2, etc. Input 271 * clock is 200MHz, which is a period of 5 ns. Dividing the clock 272 * frequency by X is the same as multiplying the period by X. 273 */ 274 if (ssys_use_rcc2(s)) { 275 period_ns = 5 * (((s->rcc2 >> 23) & 0x3f) + 1); 276 } else { 277 period_ns = 5 * (((s->rcc >> 23) & 0xf) + 1); 278 } 279 clock_set_ns(s->sysclk, period_ns); 280 if (propagate_clock) { 281 clock_propagate(s->sysclk); 282 } 283 } 284 285 static void ssys_write(void *opaque, hwaddr offset, 286 uint64_t value, unsigned size) 287 { 288 ssys_state *s = (ssys_state *)opaque; 289 290 switch (offset) { 291 case 0x030: /* PBORCTL */ 292 s->pborctl = value & 0xffff; 293 break; 294 case 0x034: /* LDOPCTL */ 295 s->ldopctl = value & 0x1f; 296 break; 297 case 0x040: /* SRCR0 */ 298 case 0x044: /* SRCR1 */ 299 case 0x048: /* SRCR2 */ 300 qemu_log_mask(LOG_UNIMP, "Peripheral reset not implemented\n"); 301 break; 302 case 0x054: /* IMC */ 303 s->int_mask = value & 0x7f; 304 break; 305 case 0x058: /* MISC */ 306 s->int_status &= ~value; 307 break; 308 case 0x05c: /* RESC */ 309 s->resc = value & 0x3f; 310 break; 311 case 0x060: /* RCC */ 312 if ((s->rcc & (1 << 13)) != 0 && (value & (1 << 13)) == 0) { 313 /* PLL enable. */ 314 s->int_status |= (1 << 6); 315 } 316 s->rcc = value; 317 ssys_calculate_system_clock(s, true); 318 break; 319 case 0x070: /* RCC2 */ 320 if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) { 321 break; 322 } 323 324 if ((s->rcc2 & (1 << 13)) != 0 && (value & (1 << 13)) == 0) { 325 /* PLL enable. */ 326 s->int_status |= (1 << 6); 327 } 328 s->rcc2 = value; 329 ssys_calculate_system_clock(s, true); 330 break; 331 case 0x100: /* RCGC0 */ 332 s->rcgc[0] = value; 333 break; 334 case 0x104: /* RCGC1 */ 335 s->rcgc[1] = value; 336 break; 337 case 0x108: /* RCGC2 */ 338 s->rcgc[2] = value; 339 break; 340 case 0x110: /* SCGC0 */ 341 s->scgc[0] = value; 342 break; 343 case 0x114: /* SCGC1 */ 344 s->scgc[1] = value; 345 break; 346 case 0x118: /* SCGC2 */ 347 s->scgc[2] = value; 348 break; 349 case 0x120: /* DCGC0 */ 350 s->dcgc[0] = value; 351 break; 352 case 0x124: /* DCGC1 */ 353 s->dcgc[1] = value; 354 break; 355 case 0x128: /* DCGC2 */ 356 s->dcgc[2] = value; 357 break; 358 case 0x150: /* CLKVCLR */ 359 s->clkvclr = value; 360 break; 361 case 0x160: /* LDOARST */ 362 s->ldoarst = value; 363 break; 364 default: 365 qemu_log_mask(LOG_GUEST_ERROR, 366 "SSYS: write at bad offset 0x%x\n", (int)offset); 367 } 368 ssys_update(s); 369 } 370 371 static const MemoryRegionOps ssys_ops = { 372 .read = ssys_read, 373 .write = ssys_write, 374 .endianness = DEVICE_NATIVE_ENDIAN, 375 }; 376 377 static void stellaris_sys_reset_enter(Object *obj, ResetType type) 378 { 379 ssys_state *s = STELLARIS_SYS(obj); 380 381 s->pborctl = 0x7ffd; 382 s->rcc = 0x078e3ac0; 383 384 if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) { 385 s->rcc2 = 0; 386 } else { 387 s->rcc2 = 0x07802810; 388 } 389 s->rcgc[0] = 1; 390 s->scgc[0] = 1; 391 s->dcgc[0] = 1; 392 } 393 394 static void stellaris_sys_reset_hold(Object *obj) 395 { 396 ssys_state *s = STELLARIS_SYS(obj); 397 398 /* OK to propagate clocks from the hold phase */ 399 ssys_calculate_system_clock(s, true); 400 } 401 402 static void stellaris_sys_reset_exit(Object *obj) 403 { 404 } 405 406 static int stellaris_sys_post_load(void *opaque, int version_id) 407 { 408 ssys_state *s = opaque; 409 410 ssys_calculate_system_clock(s, false); 411 412 return 0; 413 } 414 415 static const VMStateDescription vmstate_stellaris_sys = { 416 .name = "stellaris_sys", 417 .version_id = 2, 418 .minimum_version_id = 1, 419 .post_load = stellaris_sys_post_load, 420 .fields = (VMStateField[]) { 421 VMSTATE_UINT32(pborctl, ssys_state), 422 VMSTATE_UINT32(ldopctl, ssys_state), 423 VMSTATE_UINT32(int_mask, ssys_state), 424 VMSTATE_UINT32(int_status, ssys_state), 425 VMSTATE_UINT32(resc, ssys_state), 426 VMSTATE_UINT32(rcc, ssys_state), 427 VMSTATE_UINT32_V(rcc2, ssys_state, 2), 428 VMSTATE_UINT32_ARRAY(rcgc, ssys_state, 3), 429 VMSTATE_UINT32_ARRAY(scgc, ssys_state, 3), 430 VMSTATE_UINT32_ARRAY(dcgc, ssys_state, 3), 431 VMSTATE_UINT32(clkvclr, ssys_state), 432 VMSTATE_UINT32(ldoarst, ssys_state), 433 /* No field for sysclk -- handled in post-load instead */ 434 VMSTATE_END_OF_LIST() 435 } 436 }; 437 438 static Property stellaris_sys_properties[] = { 439 DEFINE_PROP_UINT32("user0", ssys_state, user0, 0), 440 DEFINE_PROP_UINT32("user1", ssys_state, user1, 0), 441 DEFINE_PROP_UINT32("did0", ssys_state, did0, 0), 442 DEFINE_PROP_UINT32("did1", ssys_state, did1, 0), 443 DEFINE_PROP_UINT32("dc0", ssys_state, dc0, 0), 444 DEFINE_PROP_UINT32("dc1", ssys_state, dc1, 0), 445 DEFINE_PROP_UINT32("dc2", ssys_state, dc2, 0), 446 DEFINE_PROP_UINT32("dc3", ssys_state, dc3, 0), 447 DEFINE_PROP_UINT32("dc4", ssys_state, dc4, 0), 448 DEFINE_PROP_END_OF_LIST() 449 }; 450 451 static void stellaris_sys_instance_init(Object *obj) 452 { 453 ssys_state *s = STELLARIS_SYS(obj); 454 SysBusDevice *sbd = SYS_BUS_DEVICE(s); 455 456 memory_region_init_io(&s->iomem, obj, &ssys_ops, s, "ssys", 0x00001000); 457 sysbus_init_mmio(sbd, &s->iomem); 458 sysbus_init_irq(sbd, &s->irq); 459 s->sysclk = qdev_init_clock_out(DEVICE(s), "SYSCLK"); 460 } 461 462 /* I2C controller. */ 463 464 #define TYPE_STELLARIS_I2C "stellaris-i2c" 465 OBJECT_DECLARE_SIMPLE_TYPE(stellaris_i2c_state, STELLARIS_I2C) 466 467 struct stellaris_i2c_state { 468 SysBusDevice parent_obj; 469 470 I2CBus *bus; 471 qemu_irq irq; 472 MemoryRegion iomem; 473 uint32_t msa; 474 uint32_t mcs; 475 uint32_t mdr; 476 uint32_t mtpr; 477 uint32_t mimr; 478 uint32_t mris; 479 uint32_t mcr; 480 }; 481 482 #define STELLARIS_I2C_MCS_BUSY 0x01 483 #define STELLARIS_I2C_MCS_ERROR 0x02 484 #define STELLARIS_I2C_MCS_ADRACK 0x04 485 #define STELLARIS_I2C_MCS_DATACK 0x08 486 #define STELLARIS_I2C_MCS_ARBLST 0x10 487 #define STELLARIS_I2C_MCS_IDLE 0x20 488 #define STELLARIS_I2C_MCS_BUSBSY 0x40 489 490 static uint64_t stellaris_i2c_read(void *opaque, hwaddr offset, 491 unsigned size) 492 { 493 stellaris_i2c_state *s = (stellaris_i2c_state *)opaque; 494 495 switch (offset) { 496 case 0x00: /* MSA */ 497 return s->msa; 498 case 0x04: /* MCS */ 499 /* We don't emulate timing, so the controller is never busy. */ 500 return s->mcs | STELLARIS_I2C_MCS_IDLE; 501 case 0x08: /* MDR */ 502 return s->mdr; 503 case 0x0c: /* MTPR */ 504 return s->mtpr; 505 case 0x10: /* MIMR */ 506 return s->mimr; 507 case 0x14: /* MRIS */ 508 return s->mris; 509 case 0x18: /* MMIS */ 510 return s->mris & s->mimr; 511 case 0x20: /* MCR */ 512 return s->mcr; 513 default: 514 qemu_log_mask(LOG_GUEST_ERROR, 515 "stellaris_i2c: read at bad offset 0x%x\n", (int)offset); 516 return 0; 517 } 518 } 519 520 static void stellaris_i2c_update(stellaris_i2c_state *s) 521 { 522 int level; 523 524 level = (s->mris & s->mimr) != 0; 525 qemu_set_irq(s->irq, level); 526 } 527 528 static void stellaris_i2c_write(void *opaque, hwaddr offset, 529 uint64_t value, unsigned size) 530 { 531 stellaris_i2c_state *s = (stellaris_i2c_state *)opaque; 532 533 switch (offset) { 534 case 0x00: /* MSA */ 535 s->msa = value & 0xff; 536 break; 537 case 0x04: /* MCS */ 538 if ((s->mcr & 0x10) == 0) { 539 /* Disabled. Do nothing. */ 540 break; 541 } 542 /* Grab the bus if this is starting a transfer. */ 543 if ((value & 2) && (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) { 544 if (i2c_start_transfer(s->bus, s->msa >> 1, s->msa & 1)) { 545 s->mcs |= STELLARIS_I2C_MCS_ARBLST; 546 } else { 547 s->mcs &= ~STELLARIS_I2C_MCS_ARBLST; 548 s->mcs |= STELLARIS_I2C_MCS_BUSBSY; 549 } 550 } 551 /* If we don't have the bus then indicate an error. */ 552 if (!i2c_bus_busy(s->bus) 553 || (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) { 554 s->mcs |= STELLARIS_I2C_MCS_ERROR; 555 break; 556 } 557 s->mcs &= ~STELLARIS_I2C_MCS_ERROR; 558 if (value & 1) { 559 /* Transfer a byte. */ 560 /* TODO: Handle errors. */ 561 if (s->msa & 1) { 562 /* Recv */ 563 s->mdr = i2c_recv(s->bus); 564 } else { 565 /* Send */ 566 i2c_send(s->bus, s->mdr); 567 } 568 /* Raise an interrupt. */ 569 s->mris |= 1; 570 } 571 if (value & 4) { 572 /* Finish transfer. */ 573 i2c_end_transfer(s->bus); 574 s->mcs &= ~STELLARIS_I2C_MCS_BUSBSY; 575 } 576 break; 577 case 0x08: /* MDR */ 578 s->mdr = value & 0xff; 579 break; 580 case 0x0c: /* MTPR */ 581 s->mtpr = value & 0xff; 582 break; 583 case 0x10: /* MIMR */ 584 s->mimr = 1; 585 break; 586 case 0x1c: /* MICR */ 587 s->mris &= ~value; 588 break; 589 case 0x20: /* MCR */ 590 if (value & 1) { 591 qemu_log_mask(LOG_UNIMP, 592 "stellaris_i2c: Loopback not implemented\n"); 593 } 594 if (value & 0x20) { 595 qemu_log_mask(LOG_UNIMP, 596 "stellaris_i2c: Slave mode not implemented\n"); 597 } 598 s->mcr = value & 0x31; 599 break; 600 default: 601 qemu_log_mask(LOG_GUEST_ERROR, 602 "stellaris_i2c: write at bad offset 0x%x\n", (int)offset); 603 } 604 stellaris_i2c_update(s); 605 } 606 607 static void stellaris_i2c_reset(stellaris_i2c_state *s) 608 { 609 if (s->mcs & STELLARIS_I2C_MCS_BUSBSY) 610 i2c_end_transfer(s->bus); 611 612 s->msa = 0; 613 s->mcs = 0; 614 s->mdr = 0; 615 s->mtpr = 1; 616 s->mimr = 0; 617 s->mris = 0; 618 s->mcr = 0; 619 stellaris_i2c_update(s); 620 } 621 622 static const MemoryRegionOps stellaris_i2c_ops = { 623 .read = stellaris_i2c_read, 624 .write = stellaris_i2c_write, 625 .endianness = DEVICE_NATIVE_ENDIAN, 626 }; 627 628 static const VMStateDescription vmstate_stellaris_i2c = { 629 .name = "stellaris_i2c", 630 .version_id = 1, 631 .minimum_version_id = 1, 632 .fields = (VMStateField[]) { 633 VMSTATE_UINT32(msa, stellaris_i2c_state), 634 VMSTATE_UINT32(mcs, stellaris_i2c_state), 635 VMSTATE_UINT32(mdr, stellaris_i2c_state), 636 VMSTATE_UINT32(mtpr, stellaris_i2c_state), 637 VMSTATE_UINT32(mimr, stellaris_i2c_state), 638 VMSTATE_UINT32(mris, stellaris_i2c_state), 639 VMSTATE_UINT32(mcr, stellaris_i2c_state), 640 VMSTATE_END_OF_LIST() 641 } 642 }; 643 644 static void stellaris_i2c_init(Object *obj) 645 { 646 DeviceState *dev = DEVICE(obj); 647 stellaris_i2c_state *s = STELLARIS_I2C(obj); 648 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 649 I2CBus *bus; 650 651 sysbus_init_irq(sbd, &s->irq); 652 bus = i2c_init_bus(dev, "i2c"); 653 s->bus = bus; 654 655 memory_region_init_io(&s->iomem, obj, &stellaris_i2c_ops, s, 656 "i2c", 0x1000); 657 sysbus_init_mmio(sbd, &s->iomem); 658 /* ??? For now we only implement the master interface. */ 659 stellaris_i2c_reset(s); 660 } 661 662 /* Analogue to Digital Converter. This is only partially implemented, 663 enough for applications that use a combined ADC and timer tick. */ 664 665 #define STELLARIS_ADC_EM_CONTROLLER 0 666 #define STELLARIS_ADC_EM_COMP 1 667 #define STELLARIS_ADC_EM_EXTERNAL 4 668 #define STELLARIS_ADC_EM_TIMER 5 669 #define STELLARIS_ADC_EM_PWM0 6 670 #define STELLARIS_ADC_EM_PWM1 7 671 #define STELLARIS_ADC_EM_PWM2 8 672 673 #define STELLARIS_ADC_FIFO_EMPTY 0x0100 674 #define STELLARIS_ADC_FIFO_FULL 0x1000 675 676 #define TYPE_STELLARIS_ADC "stellaris-adc" 677 typedef struct StellarisADCState StellarisADCState; 678 DECLARE_INSTANCE_CHECKER(StellarisADCState, STELLARIS_ADC, TYPE_STELLARIS_ADC) 679 680 struct StellarisADCState { 681 SysBusDevice parent_obj; 682 683 MemoryRegion iomem; 684 uint32_t actss; 685 uint32_t ris; 686 uint32_t im; 687 uint32_t emux; 688 uint32_t ostat; 689 uint32_t ustat; 690 uint32_t sspri; 691 uint32_t sac; 692 struct { 693 uint32_t state; 694 uint32_t data[16]; 695 } fifo[4]; 696 uint32_t ssmux[4]; 697 uint32_t ssctl[4]; 698 uint32_t noise; 699 qemu_irq irq[4]; 700 }; 701 702 static uint32_t stellaris_adc_fifo_read(StellarisADCState *s, int n) 703 { 704 int tail; 705 706 tail = s->fifo[n].state & 0xf; 707 if (s->fifo[n].state & STELLARIS_ADC_FIFO_EMPTY) { 708 s->ustat |= 1 << n; 709 } else { 710 s->fifo[n].state = (s->fifo[n].state & ~0xf) | ((tail + 1) & 0xf); 711 s->fifo[n].state &= ~STELLARIS_ADC_FIFO_FULL; 712 if (tail + 1 == ((s->fifo[n].state >> 4) & 0xf)) 713 s->fifo[n].state |= STELLARIS_ADC_FIFO_EMPTY; 714 } 715 return s->fifo[n].data[tail]; 716 } 717 718 static void stellaris_adc_fifo_write(StellarisADCState *s, int n, 719 uint32_t value) 720 { 721 int head; 722 723 /* TODO: Real hardware has limited size FIFOs. We have a full 16 entry 724 FIFO fir each sequencer. */ 725 head = (s->fifo[n].state >> 4) & 0xf; 726 if (s->fifo[n].state & STELLARIS_ADC_FIFO_FULL) { 727 s->ostat |= 1 << n; 728 return; 729 } 730 s->fifo[n].data[head] = value; 731 head = (head + 1) & 0xf; 732 s->fifo[n].state &= ~STELLARIS_ADC_FIFO_EMPTY; 733 s->fifo[n].state = (s->fifo[n].state & ~0xf0) | (head << 4); 734 if ((s->fifo[n].state & 0xf) == head) 735 s->fifo[n].state |= STELLARIS_ADC_FIFO_FULL; 736 } 737 738 static void stellaris_adc_update(StellarisADCState *s) 739 { 740 int level; 741 int n; 742 743 for (n = 0; n < 4; n++) { 744 level = (s->ris & s->im & (1 << n)) != 0; 745 qemu_set_irq(s->irq[n], level); 746 } 747 } 748 749 static void stellaris_adc_trigger(void *opaque, int irq, int level) 750 { 751 StellarisADCState *s = opaque; 752 int n; 753 754 for (n = 0; n < 4; n++) { 755 if ((s->actss & (1 << n)) == 0) { 756 continue; 757 } 758 759 if (((s->emux >> (n * 4)) & 0xff) != 5) { 760 continue; 761 } 762 763 /* Some applications use the ADC as a random number source, so introduce 764 some variation into the signal. */ 765 s->noise = s->noise * 314159 + 1; 766 /* ??? actual inputs not implemented. Return an arbitrary value. */ 767 stellaris_adc_fifo_write(s, n, 0x200 + ((s->noise >> 16) & 7)); 768 s->ris |= (1 << n); 769 stellaris_adc_update(s); 770 } 771 } 772 773 static void stellaris_adc_reset(StellarisADCState *s) 774 { 775 int n; 776 777 for (n = 0; n < 4; n++) { 778 s->ssmux[n] = 0; 779 s->ssctl[n] = 0; 780 s->fifo[n].state = STELLARIS_ADC_FIFO_EMPTY; 781 } 782 } 783 784 static uint64_t stellaris_adc_read(void *opaque, hwaddr offset, 785 unsigned size) 786 { 787 StellarisADCState *s = opaque; 788 789 /* TODO: Implement this. */ 790 if (offset >= 0x40 && offset < 0xc0) { 791 int n; 792 n = (offset - 0x40) >> 5; 793 switch (offset & 0x1f) { 794 case 0x00: /* SSMUX */ 795 return s->ssmux[n]; 796 case 0x04: /* SSCTL */ 797 return s->ssctl[n]; 798 case 0x08: /* SSFIFO */ 799 return stellaris_adc_fifo_read(s, n); 800 case 0x0c: /* SSFSTAT */ 801 return s->fifo[n].state; 802 default: 803 break; 804 } 805 } 806 switch (offset) { 807 case 0x00: /* ACTSS */ 808 return s->actss; 809 case 0x04: /* RIS */ 810 return s->ris; 811 case 0x08: /* IM */ 812 return s->im; 813 case 0x0c: /* ISC */ 814 return s->ris & s->im; 815 case 0x10: /* OSTAT */ 816 return s->ostat; 817 case 0x14: /* EMUX */ 818 return s->emux; 819 case 0x18: /* USTAT */ 820 return s->ustat; 821 case 0x20: /* SSPRI */ 822 return s->sspri; 823 case 0x30: /* SAC */ 824 return s->sac; 825 default: 826 qemu_log_mask(LOG_GUEST_ERROR, 827 "stellaris_adc: read at bad offset 0x%x\n", (int)offset); 828 return 0; 829 } 830 } 831 832 static void stellaris_adc_write(void *opaque, hwaddr offset, 833 uint64_t value, unsigned size) 834 { 835 StellarisADCState *s = opaque; 836 837 /* TODO: Implement this. */ 838 if (offset >= 0x40 && offset < 0xc0) { 839 int n; 840 n = (offset - 0x40) >> 5; 841 switch (offset & 0x1f) { 842 case 0x00: /* SSMUX */ 843 s->ssmux[n] = value & 0x33333333; 844 return; 845 case 0x04: /* SSCTL */ 846 if (value != 6) { 847 qemu_log_mask(LOG_UNIMP, 848 "ADC: Unimplemented sequence %" PRIx64 "\n", 849 value); 850 } 851 s->ssctl[n] = value; 852 return; 853 default: 854 break; 855 } 856 } 857 switch (offset) { 858 case 0x00: /* ACTSS */ 859 s->actss = value & 0xf; 860 break; 861 case 0x08: /* IM */ 862 s->im = value; 863 break; 864 case 0x0c: /* ISC */ 865 s->ris &= ~value; 866 break; 867 case 0x10: /* OSTAT */ 868 s->ostat &= ~value; 869 break; 870 case 0x14: /* EMUX */ 871 s->emux = value; 872 break; 873 case 0x18: /* USTAT */ 874 s->ustat &= ~value; 875 break; 876 case 0x20: /* SSPRI */ 877 s->sspri = value; 878 break; 879 case 0x28: /* PSSI */ 880 qemu_log_mask(LOG_UNIMP, "ADC: sample initiate unimplemented\n"); 881 break; 882 case 0x30: /* SAC */ 883 s->sac = value; 884 break; 885 default: 886 qemu_log_mask(LOG_GUEST_ERROR, 887 "stellaris_adc: write at bad offset 0x%x\n", (int)offset); 888 } 889 stellaris_adc_update(s); 890 } 891 892 static const MemoryRegionOps stellaris_adc_ops = { 893 .read = stellaris_adc_read, 894 .write = stellaris_adc_write, 895 .endianness = DEVICE_NATIVE_ENDIAN, 896 }; 897 898 static const VMStateDescription vmstate_stellaris_adc = { 899 .name = "stellaris_adc", 900 .version_id = 1, 901 .minimum_version_id = 1, 902 .fields = (VMStateField[]) { 903 VMSTATE_UINT32(actss, StellarisADCState), 904 VMSTATE_UINT32(ris, StellarisADCState), 905 VMSTATE_UINT32(im, StellarisADCState), 906 VMSTATE_UINT32(emux, StellarisADCState), 907 VMSTATE_UINT32(ostat, StellarisADCState), 908 VMSTATE_UINT32(ustat, StellarisADCState), 909 VMSTATE_UINT32(sspri, StellarisADCState), 910 VMSTATE_UINT32(sac, StellarisADCState), 911 VMSTATE_UINT32(fifo[0].state, StellarisADCState), 912 VMSTATE_UINT32_ARRAY(fifo[0].data, StellarisADCState, 16), 913 VMSTATE_UINT32(ssmux[0], StellarisADCState), 914 VMSTATE_UINT32(ssctl[0], StellarisADCState), 915 VMSTATE_UINT32(fifo[1].state, StellarisADCState), 916 VMSTATE_UINT32_ARRAY(fifo[1].data, StellarisADCState, 16), 917 VMSTATE_UINT32(ssmux[1], StellarisADCState), 918 VMSTATE_UINT32(ssctl[1], StellarisADCState), 919 VMSTATE_UINT32(fifo[2].state, StellarisADCState), 920 VMSTATE_UINT32_ARRAY(fifo[2].data, StellarisADCState, 16), 921 VMSTATE_UINT32(ssmux[2], StellarisADCState), 922 VMSTATE_UINT32(ssctl[2], StellarisADCState), 923 VMSTATE_UINT32(fifo[3].state, StellarisADCState), 924 VMSTATE_UINT32_ARRAY(fifo[3].data, StellarisADCState, 16), 925 VMSTATE_UINT32(ssmux[3], StellarisADCState), 926 VMSTATE_UINT32(ssctl[3], StellarisADCState), 927 VMSTATE_UINT32(noise, StellarisADCState), 928 VMSTATE_END_OF_LIST() 929 } 930 }; 931 932 static void stellaris_adc_init(Object *obj) 933 { 934 DeviceState *dev = DEVICE(obj); 935 StellarisADCState *s = STELLARIS_ADC(obj); 936 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 937 int n; 938 939 for (n = 0; n < 4; n++) { 940 sysbus_init_irq(sbd, &s->irq[n]); 941 } 942 943 memory_region_init_io(&s->iomem, obj, &stellaris_adc_ops, s, 944 "adc", 0x1000); 945 sysbus_init_mmio(sbd, &s->iomem); 946 stellaris_adc_reset(s); 947 qdev_init_gpio_in(dev, stellaris_adc_trigger, 1); 948 } 949 950 /* Board init. */ 951 static stellaris_board_info stellaris_boards[] = { 952 { "LM3S811EVB", 953 0, 954 0x0032000e, 955 0x001f001f, /* dc0 */ 956 0x001132bf, 957 0x01071013, 958 0x3f0f01ff, 959 0x0000001f, 960 BP_OLED_I2C 961 }, 962 { "LM3S6965EVB", 963 0x10010002, 964 0x1073402e, 965 0x00ff007f, /* dc0 */ 966 0x001133ff, 967 0x030f5317, 968 0x0f0f87ff, 969 0x5000007f, 970 BP_OLED_SSI | BP_GAMEPAD 971 } 972 }; 973 974 static void stellaris_init(MachineState *ms, stellaris_board_info *board) 975 { 976 static const int uart_irq[] = {5, 6, 33, 34}; 977 static const int timer_irq[] = {19, 21, 23, 35}; 978 static const uint32_t gpio_addr[7] = 979 { 0x40004000, 0x40005000, 0x40006000, 0x40007000, 980 0x40024000, 0x40025000, 0x40026000}; 981 static const int gpio_irq[7] = {0, 1, 2, 3, 4, 30, 31}; 982 983 /* Memory map of SoC devices, from 984 * Stellaris LM3S6965 Microcontroller Data Sheet (rev I) 985 * http://www.ti.com/lit/ds/symlink/lm3s6965.pdf 986 * 987 * 40000000 wdtimer 988 * 40002000 i2c (unimplemented) 989 * 40004000 GPIO 990 * 40005000 GPIO 991 * 40006000 GPIO 992 * 40007000 GPIO 993 * 40008000 SSI 994 * 4000c000 UART 995 * 4000d000 UART 996 * 4000e000 UART 997 * 40020000 i2c 998 * 40021000 i2c (unimplemented) 999 * 40024000 GPIO 1000 * 40025000 GPIO 1001 * 40026000 GPIO 1002 * 40028000 PWM (unimplemented) 1003 * 4002c000 QEI (unimplemented) 1004 * 4002d000 QEI (unimplemented) 1005 * 40030000 gptimer 1006 * 40031000 gptimer 1007 * 40032000 gptimer 1008 * 40033000 gptimer 1009 * 40038000 ADC 1010 * 4003c000 analogue comparator (unimplemented) 1011 * 40048000 ethernet 1012 * 400fc000 hibernation module (unimplemented) 1013 * 400fd000 flash memory control (unimplemented) 1014 * 400fe000 system control 1015 */ 1016 1017 DeviceState *gpio_dev[7], *nvic; 1018 qemu_irq gpio_in[7][8]; 1019 qemu_irq gpio_out[7][8]; 1020 qemu_irq adc; 1021 int sram_size; 1022 int flash_size; 1023 I2CBus *i2c; 1024 DeviceState *dev; 1025 DeviceState *ssys_dev; 1026 int i; 1027 int j; 1028 const uint8_t *macaddr; 1029 1030 MemoryRegion *sram = g_new(MemoryRegion, 1); 1031 MemoryRegion *flash = g_new(MemoryRegion, 1); 1032 MemoryRegion *system_memory = get_system_memory(); 1033 1034 flash_size = (((board->dc0 & 0xffff) + 1) << 1) * 1024; 1035 sram_size = ((board->dc0 >> 18) + 1) * 1024; 1036 1037 /* Flash programming is done via the SCU, so pretend it is ROM. */ 1038 memory_region_init_rom(flash, NULL, "stellaris.flash", flash_size, 1039 &error_fatal); 1040 memory_region_add_subregion(system_memory, 0, flash); 1041 1042 memory_region_init_ram(sram, NULL, "stellaris.sram", sram_size, 1043 &error_fatal); 1044 memory_region_add_subregion(system_memory, 0x20000000, sram); 1045 1046 /* 1047 * Create the system-registers object early, because we will 1048 * need its sysclk output. 1049 */ 1050 ssys_dev = qdev_new(TYPE_STELLARIS_SYS); 1051 /* Most devices come preprogrammed with a MAC address in the user data. */ 1052 macaddr = nd_table[0].macaddr.a; 1053 qdev_prop_set_uint32(ssys_dev, "user0", 1054 macaddr[0] | (macaddr[1] << 8) | (macaddr[2] << 16)); 1055 qdev_prop_set_uint32(ssys_dev, "user1", 1056 macaddr[3] | (macaddr[4] << 8) | (macaddr[5] << 16)); 1057 qdev_prop_set_uint32(ssys_dev, "did0", board->did0); 1058 qdev_prop_set_uint32(ssys_dev, "did1", board->did1); 1059 qdev_prop_set_uint32(ssys_dev, "dc0", board->dc0); 1060 qdev_prop_set_uint32(ssys_dev, "dc1", board->dc1); 1061 qdev_prop_set_uint32(ssys_dev, "dc2", board->dc2); 1062 qdev_prop_set_uint32(ssys_dev, "dc3", board->dc3); 1063 qdev_prop_set_uint32(ssys_dev, "dc4", board->dc4); 1064 sysbus_realize_and_unref(SYS_BUS_DEVICE(ssys_dev), &error_fatal); 1065 1066 nvic = qdev_new(TYPE_ARMV7M); 1067 qdev_prop_set_uint32(nvic, "num-irq", NUM_IRQ_LINES); 1068 qdev_prop_set_string(nvic, "cpu-type", ms->cpu_type); 1069 qdev_prop_set_bit(nvic, "enable-bitband", true); 1070 qdev_connect_clock_in(nvic, "cpuclk", 1071 qdev_get_clock_out(ssys_dev, "SYSCLK")); 1072 /* This SoC does not connect the systick reference clock */ 1073 object_property_set_link(OBJECT(nvic), "memory", 1074 OBJECT(get_system_memory()), &error_abort); 1075 /* This will exit with an error if the user passed us a bad cpu_type */ 1076 sysbus_realize_and_unref(SYS_BUS_DEVICE(nvic), &error_fatal); 1077 1078 /* Now we can wire up the IRQ and MMIO of the system registers */ 1079 sysbus_mmio_map(SYS_BUS_DEVICE(ssys_dev), 0, 0x400fe000); 1080 sysbus_connect_irq(SYS_BUS_DEVICE(ssys_dev), 0, qdev_get_gpio_in(nvic, 28)); 1081 1082 if (board->dc1 & (1 << 16)) { 1083 dev = sysbus_create_varargs(TYPE_STELLARIS_ADC, 0x40038000, 1084 qdev_get_gpio_in(nvic, 14), 1085 qdev_get_gpio_in(nvic, 15), 1086 qdev_get_gpio_in(nvic, 16), 1087 qdev_get_gpio_in(nvic, 17), 1088 NULL); 1089 adc = qdev_get_gpio_in(dev, 0); 1090 } else { 1091 adc = NULL; 1092 } 1093 for (i = 0; i < 4; i++) { 1094 if (board->dc2 & (0x10000 << i)) { 1095 SysBusDevice *sbd; 1096 1097 dev = qdev_new(TYPE_STELLARIS_GPTM); 1098 sbd = SYS_BUS_DEVICE(dev); 1099 qdev_connect_clock_in(dev, "clk", 1100 qdev_get_clock_out(ssys_dev, "SYSCLK")); 1101 sysbus_realize_and_unref(sbd, &error_fatal); 1102 sysbus_mmio_map(sbd, 0, 0x40030000 + i * 0x1000); 1103 sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(nvic, timer_irq[i])); 1104 /* TODO: This is incorrect, but we get away with it because 1105 the ADC output is only ever pulsed. */ 1106 qdev_connect_gpio_out(dev, 0, adc); 1107 } 1108 } 1109 1110 if (board->dc1 & (1 << 3)) { /* watchdog present */ 1111 dev = qdev_new(TYPE_LUMINARY_WATCHDOG); 1112 1113 qdev_connect_clock_in(dev, "WDOGCLK", 1114 qdev_get_clock_out(ssys_dev, "SYSCLK")); 1115 1116 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1117 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1118 0, 1119 0x40000000u); 1120 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1121 0, 1122 qdev_get_gpio_in(nvic, 18)); 1123 } 1124 1125 1126 for (i = 0; i < 7; i++) { 1127 if (board->dc4 & (1 << i)) { 1128 gpio_dev[i] = sysbus_create_simple("pl061_luminary", gpio_addr[i], 1129 qdev_get_gpio_in(nvic, 1130 gpio_irq[i])); 1131 for (j = 0; j < 8; j++) { 1132 gpio_in[i][j] = qdev_get_gpio_in(gpio_dev[i], j); 1133 gpio_out[i][j] = NULL; 1134 } 1135 } 1136 } 1137 1138 if (board->dc2 & (1 << 12)) { 1139 dev = sysbus_create_simple(TYPE_STELLARIS_I2C, 0x40020000, 1140 qdev_get_gpio_in(nvic, 8)); 1141 i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c"); 1142 if (board->peripherals & BP_OLED_I2C) { 1143 i2c_slave_create_simple(i2c, "ssd0303", 0x3d); 1144 } 1145 } 1146 1147 for (i = 0; i < 4; i++) { 1148 if (board->dc2 & (1 << i)) { 1149 pl011_luminary_create(0x4000c000 + i * 0x1000, 1150 qdev_get_gpio_in(nvic, uart_irq[i]), 1151 serial_hd(i)); 1152 } 1153 } 1154 if (board->dc2 & (1 << 4)) { 1155 dev = sysbus_create_simple("pl022", 0x40008000, 1156 qdev_get_gpio_in(nvic, 7)); 1157 if (board->peripherals & BP_OLED_SSI) { 1158 void *bus; 1159 DeviceState *sddev; 1160 DeviceState *ssddev; 1161 DriveInfo *dinfo; 1162 DeviceState *carddev; 1163 DeviceState *gpio_d_splitter; 1164 BlockBackend *blk; 1165 1166 /* 1167 * Some boards have both an OLED controller and SD card connected to 1168 * the same SSI port, with the SD card chip select connected to a 1169 * GPIO pin. Technically the OLED chip select is connected to the 1170 * SSI Fss pin. We do not bother emulating that as both devices 1171 * should never be selected simultaneously, and our OLED controller 1172 * ignores stray 0xff commands that occur when deselecting the SD 1173 * card. 1174 * 1175 * The h/w wiring is: 1176 * - GPIO pin D0 is wired to the active-low SD card chip select 1177 * - GPIO pin A3 is wired to the active-low OLED chip select 1178 * - The SoC wiring of the PL061 "auxiliary function" for A3 is 1179 * SSI0Fss ("frame signal"), which is an output from the SoC's 1180 * SSI controller. The SSI controller takes SSI0Fss low when it 1181 * transmits a frame, so it can work as a chip-select signal. 1182 * - GPIO A4 is aux-function SSI0Rx, and wired to the SD card Tx 1183 * (the OLED never sends data to the CPU, so no wiring needed) 1184 * - GPIO A5 is aux-function SSI0Tx, and wired to the SD card Rx 1185 * and the OLED display-data-in 1186 * - GPIO A2 is aux-function SSI0Clk, wired to SD card and OLED 1187 * serial-clock input 1188 * So a guest that wants to use the OLED can configure the PL061 1189 * to make pins A2, A3, A5 aux-function, so they are connected 1190 * directly to the SSI controller. When the SSI controller sends 1191 * data it asserts SSI0Fss which selects the OLED. 1192 * A guest that wants to use the SD card configures A2, A4 and A5 1193 * as aux-function, but leaves A3 as a software-controlled GPIO 1194 * line. It asserts the SD card chip-select by using the PL061 1195 * to control pin D0, and lets the SSI controller handle Clk, Tx 1196 * and Rx. (The SSI controller asserts Fss during tx cycles as 1197 * usual, but because A3 is not set to aux-function this is not 1198 * forwarded to the OLED, and so the OLED stays unselected.) 1199 * 1200 * The QEMU implementation instead is: 1201 * - GPIO pin D0 is wired to the active-low SD card chip select, 1202 * and also to the OLED chip-select which is implemented 1203 * as *active-high* 1204 * - SSI controller signals go to the devices regardless of 1205 * whether the guest programs A2, A4, A5 as aux-function or not 1206 * 1207 * The problem with this implementation is if the guest doesn't 1208 * care about the SD card and only uses the OLED. In that case it 1209 * may choose never to do anything with D0 (leaving it in its 1210 * default floating state, which reliably leaves the card disabled 1211 * because an SD card has a pullup on CS within the card itself), 1212 * and only set up A2, A3, A5. This for us would mean the OLED 1213 * never gets the chip-select assert it needs. We work around 1214 * this with a manual raise of D0 here (despite board creation 1215 * code being the wrong place to raise IRQ lines) to put the OLED 1216 * into an initially selected state. 1217 * 1218 * In theory the right way to model this would be: 1219 * - Implement aux-function support in the PL061, with an 1220 * extra set of AFIN and AFOUT GPIO lines (set up so that 1221 * if a GPIO line is in auxfn mode the main GPIO in and out 1222 * track the AFIN and AFOUT lines) 1223 * - Wire the AFOUT for D0 up to either a line from the 1224 * SSI controller that's pulled low around every transmit, 1225 * or at least to an always-0 line here on the board 1226 * - Make the ssd0323 OLED controller chipselect active-low 1227 */ 1228 bus = qdev_get_child_bus(dev, "ssi"); 1229 sddev = ssi_create_peripheral(bus, "ssi-sd"); 1230 1231 dinfo = drive_get(IF_SD, 0, 0); 1232 blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL; 1233 carddev = qdev_new(TYPE_SD_CARD); 1234 qdev_prop_set_drive_err(carddev, "drive", blk, &error_fatal); 1235 qdev_prop_set_bit(carddev, "spi", true); 1236 qdev_realize_and_unref(carddev, 1237 qdev_get_child_bus(sddev, "sd-bus"), 1238 &error_fatal); 1239 1240 ssddev = ssi_create_peripheral(bus, "ssd0323"); 1241 1242 gpio_d_splitter = qdev_new(TYPE_SPLIT_IRQ); 1243 qdev_prop_set_uint32(gpio_d_splitter, "num-lines", 2); 1244 qdev_realize_and_unref(gpio_d_splitter, NULL, &error_fatal); 1245 qdev_connect_gpio_out( 1246 gpio_d_splitter, 0, 1247 qdev_get_gpio_in_named(sddev, SSI_GPIO_CS, 0)); 1248 qdev_connect_gpio_out( 1249 gpio_d_splitter, 1, 1250 qdev_get_gpio_in_named(ssddev, SSI_GPIO_CS, 0)); 1251 gpio_out[GPIO_D][0] = qdev_get_gpio_in(gpio_d_splitter, 0); 1252 1253 gpio_out[GPIO_C][7] = qdev_get_gpio_in(ssddev, 0); 1254 1255 /* Make sure the select pin is high. */ 1256 qemu_irq_raise(gpio_out[GPIO_D][0]); 1257 } 1258 } 1259 if (board->dc4 & (1 << 28)) { 1260 DeviceState *enet; 1261 1262 qemu_check_nic_model(&nd_table[0], "stellaris"); 1263 1264 enet = qdev_new("stellaris_enet"); 1265 qdev_set_nic_properties(enet, &nd_table[0]); 1266 sysbus_realize_and_unref(SYS_BUS_DEVICE(enet), &error_fatal); 1267 sysbus_mmio_map(SYS_BUS_DEVICE(enet), 0, 0x40048000); 1268 sysbus_connect_irq(SYS_BUS_DEVICE(enet), 0, qdev_get_gpio_in(nvic, 42)); 1269 } 1270 if (board->peripherals & BP_GAMEPAD) { 1271 qemu_irq gpad_irq[5]; 1272 static const int gpad_keycode[5] = { 0xc8, 0xd0, 0xcb, 0xcd, 0x1d }; 1273 1274 gpad_irq[0] = qemu_irq_invert(gpio_in[GPIO_E][0]); /* up */ 1275 gpad_irq[1] = qemu_irq_invert(gpio_in[GPIO_E][1]); /* down */ 1276 gpad_irq[2] = qemu_irq_invert(gpio_in[GPIO_E][2]); /* left */ 1277 gpad_irq[3] = qemu_irq_invert(gpio_in[GPIO_E][3]); /* right */ 1278 gpad_irq[4] = qemu_irq_invert(gpio_in[GPIO_F][1]); /* select */ 1279 1280 stellaris_gamepad_init(5, gpad_irq, gpad_keycode); 1281 } 1282 for (i = 0; i < 7; i++) { 1283 if (board->dc4 & (1 << i)) { 1284 for (j = 0; j < 8; j++) { 1285 if (gpio_out[i][j]) { 1286 qdev_connect_gpio_out(gpio_dev[i], j, gpio_out[i][j]); 1287 } 1288 } 1289 } 1290 } 1291 1292 /* Add dummy regions for the devices we don't implement yet, 1293 * so guest accesses don't cause unlogged crashes. 1294 */ 1295 create_unimplemented_device("i2c-0", 0x40002000, 0x1000); 1296 create_unimplemented_device("i2c-2", 0x40021000, 0x1000); 1297 create_unimplemented_device("PWM", 0x40028000, 0x1000); 1298 create_unimplemented_device("QEI-0", 0x4002c000, 0x1000); 1299 create_unimplemented_device("QEI-1", 0x4002d000, 0x1000); 1300 create_unimplemented_device("analogue-comparator", 0x4003c000, 0x1000); 1301 create_unimplemented_device("hibernation", 0x400fc000, 0x1000); 1302 create_unimplemented_device("flash-control", 0x400fd000, 0x1000); 1303 1304 armv7m_load_kernel(ARM_CPU(first_cpu), ms->kernel_filename, 0, flash_size); 1305 } 1306 1307 /* FIXME: Figure out how to generate these from stellaris_boards. */ 1308 static void lm3s811evb_init(MachineState *machine) 1309 { 1310 stellaris_init(machine, &stellaris_boards[0]); 1311 } 1312 1313 static void lm3s6965evb_init(MachineState *machine) 1314 { 1315 stellaris_init(machine, &stellaris_boards[1]); 1316 } 1317 1318 static void lm3s811evb_class_init(ObjectClass *oc, void *data) 1319 { 1320 MachineClass *mc = MACHINE_CLASS(oc); 1321 1322 mc->desc = "Stellaris LM3S811EVB (Cortex-M3)"; 1323 mc->init = lm3s811evb_init; 1324 mc->ignore_memory_transaction_failures = true; 1325 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3"); 1326 } 1327 1328 static const TypeInfo lm3s811evb_type = { 1329 .name = MACHINE_TYPE_NAME("lm3s811evb"), 1330 .parent = TYPE_MACHINE, 1331 .class_init = lm3s811evb_class_init, 1332 }; 1333 1334 static void lm3s6965evb_class_init(ObjectClass *oc, void *data) 1335 { 1336 MachineClass *mc = MACHINE_CLASS(oc); 1337 1338 mc->desc = "Stellaris LM3S6965EVB (Cortex-M3)"; 1339 mc->init = lm3s6965evb_init; 1340 mc->ignore_memory_transaction_failures = true; 1341 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3"); 1342 } 1343 1344 static const TypeInfo lm3s6965evb_type = { 1345 .name = MACHINE_TYPE_NAME("lm3s6965evb"), 1346 .parent = TYPE_MACHINE, 1347 .class_init = lm3s6965evb_class_init, 1348 }; 1349 1350 static void stellaris_machine_init(void) 1351 { 1352 type_register_static(&lm3s811evb_type); 1353 type_register_static(&lm3s6965evb_type); 1354 } 1355 1356 type_init(stellaris_machine_init) 1357 1358 static void stellaris_i2c_class_init(ObjectClass *klass, void *data) 1359 { 1360 DeviceClass *dc = DEVICE_CLASS(klass); 1361 1362 dc->vmsd = &vmstate_stellaris_i2c; 1363 } 1364 1365 static const TypeInfo stellaris_i2c_info = { 1366 .name = TYPE_STELLARIS_I2C, 1367 .parent = TYPE_SYS_BUS_DEVICE, 1368 .instance_size = sizeof(stellaris_i2c_state), 1369 .instance_init = stellaris_i2c_init, 1370 .class_init = stellaris_i2c_class_init, 1371 }; 1372 1373 static void stellaris_adc_class_init(ObjectClass *klass, void *data) 1374 { 1375 DeviceClass *dc = DEVICE_CLASS(klass); 1376 1377 dc->vmsd = &vmstate_stellaris_adc; 1378 } 1379 1380 static const TypeInfo stellaris_adc_info = { 1381 .name = TYPE_STELLARIS_ADC, 1382 .parent = TYPE_SYS_BUS_DEVICE, 1383 .instance_size = sizeof(StellarisADCState), 1384 .instance_init = stellaris_adc_init, 1385 .class_init = stellaris_adc_class_init, 1386 }; 1387 1388 static void stellaris_sys_class_init(ObjectClass *klass, void *data) 1389 { 1390 DeviceClass *dc = DEVICE_CLASS(klass); 1391 ResettableClass *rc = RESETTABLE_CLASS(klass); 1392 1393 dc->vmsd = &vmstate_stellaris_sys; 1394 rc->phases.enter = stellaris_sys_reset_enter; 1395 rc->phases.hold = stellaris_sys_reset_hold; 1396 rc->phases.exit = stellaris_sys_reset_exit; 1397 device_class_set_props(dc, stellaris_sys_properties); 1398 } 1399 1400 static const TypeInfo stellaris_sys_info = { 1401 .name = TYPE_STELLARIS_SYS, 1402 .parent = TYPE_SYS_BUS_DEVICE, 1403 .instance_size = sizeof(ssys_state), 1404 .instance_init = stellaris_sys_instance_init, 1405 .class_init = stellaris_sys_class_init, 1406 }; 1407 1408 static void stellaris_register_types(void) 1409 { 1410 type_register_static(&stellaris_i2c_info); 1411 type_register_static(&stellaris_adc_info); 1412 type_register_static(&stellaris_sys_info); 1413 } 1414 1415 type_init(stellaris_register_types) 1416