1 /* 2 * ARM SMMUv3 support - Internal API 3 * 4 * Copyright (C) 2014-2016 Broadcom Corporation 5 * Copyright (c) 2017 Red Hat, Inc. 6 * Written by Prem Mallappa, Eric Auger 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #ifndef HW_ARM_SMMUV3_INTERNAL_H 22 #define HW_ARM_SMMUV3_INTERNAL_H 23 24 #include "hw/arm/smmu-common.h" 25 26 typedef enum SMMUTranslationStatus { 27 SMMU_TRANS_DISABLE, 28 SMMU_TRANS_ABORT, 29 SMMU_TRANS_BYPASS, 30 SMMU_TRANS_ERROR, 31 SMMU_TRANS_SUCCESS, 32 } SMMUTranslationStatus; 33 34 /* MMIO Registers */ 35 36 REG32(IDR0, 0x0) 37 FIELD(IDR0, S1P, 1 , 1) 38 FIELD(IDR0, TTF, 2 , 2) 39 FIELD(IDR0, COHACC, 4 , 1) 40 FIELD(IDR0, ASID16, 12, 1) 41 FIELD(IDR0, TTENDIAN, 21, 2) 42 FIELD(IDR0, STALL_MODEL, 24, 2) 43 FIELD(IDR0, TERM_MODEL, 26, 1) 44 FIELD(IDR0, STLEVEL, 27, 2) 45 46 REG32(IDR1, 0x4) 47 FIELD(IDR1, SIDSIZE, 0 , 6) 48 FIELD(IDR1, EVENTQS, 16, 5) 49 FIELD(IDR1, CMDQS, 21, 5) 50 51 #define SMMU_IDR1_SIDSIZE 16 52 #define SMMU_CMDQS 19 53 #define SMMU_EVENTQS 19 54 55 REG32(IDR2, 0x8) 56 REG32(IDR3, 0xc) 57 FIELD(IDR3, HAD, 2, 1); 58 FIELD(IDR3, RIL, 10, 1); 59 FIELD(IDR3, BBML, 11, 2); 60 REG32(IDR4, 0x10) 61 REG32(IDR5, 0x14) 62 FIELD(IDR5, OAS, 0, 3); 63 FIELD(IDR5, GRAN4K, 4, 1); 64 FIELD(IDR5, GRAN16K, 5, 1); 65 FIELD(IDR5, GRAN64K, 6, 1); 66 67 #define SMMU_IDR5_OAS 4 68 69 REG32(IIDR, 0x18) 70 REG32(AIDR, 0x1c) 71 REG32(CR0, 0x20) 72 FIELD(CR0, SMMU_ENABLE, 0, 1) 73 FIELD(CR0, EVENTQEN, 2, 1) 74 FIELD(CR0, CMDQEN, 3, 1) 75 76 #define SMMU_CR0_RESERVED 0xFFFFFC20 77 78 REG32(CR0ACK, 0x24) 79 REG32(CR1, 0x28) 80 REG32(CR2, 0x2c) 81 REG32(STATUSR, 0x40) 82 REG32(GBPA, 0x44) 83 FIELD(GBPA, ABORT, 20, 1) 84 FIELD(GBPA, UPDATE, 31, 1) 85 86 /* Use incoming. */ 87 #define SMMU_GBPA_RESET_VAL 0x1000 88 89 REG32(IRQ_CTRL, 0x50) 90 FIELD(IRQ_CTRL, GERROR_IRQEN, 0, 1) 91 FIELD(IRQ_CTRL, PRI_IRQEN, 1, 1) 92 FIELD(IRQ_CTRL, EVENTQ_IRQEN, 2, 1) 93 94 REG32(IRQ_CTRL_ACK, 0x54) 95 REG32(GERROR, 0x60) 96 FIELD(GERROR, CMDQ_ERR, 0, 1) 97 FIELD(GERROR, EVENTQ_ABT_ERR, 2, 1) 98 FIELD(GERROR, PRIQ_ABT_ERR, 3, 1) 99 FIELD(GERROR, MSI_CMDQ_ABT_ERR, 4, 1) 100 FIELD(GERROR, MSI_EVENTQ_ABT_ERR, 5, 1) 101 FIELD(GERROR, MSI_PRIQ_ABT_ERR, 6, 1) 102 FIELD(GERROR, MSI_GERROR_ABT_ERR, 7, 1) 103 FIELD(GERROR, MSI_SFM_ERR, 8, 1) 104 105 REG32(GERRORN, 0x64) 106 107 #define A_GERROR_IRQ_CFG0 0x68 /* 64b */ 108 REG32(GERROR_IRQ_CFG1, 0x70) 109 REG32(GERROR_IRQ_CFG2, 0x74) 110 111 #define A_STRTAB_BASE 0x80 /* 64b */ 112 113 #define SMMU_BASE_ADDR_MASK 0xfffffffffffc0 114 115 REG32(STRTAB_BASE_CFG, 0x88) 116 FIELD(STRTAB_BASE_CFG, FMT, 16, 2) 117 FIELD(STRTAB_BASE_CFG, SPLIT, 6 , 5) 118 FIELD(STRTAB_BASE_CFG, LOG2SIZE, 0 , 6) 119 120 #define A_CMDQ_BASE 0x90 /* 64b */ 121 REG32(CMDQ_PROD, 0x98) 122 REG32(CMDQ_CONS, 0x9c) 123 FIELD(CMDQ_CONS, ERR, 24, 7) 124 125 #define A_EVENTQ_BASE 0xa0 /* 64b */ 126 REG32(EVENTQ_PROD, 0xa8) 127 REG32(EVENTQ_CONS, 0xac) 128 129 #define A_EVENTQ_IRQ_CFG0 0xb0 /* 64b */ 130 REG32(EVENTQ_IRQ_CFG1, 0xb8) 131 REG32(EVENTQ_IRQ_CFG2, 0xbc) 132 133 #define A_IDREGS 0xfd0 134 135 static inline int smmu_enabled(SMMUv3State *s) 136 { 137 return FIELD_EX32(s->cr[0], CR0, SMMU_ENABLE); 138 } 139 140 /* Command Queue Entry */ 141 typedef struct Cmd { 142 uint32_t word[4]; 143 } Cmd; 144 145 /* Event Queue Entry */ 146 typedef struct Evt { 147 uint32_t word[8]; 148 } Evt; 149 150 static inline uint32_t smmuv3_idreg(int regoffset) 151 { 152 /* 153 * Return the value of the Primecell/Corelink ID registers at the 154 * specified offset from the first ID register. 155 * These value indicate an ARM implementation of MMU600 p1 156 */ 157 static const uint8_t smmuv3_ids[] = { 158 0x04, 0, 0, 0, 0x84, 0xB4, 0xF0, 0x10, 0x0D, 0xF0, 0x05, 0xB1 159 }; 160 return smmuv3_ids[regoffset / 4]; 161 } 162 163 static inline bool smmuv3_eventq_irq_enabled(SMMUv3State *s) 164 { 165 return FIELD_EX32(s->irq_ctrl, IRQ_CTRL, EVENTQ_IRQEN); 166 } 167 168 static inline bool smmuv3_gerror_irq_enabled(SMMUv3State *s) 169 { 170 return FIELD_EX32(s->irq_ctrl, IRQ_CTRL, GERROR_IRQEN); 171 } 172 173 /* Queue Handling */ 174 175 #define Q_BASE(q) ((q)->base & SMMU_BASE_ADDR_MASK) 176 #define WRAP_MASK(q) (1 << (q)->log2size) 177 #define INDEX_MASK(q) (((1 << (q)->log2size)) - 1) 178 #define WRAP_INDEX_MASK(q) ((1 << ((q)->log2size + 1)) - 1) 179 180 #define Q_CONS(q) ((q)->cons & INDEX_MASK(q)) 181 #define Q_PROD(q) ((q)->prod & INDEX_MASK(q)) 182 183 #define Q_CONS_ENTRY(q) (Q_BASE(q) + (q)->entry_size * Q_CONS(q)) 184 #define Q_PROD_ENTRY(q) (Q_BASE(q) + (q)->entry_size * Q_PROD(q)) 185 186 #define Q_CONS_WRAP(q) (((q)->cons & WRAP_MASK(q)) >> (q)->log2size) 187 #define Q_PROD_WRAP(q) (((q)->prod & WRAP_MASK(q)) >> (q)->log2size) 188 189 static inline bool smmuv3_q_full(SMMUQueue *q) 190 { 191 return ((q->cons ^ q->prod) & WRAP_INDEX_MASK(q)) == WRAP_MASK(q); 192 } 193 194 static inline bool smmuv3_q_empty(SMMUQueue *q) 195 { 196 return (q->cons & WRAP_INDEX_MASK(q)) == (q->prod & WRAP_INDEX_MASK(q)); 197 } 198 199 static inline void queue_prod_incr(SMMUQueue *q) 200 { 201 q->prod = (q->prod + 1) & WRAP_INDEX_MASK(q); 202 } 203 204 static inline void queue_cons_incr(SMMUQueue *q) 205 { 206 /* 207 * We have to use deposit for the CONS registers to preserve 208 * the ERR field in the high bits. 209 */ 210 q->cons = deposit32(q->cons, 0, q->log2size + 1, q->cons + 1); 211 } 212 213 static inline bool smmuv3_cmdq_enabled(SMMUv3State *s) 214 { 215 return FIELD_EX32(s->cr[0], CR0, CMDQEN); 216 } 217 218 static inline bool smmuv3_eventq_enabled(SMMUv3State *s) 219 { 220 return FIELD_EX32(s->cr[0], CR0, EVENTQEN); 221 } 222 223 static inline void smmu_write_cmdq_err(SMMUv3State *s, uint32_t err_type) 224 { 225 s->cmdq.cons = FIELD_DP32(s->cmdq.cons, CMDQ_CONS, ERR, err_type); 226 } 227 228 /* Commands */ 229 230 typedef enum SMMUCommandType { 231 SMMU_CMD_NONE = 0x00, 232 SMMU_CMD_PREFETCH_CONFIG , 233 SMMU_CMD_PREFETCH_ADDR, 234 SMMU_CMD_CFGI_STE, 235 SMMU_CMD_CFGI_STE_RANGE, 236 SMMU_CMD_CFGI_CD, 237 SMMU_CMD_CFGI_CD_ALL, 238 SMMU_CMD_CFGI_ALL, 239 SMMU_CMD_TLBI_NH_ALL = 0x10, 240 SMMU_CMD_TLBI_NH_ASID, 241 SMMU_CMD_TLBI_NH_VA, 242 SMMU_CMD_TLBI_NH_VAA, 243 SMMU_CMD_TLBI_EL3_ALL = 0x18, 244 SMMU_CMD_TLBI_EL3_VA = 0x1a, 245 SMMU_CMD_TLBI_EL2_ALL = 0x20, 246 SMMU_CMD_TLBI_EL2_ASID, 247 SMMU_CMD_TLBI_EL2_VA, 248 SMMU_CMD_TLBI_EL2_VAA, 249 SMMU_CMD_TLBI_S12_VMALL = 0x28, 250 SMMU_CMD_TLBI_S2_IPA = 0x2a, 251 SMMU_CMD_TLBI_NSNH_ALL = 0x30, 252 SMMU_CMD_ATC_INV = 0x40, 253 SMMU_CMD_PRI_RESP, 254 SMMU_CMD_RESUME = 0x44, 255 SMMU_CMD_STALL_TERM, 256 SMMU_CMD_SYNC, 257 } SMMUCommandType; 258 259 static const char *cmd_stringify[] = { 260 [SMMU_CMD_PREFETCH_CONFIG] = "SMMU_CMD_PREFETCH_CONFIG", 261 [SMMU_CMD_PREFETCH_ADDR] = "SMMU_CMD_PREFETCH_ADDR", 262 [SMMU_CMD_CFGI_STE] = "SMMU_CMD_CFGI_STE", 263 [SMMU_CMD_CFGI_STE_RANGE] = "SMMU_CMD_CFGI_STE_RANGE", 264 [SMMU_CMD_CFGI_CD] = "SMMU_CMD_CFGI_CD", 265 [SMMU_CMD_CFGI_CD_ALL] = "SMMU_CMD_CFGI_CD_ALL", 266 [SMMU_CMD_CFGI_ALL] = "SMMU_CMD_CFGI_ALL", 267 [SMMU_CMD_TLBI_NH_ALL] = "SMMU_CMD_TLBI_NH_ALL", 268 [SMMU_CMD_TLBI_NH_ASID] = "SMMU_CMD_TLBI_NH_ASID", 269 [SMMU_CMD_TLBI_NH_VA] = "SMMU_CMD_TLBI_NH_VA", 270 [SMMU_CMD_TLBI_NH_VAA] = "SMMU_CMD_TLBI_NH_VAA", 271 [SMMU_CMD_TLBI_EL3_ALL] = "SMMU_CMD_TLBI_EL3_ALL", 272 [SMMU_CMD_TLBI_EL3_VA] = "SMMU_CMD_TLBI_EL3_VA", 273 [SMMU_CMD_TLBI_EL2_ALL] = "SMMU_CMD_TLBI_EL2_ALL", 274 [SMMU_CMD_TLBI_EL2_ASID] = "SMMU_CMD_TLBI_EL2_ASID", 275 [SMMU_CMD_TLBI_EL2_VA] = "SMMU_CMD_TLBI_EL2_VA", 276 [SMMU_CMD_TLBI_EL2_VAA] = "SMMU_CMD_TLBI_EL2_VAA", 277 [SMMU_CMD_TLBI_S12_VMALL] = "SMMU_CMD_TLBI_S12_VMALL", 278 [SMMU_CMD_TLBI_S2_IPA] = "SMMU_CMD_TLBI_S2_IPA", 279 [SMMU_CMD_TLBI_NSNH_ALL] = "SMMU_CMD_TLBI_NSNH_ALL", 280 [SMMU_CMD_ATC_INV] = "SMMU_CMD_ATC_INV", 281 [SMMU_CMD_PRI_RESP] = "SMMU_CMD_PRI_RESP", 282 [SMMU_CMD_RESUME] = "SMMU_CMD_RESUME", 283 [SMMU_CMD_STALL_TERM] = "SMMU_CMD_STALL_TERM", 284 [SMMU_CMD_SYNC] = "SMMU_CMD_SYNC", 285 }; 286 287 static inline const char *smmu_cmd_string(SMMUCommandType type) 288 { 289 if (type > SMMU_CMD_NONE && type < ARRAY_SIZE(cmd_stringify)) { 290 return cmd_stringify[type] ? cmd_stringify[type] : "UNKNOWN"; 291 } else { 292 return "INVALID"; 293 } 294 } 295 296 /* CMDQ fields */ 297 298 typedef enum { 299 SMMU_CERROR_NONE = 0, 300 SMMU_CERROR_ILL, 301 SMMU_CERROR_ABT, 302 SMMU_CERROR_ATC_INV_SYNC, 303 } SMMUCmdError; 304 305 enum { /* Command completion notification */ 306 CMD_SYNC_SIG_NONE, 307 CMD_SYNC_SIG_IRQ, 308 CMD_SYNC_SIG_SEV, 309 }; 310 311 #define CMD_TYPE(x) extract32((x)->word[0], 0 , 8) 312 #define CMD_NUM(x) extract32((x)->word[0], 12 , 5) 313 #define CMD_SCALE(x) extract32((x)->word[0], 20 , 5) 314 #define CMD_SSEC(x) extract32((x)->word[0], 10, 1) 315 #define CMD_SSV(x) extract32((x)->word[0], 11, 1) 316 #define CMD_RESUME_AC(x) extract32((x)->word[0], 12, 1) 317 #define CMD_RESUME_AB(x) extract32((x)->word[0], 13, 1) 318 #define CMD_SYNC_CS(x) extract32((x)->word[0], 12, 2) 319 #define CMD_SSID(x) extract32((x)->word[0], 12, 20) 320 #define CMD_SID(x) ((x)->word[1]) 321 #define CMD_VMID(x) extract32((x)->word[1], 0 , 16) 322 #define CMD_ASID(x) extract32((x)->word[1], 16, 16) 323 #define CMD_RESUME_STAG(x) extract32((x)->word[2], 0 , 16) 324 #define CMD_RESP(x) extract32((x)->word[2], 11, 2) 325 #define CMD_LEAF(x) extract32((x)->word[2], 0 , 1) 326 #define CMD_TTL(x) extract32((x)->word[2], 8 , 2) 327 #define CMD_TG(x) extract32((x)->word[2], 10, 2) 328 #define CMD_STE_RANGE(x) extract32((x)->word[2], 0 , 5) 329 #define CMD_ADDR(x) ({ \ 330 uint64_t high = (uint64_t)(x)->word[3]; \ 331 uint64_t low = extract32((x)->word[2], 12, 20); \ 332 uint64_t addr = high << 32 | (low << 12); \ 333 addr; \ 334 }) 335 336 #define SMMU_FEATURE_2LVL_STE (1 << 0) 337 338 /* Events */ 339 340 typedef enum SMMUEventType { 341 SMMU_EVT_NONE = 0x00, 342 SMMU_EVT_F_UUT , 343 SMMU_EVT_C_BAD_STREAMID , 344 SMMU_EVT_F_STE_FETCH , 345 SMMU_EVT_C_BAD_STE , 346 SMMU_EVT_F_BAD_ATS_TREQ , 347 SMMU_EVT_F_STREAM_DISABLED , 348 SMMU_EVT_F_TRANS_FORBIDDEN , 349 SMMU_EVT_C_BAD_SUBSTREAMID , 350 SMMU_EVT_F_CD_FETCH , 351 SMMU_EVT_C_BAD_CD , 352 SMMU_EVT_F_WALK_EABT , 353 SMMU_EVT_F_TRANSLATION = 0x10, 354 SMMU_EVT_F_ADDR_SIZE , 355 SMMU_EVT_F_ACCESS , 356 SMMU_EVT_F_PERMISSION , 357 SMMU_EVT_F_TLB_CONFLICT = 0x20, 358 SMMU_EVT_F_CFG_CONFLICT , 359 SMMU_EVT_E_PAGE_REQ = 0x24, 360 } SMMUEventType; 361 362 static const char *event_stringify[] = { 363 [SMMU_EVT_NONE] = "no recorded event", 364 [SMMU_EVT_F_UUT] = "SMMU_EVT_F_UUT", 365 [SMMU_EVT_C_BAD_STREAMID] = "SMMU_EVT_C_BAD_STREAMID", 366 [SMMU_EVT_F_STE_FETCH] = "SMMU_EVT_F_STE_FETCH", 367 [SMMU_EVT_C_BAD_STE] = "SMMU_EVT_C_BAD_STE", 368 [SMMU_EVT_F_BAD_ATS_TREQ] = "SMMU_EVT_F_BAD_ATS_TREQ", 369 [SMMU_EVT_F_STREAM_DISABLED] = "SMMU_EVT_F_STREAM_DISABLED", 370 [SMMU_EVT_F_TRANS_FORBIDDEN] = "SMMU_EVT_F_TRANS_FORBIDDEN", 371 [SMMU_EVT_C_BAD_SUBSTREAMID] = "SMMU_EVT_C_BAD_SUBSTREAMID", 372 [SMMU_EVT_F_CD_FETCH] = "SMMU_EVT_F_CD_FETCH", 373 [SMMU_EVT_C_BAD_CD] = "SMMU_EVT_C_BAD_CD", 374 [SMMU_EVT_F_WALK_EABT] = "SMMU_EVT_F_WALK_EABT", 375 [SMMU_EVT_F_TRANSLATION] = "SMMU_EVT_F_TRANSLATION", 376 [SMMU_EVT_F_ADDR_SIZE] = "SMMU_EVT_F_ADDR_SIZE", 377 [SMMU_EVT_F_ACCESS] = "SMMU_EVT_F_ACCESS", 378 [SMMU_EVT_F_PERMISSION] = "SMMU_EVT_F_PERMISSION", 379 [SMMU_EVT_F_TLB_CONFLICT] = "SMMU_EVT_F_TLB_CONFLICT", 380 [SMMU_EVT_F_CFG_CONFLICT] = "SMMU_EVT_F_CFG_CONFLICT", 381 [SMMU_EVT_E_PAGE_REQ] = "SMMU_EVT_E_PAGE_REQ", 382 }; 383 384 static inline const char *smmu_event_string(SMMUEventType type) 385 { 386 if (type < ARRAY_SIZE(event_stringify)) { 387 return event_stringify[type] ? event_stringify[type] : "UNKNOWN"; 388 } else { 389 return "INVALID"; 390 } 391 } 392 393 /* Encode an event record */ 394 typedef struct SMMUEventInfo { 395 SMMUEventType type; 396 uint32_t sid; 397 bool recorded; 398 bool inval_ste_allowed; 399 union { 400 struct { 401 uint32_t ssid; 402 bool ssv; 403 dma_addr_t addr; 404 bool rnw; 405 bool pnu; 406 bool ind; 407 } f_uut; 408 struct SSIDInfo { 409 uint32_t ssid; 410 bool ssv; 411 } c_bad_streamid; 412 struct SSIDAddrInfo { 413 uint32_t ssid; 414 bool ssv; 415 dma_addr_t addr; 416 } f_ste_fetch; 417 struct SSIDInfo c_bad_ste; 418 struct { 419 dma_addr_t addr; 420 bool rnw; 421 } f_transl_forbidden; 422 struct { 423 uint32_t ssid; 424 } c_bad_substream; 425 struct SSIDAddrInfo f_cd_fetch; 426 struct SSIDInfo c_bad_cd; 427 struct FullInfo { 428 bool stall; 429 uint16_t stag; 430 uint32_t ssid; 431 bool ssv; 432 bool s2; 433 dma_addr_t addr; 434 bool rnw; 435 bool pnu; 436 bool ind; 437 uint8_t class; 438 dma_addr_t addr2; 439 } f_walk_eabt; 440 struct FullInfo f_translation; 441 struct FullInfo f_addr_size; 442 struct FullInfo f_access; 443 struct FullInfo f_permission; 444 struct SSIDInfo f_cfg_conflict; 445 /** 446 * not supported yet: 447 * F_BAD_ATS_TREQ 448 * F_BAD_ATS_TREQ 449 * F_TLB_CONFLICT 450 * E_PAGE_REQUEST 451 * IMPDEF_EVENTn 452 */ 453 } u; 454 } SMMUEventInfo; 455 456 /* EVTQ fields */ 457 458 #define EVT_Q_OVERFLOW (1 << 31) 459 460 #define EVT_SET_TYPE(x, v) ((x)->word[0] = deposit32((x)->word[0], 0 , 8 , v)) 461 #define EVT_SET_SSV(x, v) ((x)->word[0] = deposit32((x)->word[0], 11, 1 , v)) 462 #define EVT_SET_SSID(x, v) ((x)->word[0] = deposit32((x)->word[0], 12, 20, v)) 463 #define EVT_SET_SID(x, v) ((x)->word[1] = v) 464 #define EVT_SET_STAG(x, v) ((x)->word[2] = deposit32((x)->word[2], 0 , 16, v)) 465 #define EVT_SET_STALL(x, v) ((x)->word[2] = deposit32((x)->word[2], 31, 1 , v)) 466 #define EVT_SET_PNU(x, v) ((x)->word[3] = deposit32((x)->word[3], 1 , 1 , v)) 467 #define EVT_SET_IND(x, v) ((x)->word[3] = deposit32((x)->word[3], 2 , 1 , v)) 468 #define EVT_SET_RNW(x, v) ((x)->word[3] = deposit32((x)->word[3], 3 , 1 , v)) 469 #define EVT_SET_S2(x, v) ((x)->word[3] = deposit32((x)->word[3], 7 , 1 , v)) 470 #define EVT_SET_CLASS(x, v) ((x)->word[3] = deposit32((x)->word[3], 8 , 2 , v)) 471 #define EVT_SET_ADDR(x, addr) \ 472 do { \ 473 (x)->word[5] = (uint32_t)(addr >> 32); \ 474 (x)->word[4] = (uint32_t)(addr & 0xffffffff); \ 475 } while (0) 476 #define EVT_SET_ADDR2(x, addr) \ 477 do { \ 478 (x)->word[7] = (uint32_t)(addr >> 32); \ 479 (x)->word[6] = (uint32_t)(addr & 0xffffffff); \ 480 } while (0) 481 482 void smmuv3_record_event(SMMUv3State *s, SMMUEventInfo *event); 483 484 /* Configuration Data */ 485 486 /* STE Level 1 Descriptor */ 487 typedef struct STEDesc { 488 uint32_t word[2]; 489 } STEDesc; 490 491 /* CD Level 1 Descriptor */ 492 typedef struct CDDesc { 493 uint32_t word[2]; 494 } CDDesc; 495 496 /* Stream Table Entry(STE) */ 497 typedef struct STE { 498 uint32_t word[16]; 499 } STE; 500 501 /* Context Descriptor(CD) */ 502 typedef struct CD { 503 uint32_t word[16]; 504 } CD; 505 506 /* STE fields */ 507 508 #define STE_VALID(x) extract32((x)->word[0], 0, 1) 509 510 #define STE_CONFIG(x) extract32((x)->word[0], 1, 3) 511 #define STE_CFG_S1_ENABLED(config) (config & 0x1) 512 #define STE_CFG_S2_ENABLED(config) (config & 0x2) 513 #define STE_CFG_ABORT(config) (!(config & 0x4)) 514 #define STE_CFG_BYPASS(config) (config == 0x4) 515 516 #define STE_S1FMT(x) extract32((x)->word[0], 4 , 2) 517 #define STE_S1CDMAX(x) extract32((x)->word[1], 27, 5) 518 #define STE_S1STALLD(x) extract32((x)->word[2], 27, 1) 519 #define STE_EATS(x) extract32((x)->word[2], 28, 2) 520 #define STE_STRW(x) extract32((x)->word[2], 30, 2) 521 #define STE_S2VMID(x) extract32((x)->word[4], 0 , 16) 522 #define STE_S2T0SZ(x) extract32((x)->word[5], 0 , 6) 523 #define STE_S2SL0(x) extract32((x)->word[5], 6 , 2) 524 #define STE_S2TG(x) extract32((x)->word[5], 14, 2) 525 #define STE_S2PS(x) extract32((x)->word[5], 16, 3) 526 #define STE_S2AA64(x) extract32((x)->word[5], 19, 1) 527 #define STE_S2HD(x) extract32((x)->word[5], 24, 1) 528 #define STE_S2HA(x) extract32((x)->word[5], 25, 1) 529 #define STE_S2S(x) extract32((x)->word[5], 26, 1) 530 #define STE_CTXPTR(x) \ 531 ({ \ 532 unsigned long addr; \ 533 addr = (uint64_t)extract32((x)->word[1], 0, 16) << 32; \ 534 addr |= (uint64_t)((x)->word[0] & 0xffffffc0); \ 535 addr; \ 536 }) 537 538 #define STE_S2TTB(x) \ 539 ({ \ 540 unsigned long addr; \ 541 addr = (uint64_t)extract32((x)->word[7], 0, 16) << 32; \ 542 addr |= (uint64_t)((x)->word[6] & 0xfffffff0); \ 543 addr; \ 544 }) 545 546 static inline int oas2bits(int oas_field) 547 { 548 switch (oas_field) { 549 case 0: 550 return 32; 551 case 1: 552 return 36; 553 case 2: 554 return 40; 555 case 3: 556 return 42; 557 case 4: 558 return 44; 559 case 5: 560 return 48; 561 } 562 return -1; 563 } 564 565 static inline int pa_range(STE *ste) 566 { 567 int oas_field = MIN(STE_S2PS(ste), SMMU_IDR5_OAS); 568 569 if (!STE_S2AA64(ste)) { 570 return 40; 571 } 572 573 return oas2bits(oas_field); 574 } 575 576 #define MAX_PA(ste) ((1 << pa_range(ste)) - 1) 577 578 /* CD fields */ 579 580 #define CD_VALID(x) extract32((x)->word[0], 31, 1) 581 #define CD_ASID(x) extract32((x)->word[1], 16, 16) 582 #define CD_TTB(x, sel) \ 583 ({ \ 584 uint64_t hi, lo; \ 585 hi = extract32((x)->word[(sel) * 2 + 3], 0, 19); \ 586 hi <<= 32; \ 587 lo = (x)->word[(sel) * 2 + 2] & ~0xfULL; \ 588 hi | lo; \ 589 }) 590 #define CD_HAD(x, sel) extract32((x)->word[(sel) * 2 + 2], 1, 1) 591 592 #define CD_TSZ(x, sel) extract32((x)->word[0], (16 * (sel)) + 0, 6) 593 #define CD_TG(x, sel) extract32((x)->word[0], (16 * (sel)) + 6, 2) 594 #define CD_EPD(x, sel) extract32((x)->word[0], (16 * (sel)) + 14, 1) 595 #define CD_ENDI(x) extract32((x)->word[0], 15, 1) 596 #define CD_IPS(x) extract32((x)->word[1], 0 , 3) 597 #define CD_TBI(x) extract32((x)->word[1], 6 , 2) 598 #define CD_HD(x) extract32((x)->word[1], 10 , 1) 599 #define CD_HA(x) extract32((x)->word[1], 11 , 1) 600 #define CD_S(x) extract32((x)->word[1], 12, 1) 601 #define CD_R(x) extract32((x)->word[1], 13, 1) 602 #define CD_A(x) extract32((x)->word[1], 14, 1) 603 #define CD_AARCH64(x) extract32((x)->word[1], 9 , 1) 604 605 /** 606 * tg2granule - Decodes the CD translation granule size field according 607 * to the ttbr in use 608 * @bits: TG0/1 fields 609 * @ttbr: ttbr index in use 610 */ 611 static inline int tg2granule(int bits, int ttbr) 612 { 613 switch (bits) { 614 case 0: 615 return ttbr ? 0 : 12; 616 case 1: 617 return ttbr ? 14 : 16; 618 case 2: 619 return ttbr ? 12 : 14; 620 case 3: 621 return ttbr ? 16 : 0; 622 default: 623 return 0; 624 } 625 } 626 627 static inline uint64_t l1std_l2ptr(STEDesc *desc) 628 { 629 uint64_t hi, lo; 630 631 hi = desc->word[1]; 632 lo = desc->word[0] & ~0x1fULL; 633 return hi << 32 | lo; 634 } 635 636 #define L1STD_SPAN(stm) (extract32((stm)->word[0], 0, 5)) 637 638 #endif 639