xref: /openbmc/qemu/hw/arm/smmuv3-internal.h (revision 775b30b3)
1 /*
2  * ARM SMMUv3 support - Internal API
3  *
4  * Copyright (C) 2014-2016 Broadcom Corporation
5  * Copyright (c) 2017 Red Hat, Inc.
6  * Written by Prem Mallappa, Eric Auger
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License along
18  * with this program; if not, see <http://www.gnu.org/licenses/>.
19  */
20 
21 #ifndef HW_ARM_SMMUV3_INTERNAL_H
22 #define HW_ARM_SMMUV3_INTERNAL_H
23 
24 #include "hw/arm/smmu-common.h"
25 
26 typedef enum SMMUTranslationStatus {
27     SMMU_TRANS_DISABLE,
28     SMMU_TRANS_ABORT,
29     SMMU_TRANS_BYPASS,
30     SMMU_TRANS_ERROR,
31     SMMU_TRANS_SUCCESS,
32 } SMMUTranslationStatus;
33 
34 /* MMIO Registers */
35 
36 REG32(IDR0,                0x0)
37     FIELD(IDR0, S1P,         1 , 1)
38     FIELD(IDR0, TTF,         2 , 2)
39     FIELD(IDR0, COHACC,      4 , 1)
40     FIELD(IDR0, ASID16,      12, 1)
41     FIELD(IDR0, TTENDIAN,    21, 2)
42     FIELD(IDR0, STALL_MODEL, 24, 2)
43     FIELD(IDR0, TERM_MODEL,  26, 1)
44     FIELD(IDR0, STLEVEL,     27, 2)
45 
46 REG32(IDR1,                0x4)
47     FIELD(IDR1, SIDSIZE,      0 , 6)
48     FIELD(IDR1, EVENTQS,      16, 5)
49     FIELD(IDR1, CMDQS,        21, 5)
50 
51 #define SMMU_IDR1_SIDSIZE 16
52 #define SMMU_CMDQS   19
53 #define SMMU_EVENTQS 19
54 
55 REG32(IDR2,                0x8)
56 REG32(IDR3,                0xc)
57      FIELD(IDR3, HAD,         2, 1);
58      FIELD(IDR3, RIL,        10, 1);
59      FIELD(IDR3, BBML,       11, 2);
60 REG32(IDR4,                0x10)
61 REG32(IDR5,                0x14)
62      FIELD(IDR5, OAS,         0, 3);
63      FIELD(IDR5, GRAN4K,      4, 1);
64      FIELD(IDR5, GRAN16K,     5, 1);
65      FIELD(IDR5, GRAN64K,     6, 1);
66 
67 #define SMMU_IDR5_OAS 4
68 
69 REG32(IIDR,                0x18)
70 REG32(AIDR,                0x1c)
71 REG32(CR0,                 0x20)
72     FIELD(CR0, SMMU_ENABLE,   0, 1)
73     FIELD(CR0, EVENTQEN,      2, 1)
74     FIELD(CR0, CMDQEN,        3, 1)
75 
76 #define SMMU_CR0_RESERVED 0xFFFFFC20
77 
78 REG32(CR0ACK,              0x24)
79 REG32(CR1,                 0x28)
80 REG32(CR2,                 0x2c)
81 REG32(STATUSR,             0x40)
82 REG32(IRQ_CTRL,            0x50)
83     FIELD(IRQ_CTRL, GERROR_IRQEN,        0, 1)
84     FIELD(IRQ_CTRL, PRI_IRQEN,           1, 1)
85     FIELD(IRQ_CTRL, EVENTQ_IRQEN,        2, 1)
86 
87 REG32(IRQ_CTRL_ACK,        0x54)
88 REG32(GERROR,              0x60)
89     FIELD(GERROR, CMDQ_ERR,           0, 1)
90     FIELD(GERROR, EVENTQ_ABT_ERR,     2, 1)
91     FIELD(GERROR, PRIQ_ABT_ERR,       3, 1)
92     FIELD(GERROR, MSI_CMDQ_ABT_ERR,   4, 1)
93     FIELD(GERROR, MSI_EVENTQ_ABT_ERR, 5, 1)
94     FIELD(GERROR, MSI_PRIQ_ABT_ERR,   6, 1)
95     FIELD(GERROR, MSI_GERROR_ABT_ERR, 7, 1)
96     FIELD(GERROR, MSI_SFM_ERR,        8, 1)
97 
98 REG32(GERRORN,             0x64)
99 
100 #define A_GERROR_IRQ_CFG0  0x68 /* 64b */
101 REG32(GERROR_IRQ_CFG1, 0x70)
102 REG32(GERROR_IRQ_CFG2, 0x74)
103 
104 #define A_STRTAB_BASE      0x80 /* 64b */
105 
106 #define SMMU_BASE_ADDR_MASK 0xfffffffffffc0
107 
108 REG32(STRTAB_BASE_CFG,     0x88)
109     FIELD(STRTAB_BASE_CFG, FMT,      16, 2)
110     FIELD(STRTAB_BASE_CFG, SPLIT,    6 , 5)
111     FIELD(STRTAB_BASE_CFG, LOG2SIZE, 0 , 6)
112 
113 #define A_CMDQ_BASE        0x90 /* 64b */
114 REG32(CMDQ_PROD,           0x98)
115 REG32(CMDQ_CONS,           0x9c)
116     FIELD(CMDQ_CONS, ERR, 24, 7)
117 
118 #define A_EVENTQ_BASE      0xa0 /* 64b */
119 REG32(EVENTQ_PROD,         0xa8)
120 REG32(EVENTQ_CONS,         0xac)
121 
122 #define A_EVENTQ_IRQ_CFG0  0xb0 /* 64b */
123 REG32(EVENTQ_IRQ_CFG1,     0xb8)
124 REG32(EVENTQ_IRQ_CFG2,     0xbc)
125 
126 #define A_IDREGS           0xfd0
127 
128 static inline int smmu_enabled(SMMUv3State *s)
129 {
130     return FIELD_EX32(s->cr[0], CR0, SMMU_ENABLE);
131 }
132 
133 /* Command Queue Entry */
134 typedef struct Cmd {
135     uint32_t word[4];
136 } Cmd;
137 
138 /* Event Queue Entry */
139 typedef struct Evt  {
140     uint32_t word[8];
141 } Evt;
142 
143 static inline uint32_t smmuv3_idreg(int regoffset)
144 {
145     /*
146      * Return the value of the Primecell/Corelink ID registers at the
147      * specified offset from the first ID register.
148      * These value indicate an ARM implementation of MMU600 p1
149      */
150     static const uint8_t smmuv3_ids[] = {
151         0x04, 0, 0, 0, 0x84, 0xB4, 0xF0, 0x10, 0x0D, 0xF0, 0x05, 0xB1
152     };
153     return smmuv3_ids[regoffset / 4];
154 }
155 
156 static inline bool smmuv3_eventq_irq_enabled(SMMUv3State *s)
157 {
158     return FIELD_EX32(s->irq_ctrl, IRQ_CTRL, EVENTQ_IRQEN);
159 }
160 
161 static inline bool smmuv3_gerror_irq_enabled(SMMUv3State *s)
162 {
163     return FIELD_EX32(s->irq_ctrl, IRQ_CTRL, GERROR_IRQEN);
164 }
165 
166 /* Queue Handling */
167 
168 #define Q_BASE(q)          ((q)->base & SMMU_BASE_ADDR_MASK)
169 #define WRAP_MASK(q)       (1 << (q)->log2size)
170 #define INDEX_MASK(q)      (((1 << (q)->log2size)) - 1)
171 #define WRAP_INDEX_MASK(q) ((1 << ((q)->log2size + 1)) - 1)
172 
173 #define Q_CONS(q) ((q)->cons & INDEX_MASK(q))
174 #define Q_PROD(q) ((q)->prod & INDEX_MASK(q))
175 
176 #define Q_CONS_ENTRY(q)  (Q_BASE(q) + (q)->entry_size * Q_CONS(q))
177 #define Q_PROD_ENTRY(q)  (Q_BASE(q) + (q)->entry_size * Q_PROD(q))
178 
179 #define Q_CONS_WRAP(q) (((q)->cons & WRAP_MASK(q)) >> (q)->log2size)
180 #define Q_PROD_WRAP(q) (((q)->prod & WRAP_MASK(q)) >> (q)->log2size)
181 
182 static inline bool smmuv3_q_full(SMMUQueue *q)
183 {
184     return ((q->cons ^ q->prod) & WRAP_INDEX_MASK(q)) == WRAP_MASK(q);
185 }
186 
187 static inline bool smmuv3_q_empty(SMMUQueue *q)
188 {
189     return (q->cons & WRAP_INDEX_MASK(q)) == (q->prod & WRAP_INDEX_MASK(q));
190 }
191 
192 static inline void queue_prod_incr(SMMUQueue *q)
193 {
194     q->prod = (q->prod + 1) & WRAP_INDEX_MASK(q);
195 }
196 
197 static inline void queue_cons_incr(SMMUQueue *q)
198 {
199     /*
200      * We have to use deposit for the CONS registers to preserve
201      * the ERR field in the high bits.
202      */
203     q->cons = deposit32(q->cons, 0, q->log2size + 1, q->cons + 1);
204 }
205 
206 static inline bool smmuv3_cmdq_enabled(SMMUv3State *s)
207 {
208     return FIELD_EX32(s->cr[0], CR0, CMDQEN);
209 }
210 
211 static inline bool smmuv3_eventq_enabled(SMMUv3State *s)
212 {
213     return FIELD_EX32(s->cr[0], CR0, EVENTQEN);
214 }
215 
216 static inline void smmu_write_cmdq_err(SMMUv3State *s, uint32_t err_type)
217 {
218     s->cmdq.cons = FIELD_DP32(s->cmdq.cons, CMDQ_CONS, ERR, err_type);
219 }
220 
221 /* Commands */
222 
223 typedef enum SMMUCommandType {
224     SMMU_CMD_NONE            = 0x00,
225     SMMU_CMD_PREFETCH_CONFIG       ,
226     SMMU_CMD_PREFETCH_ADDR,
227     SMMU_CMD_CFGI_STE,
228     SMMU_CMD_CFGI_STE_RANGE,
229     SMMU_CMD_CFGI_CD,
230     SMMU_CMD_CFGI_CD_ALL,
231     SMMU_CMD_CFGI_ALL,
232     SMMU_CMD_TLBI_NH_ALL     = 0x10,
233     SMMU_CMD_TLBI_NH_ASID,
234     SMMU_CMD_TLBI_NH_VA,
235     SMMU_CMD_TLBI_NH_VAA,
236     SMMU_CMD_TLBI_EL3_ALL    = 0x18,
237     SMMU_CMD_TLBI_EL3_VA     = 0x1a,
238     SMMU_CMD_TLBI_EL2_ALL    = 0x20,
239     SMMU_CMD_TLBI_EL2_ASID,
240     SMMU_CMD_TLBI_EL2_VA,
241     SMMU_CMD_TLBI_EL2_VAA,
242     SMMU_CMD_TLBI_S12_VMALL  = 0x28,
243     SMMU_CMD_TLBI_S2_IPA     = 0x2a,
244     SMMU_CMD_TLBI_NSNH_ALL   = 0x30,
245     SMMU_CMD_ATC_INV         = 0x40,
246     SMMU_CMD_PRI_RESP,
247     SMMU_CMD_RESUME          = 0x44,
248     SMMU_CMD_STALL_TERM,
249     SMMU_CMD_SYNC,
250 } SMMUCommandType;
251 
252 static const char *cmd_stringify[] = {
253     [SMMU_CMD_PREFETCH_CONFIG] = "SMMU_CMD_PREFETCH_CONFIG",
254     [SMMU_CMD_PREFETCH_ADDR]   = "SMMU_CMD_PREFETCH_ADDR",
255     [SMMU_CMD_CFGI_STE]        = "SMMU_CMD_CFGI_STE",
256     [SMMU_CMD_CFGI_STE_RANGE]  = "SMMU_CMD_CFGI_STE_RANGE",
257     [SMMU_CMD_CFGI_CD]         = "SMMU_CMD_CFGI_CD",
258     [SMMU_CMD_CFGI_CD_ALL]     = "SMMU_CMD_CFGI_CD_ALL",
259     [SMMU_CMD_CFGI_ALL]        = "SMMU_CMD_CFGI_ALL",
260     [SMMU_CMD_TLBI_NH_ALL]     = "SMMU_CMD_TLBI_NH_ALL",
261     [SMMU_CMD_TLBI_NH_ASID]    = "SMMU_CMD_TLBI_NH_ASID",
262     [SMMU_CMD_TLBI_NH_VA]      = "SMMU_CMD_TLBI_NH_VA",
263     [SMMU_CMD_TLBI_NH_VAA]     = "SMMU_CMD_TLBI_NH_VAA",
264     [SMMU_CMD_TLBI_EL3_ALL]    = "SMMU_CMD_TLBI_EL3_ALL",
265     [SMMU_CMD_TLBI_EL3_VA]     = "SMMU_CMD_TLBI_EL3_VA",
266     [SMMU_CMD_TLBI_EL2_ALL]    = "SMMU_CMD_TLBI_EL2_ALL",
267     [SMMU_CMD_TLBI_EL2_ASID]   = "SMMU_CMD_TLBI_EL2_ASID",
268     [SMMU_CMD_TLBI_EL2_VA]     = "SMMU_CMD_TLBI_EL2_VA",
269     [SMMU_CMD_TLBI_EL2_VAA]    = "SMMU_CMD_TLBI_EL2_VAA",
270     [SMMU_CMD_TLBI_S12_VMALL]  = "SMMU_CMD_TLBI_S12_VMALL",
271     [SMMU_CMD_TLBI_S2_IPA]     = "SMMU_CMD_TLBI_S2_IPA",
272     [SMMU_CMD_TLBI_NSNH_ALL]   = "SMMU_CMD_TLBI_NSNH_ALL",
273     [SMMU_CMD_ATC_INV]         = "SMMU_CMD_ATC_INV",
274     [SMMU_CMD_PRI_RESP]        = "SMMU_CMD_PRI_RESP",
275     [SMMU_CMD_RESUME]          = "SMMU_CMD_RESUME",
276     [SMMU_CMD_STALL_TERM]      = "SMMU_CMD_STALL_TERM",
277     [SMMU_CMD_SYNC]            = "SMMU_CMD_SYNC",
278 };
279 
280 static inline const char *smmu_cmd_string(SMMUCommandType type)
281 {
282     if (type > SMMU_CMD_NONE && type < ARRAY_SIZE(cmd_stringify)) {
283         return cmd_stringify[type] ? cmd_stringify[type] : "UNKNOWN";
284     } else {
285         return "INVALID";
286     }
287 }
288 
289 /* CMDQ fields */
290 
291 typedef enum {
292     SMMU_CERROR_NONE = 0,
293     SMMU_CERROR_ILL,
294     SMMU_CERROR_ABT,
295     SMMU_CERROR_ATC_INV_SYNC,
296 } SMMUCmdError;
297 
298 enum { /* Command completion notification */
299     CMD_SYNC_SIG_NONE,
300     CMD_SYNC_SIG_IRQ,
301     CMD_SYNC_SIG_SEV,
302 };
303 
304 #define CMD_TYPE(x)         extract32((x)->word[0], 0 , 8)
305 #define CMD_NUM(x)          extract32((x)->word[0], 12 , 5)
306 #define CMD_SCALE(x)        extract32((x)->word[0], 20 , 5)
307 #define CMD_SSEC(x)         extract32((x)->word[0], 10, 1)
308 #define CMD_SSV(x)          extract32((x)->word[0], 11, 1)
309 #define CMD_RESUME_AC(x)    extract32((x)->word[0], 12, 1)
310 #define CMD_RESUME_AB(x)    extract32((x)->word[0], 13, 1)
311 #define CMD_SYNC_CS(x)      extract32((x)->word[0], 12, 2)
312 #define CMD_SSID(x)         extract32((x)->word[0], 12, 20)
313 #define CMD_SID(x)          ((x)->word[1])
314 #define CMD_VMID(x)         extract32((x)->word[1], 0 , 16)
315 #define CMD_ASID(x)         extract32((x)->word[1], 16, 16)
316 #define CMD_RESUME_STAG(x)  extract32((x)->word[2], 0 , 16)
317 #define CMD_RESP(x)         extract32((x)->word[2], 11, 2)
318 #define CMD_LEAF(x)         extract32((x)->word[2], 0 , 1)
319 #define CMD_TTL(x)          extract32((x)->word[2], 8 , 2)
320 #define CMD_TG(x)           extract32((x)->word[2], 10, 2)
321 #define CMD_STE_RANGE(x)    extract32((x)->word[2], 0 , 5)
322 #define CMD_ADDR(x) ({                                        \
323             uint64_t high = (uint64_t)(x)->word[3];           \
324             uint64_t low = extract32((x)->word[2], 12, 20);    \
325             uint64_t addr = high << 32 | (low << 12);         \
326             addr;                                             \
327         })
328 
329 #define SMMU_FEATURE_2LVL_STE (1 << 0)
330 
331 /* Events */
332 
333 typedef enum SMMUEventType {
334     SMMU_EVT_NONE               = 0x00,
335     SMMU_EVT_F_UUT                    ,
336     SMMU_EVT_C_BAD_STREAMID           ,
337     SMMU_EVT_F_STE_FETCH              ,
338     SMMU_EVT_C_BAD_STE                ,
339     SMMU_EVT_F_BAD_ATS_TREQ           ,
340     SMMU_EVT_F_STREAM_DISABLED        ,
341     SMMU_EVT_F_TRANS_FORBIDDEN        ,
342     SMMU_EVT_C_BAD_SUBSTREAMID        ,
343     SMMU_EVT_F_CD_FETCH               ,
344     SMMU_EVT_C_BAD_CD                 ,
345     SMMU_EVT_F_WALK_EABT              ,
346     SMMU_EVT_F_TRANSLATION      = 0x10,
347     SMMU_EVT_F_ADDR_SIZE              ,
348     SMMU_EVT_F_ACCESS                 ,
349     SMMU_EVT_F_PERMISSION             ,
350     SMMU_EVT_F_TLB_CONFLICT     = 0x20,
351     SMMU_EVT_F_CFG_CONFLICT           ,
352     SMMU_EVT_E_PAGE_REQ         = 0x24,
353 } SMMUEventType;
354 
355 static const char *event_stringify[] = {
356     [SMMU_EVT_NONE]                     = "no recorded event",
357     [SMMU_EVT_F_UUT]                    = "SMMU_EVT_F_UUT",
358     [SMMU_EVT_C_BAD_STREAMID]           = "SMMU_EVT_C_BAD_STREAMID",
359     [SMMU_EVT_F_STE_FETCH]              = "SMMU_EVT_F_STE_FETCH",
360     [SMMU_EVT_C_BAD_STE]                = "SMMU_EVT_C_BAD_STE",
361     [SMMU_EVT_F_BAD_ATS_TREQ]           = "SMMU_EVT_F_BAD_ATS_TREQ",
362     [SMMU_EVT_F_STREAM_DISABLED]        = "SMMU_EVT_F_STREAM_DISABLED",
363     [SMMU_EVT_F_TRANS_FORBIDDEN]        = "SMMU_EVT_F_TRANS_FORBIDDEN",
364     [SMMU_EVT_C_BAD_SUBSTREAMID]        = "SMMU_EVT_C_BAD_SUBSTREAMID",
365     [SMMU_EVT_F_CD_FETCH]               = "SMMU_EVT_F_CD_FETCH",
366     [SMMU_EVT_C_BAD_CD]                 = "SMMU_EVT_C_BAD_CD",
367     [SMMU_EVT_F_WALK_EABT]              = "SMMU_EVT_F_WALK_EABT",
368     [SMMU_EVT_F_TRANSLATION]            = "SMMU_EVT_F_TRANSLATION",
369     [SMMU_EVT_F_ADDR_SIZE]              = "SMMU_EVT_F_ADDR_SIZE",
370     [SMMU_EVT_F_ACCESS]                 = "SMMU_EVT_F_ACCESS",
371     [SMMU_EVT_F_PERMISSION]             = "SMMU_EVT_F_PERMISSION",
372     [SMMU_EVT_F_TLB_CONFLICT]           = "SMMU_EVT_F_TLB_CONFLICT",
373     [SMMU_EVT_F_CFG_CONFLICT]           = "SMMU_EVT_F_CFG_CONFLICT",
374     [SMMU_EVT_E_PAGE_REQ]               = "SMMU_EVT_E_PAGE_REQ",
375 };
376 
377 static inline const char *smmu_event_string(SMMUEventType type)
378 {
379     if (type < ARRAY_SIZE(event_stringify)) {
380         return event_stringify[type] ? event_stringify[type] : "UNKNOWN";
381     } else {
382         return "INVALID";
383     }
384 }
385 
386 /*  Encode an event record */
387 typedef struct SMMUEventInfo {
388     SMMUEventType type;
389     uint32_t sid;
390     bool recorded;
391     bool inval_ste_allowed;
392     union {
393         struct {
394             uint32_t ssid;
395             bool ssv;
396             dma_addr_t addr;
397             bool rnw;
398             bool pnu;
399             bool ind;
400        } f_uut;
401        struct SSIDInfo {
402             uint32_t ssid;
403             bool ssv;
404        } c_bad_streamid;
405        struct SSIDAddrInfo {
406             uint32_t ssid;
407             bool ssv;
408             dma_addr_t addr;
409        } f_ste_fetch;
410        struct SSIDInfo c_bad_ste;
411        struct {
412             dma_addr_t addr;
413             bool rnw;
414        } f_transl_forbidden;
415        struct {
416             uint32_t ssid;
417        } c_bad_substream;
418        struct SSIDAddrInfo f_cd_fetch;
419        struct SSIDInfo c_bad_cd;
420        struct FullInfo {
421             bool stall;
422             uint16_t stag;
423             uint32_t ssid;
424             bool ssv;
425             bool s2;
426             dma_addr_t addr;
427             bool rnw;
428             bool pnu;
429             bool ind;
430             uint8_t class;
431             dma_addr_t addr2;
432        } f_walk_eabt;
433        struct FullInfo f_translation;
434        struct FullInfo f_addr_size;
435        struct FullInfo f_access;
436        struct FullInfo f_permission;
437        struct SSIDInfo f_cfg_conflict;
438        /**
439         * not supported yet:
440         * F_BAD_ATS_TREQ
441         * F_BAD_ATS_TREQ
442         * F_TLB_CONFLICT
443         * E_PAGE_REQUEST
444         * IMPDEF_EVENTn
445         */
446     } u;
447 } SMMUEventInfo;
448 
449 /* EVTQ fields */
450 
451 #define EVT_Q_OVERFLOW        (1 << 31)
452 
453 #define EVT_SET_TYPE(x, v)  ((x)->word[0] = deposit32((x)->word[0], 0 , 8 , v))
454 #define EVT_SET_SSV(x, v)   ((x)->word[0] = deposit32((x)->word[0], 11, 1 , v))
455 #define EVT_SET_SSID(x, v)  ((x)->word[0] = deposit32((x)->word[0], 12, 20, v))
456 #define EVT_SET_SID(x, v)   ((x)->word[1] = v)
457 #define EVT_SET_STAG(x, v)  ((x)->word[2] = deposit32((x)->word[2], 0 , 16, v))
458 #define EVT_SET_STALL(x, v) ((x)->word[2] = deposit32((x)->word[2], 31, 1 , v))
459 #define EVT_SET_PNU(x, v)   ((x)->word[3] = deposit32((x)->word[3], 1 , 1 , v))
460 #define EVT_SET_IND(x, v)   ((x)->word[3] = deposit32((x)->word[3], 2 , 1 , v))
461 #define EVT_SET_RNW(x, v)   ((x)->word[3] = deposit32((x)->word[3], 3 , 1 , v))
462 #define EVT_SET_S2(x, v)    ((x)->word[3] = deposit32((x)->word[3], 7 , 1 , v))
463 #define EVT_SET_CLASS(x, v) ((x)->word[3] = deposit32((x)->word[3], 8 , 2 , v))
464 #define EVT_SET_ADDR(x, addr)                             \
465     do {                                                  \
466             (x)->word[5] = (uint32_t)(addr >> 32);        \
467             (x)->word[4] = (uint32_t)(addr & 0xffffffff); \
468     } while (0)
469 #define EVT_SET_ADDR2(x, addr)                            \
470     do {                                                  \
471             (x)->word[7] = (uint32_t)(addr >> 32);        \
472             (x)->word[6] = (uint32_t)(addr & 0xffffffff); \
473     } while (0)
474 
475 void smmuv3_record_event(SMMUv3State *s, SMMUEventInfo *event);
476 
477 /* Configuration Data */
478 
479 /* STE Level 1 Descriptor */
480 typedef struct STEDesc {
481     uint32_t word[2];
482 } STEDesc;
483 
484 /* CD Level 1 Descriptor */
485 typedef struct CDDesc {
486     uint32_t word[2];
487 } CDDesc;
488 
489 /* Stream Table Entry(STE) */
490 typedef struct STE {
491     uint32_t word[16];
492 } STE;
493 
494 /* Context Descriptor(CD) */
495 typedef struct CD {
496     uint32_t word[16];
497 } CD;
498 
499 /* STE fields */
500 
501 #define STE_VALID(x)   extract32((x)->word[0], 0, 1)
502 
503 #define STE_CONFIG(x)  extract32((x)->word[0], 1, 3)
504 #define STE_CFG_S1_ENABLED(config) (config & 0x1)
505 #define STE_CFG_S2_ENABLED(config) (config & 0x2)
506 #define STE_CFG_ABORT(config)      (!(config & 0x4))
507 #define STE_CFG_BYPASS(config)     (config == 0x4)
508 
509 #define STE_S1FMT(x)       extract32((x)->word[0], 4 , 2)
510 #define STE_S1CDMAX(x)     extract32((x)->word[1], 27, 5)
511 #define STE_S1STALLD(x)    extract32((x)->word[2], 27, 1)
512 #define STE_EATS(x)        extract32((x)->word[2], 28, 2)
513 #define STE_STRW(x)        extract32((x)->word[2], 30, 2)
514 #define STE_S2VMID(x)      extract32((x)->word[4], 0 , 16)
515 #define STE_S2T0SZ(x)      extract32((x)->word[5], 0 , 6)
516 #define STE_S2SL0(x)       extract32((x)->word[5], 6 , 2)
517 #define STE_S2TG(x)        extract32((x)->word[5], 14, 2)
518 #define STE_S2PS(x)        extract32((x)->word[5], 16, 3)
519 #define STE_S2AA64(x)      extract32((x)->word[5], 19, 1)
520 #define STE_S2HD(x)        extract32((x)->word[5], 24, 1)
521 #define STE_S2HA(x)        extract32((x)->word[5], 25, 1)
522 #define STE_S2S(x)         extract32((x)->word[5], 26, 1)
523 #define STE_CTXPTR(x)                                           \
524     ({                                                          \
525         unsigned long addr;                                     \
526         addr = (uint64_t)extract32((x)->word[1], 0, 16) << 32;  \
527         addr |= (uint64_t)((x)->word[0] & 0xffffffc0);          \
528         addr;                                                   \
529     })
530 
531 #define STE_S2TTB(x)                                            \
532     ({                                                          \
533         unsigned long addr;                                     \
534         addr = (uint64_t)extract32((x)->word[7], 0, 16) << 32;  \
535         addr |= (uint64_t)((x)->word[6] & 0xfffffff0);          \
536         addr;                                                   \
537     })
538 
539 static inline int oas2bits(int oas_field)
540 {
541     switch (oas_field) {
542     case 0:
543         return 32;
544     case 1:
545         return 36;
546     case 2:
547         return 40;
548     case 3:
549         return 42;
550     case 4:
551         return 44;
552     case 5:
553         return 48;
554     }
555     return -1;
556 }
557 
558 static inline int pa_range(STE *ste)
559 {
560     int oas_field = MIN(STE_S2PS(ste), SMMU_IDR5_OAS);
561 
562     if (!STE_S2AA64(ste)) {
563         return 40;
564     }
565 
566     return oas2bits(oas_field);
567 }
568 
569 #define MAX_PA(ste) ((1 << pa_range(ste)) - 1)
570 
571 /* CD fields */
572 
573 #define CD_VALID(x)   extract32((x)->word[0], 31, 1)
574 #define CD_ASID(x)    extract32((x)->word[1], 16, 16)
575 #define CD_TTB(x, sel)                                      \
576     ({                                                      \
577         uint64_t hi, lo;                                    \
578         hi = extract32((x)->word[(sel) * 2 + 3], 0, 19);    \
579         hi <<= 32;                                          \
580         lo = (x)->word[(sel) * 2 + 2] & ~0xfULL;            \
581         hi | lo;                                            \
582     })
583 #define CD_HAD(x, sel)   extract32((x)->word[(sel) * 2 + 2], 1, 1)
584 
585 #define CD_TSZ(x, sel)   extract32((x)->word[0], (16 * (sel)) + 0, 6)
586 #define CD_TG(x, sel)    extract32((x)->word[0], (16 * (sel)) + 6, 2)
587 #define CD_EPD(x, sel)   extract32((x)->word[0], (16 * (sel)) + 14, 1)
588 #define CD_ENDI(x)       extract32((x)->word[0], 15, 1)
589 #define CD_IPS(x)        extract32((x)->word[1], 0 , 3)
590 #define CD_TBI(x)        extract32((x)->word[1], 6 , 2)
591 #define CD_HD(x)         extract32((x)->word[1], 10 , 1)
592 #define CD_HA(x)         extract32((x)->word[1], 11 , 1)
593 #define CD_S(x)          extract32((x)->word[1], 12, 1)
594 #define CD_R(x)          extract32((x)->word[1], 13, 1)
595 #define CD_A(x)          extract32((x)->word[1], 14, 1)
596 #define CD_AARCH64(x)    extract32((x)->word[1], 9 , 1)
597 
598 /**
599  * tg2granule - Decodes the CD translation granule size field according
600  * to the ttbr in use
601  * @bits: TG0/1 fields
602  * @ttbr: ttbr index in use
603  */
604 static inline int tg2granule(int bits, int ttbr)
605 {
606     switch (bits) {
607     case 0:
608         return ttbr ? 0  : 12;
609     case 1:
610         return ttbr ? 14 : 16;
611     case 2:
612         return ttbr ? 12 : 14;
613     case 3:
614         return ttbr ? 16 :  0;
615     default:
616         return 0;
617     }
618 }
619 
620 static inline uint64_t l1std_l2ptr(STEDesc *desc)
621 {
622     uint64_t hi, lo;
623 
624     hi = desc->word[1];
625     lo = desc->word[0] & ~0x1fULL;
626     return hi << 32 | lo;
627 }
628 
629 #define L1STD_SPAN(stm) (extract32((stm)->word[0], 0, 5))
630 
631 #endif
632