1 /* 2 * ARM SBSA Reference Platform emulation 3 * 4 * Copyright (c) 2018 Linaro Limited 5 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 6 * Written by Hongbo Zhang <hongbo.zhang@linaro.org> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2 or later, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/datadir.h" 23 #include "qapi/error.h" 24 #include "qemu/error-report.h" 25 #include "qemu/units.h" 26 #include "sysemu/device_tree.h" 27 #include "sysemu/kvm.h" 28 #include "sysemu/numa.h" 29 #include "sysemu/runstate.h" 30 #include "sysemu/sysemu.h" 31 #include "exec/hwaddr.h" 32 #include "kvm_arm.h" 33 #include "hw/arm/boot.h" 34 #include "hw/arm/bsa.h" 35 #include "hw/arm/fdt.h" 36 #include "hw/arm/smmuv3.h" 37 #include "hw/block/flash.h" 38 #include "hw/boards.h" 39 #include "hw/ide/internal.h" 40 #include "hw/ide/ahci_internal.h" 41 #include "hw/intc/arm_gicv3_common.h" 42 #include "hw/intc/arm_gicv3_its_common.h" 43 #include "hw/loader.h" 44 #include "hw/pci-host/gpex.h" 45 #include "hw/qdev-properties.h" 46 #include "hw/usb.h" 47 #include "hw/usb/xhci.h" 48 #include "hw/char/pl011.h" 49 #include "hw/watchdog/sbsa_gwdt.h" 50 #include "net/net.h" 51 #include "qom/object.h" 52 53 #define RAMLIMIT_GB 8192 54 #define RAMLIMIT_BYTES (RAMLIMIT_GB * GiB) 55 56 #define NUM_IRQS 256 57 #define NUM_SMMU_IRQS 4 58 #define NUM_SATA_PORTS 6 59 60 enum { 61 SBSA_FLASH, 62 SBSA_MEM, 63 SBSA_CPUPERIPHS, 64 SBSA_GIC_DIST, 65 SBSA_GIC_REDIST, 66 SBSA_GIC_ITS, 67 SBSA_SECURE_EC, 68 SBSA_GWDT_WS0, 69 SBSA_GWDT_REFRESH, 70 SBSA_GWDT_CONTROL, 71 SBSA_SMMU, 72 SBSA_UART, 73 SBSA_RTC, 74 SBSA_PCIE, 75 SBSA_PCIE_MMIO, 76 SBSA_PCIE_MMIO_HIGH, 77 SBSA_PCIE_PIO, 78 SBSA_PCIE_ECAM, 79 SBSA_GPIO, 80 SBSA_SECURE_UART, 81 SBSA_SECURE_UART_MM, 82 SBSA_SECURE_MEM, 83 SBSA_AHCI, 84 SBSA_XHCI, 85 }; 86 87 struct SBSAMachineState { 88 MachineState parent; 89 struct arm_boot_info bootinfo; 90 int smp_cpus; 91 void *fdt; 92 int fdt_size; 93 int psci_conduit; 94 DeviceState *gic; 95 PFlashCFI01 *flash[2]; 96 }; 97 98 #define TYPE_SBSA_MACHINE MACHINE_TYPE_NAME("sbsa-ref") 99 OBJECT_DECLARE_SIMPLE_TYPE(SBSAMachineState, SBSA_MACHINE) 100 101 static const MemMapEntry sbsa_ref_memmap[] = { 102 /* 512M boot ROM */ 103 [SBSA_FLASH] = { 0, 0x20000000 }, 104 /* 512M secure memory */ 105 [SBSA_SECURE_MEM] = { 0x20000000, 0x20000000 }, 106 /* Space reserved for CPU peripheral devices */ 107 [SBSA_CPUPERIPHS] = { 0x40000000, 0x00040000 }, 108 [SBSA_GIC_DIST] = { 0x40060000, 0x00010000 }, 109 [SBSA_GIC_REDIST] = { 0x40080000, 0x04000000 }, 110 [SBSA_GIC_ITS] = { 0x44081000, 0x00020000 }, 111 [SBSA_SECURE_EC] = { 0x50000000, 0x00001000 }, 112 [SBSA_GWDT_REFRESH] = { 0x50010000, 0x00001000 }, 113 [SBSA_GWDT_CONTROL] = { 0x50011000, 0x00001000 }, 114 [SBSA_UART] = { 0x60000000, 0x00001000 }, 115 [SBSA_RTC] = { 0x60010000, 0x00001000 }, 116 [SBSA_GPIO] = { 0x60020000, 0x00001000 }, 117 [SBSA_SECURE_UART] = { 0x60030000, 0x00001000 }, 118 [SBSA_SECURE_UART_MM] = { 0x60040000, 0x00001000 }, 119 [SBSA_SMMU] = { 0x60050000, 0x00020000 }, 120 /* Space here reserved for more SMMUs */ 121 [SBSA_AHCI] = { 0x60100000, 0x00010000 }, 122 [SBSA_XHCI] = { 0x60110000, 0x00010000 }, 123 /* Space here reserved for other devices */ 124 [SBSA_PCIE_PIO] = { 0x7fff0000, 0x00010000 }, 125 /* 32-bit address PCIE MMIO space */ 126 [SBSA_PCIE_MMIO] = { 0x80000000, 0x70000000 }, 127 /* 256M PCIE ECAM space */ 128 [SBSA_PCIE_ECAM] = { 0xf0000000, 0x10000000 }, 129 /* ~1TB PCIE MMIO space (4GB to 1024GB boundary) */ 130 [SBSA_PCIE_MMIO_HIGH] = { 0x100000000ULL, 0xFF00000000ULL }, 131 [SBSA_MEM] = { 0x10000000000ULL, RAMLIMIT_BYTES }, 132 }; 133 134 static const int sbsa_ref_irqmap[] = { 135 [SBSA_UART] = 1, 136 [SBSA_RTC] = 2, 137 [SBSA_PCIE] = 3, /* ... to 6 */ 138 [SBSA_GPIO] = 7, 139 [SBSA_SECURE_UART] = 8, 140 [SBSA_SECURE_UART_MM] = 9, 141 [SBSA_AHCI] = 10, 142 [SBSA_XHCI] = 11, 143 [SBSA_SMMU] = 12, /* ... to 15 */ 144 [SBSA_GWDT_WS0] = 16, 145 }; 146 147 static const char * const valid_cpus[] = { 148 ARM_CPU_TYPE_NAME("cortex-a57"), 149 ARM_CPU_TYPE_NAME("cortex-a72"), 150 ARM_CPU_TYPE_NAME("neoverse-n1"), 151 ARM_CPU_TYPE_NAME("neoverse-v1"), 152 ARM_CPU_TYPE_NAME("neoverse-n2"), 153 ARM_CPU_TYPE_NAME("max"), 154 }; 155 156 static bool cpu_type_valid(const char *cpu) 157 { 158 int i; 159 160 for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) { 161 if (strcmp(cpu, valid_cpus[i]) == 0) { 162 return true; 163 } 164 } 165 return false; 166 } 167 168 static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx) 169 { 170 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER; 171 return arm_cpu_mp_affinity(idx, clustersz); 172 } 173 174 static void sbsa_fdt_add_gic_node(SBSAMachineState *sms) 175 { 176 char *nodename; 177 178 nodename = g_strdup_printf("/intc"); 179 qemu_fdt_add_subnode(sms->fdt, nodename); 180 qemu_fdt_setprop_sized_cells(sms->fdt, nodename, "reg", 181 2, sbsa_ref_memmap[SBSA_GIC_DIST].base, 182 2, sbsa_ref_memmap[SBSA_GIC_DIST].size, 183 2, sbsa_ref_memmap[SBSA_GIC_REDIST].base, 184 2, sbsa_ref_memmap[SBSA_GIC_REDIST].size); 185 186 nodename = g_strdup_printf("/intc/its"); 187 qemu_fdt_add_subnode(sms->fdt, nodename); 188 qemu_fdt_setprop_sized_cells(sms->fdt, nodename, "reg", 189 2, sbsa_ref_memmap[SBSA_GIC_ITS].base, 190 2, sbsa_ref_memmap[SBSA_GIC_ITS].size); 191 192 g_free(nodename); 193 } 194 195 /* 196 * Firmware on this machine only uses ACPI table to load OS, these limited 197 * device tree nodes are just to let firmware know the info which varies from 198 * command line parameters, so it is not necessary to be fully compatible 199 * with the kernel CPU and NUMA binding rules. 200 */ 201 static void create_fdt(SBSAMachineState *sms) 202 { 203 void *fdt = create_device_tree(&sms->fdt_size); 204 const MachineState *ms = MACHINE(sms); 205 int nb_numa_nodes = ms->numa_state->num_nodes; 206 int cpu; 207 208 if (!fdt) { 209 error_report("create_device_tree() failed"); 210 exit(1); 211 } 212 213 sms->fdt = fdt; 214 215 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,sbsa-ref"); 216 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 217 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 218 219 /* 220 * This versioning scheme is for informing platform fw only. It is neither: 221 * - A QEMU versioned machine type; a given version of QEMU will emulate 222 * a given version of the platform. 223 * - A reflection of level of SBSA (now SystemReady SR) support provided. 224 * 225 * machine-version-major: updated when changes breaking fw compatibility 226 * are introduced. 227 * machine-version-minor: updated when features are added that don't break 228 * fw compatibility. 229 */ 230 qemu_fdt_setprop_cell(fdt, "/", "machine-version-major", 0); 231 qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 3); 232 233 if (ms->numa_state->have_numa_distance) { 234 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); 235 uint32_t *matrix = g_malloc0(size); 236 int idx, i, j; 237 238 for (i = 0; i < nb_numa_nodes; i++) { 239 for (j = 0; j < nb_numa_nodes; j++) { 240 idx = (i * nb_numa_nodes + j) * 3; 241 matrix[idx + 0] = cpu_to_be32(i); 242 matrix[idx + 1] = cpu_to_be32(j); 243 matrix[idx + 2] = 244 cpu_to_be32(ms->numa_state->nodes[i].distance[j]); 245 } 246 } 247 248 qemu_fdt_add_subnode(fdt, "/distance-map"); 249 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", 250 matrix, size); 251 g_free(matrix); 252 } 253 254 /* 255 * From Documentation/devicetree/bindings/arm/cpus.yaml 256 * On ARM v8 64-bit systems this property is required 257 * and matches the MPIDR_EL1 register affinity bits. 258 * 259 * * If cpus node's #address-cells property is set to 2 260 * 261 * The first reg cell bits [7:0] must be set to 262 * bits [39:32] of MPIDR_EL1. 263 * 264 * The second reg cell bits [23:0] must be set to 265 * bits [23:0] of MPIDR_EL1. 266 */ 267 qemu_fdt_add_subnode(sms->fdt, "/cpus"); 268 qemu_fdt_setprop_cell(sms->fdt, "/cpus", "#address-cells", 2); 269 qemu_fdt_setprop_cell(sms->fdt, "/cpus", "#size-cells", 0x0); 270 271 for (cpu = sms->smp_cpus - 1; cpu >= 0; cpu--) { 272 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 273 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 274 CPUState *cs = CPU(armcpu); 275 uint64_t mpidr = sbsa_ref_cpu_mp_affinity(sms, cpu); 276 277 qemu_fdt_add_subnode(sms->fdt, nodename); 278 qemu_fdt_setprop_u64(sms->fdt, nodename, "reg", mpidr); 279 280 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 281 qemu_fdt_setprop_cell(sms->fdt, nodename, "numa-node-id", 282 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 283 } 284 285 g_free(nodename); 286 } 287 288 sbsa_fdt_add_gic_node(sms); 289 } 290 291 #define SBSA_FLASH_SECTOR_SIZE (256 * KiB) 292 293 static PFlashCFI01 *sbsa_flash_create1(SBSAMachineState *sms, 294 const char *name, 295 const char *alias_prop_name) 296 { 297 /* 298 * Create a single flash device. We use the same parameters as 299 * the flash devices on the Versatile Express board. 300 */ 301 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 302 303 qdev_prop_set_uint64(dev, "sector-length", SBSA_FLASH_SECTOR_SIZE); 304 qdev_prop_set_uint8(dev, "width", 4); 305 qdev_prop_set_uint8(dev, "device-width", 2); 306 qdev_prop_set_bit(dev, "big-endian", false); 307 qdev_prop_set_uint16(dev, "id0", 0x89); 308 qdev_prop_set_uint16(dev, "id1", 0x18); 309 qdev_prop_set_uint16(dev, "id2", 0x00); 310 qdev_prop_set_uint16(dev, "id3", 0x00); 311 qdev_prop_set_string(dev, "name", name); 312 object_property_add_child(OBJECT(sms), name, OBJECT(dev)); 313 object_property_add_alias(OBJECT(sms), alias_prop_name, 314 OBJECT(dev), "drive"); 315 return PFLASH_CFI01(dev); 316 } 317 318 static void sbsa_flash_create(SBSAMachineState *sms) 319 { 320 sms->flash[0] = sbsa_flash_create1(sms, "sbsa.flash0", "pflash0"); 321 sms->flash[1] = sbsa_flash_create1(sms, "sbsa.flash1", "pflash1"); 322 } 323 324 static void sbsa_flash_map1(PFlashCFI01 *flash, 325 hwaddr base, hwaddr size, 326 MemoryRegion *sysmem) 327 { 328 DeviceState *dev = DEVICE(flash); 329 330 assert(QEMU_IS_ALIGNED(size, SBSA_FLASH_SECTOR_SIZE)); 331 assert(size / SBSA_FLASH_SECTOR_SIZE <= UINT32_MAX); 332 qdev_prop_set_uint32(dev, "num-blocks", size / SBSA_FLASH_SECTOR_SIZE); 333 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 334 335 memory_region_add_subregion(sysmem, base, 336 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 337 0)); 338 } 339 340 static void sbsa_flash_map(SBSAMachineState *sms, 341 MemoryRegion *sysmem, 342 MemoryRegion *secure_sysmem) 343 { 344 /* 345 * Map two flash devices to fill the SBSA_FLASH space in the memmap. 346 * sysmem is the system memory space. secure_sysmem is the secure view 347 * of the system, and the first flash device should be made visible only 348 * there. The second flash device is visible to both secure and nonsecure. 349 */ 350 hwaddr flashsize = sbsa_ref_memmap[SBSA_FLASH].size / 2; 351 hwaddr flashbase = sbsa_ref_memmap[SBSA_FLASH].base; 352 353 sbsa_flash_map1(sms->flash[0], flashbase, flashsize, 354 secure_sysmem); 355 sbsa_flash_map1(sms->flash[1], flashbase + flashsize, flashsize, 356 sysmem); 357 } 358 359 static bool sbsa_firmware_init(SBSAMachineState *sms, 360 MemoryRegion *sysmem, 361 MemoryRegion *secure_sysmem) 362 { 363 const char *bios_name; 364 int i; 365 BlockBackend *pflash_blk0; 366 367 /* Map legacy -drive if=pflash to machine properties */ 368 for (i = 0; i < ARRAY_SIZE(sms->flash); i++) { 369 pflash_cfi01_legacy_drive(sms->flash[i], 370 drive_get(IF_PFLASH, 0, i)); 371 } 372 373 sbsa_flash_map(sms, sysmem, secure_sysmem); 374 375 pflash_blk0 = pflash_cfi01_get_blk(sms->flash[0]); 376 377 bios_name = MACHINE(sms)->firmware; 378 if (bios_name) { 379 char *fname; 380 MemoryRegion *mr; 381 int image_size; 382 383 if (pflash_blk0) { 384 error_report("The contents of the first flash device may be " 385 "specified with -bios or with -drive if=pflash... " 386 "but you cannot use both options at once"); 387 exit(1); 388 } 389 390 /* Fall back to -bios */ 391 392 fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 393 if (!fname) { 394 error_report("Could not find ROM image '%s'", bios_name); 395 exit(1); 396 } 397 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(sms->flash[0]), 0); 398 image_size = load_image_mr(fname, mr); 399 g_free(fname); 400 if (image_size < 0) { 401 error_report("Could not load ROM image '%s'", bios_name); 402 exit(1); 403 } 404 } 405 406 return pflash_blk0 || bios_name; 407 } 408 409 static void create_secure_ram(SBSAMachineState *sms, 410 MemoryRegion *secure_sysmem) 411 { 412 MemoryRegion *secram = g_new(MemoryRegion, 1); 413 hwaddr base = sbsa_ref_memmap[SBSA_SECURE_MEM].base; 414 hwaddr size = sbsa_ref_memmap[SBSA_SECURE_MEM].size; 415 416 memory_region_init_ram(secram, NULL, "sbsa-ref.secure-ram", size, 417 &error_fatal); 418 memory_region_add_subregion(secure_sysmem, base, secram); 419 } 420 421 static void create_its(SBSAMachineState *sms) 422 { 423 const char *itsclass = its_class_name(); 424 DeviceState *dev; 425 426 dev = qdev_new(itsclass); 427 428 object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(sms->gic), 429 &error_abort); 430 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 431 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, sbsa_ref_memmap[SBSA_GIC_ITS].base); 432 } 433 434 static void create_gic(SBSAMachineState *sms, MemoryRegion *mem) 435 { 436 unsigned int smp_cpus = MACHINE(sms)->smp.cpus; 437 SysBusDevice *gicbusdev; 438 const char *gictype; 439 uint32_t redist0_capacity, redist0_count; 440 int i; 441 442 gictype = gicv3_class_name(); 443 444 sms->gic = qdev_new(gictype); 445 qdev_prop_set_uint32(sms->gic, "revision", 3); 446 qdev_prop_set_uint32(sms->gic, "num-cpu", smp_cpus); 447 /* 448 * Note that the num-irq property counts both internal and external 449 * interrupts; there are always 32 of the former (mandated by GIC spec). 450 */ 451 qdev_prop_set_uint32(sms->gic, "num-irq", NUM_IRQS + 32); 452 qdev_prop_set_bit(sms->gic, "has-security-extensions", true); 453 454 redist0_capacity = 455 sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE; 456 redist0_count = MIN(smp_cpus, redist0_capacity); 457 458 qdev_prop_set_uint32(sms->gic, "len-redist-region-count", 1); 459 qdev_prop_set_uint32(sms->gic, "redist-region-count[0]", redist0_count); 460 461 object_property_set_link(OBJECT(sms->gic), "sysmem", 462 OBJECT(mem), &error_fatal); 463 qdev_prop_set_bit(sms->gic, "has-lpi", true); 464 465 gicbusdev = SYS_BUS_DEVICE(sms->gic); 466 sysbus_realize_and_unref(gicbusdev, &error_fatal); 467 sysbus_mmio_map(gicbusdev, 0, sbsa_ref_memmap[SBSA_GIC_DIST].base); 468 sysbus_mmio_map(gicbusdev, 1, sbsa_ref_memmap[SBSA_GIC_REDIST].base); 469 470 /* 471 * Wire the outputs from each CPU's generic timer and the GICv3 472 * maintenance interrupt signal to the appropriate GIC PPI inputs, 473 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. 474 */ 475 for (i = 0; i < smp_cpus; i++) { 476 DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); 477 int intidbase = NUM_IRQS + i * GIC_INTERNAL; 478 int irq; 479 /* 480 * Mapping from the output timer irq lines from the CPU to the 481 * GIC PPI inputs used for this board. 482 */ 483 const int timer_irq[] = { 484 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 485 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 486 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 487 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 488 [GTIMER_HYPVIRT] = ARCH_TIMER_NS_EL2_VIRT_IRQ, 489 }; 490 491 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 492 qdev_connect_gpio_out(cpudev, irq, 493 qdev_get_gpio_in(sms->gic, 494 intidbase + timer_irq[irq])); 495 } 496 497 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0, 498 qdev_get_gpio_in(sms->gic, 499 intidbase 500 + ARCH_GIC_MAINT_IRQ)); 501 502 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 503 qdev_get_gpio_in(sms->gic, 504 intidbase 505 + VIRTUAL_PMU_IRQ)); 506 507 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 508 sysbus_connect_irq(gicbusdev, i + smp_cpus, 509 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 510 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, 511 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 512 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, 513 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 514 } 515 create_its(sms); 516 } 517 518 static void create_uart(const SBSAMachineState *sms, int uart, 519 MemoryRegion *mem, Chardev *chr) 520 { 521 hwaddr base = sbsa_ref_memmap[uart].base; 522 int irq = sbsa_ref_irqmap[uart]; 523 DeviceState *dev = qdev_new(TYPE_PL011); 524 SysBusDevice *s = SYS_BUS_DEVICE(dev); 525 526 qdev_prop_set_chr(dev, "chardev", chr); 527 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 528 memory_region_add_subregion(mem, base, 529 sysbus_mmio_get_region(s, 0)); 530 sysbus_connect_irq(s, 0, qdev_get_gpio_in(sms->gic, irq)); 531 } 532 533 static void create_rtc(const SBSAMachineState *sms) 534 { 535 hwaddr base = sbsa_ref_memmap[SBSA_RTC].base; 536 int irq = sbsa_ref_irqmap[SBSA_RTC]; 537 538 sysbus_create_simple("pl031", base, qdev_get_gpio_in(sms->gic, irq)); 539 } 540 541 static void create_wdt(const SBSAMachineState *sms) 542 { 543 hwaddr rbase = sbsa_ref_memmap[SBSA_GWDT_REFRESH].base; 544 hwaddr cbase = sbsa_ref_memmap[SBSA_GWDT_CONTROL].base; 545 DeviceState *dev = qdev_new(TYPE_WDT_SBSA); 546 SysBusDevice *s = SYS_BUS_DEVICE(dev); 547 int irq = sbsa_ref_irqmap[SBSA_GWDT_WS0]; 548 549 sysbus_realize_and_unref(s, &error_fatal); 550 sysbus_mmio_map(s, 0, rbase); 551 sysbus_mmio_map(s, 1, cbase); 552 sysbus_connect_irq(s, 0, qdev_get_gpio_in(sms->gic, irq)); 553 } 554 555 static DeviceState *gpio_key_dev; 556 static void sbsa_ref_powerdown_req(Notifier *n, void *opaque) 557 { 558 /* use gpio Pin 3 for power button event */ 559 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); 560 } 561 562 static Notifier sbsa_ref_powerdown_notifier = { 563 .notify = sbsa_ref_powerdown_req 564 }; 565 566 static void create_gpio(const SBSAMachineState *sms) 567 { 568 DeviceState *pl061_dev; 569 hwaddr base = sbsa_ref_memmap[SBSA_GPIO].base; 570 int irq = sbsa_ref_irqmap[SBSA_GPIO]; 571 572 pl061_dev = sysbus_create_simple("pl061", base, 573 qdev_get_gpio_in(sms->gic, irq)); 574 575 gpio_key_dev = sysbus_create_simple("gpio-key", -1, 576 qdev_get_gpio_in(pl061_dev, 3)); 577 578 /* connect powerdown request */ 579 qemu_register_powerdown_notifier(&sbsa_ref_powerdown_notifier); 580 } 581 582 static void create_ahci(const SBSAMachineState *sms) 583 { 584 hwaddr base = sbsa_ref_memmap[SBSA_AHCI].base; 585 int irq = sbsa_ref_irqmap[SBSA_AHCI]; 586 DeviceState *dev; 587 DriveInfo *hd[NUM_SATA_PORTS]; 588 SysbusAHCIState *sysahci; 589 AHCIState *ahci; 590 int i; 591 592 dev = qdev_new("sysbus-ahci"); 593 qdev_prop_set_uint32(dev, "num-ports", NUM_SATA_PORTS); 594 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 595 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 596 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(sms->gic, irq)); 597 598 sysahci = SYSBUS_AHCI(dev); 599 ahci = &sysahci->ahci; 600 ide_drive_get(hd, ARRAY_SIZE(hd)); 601 for (i = 0; i < ahci->ports; i++) { 602 if (hd[i] == NULL) { 603 continue; 604 } 605 ide_bus_create_drive(&ahci->dev[i].port, 0, hd[i]); 606 } 607 } 608 609 static void create_xhci(const SBSAMachineState *sms) 610 { 611 hwaddr base = sbsa_ref_memmap[SBSA_XHCI].base; 612 int irq = sbsa_ref_irqmap[SBSA_XHCI]; 613 DeviceState *dev = qdev_new(TYPE_XHCI_SYSBUS); 614 qdev_prop_set_uint32(dev, "slots", XHCI_MAXSLOTS); 615 616 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 617 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 618 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(sms->gic, irq)); 619 } 620 621 static void create_smmu(const SBSAMachineState *sms, PCIBus *bus) 622 { 623 hwaddr base = sbsa_ref_memmap[SBSA_SMMU].base; 624 int irq = sbsa_ref_irqmap[SBSA_SMMU]; 625 DeviceState *dev; 626 int i; 627 628 dev = qdev_new(TYPE_ARM_SMMUV3); 629 630 object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus), 631 &error_abort); 632 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 633 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 634 for (i = 0; i < NUM_SMMU_IRQS; i++) { 635 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 636 qdev_get_gpio_in(sms->gic, irq + i)); 637 } 638 } 639 640 static void create_pcie(SBSAMachineState *sms) 641 { 642 hwaddr base_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].base; 643 hwaddr size_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].size; 644 hwaddr base_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].base; 645 hwaddr size_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].size; 646 hwaddr base_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].base; 647 hwaddr size_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].size; 648 hwaddr base_pio = sbsa_ref_memmap[SBSA_PCIE_PIO].base; 649 int irq = sbsa_ref_irqmap[SBSA_PCIE]; 650 MachineClass *mc = MACHINE_GET_CLASS(sms); 651 MemoryRegion *mmio_alias, *mmio_alias_high, *mmio_reg; 652 MemoryRegion *ecam_alias, *ecam_reg; 653 DeviceState *dev; 654 PCIHostState *pci; 655 int i; 656 657 dev = qdev_new(TYPE_GPEX_HOST); 658 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 659 660 /* Map ECAM space */ 661 ecam_alias = g_new0(MemoryRegion, 1); 662 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 663 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 664 ecam_reg, 0, size_ecam); 665 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); 666 667 /* Map the MMIO space */ 668 mmio_alias = g_new0(MemoryRegion, 1); 669 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 670 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 671 mmio_reg, base_mmio, size_mmio); 672 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); 673 674 /* Map the MMIO_HIGH space */ 675 mmio_alias_high = g_new0(MemoryRegion, 1); 676 memory_region_init_alias(mmio_alias_high, OBJECT(dev), "pcie-mmio-high", 677 mmio_reg, base_mmio_high, size_mmio_high); 678 memory_region_add_subregion(get_system_memory(), base_mmio_high, 679 mmio_alias_high); 680 681 /* Map IO port space */ 682 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); 683 684 for (i = 0; i < GPEX_NUM_IRQS; i++) { 685 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 686 qdev_get_gpio_in(sms->gic, irq + i)); 687 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); 688 } 689 690 pci = PCI_HOST_BRIDGE(dev); 691 if (pci->bus) { 692 for (i = 0; i < nb_nics; i++) { 693 pci_nic_init_nofail(&nd_table[i], pci->bus, mc->default_nic, NULL); 694 } 695 } 696 697 pci_create_simple(pci->bus, -1, "bochs-display"); 698 699 create_smmu(sms, pci->bus); 700 } 701 702 static void *sbsa_ref_dtb(const struct arm_boot_info *binfo, int *fdt_size) 703 { 704 const SBSAMachineState *board = container_of(binfo, SBSAMachineState, 705 bootinfo); 706 707 *fdt_size = board->fdt_size; 708 return board->fdt; 709 } 710 711 static void create_secure_ec(MemoryRegion *mem) 712 { 713 hwaddr base = sbsa_ref_memmap[SBSA_SECURE_EC].base; 714 DeviceState *dev = qdev_new("sbsa-ec"); 715 SysBusDevice *s = SYS_BUS_DEVICE(dev); 716 717 memory_region_add_subregion(mem, base, 718 sysbus_mmio_get_region(s, 0)); 719 } 720 721 static void sbsa_ref_init(MachineState *machine) 722 { 723 unsigned int smp_cpus = machine->smp.cpus; 724 unsigned int max_cpus = machine->smp.max_cpus; 725 SBSAMachineState *sms = SBSA_MACHINE(machine); 726 MachineClass *mc = MACHINE_GET_CLASS(machine); 727 MemoryRegion *sysmem = get_system_memory(); 728 MemoryRegion *secure_sysmem = g_new(MemoryRegion, 1); 729 bool firmware_loaded; 730 const CPUArchIdList *possible_cpus; 731 int n, sbsa_max_cpus; 732 733 if (!cpu_type_valid(machine->cpu_type)) { 734 error_report("sbsa-ref: CPU type %s not supported", machine->cpu_type); 735 exit(1); 736 } 737 738 if (kvm_enabled()) { 739 error_report("sbsa-ref: KVM is not supported for this machine"); 740 exit(1); 741 } 742 743 /* 744 * The Secure view of the world is the same as the NonSecure, 745 * but with a few extra devices. Create it as a container region 746 * containing the system memory at low priority; any secure-only 747 * devices go in at higher priority and take precedence. 748 */ 749 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", 750 UINT64_MAX); 751 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); 752 753 firmware_loaded = sbsa_firmware_init(sms, sysmem, secure_sysmem); 754 755 /* 756 * This machine has EL3 enabled, external firmware should supply PSCI 757 * implementation, so the QEMU's internal PSCI is disabled. 758 */ 759 sms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; 760 761 sbsa_max_cpus = sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE; 762 763 if (max_cpus > sbsa_max_cpus) { 764 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " 765 "supported by machine 'sbsa-ref' (%d)", 766 max_cpus, sbsa_max_cpus); 767 exit(1); 768 } 769 770 sms->smp_cpus = smp_cpus; 771 772 if (machine->ram_size > sbsa_ref_memmap[SBSA_MEM].size) { 773 error_report("sbsa-ref: cannot model more than %dGB RAM", RAMLIMIT_GB); 774 exit(1); 775 } 776 777 possible_cpus = mc->possible_cpu_arch_ids(machine); 778 for (n = 0; n < possible_cpus->len; n++) { 779 Object *cpuobj; 780 CPUState *cs; 781 782 if (n >= smp_cpus) { 783 break; 784 } 785 786 cpuobj = object_new(possible_cpus->cpus[n].type); 787 object_property_set_int(cpuobj, "mp-affinity", 788 possible_cpus->cpus[n].arch_id, NULL); 789 790 cs = CPU(cpuobj); 791 cs->cpu_index = n; 792 793 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj), 794 &error_fatal); 795 796 if (object_property_find(cpuobj, "reset-cbar")) { 797 object_property_set_int(cpuobj, "reset-cbar", 798 sbsa_ref_memmap[SBSA_CPUPERIPHS].base, 799 &error_abort); 800 } 801 802 object_property_set_link(cpuobj, "memory", OBJECT(sysmem), 803 &error_abort); 804 805 object_property_set_link(cpuobj, "secure-memory", 806 OBJECT(secure_sysmem), &error_abort); 807 808 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); 809 object_unref(cpuobj); 810 } 811 812 memory_region_add_subregion(sysmem, sbsa_ref_memmap[SBSA_MEM].base, 813 machine->ram); 814 815 create_fdt(sms); 816 817 create_secure_ram(sms, secure_sysmem); 818 819 create_gic(sms, sysmem); 820 821 create_uart(sms, SBSA_UART, sysmem, serial_hd(0)); 822 create_uart(sms, SBSA_SECURE_UART, secure_sysmem, serial_hd(1)); 823 /* Second secure UART for RAS and MM from EL0 */ 824 create_uart(sms, SBSA_SECURE_UART_MM, secure_sysmem, serial_hd(2)); 825 826 create_rtc(sms); 827 828 create_wdt(sms); 829 830 create_gpio(sms); 831 832 create_ahci(sms); 833 834 create_xhci(sms); 835 836 create_pcie(sms); 837 838 create_secure_ec(secure_sysmem); 839 840 sms->bootinfo.ram_size = machine->ram_size; 841 sms->bootinfo.board_id = -1; 842 sms->bootinfo.loader_start = sbsa_ref_memmap[SBSA_MEM].base; 843 sms->bootinfo.get_dtb = sbsa_ref_dtb; 844 sms->bootinfo.firmware_loaded = firmware_loaded; 845 arm_load_kernel(ARM_CPU(first_cpu), machine, &sms->bootinfo); 846 } 847 848 static const CPUArchIdList *sbsa_ref_possible_cpu_arch_ids(MachineState *ms) 849 { 850 unsigned int max_cpus = ms->smp.max_cpus; 851 SBSAMachineState *sms = SBSA_MACHINE(ms); 852 int n; 853 854 if (ms->possible_cpus) { 855 assert(ms->possible_cpus->len == max_cpus); 856 return ms->possible_cpus; 857 } 858 859 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 860 sizeof(CPUArchId) * max_cpus); 861 ms->possible_cpus->len = max_cpus; 862 for (n = 0; n < ms->possible_cpus->len; n++) { 863 ms->possible_cpus->cpus[n].type = ms->cpu_type; 864 ms->possible_cpus->cpus[n].arch_id = 865 sbsa_ref_cpu_mp_affinity(sms, n); 866 ms->possible_cpus->cpus[n].props.has_thread_id = true; 867 ms->possible_cpus->cpus[n].props.thread_id = n; 868 } 869 return ms->possible_cpus; 870 } 871 872 static CpuInstanceProperties 873 sbsa_ref_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 874 { 875 MachineClass *mc = MACHINE_GET_CLASS(ms); 876 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 877 878 assert(cpu_index < possible_cpus->len); 879 return possible_cpus->cpus[cpu_index].props; 880 } 881 882 static int64_t 883 sbsa_ref_get_default_cpu_node_id(const MachineState *ms, int idx) 884 { 885 return idx % ms->numa_state->num_nodes; 886 } 887 888 static void sbsa_ref_instance_init(Object *obj) 889 { 890 SBSAMachineState *sms = SBSA_MACHINE(obj); 891 892 sbsa_flash_create(sms); 893 } 894 895 static void sbsa_ref_class_init(ObjectClass *oc, void *data) 896 { 897 MachineClass *mc = MACHINE_CLASS(oc); 898 899 mc->init = sbsa_ref_init; 900 mc->desc = "QEMU 'SBSA Reference' ARM Virtual Machine"; 901 mc->default_cpu_type = ARM_CPU_TYPE_NAME("neoverse-n1"); 902 mc->max_cpus = 512; 903 mc->pci_allow_0_address = true; 904 mc->minimum_page_bits = 12; 905 mc->block_default_type = IF_IDE; 906 mc->no_cdrom = 1; 907 mc->default_nic = "e1000e"; 908 mc->default_ram_size = 1 * GiB; 909 mc->default_ram_id = "sbsa-ref.ram"; 910 mc->default_cpus = 4; 911 mc->possible_cpu_arch_ids = sbsa_ref_possible_cpu_arch_ids; 912 mc->cpu_index_to_instance_props = sbsa_ref_cpu_index_to_props; 913 mc->get_default_cpu_node_id = sbsa_ref_get_default_cpu_node_id; 914 /* platform instead of architectural choice */ 915 mc->cpu_cluster_has_numa_boundary = true; 916 } 917 918 static const TypeInfo sbsa_ref_info = { 919 .name = TYPE_SBSA_MACHINE, 920 .parent = TYPE_MACHINE, 921 .instance_init = sbsa_ref_instance_init, 922 .class_init = sbsa_ref_class_init, 923 .instance_size = sizeof(SBSAMachineState), 924 }; 925 926 static void sbsa_ref_machine_init(void) 927 { 928 type_register_static(&sbsa_ref_info); 929 } 930 931 type_init(sbsa_ref_machine_init); 932