xref: /openbmc/qemu/hw/arm/sbsa-ref.c (revision f3635813)
1 /*
2  * ARM SBSA Reference Platform emulation
3  *
4  * Copyright (c) 2018 Linaro Limited
5  * Written by Hongbo Zhang <hongbo.zhang@linaro.org>
6  *
7  * This program is free software; you can redistribute it and/or modify it
8  * under the terms and conditions of the GNU General Public License,
9  * version 2 or later, as published by the Free Software Foundation.
10  *
11  * This program is distributed in the hope it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along with
17  * this program.  If not, see <http://www.gnu.org/licenses/>.
18  */
19 
20 #include "qemu/osdep.h"
21 #include "qemu-common.h"
22 #include "qapi/error.h"
23 #include "qemu/error-report.h"
24 #include "qemu/units.h"
25 #include "sysemu/device_tree.h"
26 #include "sysemu/numa.h"
27 #include "sysemu/runstate.h"
28 #include "sysemu/sysemu.h"
29 #include "exec/address-spaces.h"
30 #include "exec/hwaddr.h"
31 #include "kvm_arm.h"
32 #include "hw/arm/boot.h"
33 #include "hw/block/flash.h"
34 #include "hw/boards.h"
35 #include "hw/ide/internal.h"
36 #include "hw/ide/ahci_internal.h"
37 #include "hw/intc/arm_gicv3_common.h"
38 #include "hw/loader.h"
39 #include "hw/pci-host/gpex.h"
40 #include "hw/qdev-properties.h"
41 #include "hw/usb.h"
42 #include "net/net.h"
43 
44 #define RAMLIMIT_GB 8192
45 #define RAMLIMIT_BYTES (RAMLIMIT_GB * GiB)
46 
47 #define NUM_IRQS        256
48 #define NUM_SMMU_IRQS   4
49 #define NUM_SATA_PORTS  6
50 
51 #define VIRTUAL_PMU_IRQ        7
52 #define ARCH_GIC_MAINT_IRQ     9
53 #define ARCH_TIMER_VIRT_IRQ    11
54 #define ARCH_TIMER_S_EL1_IRQ   13
55 #define ARCH_TIMER_NS_EL1_IRQ  14
56 #define ARCH_TIMER_NS_EL2_IRQ  10
57 
58 enum {
59     SBSA_FLASH,
60     SBSA_MEM,
61     SBSA_CPUPERIPHS,
62     SBSA_GIC_DIST,
63     SBSA_GIC_REDIST,
64     SBSA_SMMU,
65     SBSA_UART,
66     SBSA_RTC,
67     SBSA_PCIE,
68     SBSA_PCIE_MMIO,
69     SBSA_PCIE_MMIO_HIGH,
70     SBSA_PCIE_PIO,
71     SBSA_PCIE_ECAM,
72     SBSA_GPIO,
73     SBSA_SECURE_UART,
74     SBSA_SECURE_UART_MM,
75     SBSA_SECURE_MEM,
76     SBSA_AHCI,
77     SBSA_EHCI,
78 };
79 
80 typedef struct MemMapEntry {
81     hwaddr base;
82     hwaddr size;
83 } MemMapEntry;
84 
85 typedef struct {
86     MachineState parent;
87     struct arm_boot_info bootinfo;
88     int smp_cpus;
89     void *fdt;
90     int fdt_size;
91     int psci_conduit;
92     DeviceState *gic;
93     PFlashCFI01 *flash[2];
94 } SBSAMachineState;
95 
96 #define TYPE_SBSA_MACHINE   MACHINE_TYPE_NAME("sbsa-ref")
97 #define SBSA_MACHINE(obj) \
98     OBJECT_CHECK(SBSAMachineState, (obj), TYPE_SBSA_MACHINE)
99 
100 static const MemMapEntry sbsa_ref_memmap[] = {
101     /* 512M boot ROM */
102     [SBSA_FLASH] =              {          0, 0x20000000 },
103     /* 512M secure memory */
104     [SBSA_SECURE_MEM] =         { 0x20000000, 0x20000000 },
105     /* Space reserved for CPU peripheral devices */
106     [SBSA_CPUPERIPHS] =         { 0x40000000, 0x00040000 },
107     [SBSA_GIC_DIST] =           { 0x40060000, 0x00010000 },
108     [SBSA_GIC_REDIST] =         { 0x40080000, 0x04000000 },
109     [SBSA_UART] =               { 0x60000000, 0x00001000 },
110     [SBSA_RTC] =                { 0x60010000, 0x00001000 },
111     [SBSA_GPIO] =               { 0x60020000, 0x00001000 },
112     [SBSA_SECURE_UART] =        { 0x60030000, 0x00001000 },
113     [SBSA_SECURE_UART_MM] =     { 0x60040000, 0x00001000 },
114     [SBSA_SMMU] =               { 0x60050000, 0x00020000 },
115     /* Space here reserved for more SMMUs */
116     [SBSA_AHCI] =               { 0x60100000, 0x00010000 },
117     [SBSA_EHCI] =               { 0x60110000, 0x00010000 },
118     /* Space here reserved for other devices */
119     [SBSA_PCIE_PIO] =           { 0x7fff0000, 0x00010000 },
120     /* 32-bit address PCIE MMIO space */
121     [SBSA_PCIE_MMIO] =          { 0x80000000, 0x70000000 },
122     /* 256M PCIE ECAM space */
123     [SBSA_PCIE_ECAM] =          { 0xf0000000, 0x10000000 },
124     /* ~1TB PCIE MMIO space (4GB to 1024GB boundary) */
125     [SBSA_PCIE_MMIO_HIGH] =     { 0x100000000ULL, 0xFF00000000ULL },
126     [SBSA_MEM] =                { 0x10000000000ULL, RAMLIMIT_BYTES },
127 };
128 
129 static const int sbsa_ref_irqmap[] = {
130     [SBSA_UART] = 1,
131     [SBSA_RTC] = 2,
132     [SBSA_PCIE] = 3, /* ... to 6 */
133     [SBSA_GPIO] = 7,
134     [SBSA_SECURE_UART] = 8,
135     [SBSA_SECURE_UART_MM] = 9,
136     [SBSA_AHCI] = 10,
137     [SBSA_EHCI] = 11,
138 };
139 
140 /*
141  * Firmware on this machine only uses ACPI table to load OS, these limited
142  * device tree nodes are just to let firmware know the info which varies from
143  * command line parameters, so it is not necessary to be fully compatible
144  * with the kernel CPU and NUMA binding rules.
145  */
146 static void create_fdt(SBSAMachineState *sms)
147 {
148     void *fdt = create_device_tree(&sms->fdt_size);
149     const MachineState *ms = MACHINE(sms);
150     int nb_numa_nodes = ms->numa_state->num_nodes;
151     int cpu;
152 
153     if (!fdt) {
154         error_report("create_device_tree() failed");
155         exit(1);
156     }
157 
158     sms->fdt = fdt;
159 
160     qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,sbsa-ref");
161     qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
162     qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
163 
164     if (ms->numa_state->have_numa_distance) {
165         int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t);
166         uint32_t *matrix = g_malloc0(size);
167         int idx, i, j;
168 
169         for (i = 0; i < nb_numa_nodes; i++) {
170             for (j = 0; j < nb_numa_nodes; j++) {
171                 idx = (i * nb_numa_nodes + j) * 3;
172                 matrix[idx + 0] = cpu_to_be32(i);
173                 matrix[idx + 1] = cpu_to_be32(j);
174                 matrix[idx + 2] =
175                     cpu_to_be32(ms->numa_state->nodes[i].distance[j]);
176             }
177         }
178 
179         qemu_fdt_add_subnode(fdt, "/distance-map");
180         qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix",
181                          matrix, size);
182         g_free(matrix);
183     }
184 
185     qemu_fdt_add_subnode(sms->fdt, "/cpus");
186 
187     for (cpu = sms->smp_cpus - 1; cpu >= 0; cpu--) {
188         char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
189         ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
190         CPUState *cs = CPU(armcpu);
191 
192         qemu_fdt_add_subnode(sms->fdt, nodename);
193 
194         if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) {
195             qemu_fdt_setprop_cell(sms->fdt, nodename, "numa-node-id",
196                 ms->possible_cpus->cpus[cs->cpu_index].props.node_id);
197         }
198 
199         g_free(nodename);
200     }
201 }
202 
203 #define SBSA_FLASH_SECTOR_SIZE (256 * KiB)
204 
205 static PFlashCFI01 *sbsa_flash_create1(SBSAMachineState *sms,
206                                         const char *name,
207                                         const char *alias_prop_name)
208 {
209     /*
210      * Create a single flash device.  We use the same parameters as
211      * the flash devices on the Versatile Express board.
212      */
213     DeviceState *dev = qdev_create(NULL, TYPE_PFLASH_CFI01);
214 
215     qdev_prop_set_uint64(dev, "sector-length", SBSA_FLASH_SECTOR_SIZE);
216     qdev_prop_set_uint8(dev, "width", 4);
217     qdev_prop_set_uint8(dev, "device-width", 2);
218     qdev_prop_set_bit(dev, "big-endian", false);
219     qdev_prop_set_uint16(dev, "id0", 0x89);
220     qdev_prop_set_uint16(dev, "id1", 0x18);
221     qdev_prop_set_uint16(dev, "id2", 0x00);
222     qdev_prop_set_uint16(dev, "id3", 0x00);
223     qdev_prop_set_string(dev, "name", name);
224     object_property_add_child(OBJECT(sms), name, OBJECT(dev),
225                               &error_abort);
226     object_property_add_alias(OBJECT(sms), alias_prop_name,
227                               OBJECT(dev), "drive", &error_abort);
228     return PFLASH_CFI01(dev);
229 }
230 
231 static void sbsa_flash_create(SBSAMachineState *sms)
232 {
233     sms->flash[0] = sbsa_flash_create1(sms, "sbsa.flash0", "pflash0");
234     sms->flash[1] = sbsa_flash_create1(sms, "sbsa.flash1", "pflash1");
235 }
236 
237 static void sbsa_flash_map1(PFlashCFI01 *flash,
238                             hwaddr base, hwaddr size,
239                             MemoryRegion *sysmem)
240 {
241     DeviceState *dev = DEVICE(flash);
242 
243     assert(size % SBSA_FLASH_SECTOR_SIZE == 0);
244     assert(size / SBSA_FLASH_SECTOR_SIZE <= UINT32_MAX);
245     qdev_prop_set_uint32(dev, "num-blocks", size / SBSA_FLASH_SECTOR_SIZE);
246     qdev_init_nofail(dev);
247 
248     memory_region_add_subregion(sysmem, base,
249                                 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev),
250                                                        0));
251 }
252 
253 static void sbsa_flash_map(SBSAMachineState *sms,
254                            MemoryRegion *sysmem,
255                            MemoryRegion *secure_sysmem)
256 {
257     /*
258      * Map two flash devices to fill the SBSA_FLASH space in the memmap.
259      * sysmem is the system memory space. secure_sysmem is the secure view
260      * of the system, and the first flash device should be made visible only
261      * there. The second flash device is visible to both secure and nonsecure.
262      */
263     hwaddr flashsize = sbsa_ref_memmap[SBSA_FLASH].size / 2;
264     hwaddr flashbase = sbsa_ref_memmap[SBSA_FLASH].base;
265 
266     sbsa_flash_map1(sms->flash[0], flashbase, flashsize,
267                     secure_sysmem);
268     sbsa_flash_map1(sms->flash[1], flashbase + flashsize, flashsize,
269                     sysmem);
270 }
271 
272 static bool sbsa_firmware_init(SBSAMachineState *sms,
273                                MemoryRegion *sysmem,
274                                MemoryRegion *secure_sysmem)
275 {
276     int i;
277     BlockBackend *pflash_blk0;
278 
279     /* Map legacy -drive if=pflash to machine properties */
280     for (i = 0; i < ARRAY_SIZE(sms->flash); i++) {
281         pflash_cfi01_legacy_drive(sms->flash[i],
282                                   drive_get(IF_PFLASH, 0, i));
283     }
284 
285     sbsa_flash_map(sms, sysmem, secure_sysmem);
286 
287     pflash_blk0 = pflash_cfi01_get_blk(sms->flash[0]);
288 
289     if (bios_name) {
290         char *fname;
291         MemoryRegion *mr;
292         int image_size;
293 
294         if (pflash_blk0) {
295             error_report("The contents of the first flash device may be "
296                          "specified with -bios or with -drive if=pflash... "
297                          "but you cannot use both options at once");
298             exit(1);
299         }
300 
301         /* Fall back to -bios */
302 
303         fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
304         if (!fname) {
305             error_report("Could not find ROM image '%s'", bios_name);
306             exit(1);
307         }
308         mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(sms->flash[0]), 0);
309         image_size = load_image_mr(fname, mr);
310         g_free(fname);
311         if (image_size < 0) {
312             error_report("Could not load ROM image '%s'", bios_name);
313             exit(1);
314         }
315     }
316 
317     return pflash_blk0 || bios_name;
318 }
319 
320 static void create_secure_ram(SBSAMachineState *sms,
321                               MemoryRegion *secure_sysmem)
322 {
323     MemoryRegion *secram = g_new(MemoryRegion, 1);
324     hwaddr base = sbsa_ref_memmap[SBSA_SECURE_MEM].base;
325     hwaddr size = sbsa_ref_memmap[SBSA_SECURE_MEM].size;
326 
327     memory_region_init_ram(secram, NULL, "sbsa-ref.secure-ram", size,
328                            &error_fatal);
329     memory_region_add_subregion(secure_sysmem, base, secram);
330 }
331 
332 static void create_gic(SBSAMachineState *sms)
333 {
334     unsigned int smp_cpus = MACHINE(sms)->smp.cpus;
335     SysBusDevice *gicbusdev;
336     const char *gictype;
337     uint32_t redist0_capacity, redist0_count;
338     int i;
339 
340     gictype = gicv3_class_name();
341 
342     sms->gic = qdev_create(NULL, gictype);
343     qdev_prop_set_uint32(sms->gic, "revision", 3);
344     qdev_prop_set_uint32(sms->gic, "num-cpu", smp_cpus);
345     /*
346      * Note that the num-irq property counts both internal and external
347      * interrupts; there are always 32 of the former (mandated by GIC spec).
348      */
349     qdev_prop_set_uint32(sms->gic, "num-irq", NUM_IRQS + 32);
350     qdev_prop_set_bit(sms->gic, "has-security-extensions", true);
351 
352     redist0_capacity =
353                 sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE;
354     redist0_count = MIN(smp_cpus, redist0_capacity);
355 
356     qdev_prop_set_uint32(sms->gic, "len-redist-region-count", 1);
357     qdev_prop_set_uint32(sms->gic, "redist-region-count[0]", redist0_count);
358 
359     qdev_init_nofail(sms->gic);
360     gicbusdev = SYS_BUS_DEVICE(sms->gic);
361     sysbus_mmio_map(gicbusdev, 0, sbsa_ref_memmap[SBSA_GIC_DIST].base);
362     sysbus_mmio_map(gicbusdev, 1, sbsa_ref_memmap[SBSA_GIC_REDIST].base);
363 
364     /*
365      * Wire the outputs from each CPU's generic timer and the GICv3
366      * maintenance interrupt signal to the appropriate GIC PPI inputs,
367      * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
368      */
369     for (i = 0; i < smp_cpus; i++) {
370         DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
371         int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS;
372         int irq;
373         /*
374          * Mapping from the output timer irq lines from the CPU to the
375          * GIC PPI inputs used for this board.
376          */
377         const int timer_irq[] = {
378             [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ,
379             [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
380             [GTIMER_HYP]  = ARCH_TIMER_NS_EL2_IRQ,
381             [GTIMER_SEC]  = ARCH_TIMER_S_EL1_IRQ,
382         };
383 
384         for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
385             qdev_connect_gpio_out(cpudev, irq,
386                                   qdev_get_gpio_in(sms->gic,
387                                                    ppibase + timer_irq[irq]));
388         }
389 
390         qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0,
391                                     qdev_get_gpio_in(sms->gic, ppibase
392                                                      + ARCH_GIC_MAINT_IRQ));
393         qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
394                                     qdev_get_gpio_in(sms->gic, ppibase
395                                                      + VIRTUAL_PMU_IRQ));
396 
397         sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
398         sysbus_connect_irq(gicbusdev, i + smp_cpus,
399                            qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
400         sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus,
401                            qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
402         sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus,
403                            qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
404     }
405 }
406 
407 static void create_uart(const SBSAMachineState *sms, int uart,
408                         MemoryRegion *mem, Chardev *chr)
409 {
410     hwaddr base = sbsa_ref_memmap[uart].base;
411     int irq = sbsa_ref_irqmap[uart];
412     DeviceState *dev = qdev_create(NULL, "pl011");
413     SysBusDevice *s = SYS_BUS_DEVICE(dev);
414 
415     qdev_prop_set_chr(dev, "chardev", chr);
416     qdev_init_nofail(dev);
417     memory_region_add_subregion(mem, base,
418                                 sysbus_mmio_get_region(s, 0));
419     sysbus_connect_irq(s, 0, qdev_get_gpio_in(sms->gic, irq));
420 }
421 
422 static void create_rtc(const SBSAMachineState *sms)
423 {
424     hwaddr base = sbsa_ref_memmap[SBSA_RTC].base;
425     int irq = sbsa_ref_irqmap[SBSA_RTC];
426 
427     sysbus_create_simple("pl031", base, qdev_get_gpio_in(sms->gic, irq));
428 }
429 
430 static DeviceState *gpio_key_dev;
431 static void sbsa_ref_powerdown_req(Notifier *n, void *opaque)
432 {
433     /* use gpio Pin 3 for power button event */
434     qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1);
435 }
436 
437 static Notifier sbsa_ref_powerdown_notifier = {
438     .notify = sbsa_ref_powerdown_req
439 };
440 
441 static void create_gpio(const SBSAMachineState *sms)
442 {
443     DeviceState *pl061_dev;
444     hwaddr base = sbsa_ref_memmap[SBSA_GPIO].base;
445     int irq = sbsa_ref_irqmap[SBSA_GPIO];
446 
447     pl061_dev = sysbus_create_simple("pl061", base,
448                                      qdev_get_gpio_in(sms->gic, irq));
449 
450     gpio_key_dev = sysbus_create_simple("gpio-key", -1,
451                                         qdev_get_gpio_in(pl061_dev, 3));
452 
453     /* connect powerdown request */
454     qemu_register_powerdown_notifier(&sbsa_ref_powerdown_notifier);
455 }
456 
457 static void create_ahci(const SBSAMachineState *sms)
458 {
459     hwaddr base = sbsa_ref_memmap[SBSA_AHCI].base;
460     int irq = sbsa_ref_irqmap[SBSA_AHCI];
461     DeviceState *dev;
462     DriveInfo *hd[NUM_SATA_PORTS];
463     SysbusAHCIState *sysahci;
464     AHCIState *ahci;
465     int i;
466 
467     dev = qdev_create(NULL, "sysbus-ahci");
468     qdev_prop_set_uint32(dev, "num-ports", NUM_SATA_PORTS);
469     qdev_init_nofail(dev);
470     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
471     sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(sms->gic, irq));
472 
473     sysahci = SYSBUS_AHCI(dev);
474     ahci = &sysahci->ahci;
475     ide_drive_get(hd, ARRAY_SIZE(hd));
476     for (i = 0; i < ahci->ports; i++) {
477         if (hd[i] == NULL) {
478             continue;
479         }
480         ide_create_drive(&ahci->dev[i].port, 0, hd[i]);
481     }
482 }
483 
484 static void create_ehci(const SBSAMachineState *sms)
485 {
486     hwaddr base = sbsa_ref_memmap[SBSA_EHCI].base;
487     int irq = sbsa_ref_irqmap[SBSA_EHCI];
488 
489     sysbus_create_simple("platform-ehci-usb", base,
490                          qdev_get_gpio_in(sms->gic, irq));
491 }
492 
493 static void create_smmu(const SBSAMachineState *sms, PCIBus *bus)
494 {
495     hwaddr base = sbsa_ref_memmap[SBSA_SMMU].base;
496     int irq =  sbsa_ref_irqmap[SBSA_SMMU];
497     DeviceState *dev;
498     int i;
499 
500     dev = qdev_create(NULL, "arm-smmuv3");
501 
502     object_property_set_link(OBJECT(dev), OBJECT(bus), "primary-bus",
503                              &error_abort);
504     qdev_init_nofail(dev);
505     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
506     for (i = 0; i < NUM_SMMU_IRQS; i++) {
507         sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
508                            qdev_get_gpio_in(sms->gic, irq + 1));
509     }
510 }
511 
512 static void create_pcie(SBSAMachineState *sms)
513 {
514     hwaddr base_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].base;
515     hwaddr size_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].size;
516     hwaddr base_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].base;
517     hwaddr size_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].size;
518     hwaddr base_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].base;
519     hwaddr size_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].size;
520     hwaddr base_pio = sbsa_ref_memmap[SBSA_PCIE_PIO].base;
521     int irq = sbsa_ref_irqmap[SBSA_PCIE];
522     MemoryRegion *mmio_alias, *mmio_alias_high, *mmio_reg;
523     MemoryRegion *ecam_alias, *ecam_reg;
524     DeviceState *dev;
525     PCIHostState *pci;
526     int i;
527 
528     dev = qdev_create(NULL, TYPE_GPEX_HOST);
529     qdev_init_nofail(dev);
530 
531     /* Map ECAM space */
532     ecam_alias = g_new0(MemoryRegion, 1);
533     ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
534     memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
535                              ecam_reg, 0, size_ecam);
536     memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias);
537 
538     /* Map the MMIO space */
539     mmio_alias = g_new0(MemoryRegion, 1);
540     mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
541     memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
542                              mmio_reg, base_mmio, size_mmio);
543     memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias);
544 
545     /* Map the MMIO_HIGH space */
546     mmio_alias_high = g_new0(MemoryRegion, 1);
547     memory_region_init_alias(mmio_alias_high, OBJECT(dev), "pcie-mmio-high",
548                              mmio_reg, base_mmio_high, size_mmio_high);
549     memory_region_add_subregion(get_system_memory(), base_mmio_high,
550                                 mmio_alias_high);
551 
552     /* Map IO port space */
553     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio);
554 
555     for (i = 0; i < GPEX_NUM_IRQS; i++) {
556         sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
557                            qdev_get_gpio_in(sms->gic, irq + 1));
558         gpex_set_irq_num(GPEX_HOST(dev), i, irq + i);
559     }
560 
561     pci = PCI_HOST_BRIDGE(dev);
562     if (pci->bus) {
563         for (i = 0; i < nb_nics; i++) {
564             NICInfo *nd = &nd_table[i];
565 
566             if (!nd->model) {
567                 nd->model = g_strdup("e1000e");
568             }
569 
570             pci_nic_init_nofail(nd, pci->bus, nd->model, NULL);
571         }
572     }
573 
574     pci_create_simple(pci->bus, -1, "VGA");
575 
576     create_smmu(sms, pci->bus);
577 }
578 
579 static void *sbsa_ref_dtb(const struct arm_boot_info *binfo, int *fdt_size)
580 {
581     const SBSAMachineState *board = container_of(binfo, SBSAMachineState,
582                                                  bootinfo);
583 
584     *fdt_size = board->fdt_size;
585     return board->fdt;
586 }
587 
588 static void sbsa_ref_init(MachineState *machine)
589 {
590     unsigned int smp_cpus = machine->smp.cpus;
591     unsigned int max_cpus = machine->smp.max_cpus;
592     SBSAMachineState *sms = SBSA_MACHINE(machine);
593     MachineClass *mc = MACHINE_GET_CLASS(machine);
594     MemoryRegion *sysmem = get_system_memory();
595     MemoryRegion *secure_sysmem = g_new(MemoryRegion, 1);
596     MemoryRegion *ram = g_new(MemoryRegion, 1);
597     bool firmware_loaded;
598     const CPUArchIdList *possible_cpus;
599     int n, sbsa_max_cpus;
600 
601     if (strcmp(machine->cpu_type, ARM_CPU_TYPE_NAME("cortex-a57"))) {
602         error_report("sbsa-ref: CPU type other than the built-in "
603                      "cortex-a57 not supported");
604         exit(1);
605     }
606 
607     if (kvm_enabled()) {
608         error_report("sbsa-ref: KVM is not supported for this machine");
609         exit(1);
610     }
611 
612     /*
613      * The Secure view of the world is the same as the NonSecure,
614      * but with a few extra devices. Create it as a container region
615      * containing the system memory at low priority; any secure-only
616      * devices go in at higher priority and take precedence.
617      */
618     memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory",
619                        UINT64_MAX);
620     memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1);
621 
622     firmware_loaded = sbsa_firmware_init(sms, sysmem, secure_sysmem);
623 
624     if (machine->kernel_filename && firmware_loaded) {
625         error_report("sbsa-ref: No fw_cfg device on this machine, "
626                      "so -kernel option is not supported when firmware loaded, "
627                      "please load OS from hard disk instead");
628         exit(1);
629     }
630 
631     /*
632      * This machine has EL3 enabled, external firmware should supply PSCI
633      * implementation, so the QEMU's internal PSCI is disabled.
634      */
635     sms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED;
636 
637     sbsa_max_cpus = sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE;
638 
639     if (max_cpus > sbsa_max_cpus) {
640         error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
641                      "supported by machine 'sbsa-ref' (%d)",
642                      max_cpus, sbsa_max_cpus);
643         exit(1);
644     }
645 
646     sms->smp_cpus = smp_cpus;
647 
648     if (machine->ram_size > sbsa_ref_memmap[SBSA_MEM].size) {
649         error_report("sbsa-ref: cannot model more than %dGB RAM", RAMLIMIT_GB);
650         exit(1);
651     }
652 
653     possible_cpus = mc->possible_cpu_arch_ids(machine);
654     for (n = 0; n < possible_cpus->len; n++) {
655         Object *cpuobj;
656         CPUState *cs;
657 
658         if (n >= smp_cpus) {
659             break;
660         }
661 
662         cpuobj = object_new(possible_cpus->cpus[n].type);
663         object_property_set_int(cpuobj, possible_cpus->cpus[n].arch_id,
664                                 "mp-affinity", NULL);
665 
666         cs = CPU(cpuobj);
667         cs->cpu_index = n;
668 
669         numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj),
670                           &error_fatal);
671 
672         if (object_property_find(cpuobj, "reset-cbar", NULL)) {
673             object_property_set_int(cpuobj,
674                                     sbsa_ref_memmap[SBSA_CPUPERIPHS].base,
675                                     "reset-cbar", &error_abort);
676         }
677 
678         object_property_set_link(cpuobj, OBJECT(sysmem), "memory",
679                                  &error_abort);
680 
681         object_property_set_link(cpuobj, OBJECT(secure_sysmem),
682                                  "secure-memory", &error_abort);
683 
684         object_property_set_bool(cpuobj, true, "realized", &error_fatal);
685         object_unref(cpuobj);
686     }
687 
688     memory_region_allocate_system_memory(ram, NULL, "sbsa-ref.ram",
689                                          machine->ram_size);
690     memory_region_add_subregion(sysmem, sbsa_ref_memmap[SBSA_MEM].base, ram);
691 
692     create_fdt(sms);
693 
694     create_secure_ram(sms, secure_sysmem);
695 
696     create_gic(sms);
697 
698     create_uart(sms, SBSA_UART, sysmem, serial_hd(0));
699     create_uart(sms, SBSA_SECURE_UART, secure_sysmem, serial_hd(1));
700     /* Second secure UART for RAS and MM from EL0 */
701     create_uart(sms, SBSA_SECURE_UART_MM, secure_sysmem, serial_hd(2));
702 
703     create_rtc(sms);
704 
705     create_gpio(sms);
706 
707     create_ahci(sms);
708 
709     create_ehci(sms);
710 
711     create_pcie(sms);
712 
713     sms->bootinfo.ram_size = machine->ram_size;
714     sms->bootinfo.nb_cpus = smp_cpus;
715     sms->bootinfo.board_id = -1;
716     sms->bootinfo.loader_start = sbsa_ref_memmap[SBSA_MEM].base;
717     sms->bootinfo.get_dtb = sbsa_ref_dtb;
718     sms->bootinfo.firmware_loaded = firmware_loaded;
719     arm_load_kernel(ARM_CPU(first_cpu), machine, &sms->bootinfo);
720 }
721 
722 static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx)
723 {
724     uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER;
725     return arm_cpu_mp_affinity(idx, clustersz);
726 }
727 
728 static const CPUArchIdList *sbsa_ref_possible_cpu_arch_ids(MachineState *ms)
729 {
730     unsigned int max_cpus = ms->smp.max_cpus;
731     SBSAMachineState *sms = SBSA_MACHINE(ms);
732     int n;
733 
734     if (ms->possible_cpus) {
735         assert(ms->possible_cpus->len == max_cpus);
736         return ms->possible_cpus;
737     }
738 
739     ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
740                                   sizeof(CPUArchId) * max_cpus);
741     ms->possible_cpus->len = max_cpus;
742     for (n = 0; n < ms->possible_cpus->len; n++) {
743         ms->possible_cpus->cpus[n].type = ms->cpu_type;
744         ms->possible_cpus->cpus[n].arch_id =
745             sbsa_ref_cpu_mp_affinity(sms, n);
746         ms->possible_cpus->cpus[n].props.has_thread_id = true;
747         ms->possible_cpus->cpus[n].props.thread_id = n;
748     }
749     return ms->possible_cpus;
750 }
751 
752 static CpuInstanceProperties
753 sbsa_ref_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
754 {
755     MachineClass *mc = MACHINE_GET_CLASS(ms);
756     const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms);
757 
758     assert(cpu_index < possible_cpus->len);
759     return possible_cpus->cpus[cpu_index].props;
760 }
761 
762 static int64_t
763 sbsa_ref_get_default_cpu_node_id(const MachineState *ms, int idx)
764 {
765     return idx % ms->numa_state->num_nodes;
766 }
767 
768 static void sbsa_ref_instance_init(Object *obj)
769 {
770     SBSAMachineState *sms = SBSA_MACHINE(obj);
771 
772     sbsa_flash_create(sms);
773 }
774 
775 static void sbsa_ref_class_init(ObjectClass *oc, void *data)
776 {
777     MachineClass *mc = MACHINE_CLASS(oc);
778 
779     mc->init = sbsa_ref_init;
780     mc->desc = "QEMU 'SBSA Reference' ARM Virtual Machine";
781     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a57");
782     mc->max_cpus = 512;
783     mc->pci_allow_0_address = true;
784     mc->minimum_page_bits = 12;
785     mc->block_default_type = IF_IDE;
786     mc->no_cdrom = 1;
787     mc->default_ram_size = 1 * GiB;
788     mc->default_cpus = 4;
789     mc->possible_cpu_arch_ids = sbsa_ref_possible_cpu_arch_ids;
790     mc->cpu_index_to_instance_props = sbsa_ref_cpu_index_to_props;
791     mc->get_default_cpu_node_id = sbsa_ref_get_default_cpu_node_id;
792     mc->numa_mem_supported = true;
793 }
794 
795 static const TypeInfo sbsa_ref_info = {
796     .name          = TYPE_SBSA_MACHINE,
797     .parent        = TYPE_MACHINE,
798     .instance_init = sbsa_ref_instance_init,
799     .class_init    = sbsa_ref_class_init,
800     .instance_size = sizeof(SBSAMachineState),
801 };
802 
803 static void sbsa_ref_machine_init(void)
804 {
805     type_register_static(&sbsa_ref_info);
806 }
807 
808 type_init(sbsa_ref_machine_init);
809