1 /* 2 * ARM SBSA Reference Platform emulation 3 * 4 * Copyright (c) 2018 Linaro Limited 5 * Written by Hongbo Zhang <hongbo.zhang@linaro.org> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu-common.h" 22 #include "qapi/error.h" 23 #include "qemu/error-report.h" 24 #include "qemu/units.h" 25 #include "sysemu/device_tree.h" 26 #include "sysemu/numa.h" 27 #include "sysemu/runstate.h" 28 #include "sysemu/sysemu.h" 29 #include "exec/address-spaces.h" 30 #include "exec/hwaddr.h" 31 #include "kvm_arm.h" 32 #include "hw/arm/boot.h" 33 #include "hw/block/flash.h" 34 #include "hw/boards.h" 35 #include "hw/ide/internal.h" 36 #include "hw/ide/ahci_internal.h" 37 #include "hw/intc/arm_gicv3_common.h" 38 #include "hw/loader.h" 39 #include "hw/pci-host/gpex.h" 40 #include "hw/qdev-properties.h" 41 #include "hw/usb.h" 42 #include "hw/char/pl011.h" 43 #include "net/net.h" 44 45 #define RAMLIMIT_GB 8192 46 #define RAMLIMIT_BYTES (RAMLIMIT_GB * GiB) 47 48 #define NUM_IRQS 256 49 #define NUM_SMMU_IRQS 4 50 #define NUM_SATA_PORTS 6 51 52 #define VIRTUAL_PMU_IRQ 7 53 #define ARCH_GIC_MAINT_IRQ 9 54 #define ARCH_TIMER_VIRT_IRQ 11 55 #define ARCH_TIMER_S_EL1_IRQ 13 56 #define ARCH_TIMER_NS_EL1_IRQ 14 57 #define ARCH_TIMER_NS_EL2_IRQ 10 58 59 enum { 60 SBSA_FLASH, 61 SBSA_MEM, 62 SBSA_CPUPERIPHS, 63 SBSA_GIC_DIST, 64 SBSA_GIC_REDIST, 65 SBSA_SMMU, 66 SBSA_UART, 67 SBSA_RTC, 68 SBSA_PCIE, 69 SBSA_PCIE_MMIO, 70 SBSA_PCIE_MMIO_HIGH, 71 SBSA_PCIE_PIO, 72 SBSA_PCIE_ECAM, 73 SBSA_GPIO, 74 SBSA_SECURE_UART, 75 SBSA_SECURE_UART_MM, 76 SBSA_SECURE_MEM, 77 SBSA_AHCI, 78 SBSA_EHCI, 79 }; 80 81 typedef struct MemMapEntry { 82 hwaddr base; 83 hwaddr size; 84 } MemMapEntry; 85 86 typedef struct { 87 MachineState parent; 88 struct arm_boot_info bootinfo; 89 int smp_cpus; 90 void *fdt; 91 int fdt_size; 92 int psci_conduit; 93 DeviceState *gic; 94 PFlashCFI01 *flash[2]; 95 } SBSAMachineState; 96 97 #define TYPE_SBSA_MACHINE MACHINE_TYPE_NAME("sbsa-ref") 98 #define SBSA_MACHINE(obj) \ 99 OBJECT_CHECK(SBSAMachineState, (obj), TYPE_SBSA_MACHINE) 100 101 static const MemMapEntry sbsa_ref_memmap[] = { 102 /* 512M boot ROM */ 103 [SBSA_FLASH] = { 0, 0x20000000 }, 104 /* 512M secure memory */ 105 [SBSA_SECURE_MEM] = { 0x20000000, 0x20000000 }, 106 /* Space reserved for CPU peripheral devices */ 107 [SBSA_CPUPERIPHS] = { 0x40000000, 0x00040000 }, 108 [SBSA_GIC_DIST] = { 0x40060000, 0x00010000 }, 109 [SBSA_GIC_REDIST] = { 0x40080000, 0x04000000 }, 110 [SBSA_UART] = { 0x60000000, 0x00001000 }, 111 [SBSA_RTC] = { 0x60010000, 0x00001000 }, 112 [SBSA_GPIO] = { 0x60020000, 0x00001000 }, 113 [SBSA_SECURE_UART] = { 0x60030000, 0x00001000 }, 114 [SBSA_SECURE_UART_MM] = { 0x60040000, 0x00001000 }, 115 [SBSA_SMMU] = { 0x60050000, 0x00020000 }, 116 /* Space here reserved for more SMMUs */ 117 [SBSA_AHCI] = { 0x60100000, 0x00010000 }, 118 [SBSA_EHCI] = { 0x60110000, 0x00010000 }, 119 /* Space here reserved for other devices */ 120 [SBSA_PCIE_PIO] = { 0x7fff0000, 0x00010000 }, 121 /* 32-bit address PCIE MMIO space */ 122 [SBSA_PCIE_MMIO] = { 0x80000000, 0x70000000 }, 123 /* 256M PCIE ECAM space */ 124 [SBSA_PCIE_ECAM] = { 0xf0000000, 0x10000000 }, 125 /* ~1TB PCIE MMIO space (4GB to 1024GB boundary) */ 126 [SBSA_PCIE_MMIO_HIGH] = { 0x100000000ULL, 0xFF00000000ULL }, 127 [SBSA_MEM] = { 0x10000000000ULL, RAMLIMIT_BYTES }, 128 }; 129 130 static const int sbsa_ref_irqmap[] = { 131 [SBSA_UART] = 1, 132 [SBSA_RTC] = 2, 133 [SBSA_PCIE] = 3, /* ... to 6 */ 134 [SBSA_GPIO] = 7, 135 [SBSA_SECURE_UART] = 8, 136 [SBSA_SECURE_UART_MM] = 9, 137 [SBSA_AHCI] = 10, 138 [SBSA_EHCI] = 11, 139 }; 140 141 /* 142 * Firmware on this machine only uses ACPI table to load OS, these limited 143 * device tree nodes are just to let firmware know the info which varies from 144 * command line parameters, so it is not necessary to be fully compatible 145 * with the kernel CPU and NUMA binding rules. 146 */ 147 static void create_fdt(SBSAMachineState *sms) 148 { 149 void *fdt = create_device_tree(&sms->fdt_size); 150 const MachineState *ms = MACHINE(sms); 151 int nb_numa_nodes = ms->numa_state->num_nodes; 152 int cpu; 153 154 if (!fdt) { 155 error_report("create_device_tree() failed"); 156 exit(1); 157 } 158 159 sms->fdt = fdt; 160 161 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,sbsa-ref"); 162 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 163 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 164 165 if (ms->numa_state->have_numa_distance) { 166 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); 167 uint32_t *matrix = g_malloc0(size); 168 int idx, i, j; 169 170 for (i = 0; i < nb_numa_nodes; i++) { 171 for (j = 0; j < nb_numa_nodes; j++) { 172 idx = (i * nb_numa_nodes + j) * 3; 173 matrix[idx + 0] = cpu_to_be32(i); 174 matrix[idx + 1] = cpu_to_be32(j); 175 matrix[idx + 2] = 176 cpu_to_be32(ms->numa_state->nodes[i].distance[j]); 177 } 178 } 179 180 qemu_fdt_add_subnode(fdt, "/distance-map"); 181 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", 182 matrix, size); 183 g_free(matrix); 184 } 185 186 qemu_fdt_add_subnode(sms->fdt, "/cpus"); 187 188 for (cpu = sms->smp_cpus - 1; cpu >= 0; cpu--) { 189 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 190 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 191 CPUState *cs = CPU(armcpu); 192 193 qemu_fdt_add_subnode(sms->fdt, nodename); 194 195 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 196 qemu_fdt_setprop_cell(sms->fdt, nodename, "numa-node-id", 197 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 198 } 199 200 g_free(nodename); 201 } 202 } 203 204 #define SBSA_FLASH_SECTOR_SIZE (256 * KiB) 205 206 static PFlashCFI01 *sbsa_flash_create1(SBSAMachineState *sms, 207 const char *name, 208 const char *alias_prop_name) 209 { 210 /* 211 * Create a single flash device. We use the same parameters as 212 * the flash devices on the Versatile Express board. 213 */ 214 DeviceState *dev = qdev_create(NULL, TYPE_PFLASH_CFI01); 215 216 qdev_prop_set_uint64(dev, "sector-length", SBSA_FLASH_SECTOR_SIZE); 217 qdev_prop_set_uint8(dev, "width", 4); 218 qdev_prop_set_uint8(dev, "device-width", 2); 219 qdev_prop_set_bit(dev, "big-endian", false); 220 qdev_prop_set_uint16(dev, "id0", 0x89); 221 qdev_prop_set_uint16(dev, "id1", 0x18); 222 qdev_prop_set_uint16(dev, "id2", 0x00); 223 qdev_prop_set_uint16(dev, "id3", 0x00); 224 qdev_prop_set_string(dev, "name", name); 225 object_property_add_child(OBJECT(sms), name, OBJECT(dev), 226 &error_abort); 227 object_property_add_alias(OBJECT(sms), alias_prop_name, 228 OBJECT(dev), "drive", &error_abort); 229 return PFLASH_CFI01(dev); 230 } 231 232 static void sbsa_flash_create(SBSAMachineState *sms) 233 { 234 sms->flash[0] = sbsa_flash_create1(sms, "sbsa.flash0", "pflash0"); 235 sms->flash[1] = sbsa_flash_create1(sms, "sbsa.flash1", "pflash1"); 236 } 237 238 static void sbsa_flash_map1(PFlashCFI01 *flash, 239 hwaddr base, hwaddr size, 240 MemoryRegion *sysmem) 241 { 242 DeviceState *dev = DEVICE(flash); 243 244 assert(size % SBSA_FLASH_SECTOR_SIZE == 0); 245 assert(size / SBSA_FLASH_SECTOR_SIZE <= UINT32_MAX); 246 qdev_prop_set_uint32(dev, "num-blocks", size / SBSA_FLASH_SECTOR_SIZE); 247 qdev_init_nofail(dev); 248 249 memory_region_add_subregion(sysmem, base, 250 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 251 0)); 252 } 253 254 static void sbsa_flash_map(SBSAMachineState *sms, 255 MemoryRegion *sysmem, 256 MemoryRegion *secure_sysmem) 257 { 258 /* 259 * Map two flash devices to fill the SBSA_FLASH space in the memmap. 260 * sysmem is the system memory space. secure_sysmem is the secure view 261 * of the system, and the first flash device should be made visible only 262 * there. The second flash device is visible to both secure and nonsecure. 263 */ 264 hwaddr flashsize = sbsa_ref_memmap[SBSA_FLASH].size / 2; 265 hwaddr flashbase = sbsa_ref_memmap[SBSA_FLASH].base; 266 267 sbsa_flash_map1(sms->flash[0], flashbase, flashsize, 268 secure_sysmem); 269 sbsa_flash_map1(sms->flash[1], flashbase + flashsize, flashsize, 270 sysmem); 271 } 272 273 static bool sbsa_firmware_init(SBSAMachineState *sms, 274 MemoryRegion *sysmem, 275 MemoryRegion *secure_sysmem) 276 { 277 int i; 278 BlockBackend *pflash_blk0; 279 280 /* Map legacy -drive if=pflash to machine properties */ 281 for (i = 0; i < ARRAY_SIZE(sms->flash); i++) { 282 pflash_cfi01_legacy_drive(sms->flash[i], 283 drive_get(IF_PFLASH, 0, i)); 284 } 285 286 sbsa_flash_map(sms, sysmem, secure_sysmem); 287 288 pflash_blk0 = pflash_cfi01_get_blk(sms->flash[0]); 289 290 if (bios_name) { 291 char *fname; 292 MemoryRegion *mr; 293 int image_size; 294 295 if (pflash_blk0) { 296 error_report("The contents of the first flash device may be " 297 "specified with -bios or with -drive if=pflash... " 298 "but you cannot use both options at once"); 299 exit(1); 300 } 301 302 /* Fall back to -bios */ 303 304 fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 305 if (!fname) { 306 error_report("Could not find ROM image '%s'", bios_name); 307 exit(1); 308 } 309 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(sms->flash[0]), 0); 310 image_size = load_image_mr(fname, mr); 311 g_free(fname); 312 if (image_size < 0) { 313 error_report("Could not load ROM image '%s'", bios_name); 314 exit(1); 315 } 316 } 317 318 return pflash_blk0 || bios_name; 319 } 320 321 static void create_secure_ram(SBSAMachineState *sms, 322 MemoryRegion *secure_sysmem) 323 { 324 MemoryRegion *secram = g_new(MemoryRegion, 1); 325 hwaddr base = sbsa_ref_memmap[SBSA_SECURE_MEM].base; 326 hwaddr size = sbsa_ref_memmap[SBSA_SECURE_MEM].size; 327 328 memory_region_init_ram(secram, NULL, "sbsa-ref.secure-ram", size, 329 &error_fatal); 330 memory_region_add_subregion(secure_sysmem, base, secram); 331 } 332 333 static void create_gic(SBSAMachineState *sms) 334 { 335 unsigned int smp_cpus = MACHINE(sms)->smp.cpus; 336 SysBusDevice *gicbusdev; 337 const char *gictype; 338 uint32_t redist0_capacity, redist0_count; 339 int i; 340 341 gictype = gicv3_class_name(); 342 343 sms->gic = qdev_create(NULL, gictype); 344 qdev_prop_set_uint32(sms->gic, "revision", 3); 345 qdev_prop_set_uint32(sms->gic, "num-cpu", smp_cpus); 346 /* 347 * Note that the num-irq property counts both internal and external 348 * interrupts; there are always 32 of the former (mandated by GIC spec). 349 */ 350 qdev_prop_set_uint32(sms->gic, "num-irq", NUM_IRQS + 32); 351 qdev_prop_set_bit(sms->gic, "has-security-extensions", true); 352 353 redist0_capacity = 354 sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE; 355 redist0_count = MIN(smp_cpus, redist0_capacity); 356 357 qdev_prop_set_uint32(sms->gic, "len-redist-region-count", 1); 358 qdev_prop_set_uint32(sms->gic, "redist-region-count[0]", redist0_count); 359 360 qdev_init_nofail(sms->gic); 361 gicbusdev = SYS_BUS_DEVICE(sms->gic); 362 sysbus_mmio_map(gicbusdev, 0, sbsa_ref_memmap[SBSA_GIC_DIST].base); 363 sysbus_mmio_map(gicbusdev, 1, sbsa_ref_memmap[SBSA_GIC_REDIST].base); 364 365 /* 366 * Wire the outputs from each CPU's generic timer and the GICv3 367 * maintenance interrupt signal to the appropriate GIC PPI inputs, 368 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. 369 */ 370 for (i = 0; i < smp_cpus; i++) { 371 DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); 372 int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; 373 int irq; 374 /* 375 * Mapping from the output timer irq lines from the CPU to the 376 * GIC PPI inputs used for this board. 377 */ 378 const int timer_irq[] = { 379 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 380 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 381 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 382 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 383 }; 384 385 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 386 qdev_connect_gpio_out(cpudev, irq, 387 qdev_get_gpio_in(sms->gic, 388 ppibase + timer_irq[irq])); 389 } 390 391 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0, 392 qdev_get_gpio_in(sms->gic, ppibase 393 + ARCH_GIC_MAINT_IRQ)); 394 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 395 qdev_get_gpio_in(sms->gic, ppibase 396 + VIRTUAL_PMU_IRQ)); 397 398 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 399 sysbus_connect_irq(gicbusdev, i + smp_cpus, 400 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 401 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, 402 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 403 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, 404 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 405 } 406 } 407 408 static void create_uart(const SBSAMachineState *sms, int uart, 409 MemoryRegion *mem, Chardev *chr) 410 { 411 hwaddr base = sbsa_ref_memmap[uart].base; 412 int irq = sbsa_ref_irqmap[uart]; 413 DeviceState *dev = qdev_create(NULL, TYPE_PL011); 414 SysBusDevice *s = SYS_BUS_DEVICE(dev); 415 416 qdev_prop_set_chr(dev, "chardev", chr); 417 qdev_init_nofail(dev); 418 memory_region_add_subregion(mem, base, 419 sysbus_mmio_get_region(s, 0)); 420 sysbus_connect_irq(s, 0, qdev_get_gpio_in(sms->gic, irq)); 421 } 422 423 static void create_rtc(const SBSAMachineState *sms) 424 { 425 hwaddr base = sbsa_ref_memmap[SBSA_RTC].base; 426 int irq = sbsa_ref_irqmap[SBSA_RTC]; 427 428 sysbus_create_simple("pl031", base, qdev_get_gpio_in(sms->gic, irq)); 429 } 430 431 static DeviceState *gpio_key_dev; 432 static void sbsa_ref_powerdown_req(Notifier *n, void *opaque) 433 { 434 /* use gpio Pin 3 for power button event */ 435 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); 436 } 437 438 static Notifier sbsa_ref_powerdown_notifier = { 439 .notify = sbsa_ref_powerdown_req 440 }; 441 442 static void create_gpio(const SBSAMachineState *sms) 443 { 444 DeviceState *pl061_dev; 445 hwaddr base = sbsa_ref_memmap[SBSA_GPIO].base; 446 int irq = sbsa_ref_irqmap[SBSA_GPIO]; 447 448 pl061_dev = sysbus_create_simple("pl061", base, 449 qdev_get_gpio_in(sms->gic, irq)); 450 451 gpio_key_dev = sysbus_create_simple("gpio-key", -1, 452 qdev_get_gpio_in(pl061_dev, 3)); 453 454 /* connect powerdown request */ 455 qemu_register_powerdown_notifier(&sbsa_ref_powerdown_notifier); 456 } 457 458 static void create_ahci(const SBSAMachineState *sms) 459 { 460 hwaddr base = sbsa_ref_memmap[SBSA_AHCI].base; 461 int irq = sbsa_ref_irqmap[SBSA_AHCI]; 462 DeviceState *dev; 463 DriveInfo *hd[NUM_SATA_PORTS]; 464 SysbusAHCIState *sysahci; 465 AHCIState *ahci; 466 int i; 467 468 dev = qdev_create(NULL, "sysbus-ahci"); 469 qdev_prop_set_uint32(dev, "num-ports", NUM_SATA_PORTS); 470 qdev_init_nofail(dev); 471 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 472 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(sms->gic, irq)); 473 474 sysahci = SYSBUS_AHCI(dev); 475 ahci = &sysahci->ahci; 476 ide_drive_get(hd, ARRAY_SIZE(hd)); 477 for (i = 0; i < ahci->ports; i++) { 478 if (hd[i] == NULL) { 479 continue; 480 } 481 ide_create_drive(&ahci->dev[i].port, 0, hd[i]); 482 } 483 } 484 485 static void create_ehci(const SBSAMachineState *sms) 486 { 487 hwaddr base = sbsa_ref_memmap[SBSA_EHCI].base; 488 int irq = sbsa_ref_irqmap[SBSA_EHCI]; 489 490 sysbus_create_simple("platform-ehci-usb", base, 491 qdev_get_gpio_in(sms->gic, irq)); 492 } 493 494 static void create_smmu(const SBSAMachineState *sms, PCIBus *bus) 495 { 496 hwaddr base = sbsa_ref_memmap[SBSA_SMMU].base; 497 int irq = sbsa_ref_irqmap[SBSA_SMMU]; 498 DeviceState *dev; 499 int i; 500 501 dev = qdev_create(NULL, "arm-smmuv3"); 502 503 object_property_set_link(OBJECT(dev), OBJECT(bus), "primary-bus", 504 &error_abort); 505 qdev_init_nofail(dev); 506 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 507 for (i = 0; i < NUM_SMMU_IRQS; i++) { 508 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 509 qdev_get_gpio_in(sms->gic, irq + 1)); 510 } 511 } 512 513 static void create_pcie(SBSAMachineState *sms) 514 { 515 hwaddr base_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].base; 516 hwaddr size_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].size; 517 hwaddr base_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].base; 518 hwaddr size_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].size; 519 hwaddr base_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].base; 520 hwaddr size_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].size; 521 hwaddr base_pio = sbsa_ref_memmap[SBSA_PCIE_PIO].base; 522 int irq = sbsa_ref_irqmap[SBSA_PCIE]; 523 MemoryRegion *mmio_alias, *mmio_alias_high, *mmio_reg; 524 MemoryRegion *ecam_alias, *ecam_reg; 525 DeviceState *dev; 526 PCIHostState *pci; 527 int i; 528 529 dev = qdev_create(NULL, TYPE_GPEX_HOST); 530 qdev_init_nofail(dev); 531 532 /* Map ECAM space */ 533 ecam_alias = g_new0(MemoryRegion, 1); 534 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 535 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 536 ecam_reg, 0, size_ecam); 537 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); 538 539 /* Map the MMIO space */ 540 mmio_alias = g_new0(MemoryRegion, 1); 541 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 542 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 543 mmio_reg, base_mmio, size_mmio); 544 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); 545 546 /* Map the MMIO_HIGH space */ 547 mmio_alias_high = g_new0(MemoryRegion, 1); 548 memory_region_init_alias(mmio_alias_high, OBJECT(dev), "pcie-mmio-high", 549 mmio_reg, base_mmio_high, size_mmio_high); 550 memory_region_add_subregion(get_system_memory(), base_mmio_high, 551 mmio_alias_high); 552 553 /* Map IO port space */ 554 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); 555 556 for (i = 0; i < GPEX_NUM_IRQS; i++) { 557 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 558 qdev_get_gpio_in(sms->gic, irq + 1)); 559 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); 560 } 561 562 pci = PCI_HOST_BRIDGE(dev); 563 if (pci->bus) { 564 for (i = 0; i < nb_nics; i++) { 565 NICInfo *nd = &nd_table[i]; 566 567 if (!nd->model) { 568 nd->model = g_strdup("e1000e"); 569 } 570 571 pci_nic_init_nofail(nd, pci->bus, nd->model, NULL); 572 } 573 } 574 575 pci_create_simple(pci->bus, -1, "VGA"); 576 577 create_smmu(sms, pci->bus); 578 } 579 580 static void *sbsa_ref_dtb(const struct arm_boot_info *binfo, int *fdt_size) 581 { 582 const SBSAMachineState *board = container_of(binfo, SBSAMachineState, 583 bootinfo); 584 585 *fdt_size = board->fdt_size; 586 return board->fdt; 587 } 588 589 static void sbsa_ref_init(MachineState *machine) 590 { 591 unsigned int smp_cpus = machine->smp.cpus; 592 unsigned int max_cpus = machine->smp.max_cpus; 593 SBSAMachineState *sms = SBSA_MACHINE(machine); 594 MachineClass *mc = MACHINE_GET_CLASS(machine); 595 MemoryRegion *sysmem = get_system_memory(); 596 MemoryRegion *secure_sysmem = g_new(MemoryRegion, 1); 597 bool firmware_loaded; 598 const CPUArchIdList *possible_cpus; 599 int n, sbsa_max_cpus; 600 601 if (strcmp(machine->cpu_type, ARM_CPU_TYPE_NAME("cortex-a57"))) { 602 error_report("sbsa-ref: CPU type other than the built-in " 603 "cortex-a57 not supported"); 604 exit(1); 605 } 606 607 if (kvm_enabled()) { 608 error_report("sbsa-ref: KVM is not supported for this machine"); 609 exit(1); 610 } 611 612 /* 613 * The Secure view of the world is the same as the NonSecure, 614 * but with a few extra devices. Create it as a container region 615 * containing the system memory at low priority; any secure-only 616 * devices go in at higher priority and take precedence. 617 */ 618 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", 619 UINT64_MAX); 620 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); 621 622 firmware_loaded = sbsa_firmware_init(sms, sysmem, secure_sysmem); 623 624 if (machine->kernel_filename && firmware_loaded) { 625 error_report("sbsa-ref: No fw_cfg device on this machine, " 626 "so -kernel option is not supported when firmware loaded, " 627 "please load OS from hard disk instead"); 628 exit(1); 629 } 630 631 /* 632 * This machine has EL3 enabled, external firmware should supply PSCI 633 * implementation, so the QEMU's internal PSCI is disabled. 634 */ 635 sms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; 636 637 sbsa_max_cpus = sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE; 638 639 if (max_cpus > sbsa_max_cpus) { 640 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " 641 "supported by machine 'sbsa-ref' (%d)", 642 max_cpus, sbsa_max_cpus); 643 exit(1); 644 } 645 646 sms->smp_cpus = smp_cpus; 647 648 if (machine->ram_size > sbsa_ref_memmap[SBSA_MEM].size) { 649 error_report("sbsa-ref: cannot model more than %dGB RAM", RAMLIMIT_GB); 650 exit(1); 651 } 652 653 possible_cpus = mc->possible_cpu_arch_ids(machine); 654 for (n = 0; n < possible_cpus->len; n++) { 655 Object *cpuobj; 656 CPUState *cs; 657 658 if (n >= smp_cpus) { 659 break; 660 } 661 662 cpuobj = object_new(possible_cpus->cpus[n].type); 663 object_property_set_int(cpuobj, possible_cpus->cpus[n].arch_id, 664 "mp-affinity", NULL); 665 666 cs = CPU(cpuobj); 667 cs->cpu_index = n; 668 669 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj), 670 &error_fatal); 671 672 if (object_property_find(cpuobj, "reset-cbar", NULL)) { 673 object_property_set_int(cpuobj, 674 sbsa_ref_memmap[SBSA_CPUPERIPHS].base, 675 "reset-cbar", &error_abort); 676 } 677 678 object_property_set_link(cpuobj, OBJECT(sysmem), "memory", 679 &error_abort); 680 681 object_property_set_link(cpuobj, OBJECT(secure_sysmem), 682 "secure-memory", &error_abort); 683 684 object_property_set_bool(cpuobj, true, "realized", &error_fatal); 685 object_unref(cpuobj); 686 } 687 688 memory_region_add_subregion(sysmem, sbsa_ref_memmap[SBSA_MEM].base, 689 machine->ram); 690 691 create_fdt(sms); 692 693 create_secure_ram(sms, secure_sysmem); 694 695 create_gic(sms); 696 697 create_uart(sms, SBSA_UART, sysmem, serial_hd(0)); 698 create_uart(sms, SBSA_SECURE_UART, secure_sysmem, serial_hd(1)); 699 /* Second secure UART for RAS and MM from EL0 */ 700 create_uart(sms, SBSA_SECURE_UART_MM, secure_sysmem, serial_hd(2)); 701 702 create_rtc(sms); 703 704 create_gpio(sms); 705 706 create_ahci(sms); 707 708 create_ehci(sms); 709 710 create_pcie(sms); 711 712 sms->bootinfo.ram_size = machine->ram_size; 713 sms->bootinfo.nb_cpus = smp_cpus; 714 sms->bootinfo.board_id = -1; 715 sms->bootinfo.loader_start = sbsa_ref_memmap[SBSA_MEM].base; 716 sms->bootinfo.get_dtb = sbsa_ref_dtb; 717 sms->bootinfo.firmware_loaded = firmware_loaded; 718 arm_load_kernel(ARM_CPU(first_cpu), machine, &sms->bootinfo); 719 } 720 721 static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx) 722 { 723 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER; 724 return arm_cpu_mp_affinity(idx, clustersz); 725 } 726 727 static const CPUArchIdList *sbsa_ref_possible_cpu_arch_ids(MachineState *ms) 728 { 729 unsigned int max_cpus = ms->smp.max_cpus; 730 SBSAMachineState *sms = SBSA_MACHINE(ms); 731 int n; 732 733 if (ms->possible_cpus) { 734 assert(ms->possible_cpus->len == max_cpus); 735 return ms->possible_cpus; 736 } 737 738 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 739 sizeof(CPUArchId) * max_cpus); 740 ms->possible_cpus->len = max_cpus; 741 for (n = 0; n < ms->possible_cpus->len; n++) { 742 ms->possible_cpus->cpus[n].type = ms->cpu_type; 743 ms->possible_cpus->cpus[n].arch_id = 744 sbsa_ref_cpu_mp_affinity(sms, n); 745 ms->possible_cpus->cpus[n].props.has_thread_id = true; 746 ms->possible_cpus->cpus[n].props.thread_id = n; 747 } 748 return ms->possible_cpus; 749 } 750 751 static CpuInstanceProperties 752 sbsa_ref_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 753 { 754 MachineClass *mc = MACHINE_GET_CLASS(ms); 755 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 756 757 assert(cpu_index < possible_cpus->len); 758 return possible_cpus->cpus[cpu_index].props; 759 } 760 761 static int64_t 762 sbsa_ref_get_default_cpu_node_id(const MachineState *ms, int idx) 763 { 764 return idx % ms->numa_state->num_nodes; 765 } 766 767 static void sbsa_ref_instance_init(Object *obj) 768 { 769 SBSAMachineState *sms = SBSA_MACHINE(obj); 770 771 sbsa_flash_create(sms); 772 } 773 774 static void sbsa_ref_class_init(ObjectClass *oc, void *data) 775 { 776 MachineClass *mc = MACHINE_CLASS(oc); 777 778 mc->init = sbsa_ref_init; 779 mc->desc = "QEMU 'SBSA Reference' ARM Virtual Machine"; 780 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a57"); 781 mc->max_cpus = 512; 782 mc->pci_allow_0_address = true; 783 mc->minimum_page_bits = 12; 784 mc->block_default_type = IF_IDE; 785 mc->no_cdrom = 1; 786 mc->default_ram_size = 1 * GiB; 787 mc->default_ram_id = "sbsa-ref.ram"; 788 mc->default_cpus = 4; 789 mc->possible_cpu_arch_ids = sbsa_ref_possible_cpu_arch_ids; 790 mc->cpu_index_to_instance_props = sbsa_ref_cpu_index_to_props; 791 mc->get_default_cpu_node_id = sbsa_ref_get_default_cpu_node_id; 792 } 793 794 static const TypeInfo sbsa_ref_info = { 795 .name = TYPE_SBSA_MACHINE, 796 .parent = TYPE_MACHINE, 797 .instance_init = sbsa_ref_instance_init, 798 .class_init = sbsa_ref_class_init, 799 .instance_size = sizeof(SBSAMachineState), 800 }; 801 802 static void sbsa_ref_machine_init(void) 803 { 804 type_register_static(&sbsa_ref_info); 805 } 806 807 type_init(sbsa_ref_machine_init); 808