1 /* 2 * ARM SBSA Reference Platform emulation 3 * 4 * Copyright (c) 2018 Linaro Limited 5 * Written by Hongbo Zhang <hongbo.zhang@linaro.org> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/datadir.h" 22 #include "qapi/error.h" 23 #include "qemu/error-report.h" 24 #include "qemu/units.h" 25 #include "sysemu/device_tree.h" 26 #include "sysemu/numa.h" 27 #include "sysemu/runstate.h" 28 #include "sysemu/sysemu.h" 29 #include "exec/hwaddr.h" 30 #include "kvm_arm.h" 31 #include "hw/arm/boot.h" 32 #include "hw/block/flash.h" 33 #include "hw/boards.h" 34 #include "hw/ide/internal.h" 35 #include "hw/ide/ahci_internal.h" 36 #include "hw/intc/arm_gicv3_common.h" 37 #include "hw/loader.h" 38 #include "hw/pci-host/gpex.h" 39 #include "hw/qdev-properties.h" 40 #include "hw/usb.h" 41 #include "hw/char/pl011.h" 42 #include "hw/watchdog/sbsa_gwdt.h" 43 #include "net/net.h" 44 #include "qom/object.h" 45 46 #define RAMLIMIT_GB 8192 47 #define RAMLIMIT_BYTES (RAMLIMIT_GB * GiB) 48 49 #define NUM_IRQS 256 50 #define NUM_SMMU_IRQS 4 51 #define NUM_SATA_PORTS 6 52 53 #define VIRTUAL_PMU_IRQ 7 54 #define ARCH_GIC_MAINT_IRQ 9 55 #define ARCH_TIMER_VIRT_IRQ 11 56 #define ARCH_TIMER_S_EL1_IRQ 13 57 #define ARCH_TIMER_NS_EL1_IRQ 14 58 #define ARCH_TIMER_NS_EL2_IRQ 10 59 60 enum { 61 SBSA_FLASH, 62 SBSA_MEM, 63 SBSA_CPUPERIPHS, 64 SBSA_GIC_DIST, 65 SBSA_GIC_REDIST, 66 SBSA_SECURE_EC, 67 SBSA_GWDT_WS0, 68 SBSA_GWDT_REFRESH, 69 SBSA_GWDT_CONTROL, 70 SBSA_SMMU, 71 SBSA_UART, 72 SBSA_RTC, 73 SBSA_PCIE, 74 SBSA_PCIE_MMIO, 75 SBSA_PCIE_MMIO_HIGH, 76 SBSA_PCIE_PIO, 77 SBSA_PCIE_ECAM, 78 SBSA_GPIO, 79 SBSA_SECURE_UART, 80 SBSA_SECURE_UART_MM, 81 SBSA_SECURE_MEM, 82 SBSA_AHCI, 83 SBSA_EHCI, 84 }; 85 86 struct SBSAMachineState { 87 MachineState parent; 88 struct arm_boot_info bootinfo; 89 int smp_cpus; 90 void *fdt; 91 int fdt_size; 92 int psci_conduit; 93 DeviceState *gic; 94 PFlashCFI01 *flash[2]; 95 }; 96 97 #define TYPE_SBSA_MACHINE MACHINE_TYPE_NAME("sbsa-ref") 98 OBJECT_DECLARE_SIMPLE_TYPE(SBSAMachineState, SBSA_MACHINE) 99 100 static const MemMapEntry sbsa_ref_memmap[] = { 101 /* 512M boot ROM */ 102 [SBSA_FLASH] = { 0, 0x20000000 }, 103 /* 512M secure memory */ 104 [SBSA_SECURE_MEM] = { 0x20000000, 0x20000000 }, 105 /* Space reserved for CPU peripheral devices */ 106 [SBSA_CPUPERIPHS] = { 0x40000000, 0x00040000 }, 107 [SBSA_GIC_DIST] = { 0x40060000, 0x00010000 }, 108 [SBSA_GIC_REDIST] = { 0x40080000, 0x04000000 }, 109 [SBSA_SECURE_EC] = { 0x50000000, 0x00001000 }, 110 [SBSA_GWDT_REFRESH] = { 0x50010000, 0x00001000 }, 111 [SBSA_GWDT_CONTROL] = { 0x50011000, 0x00001000 }, 112 [SBSA_UART] = { 0x60000000, 0x00001000 }, 113 [SBSA_RTC] = { 0x60010000, 0x00001000 }, 114 [SBSA_GPIO] = { 0x60020000, 0x00001000 }, 115 [SBSA_SECURE_UART] = { 0x60030000, 0x00001000 }, 116 [SBSA_SECURE_UART_MM] = { 0x60040000, 0x00001000 }, 117 [SBSA_SMMU] = { 0x60050000, 0x00020000 }, 118 /* Space here reserved for more SMMUs */ 119 [SBSA_AHCI] = { 0x60100000, 0x00010000 }, 120 [SBSA_EHCI] = { 0x60110000, 0x00010000 }, 121 /* Space here reserved for other devices */ 122 [SBSA_PCIE_PIO] = { 0x7fff0000, 0x00010000 }, 123 /* 32-bit address PCIE MMIO space */ 124 [SBSA_PCIE_MMIO] = { 0x80000000, 0x70000000 }, 125 /* 256M PCIE ECAM space */ 126 [SBSA_PCIE_ECAM] = { 0xf0000000, 0x10000000 }, 127 /* ~1TB PCIE MMIO space (4GB to 1024GB boundary) */ 128 [SBSA_PCIE_MMIO_HIGH] = { 0x100000000ULL, 0xFF00000000ULL }, 129 [SBSA_MEM] = { 0x10000000000ULL, RAMLIMIT_BYTES }, 130 }; 131 132 static const int sbsa_ref_irqmap[] = { 133 [SBSA_UART] = 1, 134 [SBSA_RTC] = 2, 135 [SBSA_PCIE] = 3, /* ... to 6 */ 136 [SBSA_GPIO] = 7, 137 [SBSA_SECURE_UART] = 8, 138 [SBSA_SECURE_UART_MM] = 9, 139 [SBSA_AHCI] = 10, 140 [SBSA_EHCI] = 11, 141 [SBSA_SMMU] = 12, /* ... to 15 */ 142 [SBSA_GWDT_WS0] = 16, 143 }; 144 145 static const char * const valid_cpus[] = { 146 ARM_CPU_TYPE_NAME("cortex-a57"), 147 ARM_CPU_TYPE_NAME("cortex-a72"), 148 ARM_CPU_TYPE_NAME("max"), 149 }; 150 151 static bool cpu_type_valid(const char *cpu) 152 { 153 int i; 154 155 for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) { 156 if (strcmp(cpu, valid_cpus[i]) == 0) { 157 return true; 158 } 159 } 160 return false; 161 } 162 163 static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx) 164 { 165 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER; 166 return arm_cpu_mp_affinity(idx, clustersz); 167 } 168 169 /* 170 * Firmware on this machine only uses ACPI table to load OS, these limited 171 * device tree nodes are just to let firmware know the info which varies from 172 * command line parameters, so it is not necessary to be fully compatible 173 * with the kernel CPU and NUMA binding rules. 174 */ 175 static void create_fdt(SBSAMachineState *sms) 176 { 177 void *fdt = create_device_tree(&sms->fdt_size); 178 const MachineState *ms = MACHINE(sms); 179 int nb_numa_nodes = ms->numa_state->num_nodes; 180 int cpu; 181 182 if (!fdt) { 183 error_report("create_device_tree() failed"); 184 exit(1); 185 } 186 187 sms->fdt = fdt; 188 189 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,sbsa-ref"); 190 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 191 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 192 193 if (ms->numa_state->have_numa_distance) { 194 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); 195 uint32_t *matrix = g_malloc0(size); 196 int idx, i, j; 197 198 for (i = 0; i < nb_numa_nodes; i++) { 199 for (j = 0; j < nb_numa_nodes; j++) { 200 idx = (i * nb_numa_nodes + j) * 3; 201 matrix[idx + 0] = cpu_to_be32(i); 202 matrix[idx + 1] = cpu_to_be32(j); 203 matrix[idx + 2] = 204 cpu_to_be32(ms->numa_state->nodes[i].distance[j]); 205 } 206 } 207 208 qemu_fdt_add_subnode(fdt, "/distance-map"); 209 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", 210 matrix, size); 211 g_free(matrix); 212 } 213 214 /* 215 * From Documentation/devicetree/bindings/arm/cpus.yaml 216 * On ARM v8 64-bit systems this property is required 217 * and matches the MPIDR_EL1 register affinity bits. 218 * 219 * * If cpus node's #address-cells property is set to 2 220 * 221 * The first reg cell bits [7:0] must be set to 222 * bits [39:32] of MPIDR_EL1. 223 * 224 * The second reg cell bits [23:0] must be set to 225 * bits [23:0] of MPIDR_EL1. 226 */ 227 qemu_fdt_add_subnode(sms->fdt, "/cpus"); 228 qemu_fdt_setprop_cell(sms->fdt, "/cpus", "#address-cells", 2); 229 qemu_fdt_setprop_cell(sms->fdt, "/cpus", "#size-cells", 0x0); 230 231 for (cpu = sms->smp_cpus - 1; cpu >= 0; cpu--) { 232 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 233 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 234 CPUState *cs = CPU(armcpu); 235 uint64_t mpidr = sbsa_ref_cpu_mp_affinity(sms, cpu); 236 237 qemu_fdt_add_subnode(sms->fdt, nodename); 238 qemu_fdt_setprop_u64(sms->fdt, nodename, "reg", mpidr); 239 240 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 241 qemu_fdt_setprop_cell(sms->fdt, nodename, "numa-node-id", 242 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 243 } 244 245 g_free(nodename); 246 } 247 } 248 249 #define SBSA_FLASH_SECTOR_SIZE (256 * KiB) 250 251 static PFlashCFI01 *sbsa_flash_create1(SBSAMachineState *sms, 252 const char *name, 253 const char *alias_prop_name) 254 { 255 /* 256 * Create a single flash device. We use the same parameters as 257 * the flash devices on the Versatile Express board. 258 */ 259 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 260 261 qdev_prop_set_uint64(dev, "sector-length", SBSA_FLASH_SECTOR_SIZE); 262 qdev_prop_set_uint8(dev, "width", 4); 263 qdev_prop_set_uint8(dev, "device-width", 2); 264 qdev_prop_set_bit(dev, "big-endian", false); 265 qdev_prop_set_uint16(dev, "id0", 0x89); 266 qdev_prop_set_uint16(dev, "id1", 0x18); 267 qdev_prop_set_uint16(dev, "id2", 0x00); 268 qdev_prop_set_uint16(dev, "id3", 0x00); 269 qdev_prop_set_string(dev, "name", name); 270 object_property_add_child(OBJECT(sms), name, OBJECT(dev)); 271 object_property_add_alias(OBJECT(sms), alias_prop_name, 272 OBJECT(dev), "drive"); 273 return PFLASH_CFI01(dev); 274 } 275 276 static void sbsa_flash_create(SBSAMachineState *sms) 277 { 278 sms->flash[0] = sbsa_flash_create1(sms, "sbsa.flash0", "pflash0"); 279 sms->flash[1] = sbsa_flash_create1(sms, "sbsa.flash1", "pflash1"); 280 } 281 282 static void sbsa_flash_map1(PFlashCFI01 *flash, 283 hwaddr base, hwaddr size, 284 MemoryRegion *sysmem) 285 { 286 DeviceState *dev = DEVICE(flash); 287 288 assert(QEMU_IS_ALIGNED(size, SBSA_FLASH_SECTOR_SIZE)); 289 assert(size / SBSA_FLASH_SECTOR_SIZE <= UINT32_MAX); 290 qdev_prop_set_uint32(dev, "num-blocks", size / SBSA_FLASH_SECTOR_SIZE); 291 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 292 293 memory_region_add_subregion(sysmem, base, 294 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 295 0)); 296 } 297 298 static void sbsa_flash_map(SBSAMachineState *sms, 299 MemoryRegion *sysmem, 300 MemoryRegion *secure_sysmem) 301 { 302 /* 303 * Map two flash devices to fill the SBSA_FLASH space in the memmap. 304 * sysmem is the system memory space. secure_sysmem is the secure view 305 * of the system, and the first flash device should be made visible only 306 * there. The second flash device is visible to both secure and nonsecure. 307 */ 308 hwaddr flashsize = sbsa_ref_memmap[SBSA_FLASH].size / 2; 309 hwaddr flashbase = sbsa_ref_memmap[SBSA_FLASH].base; 310 311 sbsa_flash_map1(sms->flash[0], flashbase, flashsize, 312 secure_sysmem); 313 sbsa_flash_map1(sms->flash[1], flashbase + flashsize, flashsize, 314 sysmem); 315 } 316 317 static bool sbsa_firmware_init(SBSAMachineState *sms, 318 MemoryRegion *sysmem, 319 MemoryRegion *secure_sysmem) 320 { 321 const char *bios_name; 322 int i; 323 BlockBackend *pflash_blk0; 324 325 /* Map legacy -drive if=pflash to machine properties */ 326 for (i = 0; i < ARRAY_SIZE(sms->flash); i++) { 327 pflash_cfi01_legacy_drive(sms->flash[i], 328 drive_get(IF_PFLASH, 0, i)); 329 } 330 331 sbsa_flash_map(sms, sysmem, secure_sysmem); 332 333 pflash_blk0 = pflash_cfi01_get_blk(sms->flash[0]); 334 335 bios_name = MACHINE(sms)->firmware; 336 if (bios_name) { 337 char *fname; 338 MemoryRegion *mr; 339 int image_size; 340 341 if (pflash_blk0) { 342 error_report("The contents of the first flash device may be " 343 "specified with -bios or with -drive if=pflash... " 344 "but you cannot use both options at once"); 345 exit(1); 346 } 347 348 /* Fall back to -bios */ 349 350 fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 351 if (!fname) { 352 error_report("Could not find ROM image '%s'", bios_name); 353 exit(1); 354 } 355 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(sms->flash[0]), 0); 356 image_size = load_image_mr(fname, mr); 357 g_free(fname); 358 if (image_size < 0) { 359 error_report("Could not load ROM image '%s'", bios_name); 360 exit(1); 361 } 362 } 363 364 return pflash_blk0 || bios_name; 365 } 366 367 static void create_secure_ram(SBSAMachineState *sms, 368 MemoryRegion *secure_sysmem) 369 { 370 MemoryRegion *secram = g_new(MemoryRegion, 1); 371 hwaddr base = sbsa_ref_memmap[SBSA_SECURE_MEM].base; 372 hwaddr size = sbsa_ref_memmap[SBSA_SECURE_MEM].size; 373 374 memory_region_init_ram(secram, NULL, "sbsa-ref.secure-ram", size, 375 &error_fatal); 376 memory_region_add_subregion(secure_sysmem, base, secram); 377 } 378 379 static void create_gic(SBSAMachineState *sms) 380 { 381 unsigned int smp_cpus = MACHINE(sms)->smp.cpus; 382 SysBusDevice *gicbusdev; 383 const char *gictype; 384 uint32_t redist0_capacity, redist0_count; 385 int i; 386 387 gictype = gicv3_class_name(); 388 389 sms->gic = qdev_new(gictype); 390 qdev_prop_set_uint32(sms->gic, "revision", 3); 391 qdev_prop_set_uint32(sms->gic, "num-cpu", smp_cpus); 392 /* 393 * Note that the num-irq property counts both internal and external 394 * interrupts; there are always 32 of the former (mandated by GIC spec). 395 */ 396 qdev_prop_set_uint32(sms->gic, "num-irq", NUM_IRQS + 32); 397 qdev_prop_set_bit(sms->gic, "has-security-extensions", true); 398 399 redist0_capacity = 400 sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE; 401 redist0_count = MIN(smp_cpus, redist0_capacity); 402 403 qdev_prop_set_uint32(sms->gic, "len-redist-region-count", 1); 404 qdev_prop_set_uint32(sms->gic, "redist-region-count[0]", redist0_count); 405 406 gicbusdev = SYS_BUS_DEVICE(sms->gic); 407 sysbus_realize_and_unref(gicbusdev, &error_fatal); 408 sysbus_mmio_map(gicbusdev, 0, sbsa_ref_memmap[SBSA_GIC_DIST].base); 409 sysbus_mmio_map(gicbusdev, 1, sbsa_ref_memmap[SBSA_GIC_REDIST].base); 410 411 /* 412 * Wire the outputs from each CPU's generic timer and the GICv3 413 * maintenance interrupt signal to the appropriate GIC PPI inputs, 414 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. 415 */ 416 for (i = 0; i < smp_cpus; i++) { 417 DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); 418 int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; 419 int irq; 420 /* 421 * Mapping from the output timer irq lines from the CPU to the 422 * GIC PPI inputs used for this board. 423 */ 424 const int timer_irq[] = { 425 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 426 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 427 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 428 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 429 }; 430 431 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 432 qdev_connect_gpio_out(cpudev, irq, 433 qdev_get_gpio_in(sms->gic, 434 ppibase + timer_irq[irq])); 435 } 436 437 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0, 438 qdev_get_gpio_in(sms->gic, ppibase 439 + ARCH_GIC_MAINT_IRQ)); 440 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 441 qdev_get_gpio_in(sms->gic, ppibase 442 + VIRTUAL_PMU_IRQ)); 443 444 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 445 sysbus_connect_irq(gicbusdev, i + smp_cpus, 446 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 447 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, 448 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 449 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, 450 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 451 } 452 } 453 454 static void create_uart(const SBSAMachineState *sms, int uart, 455 MemoryRegion *mem, Chardev *chr) 456 { 457 hwaddr base = sbsa_ref_memmap[uart].base; 458 int irq = sbsa_ref_irqmap[uart]; 459 DeviceState *dev = qdev_new(TYPE_PL011); 460 SysBusDevice *s = SYS_BUS_DEVICE(dev); 461 462 qdev_prop_set_chr(dev, "chardev", chr); 463 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 464 memory_region_add_subregion(mem, base, 465 sysbus_mmio_get_region(s, 0)); 466 sysbus_connect_irq(s, 0, qdev_get_gpio_in(sms->gic, irq)); 467 } 468 469 static void create_rtc(const SBSAMachineState *sms) 470 { 471 hwaddr base = sbsa_ref_memmap[SBSA_RTC].base; 472 int irq = sbsa_ref_irqmap[SBSA_RTC]; 473 474 sysbus_create_simple("pl031", base, qdev_get_gpio_in(sms->gic, irq)); 475 } 476 477 static void create_wdt(const SBSAMachineState *sms) 478 { 479 hwaddr rbase = sbsa_ref_memmap[SBSA_GWDT_REFRESH].base; 480 hwaddr cbase = sbsa_ref_memmap[SBSA_GWDT_CONTROL].base; 481 DeviceState *dev = qdev_new(TYPE_WDT_SBSA); 482 SysBusDevice *s = SYS_BUS_DEVICE(dev); 483 int irq = sbsa_ref_irqmap[SBSA_GWDT_WS0]; 484 485 sysbus_realize_and_unref(s, &error_fatal); 486 sysbus_mmio_map(s, 0, rbase); 487 sysbus_mmio_map(s, 1, cbase); 488 sysbus_connect_irq(s, 0, qdev_get_gpio_in(sms->gic, irq)); 489 } 490 491 static DeviceState *gpio_key_dev; 492 static void sbsa_ref_powerdown_req(Notifier *n, void *opaque) 493 { 494 /* use gpio Pin 3 for power button event */ 495 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); 496 } 497 498 static Notifier sbsa_ref_powerdown_notifier = { 499 .notify = sbsa_ref_powerdown_req 500 }; 501 502 static void create_gpio(const SBSAMachineState *sms) 503 { 504 DeviceState *pl061_dev; 505 hwaddr base = sbsa_ref_memmap[SBSA_GPIO].base; 506 int irq = sbsa_ref_irqmap[SBSA_GPIO]; 507 508 pl061_dev = sysbus_create_simple("pl061", base, 509 qdev_get_gpio_in(sms->gic, irq)); 510 511 gpio_key_dev = sysbus_create_simple("gpio-key", -1, 512 qdev_get_gpio_in(pl061_dev, 3)); 513 514 /* connect powerdown request */ 515 qemu_register_powerdown_notifier(&sbsa_ref_powerdown_notifier); 516 } 517 518 static void create_ahci(const SBSAMachineState *sms) 519 { 520 hwaddr base = sbsa_ref_memmap[SBSA_AHCI].base; 521 int irq = sbsa_ref_irqmap[SBSA_AHCI]; 522 DeviceState *dev; 523 DriveInfo *hd[NUM_SATA_PORTS]; 524 SysbusAHCIState *sysahci; 525 AHCIState *ahci; 526 int i; 527 528 dev = qdev_new("sysbus-ahci"); 529 qdev_prop_set_uint32(dev, "num-ports", NUM_SATA_PORTS); 530 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 531 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 532 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(sms->gic, irq)); 533 534 sysahci = SYSBUS_AHCI(dev); 535 ahci = &sysahci->ahci; 536 ide_drive_get(hd, ARRAY_SIZE(hd)); 537 for (i = 0; i < ahci->ports; i++) { 538 if (hd[i] == NULL) { 539 continue; 540 } 541 ide_create_drive(&ahci->dev[i].port, 0, hd[i]); 542 } 543 } 544 545 static void create_ehci(const SBSAMachineState *sms) 546 { 547 hwaddr base = sbsa_ref_memmap[SBSA_EHCI].base; 548 int irq = sbsa_ref_irqmap[SBSA_EHCI]; 549 550 sysbus_create_simple("platform-ehci-usb", base, 551 qdev_get_gpio_in(sms->gic, irq)); 552 } 553 554 static void create_smmu(const SBSAMachineState *sms, PCIBus *bus) 555 { 556 hwaddr base = sbsa_ref_memmap[SBSA_SMMU].base; 557 int irq = sbsa_ref_irqmap[SBSA_SMMU]; 558 DeviceState *dev; 559 int i; 560 561 dev = qdev_new("arm-smmuv3"); 562 563 object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus), 564 &error_abort); 565 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 566 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 567 for (i = 0; i < NUM_SMMU_IRQS; i++) { 568 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 569 qdev_get_gpio_in(sms->gic, irq + i)); 570 } 571 } 572 573 static void create_pcie(SBSAMachineState *sms) 574 { 575 hwaddr base_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].base; 576 hwaddr size_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].size; 577 hwaddr base_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].base; 578 hwaddr size_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].size; 579 hwaddr base_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].base; 580 hwaddr size_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].size; 581 hwaddr base_pio = sbsa_ref_memmap[SBSA_PCIE_PIO].base; 582 int irq = sbsa_ref_irqmap[SBSA_PCIE]; 583 MemoryRegion *mmio_alias, *mmio_alias_high, *mmio_reg; 584 MemoryRegion *ecam_alias, *ecam_reg; 585 DeviceState *dev; 586 PCIHostState *pci; 587 int i; 588 589 dev = qdev_new(TYPE_GPEX_HOST); 590 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 591 592 /* Map ECAM space */ 593 ecam_alias = g_new0(MemoryRegion, 1); 594 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 595 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 596 ecam_reg, 0, size_ecam); 597 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); 598 599 /* Map the MMIO space */ 600 mmio_alias = g_new0(MemoryRegion, 1); 601 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 602 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 603 mmio_reg, base_mmio, size_mmio); 604 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); 605 606 /* Map the MMIO_HIGH space */ 607 mmio_alias_high = g_new0(MemoryRegion, 1); 608 memory_region_init_alias(mmio_alias_high, OBJECT(dev), "pcie-mmio-high", 609 mmio_reg, base_mmio_high, size_mmio_high); 610 memory_region_add_subregion(get_system_memory(), base_mmio_high, 611 mmio_alias_high); 612 613 /* Map IO port space */ 614 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); 615 616 for (i = 0; i < GPEX_NUM_IRQS; i++) { 617 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 618 qdev_get_gpio_in(sms->gic, irq + i)); 619 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); 620 } 621 622 pci = PCI_HOST_BRIDGE(dev); 623 if (pci->bus) { 624 for (i = 0; i < nb_nics; i++) { 625 NICInfo *nd = &nd_table[i]; 626 627 if (!nd->model) { 628 nd->model = g_strdup("e1000e"); 629 } 630 631 pci_nic_init_nofail(nd, pci->bus, nd->model, NULL); 632 } 633 } 634 635 pci_create_simple(pci->bus, -1, "VGA"); 636 637 create_smmu(sms, pci->bus); 638 } 639 640 static void *sbsa_ref_dtb(const struct arm_boot_info *binfo, int *fdt_size) 641 { 642 const SBSAMachineState *board = container_of(binfo, SBSAMachineState, 643 bootinfo); 644 645 *fdt_size = board->fdt_size; 646 return board->fdt; 647 } 648 649 static void create_secure_ec(MemoryRegion *mem) 650 { 651 hwaddr base = sbsa_ref_memmap[SBSA_SECURE_EC].base; 652 DeviceState *dev = qdev_new("sbsa-ec"); 653 SysBusDevice *s = SYS_BUS_DEVICE(dev); 654 655 memory_region_add_subregion(mem, base, 656 sysbus_mmio_get_region(s, 0)); 657 } 658 659 static void sbsa_ref_init(MachineState *machine) 660 { 661 unsigned int smp_cpus = machine->smp.cpus; 662 unsigned int max_cpus = machine->smp.max_cpus; 663 SBSAMachineState *sms = SBSA_MACHINE(machine); 664 MachineClass *mc = MACHINE_GET_CLASS(machine); 665 MemoryRegion *sysmem = get_system_memory(); 666 MemoryRegion *secure_sysmem = g_new(MemoryRegion, 1); 667 bool firmware_loaded; 668 const CPUArchIdList *possible_cpus; 669 int n, sbsa_max_cpus; 670 671 if (!cpu_type_valid(machine->cpu_type)) { 672 error_report("sbsa-ref: CPU type %s not supported", machine->cpu_type); 673 exit(1); 674 } 675 676 if (kvm_enabled()) { 677 error_report("sbsa-ref: KVM is not supported for this machine"); 678 exit(1); 679 } 680 681 /* 682 * The Secure view of the world is the same as the NonSecure, 683 * but with a few extra devices. Create it as a container region 684 * containing the system memory at low priority; any secure-only 685 * devices go in at higher priority and take precedence. 686 */ 687 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", 688 UINT64_MAX); 689 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); 690 691 firmware_loaded = sbsa_firmware_init(sms, sysmem, secure_sysmem); 692 693 /* 694 * This machine has EL3 enabled, external firmware should supply PSCI 695 * implementation, so the QEMU's internal PSCI is disabled. 696 */ 697 sms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; 698 699 sbsa_max_cpus = sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE; 700 701 if (max_cpus > sbsa_max_cpus) { 702 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " 703 "supported by machine 'sbsa-ref' (%d)", 704 max_cpus, sbsa_max_cpus); 705 exit(1); 706 } 707 708 sms->smp_cpus = smp_cpus; 709 710 if (machine->ram_size > sbsa_ref_memmap[SBSA_MEM].size) { 711 error_report("sbsa-ref: cannot model more than %dGB RAM", RAMLIMIT_GB); 712 exit(1); 713 } 714 715 possible_cpus = mc->possible_cpu_arch_ids(machine); 716 for (n = 0; n < possible_cpus->len; n++) { 717 Object *cpuobj; 718 CPUState *cs; 719 720 if (n >= smp_cpus) { 721 break; 722 } 723 724 cpuobj = object_new(possible_cpus->cpus[n].type); 725 object_property_set_int(cpuobj, "mp-affinity", 726 possible_cpus->cpus[n].arch_id, NULL); 727 728 cs = CPU(cpuobj); 729 cs->cpu_index = n; 730 731 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj), 732 &error_fatal); 733 734 if (object_property_find(cpuobj, "reset-cbar")) { 735 object_property_set_int(cpuobj, "reset-cbar", 736 sbsa_ref_memmap[SBSA_CPUPERIPHS].base, 737 &error_abort); 738 } 739 740 object_property_set_link(cpuobj, "memory", OBJECT(sysmem), 741 &error_abort); 742 743 object_property_set_link(cpuobj, "secure-memory", 744 OBJECT(secure_sysmem), &error_abort); 745 746 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); 747 object_unref(cpuobj); 748 } 749 750 memory_region_add_subregion(sysmem, sbsa_ref_memmap[SBSA_MEM].base, 751 machine->ram); 752 753 create_fdt(sms); 754 755 create_secure_ram(sms, secure_sysmem); 756 757 create_gic(sms); 758 759 create_uart(sms, SBSA_UART, sysmem, serial_hd(0)); 760 create_uart(sms, SBSA_SECURE_UART, secure_sysmem, serial_hd(1)); 761 /* Second secure UART for RAS and MM from EL0 */ 762 create_uart(sms, SBSA_SECURE_UART_MM, secure_sysmem, serial_hd(2)); 763 764 create_rtc(sms); 765 766 create_wdt(sms); 767 768 create_gpio(sms); 769 770 create_ahci(sms); 771 772 create_ehci(sms); 773 774 create_pcie(sms); 775 776 create_secure_ec(secure_sysmem); 777 778 sms->bootinfo.ram_size = machine->ram_size; 779 sms->bootinfo.nb_cpus = smp_cpus; 780 sms->bootinfo.board_id = -1; 781 sms->bootinfo.loader_start = sbsa_ref_memmap[SBSA_MEM].base; 782 sms->bootinfo.get_dtb = sbsa_ref_dtb; 783 sms->bootinfo.firmware_loaded = firmware_loaded; 784 arm_load_kernel(ARM_CPU(first_cpu), machine, &sms->bootinfo); 785 } 786 787 static const CPUArchIdList *sbsa_ref_possible_cpu_arch_ids(MachineState *ms) 788 { 789 unsigned int max_cpus = ms->smp.max_cpus; 790 SBSAMachineState *sms = SBSA_MACHINE(ms); 791 int n; 792 793 if (ms->possible_cpus) { 794 assert(ms->possible_cpus->len == max_cpus); 795 return ms->possible_cpus; 796 } 797 798 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 799 sizeof(CPUArchId) * max_cpus); 800 ms->possible_cpus->len = max_cpus; 801 for (n = 0; n < ms->possible_cpus->len; n++) { 802 ms->possible_cpus->cpus[n].type = ms->cpu_type; 803 ms->possible_cpus->cpus[n].arch_id = 804 sbsa_ref_cpu_mp_affinity(sms, n); 805 ms->possible_cpus->cpus[n].props.has_thread_id = true; 806 ms->possible_cpus->cpus[n].props.thread_id = n; 807 } 808 return ms->possible_cpus; 809 } 810 811 static CpuInstanceProperties 812 sbsa_ref_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 813 { 814 MachineClass *mc = MACHINE_GET_CLASS(ms); 815 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 816 817 assert(cpu_index < possible_cpus->len); 818 return possible_cpus->cpus[cpu_index].props; 819 } 820 821 static int64_t 822 sbsa_ref_get_default_cpu_node_id(const MachineState *ms, int idx) 823 { 824 return idx % ms->numa_state->num_nodes; 825 } 826 827 static void sbsa_ref_instance_init(Object *obj) 828 { 829 SBSAMachineState *sms = SBSA_MACHINE(obj); 830 831 sbsa_flash_create(sms); 832 } 833 834 static void sbsa_ref_class_init(ObjectClass *oc, void *data) 835 { 836 MachineClass *mc = MACHINE_CLASS(oc); 837 838 mc->init = sbsa_ref_init; 839 mc->desc = "QEMU 'SBSA Reference' ARM Virtual Machine"; 840 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a57"); 841 mc->max_cpus = 512; 842 mc->pci_allow_0_address = true; 843 mc->minimum_page_bits = 12; 844 mc->block_default_type = IF_IDE; 845 mc->no_cdrom = 1; 846 mc->default_ram_size = 1 * GiB; 847 mc->default_ram_id = "sbsa-ref.ram"; 848 mc->default_cpus = 4; 849 mc->possible_cpu_arch_ids = sbsa_ref_possible_cpu_arch_ids; 850 mc->cpu_index_to_instance_props = sbsa_ref_cpu_index_to_props; 851 mc->get_default_cpu_node_id = sbsa_ref_get_default_cpu_node_id; 852 } 853 854 static const TypeInfo sbsa_ref_info = { 855 .name = TYPE_SBSA_MACHINE, 856 .parent = TYPE_MACHINE, 857 .instance_init = sbsa_ref_instance_init, 858 .class_init = sbsa_ref_class_init, 859 .instance_size = sizeof(SBSAMachineState), 860 }; 861 862 static void sbsa_ref_machine_init(void) 863 { 864 type_register_static(&sbsa_ref_info); 865 } 866 867 type_init(sbsa_ref_machine_init); 868