1 /* 2 * ARM SBSA Reference Platform emulation 3 * 4 * Copyright (c) 2018 Linaro Limited 5 * Written by Hongbo Zhang <hongbo.zhang@linaro.org> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu-common.h" 22 #include "qemu/datadir.h" 23 #include "qapi/error.h" 24 #include "qemu/error-report.h" 25 #include "qemu/units.h" 26 #include "sysemu/device_tree.h" 27 #include "sysemu/numa.h" 28 #include "sysemu/runstate.h" 29 #include "sysemu/sysemu.h" 30 #include "exec/address-spaces.h" 31 #include "exec/hwaddr.h" 32 #include "kvm_arm.h" 33 #include "hw/arm/boot.h" 34 #include "hw/block/flash.h" 35 #include "hw/boards.h" 36 #include "hw/ide/internal.h" 37 #include "hw/ide/ahci_internal.h" 38 #include "hw/intc/arm_gicv3_common.h" 39 #include "hw/loader.h" 40 #include "hw/pci-host/gpex.h" 41 #include "hw/qdev-properties.h" 42 #include "hw/usb.h" 43 #include "hw/char/pl011.h" 44 #include "hw/watchdog/sbsa_gwdt.h" 45 #include "net/net.h" 46 #include "qom/object.h" 47 48 #define RAMLIMIT_GB 8192 49 #define RAMLIMIT_BYTES (RAMLIMIT_GB * GiB) 50 51 #define NUM_IRQS 256 52 #define NUM_SMMU_IRQS 4 53 #define NUM_SATA_PORTS 6 54 55 #define VIRTUAL_PMU_IRQ 7 56 #define ARCH_GIC_MAINT_IRQ 9 57 #define ARCH_TIMER_VIRT_IRQ 11 58 #define ARCH_TIMER_S_EL1_IRQ 13 59 #define ARCH_TIMER_NS_EL1_IRQ 14 60 #define ARCH_TIMER_NS_EL2_IRQ 10 61 62 enum { 63 SBSA_FLASH, 64 SBSA_MEM, 65 SBSA_CPUPERIPHS, 66 SBSA_GIC_DIST, 67 SBSA_GIC_REDIST, 68 SBSA_SECURE_EC, 69 SBSA_GWDT, 70 SBSA_GWDT_REFRESH, 71 SBSA_GWDT_CONTROL, 72 SBSA_SMMU, 73 SBSA_UART, 74 SBSA_RTC, 75 SBSA_PCIE, 76 SBSA_PCIE_MMIO, 77 SBSA_PCIE_MMIO_HIGH, 78 SBSA_PCIE_PIO, 79 SBSA_PCIE_ECAM, 80 SBSA_GPIO, 81 SBSA_SECURE_UART, 82 SBSA_SECURE_UART_MM, 83 SBSA_SECURE_MEM, 84 SBSA_AHCI, 85 SBSA_EHCI, 86 }; 87 88 struct SBSAMachineState { 89 MachineState parent; 90 struct arm_boot_info bootinfo; 91 int smp_cpus; 92 void *fdt; 93 int fdt_size; 94 int psci_conduit; 95 DeviceState *gic; 96 PFlashCFI01 *flash[2]; 97 }; 98 99 #define TYPE_SBSA_MACHINE MACHINE_TYPE_NAME("sbsa-ref") 100 OBJECT_DECLARE_SIMPLE_TYPE(SBSAMachineState, SBSA_MACHINE) 101 102 static const MemMapEntry sbsa_ref_memmap[] = { 103 /* 512M boot ROM */ 104 [SBSA_FLASH] = { 0, 0x20000000 }, 105 /* 512M secure memory */ 106 [SBSA_SECURE_MEM] = { 0x20000000, 0x20000000 }, 107 /* Space reserved for CPU peripheral devices */ 108 [SBSA_CPUPERIPHS] = { 0x40000000, 0x00040000 }, 109 [SBSA_GIC_DIST] = { 0x40060000, 0x00010000 }, 110 [SBSA_GIC_REDIST] = { 0x40080000, 0x04000000 }, 111 [SBSA_SECURE_EC] = { 0x50000000, 0x00001000 }, 112 [SBSA_GWDT_REFRESH] = { 0x50010000, 0x00001000 }, 113 [SBSA_GWDT_CONTROL] = { 0x50011000, 0x00001000 }, 114 [SBSA_UART] = { 0x60000000, 0x00001000 }, 115 [SBSA_RTC] = { 0x60010000, 0x00001000 }, 116 [SBSA_GPIO] = { 0x60020000, 0x00001000 }, 117 [SBSA_SECURE_UART] = { 0x60030000, 0x00001000 }, 118 [SBSA_SECURE_UART_MM] = { 0x60040000, 0x00001000 }, 119 [SBSA_SMMU] = { 0x60050000, 0x00020000 }, 120 /* Space here reserved for more SMMUs */ 121 [SBSA_AHCI] = { 0x60100000, 0x00010000 }, 122 [SBSA_EHCI] = { 0x60110000, 0x00010000 }, 123 /* Space here reserved for other devices */ 124 [SBSA_PCIE_PIO] = { 0x7fff0000, 0x00010000 }, 125 /* 32-bit address PCIE MMIO space */ 126 [SBSA_PCIE_MMIO] = { 0x80000000, 0x70000000 }, 127 /* 256M PCIE ECAM space */ 128 [SBSA_PCIE_ECAM] = { 0xf0000000, 0x10000000 }, 129 /* ~1TB PCIE MMIO space (4GB to 1024GB boundary) */ 130 [SBSA_PCIE_MMIO_HIGH] = { 0x100000000ULL, 0xFF00000000ULL }, 131 [SBSA_MEM] = { 0x10000000000ULL, RAMLIMIT_BYTES }, 132 }; 133 134 static const int sbsa_ref_irqmap[] = { 135 [SBSA_UART] = 1, 136 [SBSA_RTC] = 2, 137 [SBSA_PCIE] = 3, /* ... to 6 */ 138 [SBSA_GPIO] = 7, 139 [SBSA_SECURE_UART] = 8, 140 [SBSA_SECURE_UART_MM] = 9, 141 [SBSA_AHCI] = 10, 142 [SBSA_EHCI] = 11, 143 [SBSA_SMMU] = 12, /* ... to 15 */ 144 [SBSA_GWDT] = 16, 145 }; 146 147 static const char * const valid_cpus[] = { 148 ARM_CPU_TYPE_NAME("cortex-a57"), 149 ARM_CPU_TYPE_NAME("cortex-a72"), 150 ARM_CPU_TYPE_NAME("max"), 151 }; 152 153 static bool cpu_type_valid(const char *cpu) 154 { 155 int i; 156 157 for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) { 158 if (strcmp(cpu, valid_cpus[i]) == 0) { 159 return true; 160 } 161 } 162 return false; 163 } 164 165 static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx) 166 { 167 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER; 168 return arm_cpu_mp_affinity(idx, clustersz); 169 } 170 171 /* 172 * Firmware on this machine only uses ACPI table to load OS, these limited 173 * device tree nodes are just to let firmware know the info which varies from 174 * command line parameters, so it is not necessary to be fully compatible 175 * with the kernel CPU and NUMA binding rules. 176 */ 177 static void create_fdt(SBSAMachineState *sms) 178 { 179 void *fdt = create_device_tree(&sms->fdt_size); 180 const MachineState *ms = MACHINE(sms); 181 int nb_numa_nodes = ms->numa_state->num_nodes; 182 int cpu; 183 184 if (!fdt) { 185 error_report("create_device_tree() failed"); 186 exit(1); 187 } 188 189 sms->fdt = fdt; 190 191 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,sbsa-ref"); 192 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 193 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 194 195 if (ms->numa_state->have_numa_distance) { 196 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); 197 uint32_t *matrix = g_malloc0(size); 198 int idx, i, j; 199 200 for (i = 0; i < nb_numa_nodes; i++) { 201 for (j = 0; j < nb_numa_nodes; j++) { 202 idx = (i * nb_numa_nodes + j) * 3; 203 matrix[idx + 0] = cpu_to_be32(i); 204 matrix[idx + 1] = cpu_to_be32(j); 205 matrix[idx + 2] = 206 cpu_to_be32(ms->numa_state->nodes[i].distance[j]); 207 } 208 } 209 210 qemu_fdt_add_subnode(fdt, "/distance-map"); 211 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", 212 matrix, size); 213 g_free(matrix); 214 } 215 216 /* 217 * From Documentation/devicetree/bindings/arm/cpus.yaml 218 * On ARM v8 64-bit systems this property is required 219 * and matches the MPIDR_EL1 register affinity bits. 220 * 221 * * If cpus node's #address-cells property is set to 2 222 * 223 * The first reg cell bits [7:0] must be set to 224 * bits [39:32] of MPIDR_EL1. 225 * 226 * The second reg cell bits [23:0] must be set to 227 * bits [23:0] of MPIDR_EL1. 228 */ 229 qemu_fdt_add_subnode(sms->fdt, "/cpus"); 230 qemu_fdt_setprop_cell(sms->fdt, "/cpus", "#address-cells", 2); 231 qemu_fdt_setprop_cell(sms->fdt, "/cpus", "#size-cells", 0x0); 232 233 for (cpu = sms->smp_cpus - 1; cpu >= 0; cpu--) { 234 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 235 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 236 CPUState *cs = CPU(armcpu); 237 uint64_t mpidr = sbsa_ref_cpu_mp_affinity(sms, cpu); 238 239 qemu_fdt_add_subnode(sms->fdt, nodename); 240 qemu_fdt_setprop_u64(sms->fdt, nodename, "reg", mpidr); 241 242 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 243 qemu_fdt_setprop_cell(sms->fdt, nodename, "numa-node-id", 244 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 245 } 246 247 g_free(nodename); 248 } 249 } 250 251 #define SBSA_FLASH_SECTOR_SIZE (256 * KiB) 252 253 static PFlashCFI01 *sbsa_flash_create1(SBSAMachineState *sms, 254 const char *name, 255 const char *alias_prop_name) 256 { 257 /* 258 * Create a single flash device. We use the same parameters as 259 * the flash devices on the Versatile Express board. 260 */ 261 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 262 263 qdev_prop_set_uint64(dev, "sector-length", SBSA_FLASH_SECTOR_SIZE); 264 qdev_prop_set_uint8(dev, "width", 4); 265 qdev_prop_set_uint8(dev, "device-width", 2); 266 qdev_prop_set_bit(dev, "big-endian", false); 267 qdev_prop_set_uint16(dev, "id0", 0x89); 268 qdev_prop_set_uint16(dev, "id1", 0x18); 269 qdev_prop_set_uint16(dev, "id2", 0x00); 270 qdev_prop_set_uint16(dev, "id3", 0x00); 271 qdev_prop_set_string(dev, "name", name); 272 object_property_add_child(OBJECT(sms), name, OBJECT(dev)); 273 object_property_add_alias(OBJECT(sms), alias_prop_name, 274 OBJECT(dev), "drive"); 275 return PFLASH_CFI01(dev); 276 } 277 278 static void sbsa_flash_create(SBSAMachineState *sms) 279 { 280 sms->flash[0] = sbsa_flash_create1(sms, "sbsa.flash0", "pflash0"); 281 sms->flash[1] = sbsa_flash_create1(sms, "sbsa.flash1", "pflash1"); 282 } 283 284 static void sbsa_flash_map1(PFlashCFI01 *flash, 285 hwaddr base, hwaddr size, 286 MemoryRegion *sysmem) 287 { 288 DeviceState *dev = DEVICE(flash); 289 290 assert(QEMU_IS_ALIGNED(size, SBSA_FLASH_SECTOR_SIZE)); 291 assert(size / SBSA_FLASH_SECTOR_SIZE <= UINT32_MAX); 292 qdev_prop_set_uint32(dev, "num-blocks", size / SBSA_FLASH_SECTOR_SIZE); 293 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 294 295 memory_region_add_subregion(sysmem, base, 296 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 297 0)); 298 } 299 300 static void sbsa_flash_map(SBSAMachineState *sms, 301 MemoryRegion *sysmem, 302 MemoryRegion *secure_sysmem) 303 { 304 /* 305 * Map two flash devices to fill the SBSA_FLASH space in the memmap. 306 * sysmem is the system memory space. secure_sysmem is the secure view 307 * of the system, and the first flash device should be made visible only 308 * there. The second flash device is visible to both secure and nonsecure. 309 */ 310 hwaddr flashsize = sbsa_ref_memmap[SBSA_FLASH].size / 2; 311 hwaddr flashbase = sbsa_ref_memmap[SBSA_FLASH].base; 312 313 sbsa_flash_map1(sms->flash[0], flashbase, flashsize, 314 secure_sysmem); 315 sbsa_flash_map1(sms->flash[1], flashbase + flashsize, flashsize, 316 sysmem); 317 } 318 319 static bool sbsa_firmware_init(SBSAMachineState *sms, 320 MemoryRegion *sysmem, 321 MemoryRegion *secure_sysmem) 322 { 323 const char *bios_name; 324 int i; 325 BlockBackend *pflash_blk0; 326 327 /* Map legacy -drive if=pflash to machine properties */ 328 for (i = 0; i < ARRAY_SIZE(sms->flash); i++) { 329 pflash_cfi01_legacy_drive(sms->flash[i], 330 drive_get(IF_PFLASH, 0, i)); 331 } 332 333 sbsa_flash_map(sms, sysmem, secure_sysmem); 334 335 pflash_blk0 = pflash_cfi01_get_blk(sms->flash[0]); 336 337 bios_name = MACHINE(sms)->firmware; 338 if (bios_name) { 339 char *fname; 340 MemoryRegion *mr; 341 int image_size; 342 343 if (pflash_blk0) { 344 error_report("The contents of the first flash device may be " 345 "specified with -bios or with -drive if=pflash... " 346 "but you cannot use both options at once"); 347 exit(1); 348 } 349 350 /* Fall back to -bios */ 351 352 fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 353 if (!fname) { 354 error_report("Could not find ROM image '%s'", bios_name); 355 exit(1); 356 } 357 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(sms->flash[0]), 0); 358 image_size = load_image_mr(fname, mr); 359 g_free(fname); 360 if (image_size < 0) { 361 error_report("Could not load ROM image '%s'", bios_name); 362 exit(1); 363 } 364 } 365 366 return pflash_blk0 || bios_name; 367 } 368 369 static void create_secure_ram(SBSAMachineState *sms, 370 MemoryRegion *secure_sysmem) 371 { 372 MemoryRegion *secram = g_new(MemoryRegion, 1); 373 hwaddr base = sbsa_ref_memmap[SBSA_SECURE_MEM].base; 374 hwaddr size = sbsa_ref_memmap[SBSA_SECURE_MEM].size; 375 376 memory_region_init_ram(secram, NULL, "sbsa-ref.secure-ram", size, 377 &error_fatal); 378 memory_region_add_subregion(secure_sysmem, base, secram); 379 } 380 381 static void create_gic(SBSAMachineState *sms) 382 { 383 unsigned int smp_cpus = MACHINE(sms)->smp.cpus; 384 SysBusDevice *gicbusdev; 385 const char *gictype; 386 uint32_t redist0_capacity, redist0_count; 387 int i; 388 389 gictype = gicv3_class_name(); 390 391 sms->gic = qdev_new(gictype); 392 qdev_prop_set_uint32(sms->gic, "revision", 3); 393 qdev_prop_set_uint32(sms->gic, "num-cpu", smp_cpus); 394 /* 395 * Note that the num-irq property counts both internal and external 396 * interrupts; there are always 32 of the former (mandated by GIC spec). 397 */ 398 qdev_prop_set_uint32(sms->gic, "num-irq", NUM_IRQS + 32); 399 qdev_prop_set_bit(sms->gic, "has-security-extensions", true); 400 401 redist0_capacity = 402 sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE; 403 redist0_count = MIN(smp_cpus, redist0_capacity); 404 405 qdev_prop_set_uint32(sms->gic, "len-redist-region-count", 1); 406 qdev_prop_set_uint32(sms->gic, "redist-region-count[0]", redist0_count); 407 408 gicbusdev = SYS_BUS_DEVICE(sms->gic); 409 sysbus_realize_and_unref(gicbusdev, &error_fatal); 410 sysbus_mmio_map(gicbusdev, 0, sbsa_ref_memmap[SBSA_GIC_DIST].base); 411 sysbus_mmio_map(gicbusdev, 1, sbsa_ref_memmap[SBSA_GIC_REDIST].base); 412 413 /* 414 * Wire the outputs from each CPU's generic timer and the GICv3 415 * maintenance interrupt signal to the appropriate GIC PPI inputs, 416 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. 417 */ 418 for (i = 0; i < smp_cpus; i++) { 419 DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); 420 int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; 421 int irq; 422 /* 423 * Mapping from the output timer irq lines from the CPU to the 424 * GIC PPI inputs used for this board. 425 */ 426 const int timer_irq[] = { 427 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 428 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 429 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 430 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 431 }; 432 433 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 434 qdev_connect_gpio_out(cpudev, irq, 435 qdev_get_gpio_in(sms->gic, 436 ppibase + timer_irq[irq])); 437 } 438 439 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0, 440 qdev_get_gpio_in(sms->gic, ppibase 441 + ARCH_GIC_MAINT_IRQ)); 442 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 443 qdev_get_gpio_in(sms->gic, ppibase 444 + VIRTUAL_PMU_IRQ)); 445 446 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 447 sysbus_connect_irq(gicbusdev, i + smp_cpus, 448 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 449 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, 450 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 451 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, 452 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 453 } 454 } 455 456 static void create_uart(const SBSAMachineState *sms, int uart, 457 MemoryRegion *mem, Chardev *chr) 458 { 459 hwaddr base = sbsa_ref_memmap[uart].base; 460 int irq = sbsa_ref_irqmap[uart]; 461 DeviceState *dev = qdev_new(TYPE_PL011); 462 SysBusDevice *s = SYS_BUS_DEVICE(dev); 463 464 qdev_prop_set_chr(dev, "chardev", chr); 465 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 466 memory_region_add_subregion(mem, base, 467 sysbus_mmio_get_region(s, 0)); 468 sysbus_connect_irq(s, 0, qdev_get_gpio_in(sms->gic, irq)); 469 } 470 471 static void create_rtc(const SBSAMachineState *sms) 472 { 473 hwaddr base = sbsa_ref_memmap[SBSA_RTC].base; 474 int irq = sbsa_ref_irqmap[SBSA_RTC]; 475 476 sysbus_create_simple("pl031", base, qdev_get_gpio_in(sms->gic, irq)); 477 } 478 479 static void create_wdt(const SBSAMachineState *sms) 480 { 481 hwaddr rbase = sbsa_ref_memmap[SBSA_GWDT_REFRESH].base; 482 hwaddr cbase = sbsa_ref_memmap[SBSA_GWDT_CONTROL].base; 483 DeviceState *dev = qdev_new(TYPE_WDT_SBSA); 484 SysBusDevice *s = SYS_BUS_DEVICE(dev); 485 int irq = sbsa_ref_irqmap[SBSA_GWDT]; 486 487 sysbus_realize_and_unref(s, &error_fatal); 488 sysbus_mmio_map(s, 0, rbase); 489 sysbus_mmio_map(s, 1, cbase); 490 sysbus_connect_irq(s, 0, qdev_get_gpio_in(sms->gic, irq)); 491 } 492 493 static DeviceState *gpio_key_dev; 494 static void sbsa_ref_powerdown_req(Notifier *n, void *opaque) 495 { 496 /* use gpio Pin 3 for power button event */ 497 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); 498 } 499 500 static Notifier sbsa_ref_powerdown_notifier = { 501 .notify = sbsa_ref_powerdown_req 502 }; 503 504 static void create_gpio(const SBSAMachineState *sms) 505 { 506 DeviceState *pl061_dev; 507 hwaddr base = sbsa_ref_memmap[SBSA_GPIO].base; 508 int irq = sbsa_ref_irqmap[SBSA_GPIO]; 509 510 pl061_dev = sysbus_create_simple("pl061", base, 511 qdev_get_gpio_in(sms->gic, irq)); 512 513 gpio_key_dev = sysbus_create_simple("gpio-key", -1, 514 qdev_get_gpio_in(pl061_dev, 3)); 515 516 /* connect powerdown request */ 517 qemu_register_powerdown_notifier(&sbsa_ref_powerdown_notifier); 518 } 519 520 static void create_ahci(const SBSAMachineState *sms) 521 { 522 hwaddr base = sbsa_ref_memmap[SBSA_AHCI].base; 523 int irq = sbsa_ref_irqmap[SBSA_AHCI]; 524 DeviceState *dev; 525 DriveInfo *hd[NUM_SATA_PORTS]; 526 SysbusAHCIState *sysahci; 527 AHCIState *ahci; 528 int i; 529 530 dev = qdev_new("sysbus-ahci"); 531 qdev_prop_set_uint32(dev, "num-ports", NUM_SATA_PORTS); 532 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 533 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 534 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(sms->gic, irq)); 535 536 sysahci = SYSBUS_AHCI(dev); 537 ahci = &sysahci->ahci; 538 ide_drive_get(hd, ARRAY_SIZE(hd)); 539 for (i = 0; i < ahci->ports; i++) { 540 if (hd[i] == NULL) { 541 continue; 542 } 543 ide_create_drive(&ahci->dev[i].port, 0, hd[i]); 544 } 545 } 546 547 static void create_ehci(const SBSAMachineState *sms) 548 { 549 hwaddr base = sbsa_ref_memmap[SBSA_EHCI].base; 550 int irq = sbsa_ref_irqmap[SBSA_EHCI]; 551 552 sysbus_create_simple("platform-ehci-usb", base, 553 qdev_get_gpio_in(sms->gic, irq)); 554 } 555 556 static void create_smmu(const SBSAMachineState *sms, PCIBus *bus) 557 { 558 hwaddr base = sbsa_ref_memmap[SBSA_SMMU].base; 559 int irq = sbsa_ref_irqmap[SBSA_SMMU]; 560 DeviceState *dev; 561 int i; 562 563 dev = qdev_new("arm-smmuv3"); 564 565 object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus), 566 &error_abort); 567 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 568 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 569 for (i = 0; i < NUM_SMMU_IRQS; i++) { 570 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 571 qdev_get_gpio_in(sms->gic, irq + i)); 572 } 573 } 574 575 static void create_pcie(SBSAMachineState *sms) 576 { 577 hwaddr base_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].base; 578 hwaddr size_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].size; 579 hwaddr base_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].base; 580 hwaddr size_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].size; 581 hwaddr base_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].base; 582 hwaddr size_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].size; 583 hwaddr base_pio = sbsa_ref_memmap[SBSA_PCIE_PIO].base; 584 int irq = sbsa_ref_irqmap[SBSA_PCIE]; 585 MemoryRegion *mmio_alias, *mmio_alias_high, *mmio_reg; 586 MemoryRegion *ecam_alias, *ecam_reg; 587 DeviceState *dev; 588 PCIHostState *pci; 589 int i; 590 591 dev = qdev_new(TYPE_GPEX_HOST); 592 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 593 594 /* Map ECAM space */ 595 ecam_alias = g_new0(MemoryRegion, 1); 596 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 597 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 598 ecam_reg, 0, size_ecam); 599 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); 600 601 /* Map the MMIO space */ 602 mmio_alias = g_new0(MemoryRegion, 1); 603 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 604 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 605 mmio_reg, base_mmio, size_mmio); 606 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); 607 608 /* Map the MMIO_HIGH space */ 609 mmio_alias_high = g_new0(MemoryRegion, 1); 610 memory_region_init_alias(mmio_alias_high, OBJECT(dev), "pcie-mmio-high", 611 mmio_reg, base_mmio_high, size_mmio_high); 612 memory_region_add_subregion(get_system_memory(), base_mmio_high, 613 mmio_alias_high); 614 615 /* Map IO port space */ 616 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); 617 618 for (i = 0; i < GPEX_NUM_IRQS; i++) { 619 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 620 qdev_get_gpio_in(sms->gic, irq + i)); 621 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); 622 } 623 624 pci = PCI_HOST_BRIDGE(dev); 625 if (pci->bus) { 626 for (i = 0; i < nb_nics; i++) { 627 NICInfo *nd = &nd_table[i]; 628 629 if (!nd->model) { 630 nd->model = g_strdup("e1000e"); 631 } 632 633 pci_nic_init_nofail(nd, pci->bus, nd->model, NULL); 634 } 635 } 636 637 pci_create_simple(pci->bus, -1, "VGA"); 638 639 create_smmu(sms, pci->bus); 640 } 641 642 static void *sbsa_ref_dtb(const struct arm_boot_info *binfo, int *fdt_size) 643 { 644 const SBSAMachineState *board = container_of(binfo, SBSAMachineState, 645 bootinfo); 646 647 *fdt_size = board->fdt_size; 648 return board->fdt; 649 } 650 651 static void create_secure_ec(MemoryRegion *mem) 652 { 653 hwaddr base = sbsa_ref_memmap[SBSA_SECURE_EC].base; 654 DeviceState *dev = qdev_new("sbsa-ec"); 655 SysBusDevice *s = SYS_BUS_DEVICE(dev); 656 657 memory_region_add_subregion(mem, base, 658 sysbus_mmio_get_region(s, 0)); 659 } 660 661 static void sbsa_ref_init(MachineState *machine) 662 { 663 unsigned int smp_cpus = machine->smp.cpus; 664 unsigned int max_cpus = machine->smp.max_cpus; 665 SBSAMachineState *sms = SBSA_MACHINE(machine); 666 MachineClass *mc = MACHINE_GET_CLASS(machine); 667 MemoryRegion *sysmem = get_system_memory(); 668 MemoryRegion *secure_sysmem = g_new(MemoryRegion, 1); 669 bool firmware_loaded; 670 const CPUArchIdList *possible_cpus; 671 int n, sbsa_max_cpus; 672 673 if (!cpu_type_valid(machine->cpu_type)) { 674 error_report("mach-virt: CPU type %s not supported", machine->cpu_type); 675 exit(1); 676 } 677 678 if (kvm_enabled()) { 679 error_report("sbsa-ref: KVM is not supported for this machine"); 680 exit(1); 681 } 682 683 /* 684 * The Secure view of the world is the same as the NonSecure, 685 * but with a few extra devices. Create it as a container region 686 * containing the system memory at low priority; any secure-only 687 * devices go in at higher priority and take precedence. 688 */ 689 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", 690 UINT64_MAX); 691 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); 692 693 firmware_loaded = sbsa_firmware_init(sms, sysmem, secure_sysmem); 694 695 if (machine->kernel_filename && firmware_loaded) { 696 error_report("sbsa-ref: No fw_cfg device on this machine, " 697 "so -kernel option is not supported when firmware loaded, " 698 "please load OS from hard disk instead"); 699 exit(1); 700 } 701 702 /* 703 * This machine has EL3 enabled, external firmware should supply PSCI 704 * implementation, so the QEMU's internal PSCI is disabled. 705 */ 706 sms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; 707 708 sbsa_max_cpus = sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE; 709 710 if (max_cpus > sbsa_max_cpus) { 711 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " 712 "supported by machine 'sbsa-ref' (%d)", 713 max_cpus, sbsa_max_cpus); 714 exit(1); 715 } 716 717 sms->smp_cpus = smp_cpus; 718 719 if (machine->ram_size > sbsa_ref_memmap[SBSA_MEM].size) { 720 error_report("sbsa-ref: cannot model more than %dGB RAM", RAMLIMIT_GB); 721 exit(1); 722 } 723 724 possible_cpus = mc->possible_cpu_arch_ids(machine); 725 for (n = 0; n < possible_cpus->len; n++) { 726 Object *cpuobj; 727 CPUState *cs; 728 729 if (n >= smp_cpus) { 730 break; 731 } 732 733 cpuobj = object_new(possible_cpus->cpus[n].type); 734 object_property_set_int(cpuobj, "mp-affinity", 735 possible_cpus->cpus[n].arch_id, NULL); 736 737 cs = CPU(cpuobj); 738 cs->cpu_index = n; 739 740 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj), 741 &error_fatal); 742 743 if (object_property_find(cpuobj, "reset-cbar")) { 744 object_property_set_int(cpuobj, "reset-cbar", 745 sbsa_ref_memmap[SBSA_CPUPERIPHS].base, 746 &error_abort); 747 } 748 749 object_property_set_link(cpuobj, "memory", OBJECT(sysmem), 750 &error_abort); 751 752 object_property_set_link(cpuobj, "secure-memory", 753 OBJECT(secure_sysmem), &error_abort); 754 755 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); 756 object_unref(cpuobj); 757 } 758 759 memory_region_add_subregion(sysmem, sbsa_ref_memmap[SBSA_MEM].base, 760 machine->ram); 761 762 create_fdt(sms); 763 764 create_secure_ram(sms, secure_sysmem); 765 766 create_gic(sms); 767 768 create_uart(sms, SBSA_UART, sysmem, serial_hd(0)); 769 create_uart(sms, SBSA_SECURE_UART, secure_sysmem, serial_hd(1)); 770 /* Second secure UART for RAS and MM from EL0 */ 771 create_uart(sms, SBSA_SECURE_UART_MM, secure_sysmem, serial_hd(2)); 772 773 create_rtc(sms); 774 775 create_wdt(sms); 776 777 create_gpio(sms); 778 779 create_ahci(sms); 780 781 create_ehci(sms); 782 783 create_pcie(sms); 784 785 create_secure_ec(secure_sysmem); 786 787 sms->bootinfo.ram_size = machine->ram_size; 788 sms->bootinfo.nb_cpus = smp_cpus; 789 sms->bootinfo.board_id = -1; 790 sms->bootinfo.loader_start = sbsa_ref_memmap[SBSA_MEM].base; 791 sms->bootinfo.get_dtb = sbsa_ref_dtb; 792 sms->bootinfo.firmware_loaded = firmware_loaded; 793 arm_load_kernel(ARM_CPU(first_cpu), machine, &sms->bootinfo); 794 } 795 796 static const CPUArchIdList *sbsa_ref_possible_cpu_arch_ids(MachineState *ms) 797 { 798 unsigned int max_cpus = ms->smp.max_cpus; 799 SBSAMachineState *sms = SBSA_MACHINE(ms); 800 int n; 801 802 if (ms->possible_cpus) { 803 assert(ms->possible_cpus->len == max_cpus); 804 return ms->possible_cpus; 805 } 806 807 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 808 sizeof(CPUArchId) * max_cpus); 809 ms->possible_cpus->len = max_cpus; 810 for (n = 0; n < ms->possible_cpus->len; n++) { 811 ms->possible_cpus->cpus[n].type = ms->cpu_type; 812 ms->possible_cpus->cpus[n].arch_id = 813 sbsa_ref_cpu_mp_affinity(sms, n); 814 ms->possible_cpus->cpus[n].props.has_thread_id = true; 815 ms->possible_cpus->cpus[n].props.thread_id = n; 816 } 817 return ms->possible_cpus; 818 } 819 820 static CpuInstanceProperties 821 sbsa_ref_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 822 { 823 MachineClass *mc = MACHINE_GET_CLASS(ms); 824 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 825 826 assert(cpu_index < possible_cpus->len); 827 return possible_cpus->cpus[cpu_index].props; 828 } 829 830 static int64_t 831 sbsa_ref_get_default_cpu_node_id(const MachineState *ms, int idx) 832 { 833 return idx % ms->numa_state->num_nodes; 834 } 835 836 static void sbsa_ref_instance_init(Object *obj) 837 { 838 SBSAMachineState *sms = SBSA_MACHINE(obj); 839 840 sbsa_flash_create(sms); 841 } 842 843 static void sbsa_ref_class_init(ObjectClass *oc, void *data) 844 { 845 MachineClass *mc = MACHINE_CLASS(oc); 846 847 mc->init = sbsa_ref_init; 848 mc->desc = "QEMU 'SBSA Reference' ARM Virtual Machine"; 849 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a57"); 850 mc->max_cpus = 512; 851 mc->pci_allow_0_address = true; 852 mc->minimum_page_bits = 12; 853 mc->block_default_type = IF_IDE; 854 mc->no_cdrom = 1; 855 mc->default_ram_size = 1 * GiB; 856 mc->default_ram_id = "sbsa-ref.ram"; 857 mc->default_cpus = 4; 858 mc->possible_cpu_arch_ids = sbsa_ref_possible_cpu_arch_ids; 859 mc->cpu_index_to_instance_props = sbsa_ref_cpu_index_to_props; 860 mc->get_default_cpu_node_id = sbsa_ref_get_default_cpu_node_id; 861 } 862 863 static const TypeInfo sbsa_ref_info = { 864 .name = TYPE_SBSA_MACHINE, 865 .parent = TYPE_MACHINE, 866 .instance_init = sbsa_ref_instance_init, 867 .class_init = sbsa_ref_class_init, 868 .instance_size = sizeof(SBSAMachineState), 869 }; 870 871 static void sbsa_ref_machine_init(void) 872 { 873 type_register_static(&sbsa_ref_info); 874 } 875 876 type_init(sbsa_ref_machine_init); 877