1 /* 2 * ARM SBSA Reference Platform emulation 3 * 4 * Copyright (c) 2018 Linaro Limited 5 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 6 * Written by Hongbo Zhang <hongbo.zhang@linaro.org> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2 or later, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/datadir.h" 23 #include "qapi/error.h" 24 #include "qemu/error-report.h" 25 #include "qemu/units.h" 26 #include "sysemu/device_tree.h" 27 #include "sysemu/kvm.h" 28 #include "sysemu/numa.h" 29 #include "sysemu/runstate.h" 30 #include "sysemu/sysemu.h" 31 #include "exec/hwaddr.h" 32 #include "kvm_arm.h" 33 #include "hw/arm/boot.h" 34 #include "hw/arm/bsa.h" 35 #include "hw/arm/fdt.h" 36 #include "hw/arm/smmuv3.h" 37 #include "hw/block/flash.h" 38 #include "hw/boards.h" 39 #include "hw/ide/internal.h" 40 #include "hw/ide/ahci_internal.h" 41 #include "hw/intc/arm_gicv3_common.h" 42 #include "hw/intc/arm_gicv3_its_common.h" 43 #include "hw/loader.h" 44 #include "hw/pci-host/gpex.h" 45 #include "hw/qdev-properties.h" 46 #include "hw/usb.h" 47 #include "hw/usb/xhci.h" 48 #include "hw/char/pl011.h" 49 #include "hw/watchdog/sbsa_gwdt.h" 50 #include "net/net.h" 51 #include "qapi/qmp/qlist.h" 52 #include "qom/object.h" 53 #include "target/arm/cpu-qom.h" 54 #include "target/arm/gtimer.h" 55 56 #define RAMLIMIT_GB 8192 57 #define RAMLIMIT_BYTES (RAMLIMIT_GB * GiB) 58 59 #define NUM_IRQS 256 60 #define NUM_SMMU_IRQS 4 61 #define NUM_SATA_PORTS 6 62 63 enum { 64 SBSA_FLASH, 65 SBSA_MEM, 66 SBSA_CPUPERIPHS, 67 SBSA_GIC_DIST, 68 SBSA_GIC_REDIST, 69 SBSA_GIC_ITS, 70 SBSA_SECURE_EC, 71 SBSA_GWDT_WS0, 72 SBSA_GWDT_REFRESH, 73 SBSA_GWDT_CONTROL, 74 SBSA_SMMU, 75 SBSA_UART, 76 SBSA_RTC, 77 SBSA_PCIE, 78 SBSA_PCIE_MMIO, 79 SBSA_PCIE_MMIO_HIGH, 80 SBSA_PCIE_PIO, 81 SBSA_PCIE_ECAM, 82 SBSA_GPIO, 83 SBSA_SECURE_UART, 84 SBSA_SECURE_UART_MM, 85 SBSA_SECURE_MEM, 86 SBSA_AHCI, 87 SBSA_XHCI, 88 }; 89 90 struct SBSAMachineState { 91 MachineState parent; 92 struct arm_boot_info bootinfo; 93 int smp_cpus; 94 void *fdt; 95 int fdt_size; 96 int psci_conduit; 97 DeviceState *gic; 98 PFlashCFI01 *flash[2]; 99 }; 100 101 #define TYPE_SBSA_MACHINE MACHINE_TYPE_NAME("sbsa-ref") 102 OBJECT_DECLARE_SIMPLE_TYPE(SBSAMachineState, SBSA_MACHINE) 103 104 static const MemMapEntry sbsa_ref_memmap[] = { 105 /* 512M boot ROM */ 106 [SBSA_FLASH] = { 0, 0x20000000 }, 107 /* 512M secure memory */ 108 [SBSA_SECURE_MEM] = { 0x20000000, 0x20000000 }, 109 /* Space reserved for CPU peripheral devices */ 110 [SBSA_CPUPERIPHS] = { 0x40000000, 0x00040000 }, 111 [SBSA_GIC_DIST] = { 0x40060000, 0x00010000 }, 112 [SBSA_GIC_REDIST] = { 0x40080000, 0x04000000 }, 113 [SBSA_GIC_ITS] = { 0x44081000, 0x00020000 }, 114 [SBSA_SECURE_EC] = { 0x50000000, 0x00001000 }, 115 [SBSA_GWDT_REFRESH] = { 0x50010000, 0x00001000 }, 116 [SBSA_GWDT_CONTROL] = { 0x50011000, 0x00001000 }, 117 [SBSA_UART] = { 0x60000000, 0x00001000 }, 118 [SBSA_RTC] = { 0x60010000, 0x00001000 }, 119 [SBSA_GPIO] = { 0x60020000, 0x00001000 }, 120 [SBSA_SECURE_UART] = { 0x60030000, 0x00001000 }, 121 [SBSA_SECURE_UART_MM] = { 0x60040000, 0x00001000 }, 122 [SBSA_SMMU] = { 0x60050000, 0x00020000 }, 123 /* Space here reserved for more SMMUs */ 124 [SBSA_AHCI] = { 0x60100000, 0x00010000 }, 125 [SBSA_XHCI] = { 0x60110000, 0x00010000 }, 126 /* Space here reserved for other devices */ 127 [SBSA_PCIE_PIO] = { 0x7fff0000, 0x00010000 }, 128 /* 32-bit address PCIE MMIO space */ 129 [SBSA_PCIE_MMIO] = { 0x80000000, 0x70000000 }, 130 /* 256M PCIE ECAM space */ 131 [SBSA_PCIE_ECAM] = { 0xf0000000, 0x10000000 }, 132 /* ~1TB PCIE MMIO space (4GB to 1024GB boundary) */ 133 [SBSA_PCIE_MMIO_HIGH] = { 0x100000000ULL, 0xFF00000000ULL }, 134 [SBSA_MEM] = { 0x10000000000ULL, RAMLIMIT_BYTES }, 135 }; 136 137 static const int sbsa_ref_irqmap[] = { 138 [SBSA_UART] = 1, 139 [SBSA_RTC] = 2, 140 [SBSA_PCIE] = 3, /* ... to 6 */ 141 [SBSA_GPIO] = 7, 142 [SBSA_SECURE_UART] = 8, 143 [SBSA_SECURE_UART_MM] = 9, 144 [SBSA_AHCI] = 10, 145 [SBSA_XHCI] = 11, 146 [SBSA_SMMU] = 12, /* ... to 15 */ 147 [SBSA_GWDT_WS0] = 16, 148 }; 149 150 static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx) 151 { 152 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER; 153 return arm_build_mp_affinity(idx, clustersz); 154 } 155 156 static void sbsa_fdt_add_gic_node(SBSAMachineState *sms) 157 { 158 char *nodename; 159 160 nodename = g_strdup_printf("/intc"); 161 qemu_fdt_add_subnode(sms->fdt, nodename); 162 qemu_fdt_setprop_sized_cells(sms->fdt, nodename, "reg", 163 2, sbsa_ref_memmap[SBSA_GIC_DIST].base, 164 2, sbsa_ref_memmap[SBSA_GIC_DIST].size, 165 2, sbsa_ref_memmap[SBSA_GIC_REDIST].base, 166 2, sbsa_ref_memmap[SBSA_GIC_REDIST].size); 167 168 nodename = g_strdup_printf("/intc/its"); 169 qemu_fdt_add_subnode(sms->fdt, nodename); 170 qemu_fdt_setprop_sized_cells(sms->fdt, nodename, "reg", 171 2, sbsa_ref_memmap[SBSA_GIC_ITS].base, 172 2, sbsa_ref_memmap[SBSA_GIC_ITS].size); 173 174 g_free(nodename); 175 } 176 177 /* 178 * Firmware on this machine only uses ACPI table to load OS, these limited 179 * device tree nodes are just to let firmware know the info which varies from 180 * command line parameters, so it is not necessary to be fully compatible 181 * with the kernel CPU and NUMA binding rules. 182 */ 183 static void create_fdt(SBSAMachineState *sms) 184 { 185 void *fdt = create_device_tree(&sms->fdt_size); 186 const MachineState *ms = MACHINE(sms); 187 int nb_numa_nodes = ms->numa_state->num_nodes; 188 int cpu; 189 190 if (!fdt) { 191 error_report("create_device_tree() failed"); 192 exit(1); 193 } 194 195 sms->fdt = fdt; 196 197 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,sbsa-ref"); 198 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 199 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 200 201 /* 202 * This versioning scheme is for informing platform fw only. It is neither: 203 * - A QEMU versioned machine type; a given version of QEMU will emulate 204 * a given version of the platform. 205 * - A reflection of level of SBSA (now SystemReady SR) support provided. 206 * 207 * machine-version-major: updated when changes breaking fw compatibility 208 * are introduced. 209 * machine-version-minor: updated when features are added that don't break 210 * fw compatibility. 211 */ 212 qemu_fdt_setprop_cell(fdt, "/", "machine-version-major", 0); 213 qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 3); 214 215 if (ms->numa_state->have_numa_distance) { 216 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); 217 uint32_t *matrix = g_malloc0(size); 218 int idx, i, j; 219 220 for (i = 0; i < nb_numa_nodes; i++) { 221 for (j = 0; j < nb_numa_nodes; j++) { 222 idx = (i * nb_numa_nodes + j) * 3; 223 matrix[idx + 0] = cpu_to_be32(i); 224 matrix[idx + 1] = cpu_to_be32(j); 225 matrix[idx + 2] = 226 cpu_to_be32(ms->numa_state->nodes[i].distance[j]); 227 } 228 } 229 230 qemu_fdt_add_subnode(fdt, "/distance-map"); 231 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", 232 matrix, size); 233 g_free(matrix); 234 } 235 236 /* 237 * From Documentation/devicetree/bindings/arm/cpus.yaml 238 * On ARM v8 64-bit systems this property is required 239 * and matches the MPIDR_EL1 register affinity bits. 240 * 241 * * If cpus node's #address-cells property is set to 2 242 * 243 * The first reg cell bits [7:0] must be set to 244 * bits [39:32] of MPIDR_EL1. 245 * 246 * The second reg cell bits [23:0] must be set to 247 * bits [23:0] of MPIDR_EL1. 248 */ 249 qemu_fdt_add_subnode(sms->fdt, "/cpus"); 250 qemu_fdt_setprop_cell(sms->fdt, "/cpus", "#address-cells", 2); 251 qemu_fdt_setprop_cell(sms->fdt, "/cpus", "#size-cells", 0x0); 252 253 for (cpu = sms->smp_cpus - 1; cpu >= 0; cpu--) { 254 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 255 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 256 CPUState *cs = CPU(armcpu); 257 uint64_t mpidr = sbsa_ref_cpu_mp_affinity(sms, cpu); 258 259 qemu_fdt_add_subnode(sms->fdt, nodename); 260 qemu_fdt_setprop_u64(sms->fdt, nodename, "reg", mpidr); 261 262 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 263 qemu_fdt_setprop_cell(sms->fdt, nodename, "numa-node-id", 264 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 265 } 266 267 g_free(nodename); 268 } 269 270 sbsa_fdt_add_gic_node(sms); 271 } 272 273 #define SBSA_FLASH_SECTOR_SIZE (256 * KiB) 274 275 static PFlashCFI01 *sbsa_flash_create1(SBSAMachineState *sms, 276 const char *name, 277 const char *alias_prop_name) 278 { 279 /* 280 * Create a single flash device. We use the same parameters as 281 * the flash devices on the Versatile Express board. 282 */ 283 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 284 285 qdev_prop_set_uint64(dev, "sector-length", SBSA_FLASH_SECTOR_SIZE); 286 qdev_prop_set_uint8(dev, "width", 4); 287 qdev_prop_set_uint8(dev, "device-width", 2); 288 qdev_prop_set_bit(dev, "big-endian", false); 289 qdev_prop_set_uint16(dev, "id0", 0x89); 290 qdev_prop_set_uint16(dev, "id1", 0x18); 291 qdev_prop_set_uint16(dev, "id2", 0x00); 292 qdev_prop_set_uint16(dev, "id3", 0x00); 293 qdev_prop_set_string(dev, "name", name); 294 object_property_add_child(OBJECT(sms), name, OBJECT(dev)); 295 object_property_add_alias(OBJECT(sms), alias_prop_name, 296 OBJECT(dev), "drive"); 297 return PFLASH_CFI01(dev); 298 } 299 300 static void sbsa_flash_create(SBSAMachineState *sms) 301 { 302 sms->flash[0] = sbsa_flash_create1(sms, "sbsa.flash0", "pflash0"); 303 sms->flash[1] = sbsa_flash_create1(sms, "sbsa.flash1", "pflash1"); 304 } 305 306 static void sbsa_flash_map1(PFlashCFI01 *flash, 307 hwaddr base, hwaddr size, 308 MemoryRegion *sysmem) 309 { 310 DeviceState *dev = DEVICE(flash); 311 312 assert(QEMU_IS_ALIGNED(size, SBSA_FLASH_SECTOR_SIZE)); 313 assert(size / SBSA_FLASH_SECTOR_SIZE <= UINT32_MAX); 314 qdev_prop_set_uint32(dev, "num-blocks", size / SBSA_FLASH_SECTOR_SIZE); 315 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 316 317 memory_region_add_subregion(sysmem, base, 318 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 319 0)); 320 } 321 322 static void sbsa_flash_map(SBSAMachineState *sms, 323 MemoryRegion *sysmem, 324 MemoryRegion *secure_sysmem) 325 { 326 /* 327 * Map two flash devices to fill the SBSA_FLASH space in the memmap. 328 * sysmem is the system memory space. secure_sysmem is the secure view 329 * of the system, and the first flash device should be made visible only 330 * there. The second flash device is visible to both secure and nonsecure. 331 */ 332 hwaddr flashsize = sbsa_ref_memmap[SBSA_FLASH].size / 2; 333 hwaddr flashbase = sbsa_ref_memmap[SBSA_FLASH].base; 334 335 sbsa_flash_map1(sms->flash[0], flashbase, flashsize, 336 secure_sysmem); 337 sbsa_flash_map1(sms->flash[1], flashbase + flashsize, flashsize, 338 sysmem); 339 } 340 341 static bool sbsa_firmware_init(SBSAMachineState *sms, 342 MemoryRegion *sysmem, 343 MemoryRegion *secure_sysmem) 344 { 345 const char *bios_name; 346 int i; 347 BlockBackend *pflash_blk0; 348 349 /* Map legacy -drive if=pflash to machine properties */ 350 for (i = 0; i < ARRAY_SIZE(sms->flash); i++) { 351 pflash_cfi01_legacy_drive(sms->flash[i], 352 drive_get(IF_PFLASH, 0, i)); 353 } 354 355 sbsa_flash_map(sms, sysmem, secure_sysmem); 356 357 pflash_blk0 = pflash_cfi01_get_blk(sms->flash[0]); 358 359 bios_name = MACHINE(sms)->firmware; 360 if (bios_name) { 361 char *fname; 362 MemoryRegion *mr; 363 int image_size; 364 365 if (pflash_blk0) { 366 error_report("The contents of the first flash device may be " 367 "specified with -bios or with -drive if=pflash... " 368 "but you cannot use both options at once"); 369 exit(1); 370 } 371 372 /* Fall back to -bios */ 373 374 fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 375 if (!fname) { 376 error_report("Could not find ROM image '%s'", bios_name); 377 exit(1); 378 } 379 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(sms->flash[0]), 0); 380 image_size = load_image_mr(fname, mr); 381 g_free(fname); 382 if (image_size < 0) { 383 error_report("Could not load ROM image '%s'", bios_name); 384 exit(1); 385 } 386 } 387 388 return pflash_blk0 || bios_name; 389 } 390 391 static void create_secure_ram(SBSAMachineState *sms, 392 MemoryRegion *secure_sysmem) 393 { 394 MemoryRegion *secram = g_new(MemoryRegion, 1); 395 hwaddr base = sbsa_ref_memmap[SBSA_SECURE_MEM].base; 396 hwaddr size = sbsa_ref_memmap[SBSA_SECURE_MEM].size; 397 398 memory_region_init_ram(secram, NULL, "sbsa-ref.secure-ram", size, 399 &error_fatal); 400 memory_region_add_subregion(secure_sysmem, base, secram); 401 } 402 403 static void create_its(SBSAMachineState *sms) 404 { 405 const char *itsclass = its_class_name(); 406 DeviceState *dev; 407 408 dev = qdev_new(itsclass); 409 410 object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(sms->gic), 411 &error_abort); 412 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 413 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, sbsa_ref_memmap[SBSA_GIC_ITS].base); 414 } 415 416 static void create_gic(SBSAMachineState *sms, MemoryRegion *mem) 417 { 418 unsigned int smp_cpus = MACHINE(sms)->smp.cpus; 419 SysBusDevice *gicbusdev; 420 const char *gictype; 421 uint32_t redist0_capacity, redist0_count; 422 QList *redist_region_count; 423 int i; 424 425 gictype = gicv3_class_name(); 426 427 sms->gic = qdev_new(gictype); 428 qdev_prop_set_uint32(sms->gic, "revision", 3); 429 qdev_prop_set_uint32(sms->gic, "num-cpu", smp_cpus); 430 /* 431 * Note that the num-irq property counts both internal and external 432 * interrupts; there are always 32 of the former (mandated by GIC spec). 433 */ 434 qdev_prop_set_uint32(sms->gic, "num-irq", NUM_IRQS + 32); 435 qdev_prop_set_bit(sms->gic, "has-security-extensions", true); 436 437 redist0_capacity = 438 sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE; 439 redist0_count = MIN(smp_cpus, redist0_capacity); 440 441 redist_region_count = qlist_new(); 442 qlist_append_int(redist_region_count, redist0_count); 443 qdev_prop_set_array(sms->gic, "redist-region-count", redist_region_count); 444 445 object_property_set_link(OBJECT(sms->gic), "sysmem", 446 OBJECT(mem), &error_fatal); 447 qdev_prop_set_bit(sms->gic, "has-lpi", true); 448 449 gicbusdev = SYS_BUS_DEVICE(sms->gic); 450 sysbus_realize_and_unref(gicbusdev, &error_fatal); 451 sysbus_mmio_map(gicbusdev, 0, sbsa_ref_memmap[SBSA_GIC_DIST].base); 452 sysbus_mmio_map(gicbusdev, 1, sbsa_ref_memmap[SBSA_GIC_REDIST].base); 453 454 /* 455 * Wire the outputs from each CPU's generic timer and the GICv3 456 * maintenance interrupt signal to the appropriate GIC PPI inputs, 457 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. 458 */ 459 for (i = 0; i < smp_cpus; i++) { 460 DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); 461 int intidbase = NUM_IRQS + i * GIC_INTERNAL; 462 int irq; 463 /* 464 * Mapping from the output timer irq lines from the CPU to the 465 * GIC PPI inputs used for this board. 466 */ 467 const int timer_irq[] = { 468 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 469 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 470 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 471 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 472 [GTIMER_HYPVIRT] = ARCH_TIMER_NS_EL2_VIRT_IRQ, 473 }; 474 475 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 476 qdev_connect_gpio_out(cpudev, irq, 477 qdev_get_gpio_in(sms->gic, 478 intidbase + timer_irq[irq])); 479 } 480 481 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0, 482 qdev_get_gpio_in(sms->gic, 483 intidbase 484 + ARCH_GIC_MAINT_IRQ)); 485 486 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 487 qdev_get_gpio_in(sms->gic, 488 intidbase 489 + VIRTUAL_PMU_IRQ)); 490 491 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 492 sysbus_connect_irq(gicbusdev, i + smp_cpus, 493 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 494 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, 495 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 496 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, 497 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 498 } 499 create_its(sms); 500 } 501 502 static void create_uart(const SBSAMachineState *sms, int uart, 503 MemoryRegion *mem, Chardev *chr) 504 { 505 hwaddr base = sbsa_ref_memmap[uart].base; 506 int irq = sbsa_ref_irqmap[uart]; 507 DeviceState *dev = qdev_new(TYPE_PL011); 508 SysBusDevice *s = SYS_BUS_DEVICE(dev); 509 510 qdev_prop_set_chr(dev, "chardev", chr); 511 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 512 memory_region_add_subregion(mem, base, 513 sysbus_mmio_get_region(s, 0)); 514 sysbus_connect_irq(s, 0, qdev_get_gpio_in(sms->gic, irq)); 515 } 516 517 static void create_rtc(const SBSAMachineState *sms) 518 { 519 hwaddr base = sbsa_ref_memmap[SBSA_RTC].base; 520 int irq = sbsa_ref_irqmap[SBSA_RTC]; 521 522 sysbus_create_simple("pl031", base, qdev_get_gpio_in(sms->gic, irq)); 523 } 524 525 static void create_wdt(const SBSAMachineState *sms) 526 { 527 hwaddr rbase = sbsa_ref_memmap[SBSA_GWDT_REFRESH].base; 528 hwaddr cbase = sbsa_ref_memmap[SBSA_GWDT_CONTROL].base; 529 DeviceState *dev = qdev_new(TYPE_WDT_SBSA); 530 SysBusDevice *s = SYS_BUS_DEVICE(dev); 531 int irq = sbsa_ref_irqmap[SBSA_GWDT_WS0]; 532 533 sysbus_realize_and_unref(s, &error_fatal); 534 sysbus_mmio_map(s, 0, rbase); 535 sysbus_mmio_map(s, 1, cbase); 536 sysbus_connect_irq(s, 0, qdev_get_gpio_in(sms->gic, irq)); 537 } 538 539 static DeviceState *gpio_key_dev; 540 static void sbsa_ref_powerdown_req(Notifier *n, void *opaque) 541 { 542 /* use gpio Pin 3 for power button event */ 543 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); 544 } 545 546 static Notifier sbsa_ref_powerdown_notifier = { 547 .notify = sbsa_ref_powerdown_req 548 }; 549 550 static void create_gpio(const SBSAMachineState *sms) 551 { 552 DeviceState *pl061_dev; 553 hwaddr base = sbsa_ref_memmap[SBSA_GPIO].base; 554 int irq = sbsa_ref_irqmap[SBSA_GPIO]; 555 556 pl061_dev = sysbus_create_simple("pl061", base, 557 qdev_get_gpio_in(sms->gic, irq)); 558 559 gpio_key_dev = sysbus_create_simple("gpio-key", -1, 560 qdev_get_gpio_in(pl061_dev, 3)); 561 562 /* connect powerdown request */ 563 qemu_register_powerdown_notifier(&sbsa_ref_powerdown_notifier); 564 } 565 566 static void create_ahci(const SBSAMachineState *sms) 567 { 568 hwaddr base = sbsa_ref_memmap[SBSA_AHCI].base; 569 int irq = sbsa_ref_irqmap[SBSA_AHCI]; 570 DeviceState *dev; 571 DriveInfo *hd[NUM_SATA_PORTS]; 572 SysbusAHCIState *sysahci; 573 AHCIState *ahci; 574 int i; 575 576 dev = qdev_new("sysbus-ahci"); 577 qdev_prop_set_uint32(dev, "num-ports", NUM_SATA_PORTS); 578 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 579 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 580 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(sms->gic, irq)); 581 582 sysahci = SYSBUS_AHCI(dev); 583 ahci = &sysahci->ahci; 584 ide_drive_get(hd, ARRAY_SIZE(hd)); 585 for (i = 0; i < ahci->ports; i++) { 586 if (hd[i] == NULL) { 587 continue; 588 } 589 ide_bus_create_drive(&ahci->dev[i].port, 0, hd[i]); 590 } 591 } 592 593 static void create_xhci(const SBSAMachineState *sms) 594 { 595 hwaddr base = sbsa_ref_memmap[SBSA_XHCI].base; 596 int irq = sbsa_ref_irqmap[SBSA_XHCI]; 597 DeviceState *dev = qdev_new(TYPE_XHCI_SYSBUS); 598 qdev_prop_set_uint32(dev, "slots", XHCI_MAXSLOTS); 599 600 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 601 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 602 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(sms->gic, irq)); 603 } 604 605 static void create_smmu(const SBSAMachineState *sms, PCIBus *bus) 606 { 607 hwaddr base = sbsa_ref_memmap[SBSA_SMMU].base; 608 int irq = sbsa_ref_irqmap[SBSA_SMMU]; 609 DeviceState *dev; 610 int i; 611 612 dev = qdev_new(TYPE_ARM_SMMUV3); 613 614 object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus), 615 &error_abort); 616 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 617 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 618 for (i = 0; i < NUM_SMMU_IRQS; i++) { 619 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 620 qdev_get_gpio_in(sms->gic, irq + i)); 621 } 622 } 623 624 static void create_pcie(SBSAMachineState *sms) 625 { 626 hwaddr base_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].base; 627 hwaddr size_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].size; 628 hwaddr base_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].base; 629 hwaddr size_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].size; 630 hwaddr base_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].base; 631 hwaddr size_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].size; 632 hwaddr base_pio = sbsa_ref_memmap[SBSA_PCIE_PIO].base; 633 int irq = sbsa_ref_irqmap[SBSA_PCIE]; 634 MachineClass *mc = MACHINE_GET_CLASS(sms); 635 MemoryRegion *mmio_alias, *mmio_alias_high, *mmio_reg; 636 MemoryRegion *ecam_alias, *ecam_reg; 637 DeviceState *dev; 638 PCIHostState *pci; 639 int i; 640 641 dev = qdev_new(TYPE_GPEX_HOST); 642 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 643 644 /* Map ECAM space */ 645 ecam_alias = g_new0(MemoryRegion, 1); 646 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 647 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 648 ecam_reg, 0, size_ecam); 649 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); 650 651 /* Map the MMIO space */ 652 mmio_alias = g_new0(MemoryRegion, 1); 653 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 654 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 655 mmio_reg, base_mmio, size_mmio); 656 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); 657 658 /* Map the MMIO_HIGH space */ 659 mmio_alias_high = g_new0(MemoryRegion, 1); 660 memory_region_init_alias(mmio_alias_high, OBJECT(dev), "pcie-mmio-high", 661 mmio_reg, base_mmio_high, size_mmio_high); 662 memory_region_add_subregion(get_system_memory(), base_mmio_high, 663 mmio_alias_high); 664 665 /* Map IO port space */ 666 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); 667 668 for (i = 0; i < GPEX_NUM_IRQS; i++) { 669 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 670 qdev_get_gpio_in(sms->gic, irq + i)); 671 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); 672 } 673 674 pci = PCI_HOST_BRIDGE(dev); 675 if (pci->bus) { 676 pci_init_nic_devices(pci->bus, mc->default_nic); 677 } 678 679 pci_create_simple(pci->bus, -1, "bochs-display"); 680 681 create_smmu(sms, pci->bus); 682 } 683 684 static void *sbsa_ref_dtb(const struct arm_boot_info *binfo, int *fdt_size) 685 { 686 const SBSAMachineState *board = container_of(binfo, SBSAMachineState, 687 bootinfo); 688 689 *fdt_size = board->fdt_size; 690 return board->fdt; 691 } 692 693 static void create_secure_ec(MemoryRegion *mem) 694 { 695 hwaddr base = sbsa_ref_memmap[SBSA_SECURE_EC].base; 696 DeviceState *dev = qdev_new("sbsa-ec"); 697 SysBusDevice *s = SYS_BUS_DEVICE(dev); 698 699 memory_region_add_subregion(mem, base, 700 sysbus_mmio_get_region(s, 0)); 701 } 702 703 static void sbsa_ref_init(MachineState *machine) 704 { 705 unsigned int smp_cpus = machine->smp.cpus; 706 unsigned int max_cpus = machine->smp.max_cpus; 707 SBSAMachineState *sms = SBSA_MACHINE(machine); 708 MachineClass *mc = MACHINE_GET_CLASS(machine); 709 MemoryRegion *sysmem = get_system_memory(); 710 MemoryRegion *secure_sysmem = g_new(MemoryRegion, 1); 711 bool firmware_loaded; 712 const CPUArchIdList *possible_cpus; 713 int n, sbsa_max_cpus; 714 715 if (kvm_enabled()) { 716 error_report("sbsa-ref: KVM is not supported for this machine"); 717 exit(1); 718 } 719 720 /* 721 * The Secure view of the world is the same as the NonSecure, 722 * but with a few extra devices. Create it as a container region 723 * containing the system memory at low priority; any secure-only 724 * devices go in at higher priority and take precedence. 725 */ 726 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", 727 UINT64_MAX); 728 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); 729 730 firmware_loaded = sbsa_firmware_init(sms, sysmem, secure_sysmem); 731 732 /* 733 * This machine has EL3 enabled, external firmware should supply PSCI 734 * implementation, so the QEMU's internal PSCI is disabled. 735 */ 736 sms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; 737 738 sbsa_max_cpus = sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE; 739 740 if (max_cpus > sbsa_max_cpus) { 741 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " 742 "supported by machine 'sbsa-ref' (%d)", 743 max_cpus, sbsa_max_cpus); 744 exit(1); 745 } 746 747 sms->smp_cpus = smp_cpus; 748 749 if (machine->ram_size > sbsa_ref_memmap[SBSA_MEM].size) { 750 error_report("sbsa-ref: cannot model more than %dGB RAM", RAMLIMIT_GB); 751 exit(1); 752 } 753 754 possible_cpus = mc->possible_cpu_arch_ids(machine); 755 for (n = 0; n < possible_cpus->len; n++) { 756 Object *cpuobj; 757 CPUState *cs; 758 759 if (n >= smp_cpus) { 760 break; 761 } 762 763 cpuobj = object_new(possible_cpus->cpus[n].type); 764 object_property_set_int(cpuobj, "mp-affinity", 765 possible_cpus->cpus[n].arch_id, NULL); 766 767 cs = CPU(cpuobj); 768 cs->cpu_index = n; 769 770 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj), 771 &error_fatal); 772 773 if (object_property_find(cpuobj, "reset-cbar")) { 774 object_property_set_int(cpuobj, "reset-cbar", 775 sbsa_ref_memmap[SBSA_CPUPERIPHS].base, 776 &error_abort); 777 } 778 779 object_property_set_link(cpuobj, "memory", OBJECT(sysmem), 780 &error_abort); 781 782 object_property_set_link(cpuobj, "secure-memory", 783 OBJECT(secure_sysmem), &error_abort); 784 785 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); 786 object_unref(cpuobj); 787 } 788 789 memory_region_add_subregion(sysmem, sbsa_ref_memmap[SBSA_MEM].base, 790 machine->ram); 791 792 create_fdt(sms); 793 794 create_secure_ram(sms, secure_sysmem); 795 796 create_gic(sms, sysmem); 797 798 create_uart(sms, SBSA_UART, sysmem, serial_hd(0)); 799 create_uart(sms, SBSA_SECURE_UART, secure_sysmem, serial_hd(1)); 800 /* Second secure UART for RAS and MM from EL0 */ 801 create_uart(sms, SBSA_SECURE_UART_MM, secure_sysmem, serial_hd(2)); 802 803 create_rtc(sms); 804 805 create_wdt(sms); 806 807 create_gpio(sms); 808 809 create_ahci(sms); 810 811 create_xhci(sms); 812 813 create_pcie(sms); 814 815 create_secure_ec(secure_sysmem); 816 817 sms->bootinfo.ram_size = machine->ram_size; 818 sms->bootinfo.board_id = -1; 819 sms->bootinfo.loader_start = sbsa_ref_memmap[SBSA_MEM].base; 820 sms->bootinfo.get_dtb = sbsa_ref_dtb; 821 sms->bootinfo.firmware_loaded = firmware_loaded; 822 arm_load_kernel(ARM_CPU(first_cpu), machine, &sms->bootinfo); 823 } 824 825 static const CPUArchIdList *sbsa_ref_possible_cpu_arch_ids(MachineState *ms) 826 { 827 unsigned int max_cpus = ms->smp.max_cpus; 828 SBSAMachineState *sms = SBSA_MACHINE(ms); 829 int n; 830 831 if (ms->possible_cpus) { 832 assert(ms->possible_cpus->len == max_cpus); 833 return ms->possible_cpus; 834 } 835 836 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 837 sizeof(CPUArchId) * max_cpus); 838 ms->possible_cpus->len = max_cpus; 839 for (n = 0; n < ms->possible_cpus->len; n++) { 840 ms->possible_cpus->cpus[n].type = ms->cpu_type; 841 ms->possible_cpus->cpus[n].arch_id = 842 sbsa_ref_cpu_mp_affinity(sms, n); 843 ms->possible_cpus->cpus[n].props.has_thread_id = true; 844 ms->possible_cpus->cpus[n].props.thread_id = n; 845 } 846 return ms->possible_cpus; 847 } 848 849 static CpuInstanceProperties 850 sbsa_ref_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 851 { 852 MachineClass *mc = MACHINE_GET_CLASS(ms); 853 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 854 855 assert(cpu_index < possible_cpus->len); 856 return possible_cpus->cpus[cpu_index].props; 857 } 858 859 static int64_t 860 sbsa_ref_get_default_cpu_node_id(const MachineState *ms, int idx) 861 { 862 return idx % ms->numa_state->num_nodes; 863 } 864 865 static void sbsa_ref_instance_init(Object *obj) 866 { 867 SBSAMachineState *sms = SBSA_MACHINE(obj); 868 869 sbsa_flash_create(sms); 870 } 871 872 static void sbsa_ref_class_init(ObjectClass *oc, void *data) 873 { 874 MachineClass *mc = MACHINE_CLASS(oc); 875 static const char * const valid_cpu_types[] = { 876 ARM_CPU_TYPE_NAME("cortex-a57"), 877 ARM_CPU_TYPE_NAME("cortex-a72"), 878 ARM_CPU_TYPE_NAME("neoverse-n1"), 879 ARM_CPU_TYPE_NAME("neoverse-v1"), 880 ARM_CPU_TYPE_NAME("neoverse-n2"), 881 ARM_CPU_TYPE_NAME("max"), 882 NULL, 883 }; 884 885 mc->init = sbsa_ref_init; 886 mc->desc = "QEMU 'SBSA Reference' ARM Virtual Machine"; 887 mc->default_cpu_type = ARM_CPU_TYPE_NAME("neoverse-n1"); 888 mc->valid_cpu_types = valid_cpu_types; 889 mc->max_cpus = 512; 890 mc->pci_allow_0_address = true; 891 mc->minimum_page_bits = 12; 892 mc->block_default_type = IF_IDE; 893 mc->no_cdrom = 1; 894 mc->default_nic = "e1000e"; 895 mc->default_ram_size = 1 * GiB; 896 mc->default_ram_id = "sbsa-ref.ram"; 897 mc->default_cpus = 4; 898 mc->possible_cpu_arch_ids = sbsa_ref_possible_cpu_arch_ids; 899 mc->cpu_index_to_instance_props = sbsa_ref_cpu_index_to_props; 900 mc->get_default_cpu_node_id = sbsa_ref_get_default_cpu_node_id; 901 /* platform instead of architectural choice */ 902 mc->cpu_cluster_has_numa_boundary = true; 903 } 904 905 static const TypeInfo sbsa_ref_info = { 906 .name = TYPE_SBSA_MACHINE, 907 .parent = TYPE_MACHINE, 908 .instance_init = sbsa_ref_instance_init, 909 .class_init = sbsa_ref_class_init, 910 .instance_size = sizeof(SBSAMachineState), 911 }; 912 913 static void sbsa_ref_machine_init(void) 914 { 915 type_register_static(&sbsa_ref_info); 916 } 917 918 type_init(sbsa_ref_machine_init); 919