1 /* 2 * ARM SBSA Reference Platform emulation 3 * 4 * Copyright (c) 2018 Linaro Limited 5 * Written by Hongbo Zhang <hongbo.zhang@linaro.org> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/datadir.h" 22 #include "qapi/error.h" 23 #include "qemu/error-report.h" 24 #include "qemu/units.h" 25 #include "sysemu/device_tree.h" 26 #include "sysemu/kvm.h" 27 #include "sysemu/numa.h" 28 #include "sysemu/runstate.h" 29 #include "sysemu/sysemu.h" 30 #include "exec/hwaddr.h" 31 #include "kvm_arm.h" 32 #include "hw/arm/boot.h" 33 #include "hw/arm/fdt.h" 34 #include "hw/arm/smmuv3.h" 35 #include "hw/block/flash.h" 36 #include "hw/boards.h" 37 #include "hw/ide/internal.h" 38 #include "hw/ide/ahci_internal.h" 39 #include "hw/intc/arm_gicv3_common.h" 40 #include "hw/intc/arm_gicv3_its_common.h" 41 #include "hw/loader.h" 42 #include "hw/pci-host/gpex.h" 43 #include "hw/qdev-properties.h" 44 #include "hw/usb.h" 45 #include "hw/usb/xhci.h" 46 #include "hw/char/pl011.h" 47 #include "hw/watchdog/sbsa_gwdt.h" 48 #include "net/net.h" 49 #include "qom/object.h" 50 51 #define RAMLIMIT_GB 8192 52 #define RAMLIMIT_BYTES (RAMLIMIT_GB * GiB) 53 54 #define NUM_IRQS 256 55 #define NUM_SMMU_IRQS 4 56 #define NUM_SATA_PORTS 6 57 58 #define VIRTUAL_PMU_IRQ 7 59 #define ARCH_GIC_MAINT_IRQ 9 60 #define ARCH_TIMER_VIRT_IRQ 11 61 #define ARCH_TIMER_S_EL1_IRQ 13 62 #define ARCH_TIMER_NS_EL1_IRQ 14 63 #define ARCH_TIMER_NS_EL2_IRQ 10 64 #define ARCH_TIMER_NS_EL2_VIRT_IRQ 12 65 66 enum { 67 SBSA_FLASH, 68 SBSA_MEM, 69 SBSA_CPUPERIPHS, 70 SBSA_GIC_DIST, 71 SBSA_GIC_REDIST, 72 SBSA_GIC_ITS, 73 SBSA_SECURE_EC, 74 SBSA_GWDT_WS0, 75 SBSA_GWDT_REFRESH, 76 SBSA_GWDT_CONTROL, 77 SBSA_SMMU, 78 SBSA_UART, 79 SBSA_RTC, 80 SBSA_PCIE, 81 SBSA_PCIE_MMIO, 82 SBSA_PCIE_MMIO_HIGH, 83 SBSA_PCIE_PIO, 84 SBSA_PCIE_ECAM, 85 SBSA_GPIO, 86 SBSA_SECURE_UART, 87 SBSA_SECURE_UART_MM, 88 SBSA_SECURE_MEM, 89 SBSA_AHCI, 90 SBSA_XHCI, 91 }; 92 93 struct SBSAMachineState { 94 MachineState parent; 95 struct arm_boot_info bootinfo; 96 int smp_cpus; 97 void *fdt; 98 int fdt_size; 99 int psci_conduit; 100 DeviceState *gic; 101 PFlashCFI01 *flash[2]; 102 }; 103 104 #define TYPE_SBSA_MACHINE MACHINE_TYPE_NAME("sbsa-ref") 105 OBJECT_DECLARE_SIMPLE_TYPE(SBSAMachineState, SBSA_MACHINE) 106 107 static const MemMapEntry sbsa_ref_memmap[] = { 108 /* 512M boot ROM */ 109 [SBSA_FLASH] = { 0, 0x20000000 }, 110 /* 512M secure memory */ 111 [SBSA_SECURE_MEM] = { 0x20000000, 0x20000000 }, 112 /* Space reserved for CPU peripheral devices */ 113 [SBSA_CPUPERIPHS] = { 0x40000000, 0x00040000 }, 114 [SBSA_GIC_DIST] = { 0x40060000, 0x00010000 }, 115 [SBSA_GIC_REDIST] = { 0x40080000, 0x04000000 }, 116 [SBSA_GIC_ITS] = { 0x44081000, 0x00020000 }, 117 [SBSA_SECURE_EC] = { 0x50000000, 0x00001000 }, 118 [SBSA_GWDT_REFRESH] = { 0x50010000, 0x00001000 }, 119 [SBSA_GWDT_CONTROL] = { 0x50011000, 0x00001000 }, 120 [SBSA_UART] = { 0x60000000, 0x00001000 }, 121 [SBSA_RTC] = { 0x60010000, 0x00001000 }, 122 [SBSA_GPIO] = { 0x60020000, 0x00001000 }, 123 [SBSA_SECURE_UART] = { 0x60030000, 0x00001000 }, 124 [SBSA_SECURE_UART_MM] = { 0x60040000, 0x00001000 }, 125 [SBSA_SMMU] = { 0x60050000, 0x00020000 }, 126 /* Space here reserved for more SMMUs */ 127 [SBSA_AHCI] = { 0x60100000, 0x00010000 }, 128 [SBSA_XHCI] = { 0x60110000, 0x00010000 }, 129 /* Space here reserved for other devices */ 130 [SBSA_PCIE_PIO] = { 0x7fff0000, 0x00010000 }, 131 /* 32-bit address PCIE MMIO space */ 132 [SBSA_PCIE_MMIO] = { 0x80000000, 0x70000000 }, 133 /* 256M PCIE ECAM space */ 134 [SBSA_PCIE_ECAM] = { 0xf0000000, 0x10000000 }, 135 /* ~1TB PCIE MMIO space (4GB to 1024GB boundary) */ 136 [SBSA_PCIE_MMIO_HIGH] = { 0x100000000ULL, 0xFF00000000ULL }, 137 [SBSA_MEM] = { 0x10000000000ULL, RAMLIMIT_BYTES }, 138 }; 139 140 static const int sbsa_ref_irqmap[] = { 141 [SBSA_UART] = 1, 142 [SBSA_RTC] = 2, 143 [SBSA_PCIE] = 3, /* ... to 6 */ 144 [SBSA_GPIO] = 7, 145 [SBSA_SECURE_UART] = 8, 146 [SBSA_SECURE_UART_MM] = 9, 147 [SBSA_AHCI] = 10, 148 [SBSA_XHCI] = 11, 149 [SBSA_SMMU] = 12, /* ... to 15 */ 150 [SBSA_GWDT_WS0] = 16, 151 }; 152 153 static const char * const valid_cpus[] = { 154 ARM_CPU_TYPE_NAME("cortex-a57"), 155 ARM_CPU_TYPE_NAME("cortex-a72"), 156 ARM_CPU_TYPE_NAME("neoverse-n1"), 157 ARM_CPU_TYPE_NAME("neoverse-v1"), 158 ARM_CPU_TYPE_NAME("max"), 159 }; 160 161 static bool cpu_type_valid(const char *cpu) 162 { 163 int i; 164 165 for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) { 166 if (strcmp(cpu, valid_cpus[i]) == 0) { 167 return true; 168 } 169 } 170 return false; 171 } 172 173 static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx) 174 { 175 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER; 176 return arm_cpu_mp_affinity(idx, clustersz); 177 } 178 179 static void sbsa_fdt_add_gic_node(SBSAMachineState *sms) 180 { 181 char *nodename; 182 183 nodename = g_strdup_printf("/intc"); 184 qemu_fdt_add_subnode(sms->fdt, nodename); 185 qemu_fdt_setprop_sized_cells(sms->fdt, nodename, "reg", 186 2, sbsa_ref_memmap[SBSA_GIC_DIST].base, 187 2, sbsa_ref_memmap[SBSA_GIC_DIST].size, 188 2, sbsa_ref_memmap[SBSA_GIC_REDIST].base, 189 2, sbsa_ref_memmap[SBSA_GIC_REDIST].size); 190 191 nodename = g_strdup_printf("/intc/its"); 192 qemu_fdt_add_subnode(sms->fdt, nodename); 193 qemu_fdt_setprop_sized_cells(sms->fdt, nodename, "reg", 194 2, sbsa_ref_memmap[SBSA_GIC_ITS].base, 195 2, sbsa_ref_memmap[SBSA_GIC_ITS].size); 196 197 g_free(nodename); 198 } 199 200 /* 201 * Firmware on this machine only uses ACPI table to load OS, these limited 202 * device tree nodes are just to let firmware know the info which varies from 203 * command line parameters, so it is not necessary to be fully compatible 204 * with the kernel CPU and NUMA binding rules. 205 */ 206 static void create_fdt(SBSAMachineState *sms) 207 { 208 void *fdt = create_device_tree(&sms->fdt_size); 209 const MachineState *ms = MACHINE(sms); 210 int nb_numa_nodes = ms->numa_state->num_nodes; 211 int cpu; 212 213 if (!fdt) { 214 error_report("create_device_tree() failed"); 215 exit(1); 216 } 217 218 sms->fdt = fdt; 219 220 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,sbsa-ref"); 221 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 222 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 223 224 /* 225 * This versioning scheme is for informing platform fw only. It is neither: 226 * - A QEMU versioned machine type; a given version of QEMU will emulate 227 * a given version of the platform. 228 * - A reflection of level of SBSA (now SystemReady SR) support provided. 229 * 230 * machine-version-major: updated when changes breaking fw compatibility 231 * are introduced. 232 * machine-version-minor: updated when features are added that don't break 233 * fw compatibility. 234 */ 235 qemu_fdt_setprop_cell(fdt, "/", "machine-version-major", 0); 236 qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 3); 237 238 if (ms->numa_state->have_numa_distance) { 239 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); 240 uint32_t *matrix = g_malloc0(size); 241 int idx, i, j; 242 243 for (i = 0; i < nb_numa_nodes; i++) { 244 for (j = 0; j < nb_numa_nodes; j++) { 245 idx = (i * nb_numa_nodes + j) * 3; 246 matrix[idx + 0] = cpu_to_be32(i); 247 matrix[idx + 1] = cpu_to_be32(j); 248 matrix[idx + 2] = 249 cpu_to_be32(ms->numa_state->nodes[i].distance[j]); 250 } 251 } 252 253 qemu_fdt_add_subnode(fdt, "/distance-map"); 254 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", 255 matrix, size); 256 g_free(matrix); 257 } 258 259 /* 260 * From Documentation/devicetree/bindings/arm/cpus.yaml 261 * On ARM v8 64-bit systems this property is required 262 * and matches the MPIDR_EL1 register affinity bits. 263 * 264 * * If cpus node's #address-cells property is set to 2 265 * 266 * The first reg cell bits [7:0] must be set to 267 * bits [39:32] of MPIDR_EL1. 268 * 269 * The second reg cell bits [23:0] must be set to 270 * bits [23:0] of MPIDR_EL1. 271 */ 272 qemu_fdt_add_subnode(sms->fdt, "/cpus"); 273 qemu_fdt_setprop_cell(sms->fdt, "/cpus", "#address-cells", 2); 274 qemu_fdt_setprop_cell(sms->fdt, "/cpus", "#size-cells", 0x0); 275 276 for (cpu = sms->smp_cpus - 1; cpu >= 0; cpu--) { 277 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 278 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 279 CPUState *cs = CPU(armcpu); 280 uint64_t mpidr = sbsa_ref_cpu_mp_affinity(sms, cpu); 281 282 qemu_fdt_add_subnode(sms->fdt, nodename); 283 qemu_fdt_setprop_u64(sms->fdt, nodename, "reg", mpidr); 284 285 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 286 qemu_fdt_setprop_cell(sms->fdt, nodename, "numa-node-id", 287 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 288 } 289 290 g_free(nodename); 291 } 292 293 sbsa_fdt_add_gic_node(sms); 294 } 295 296 #define SBSA_FLASH_SECTOR_SIZE (256 * KiB) 297 298 static PFlashCFI01 *sbsa_flash_create1(SBSAMachineState *sms, 299 const char *name, 300 const char *alias_prop_name) 301 { 302 /* 303 * Create a single flash device. We use the same parameters as 304 * the flash devices on the Versatile Express board. 305 */ 306 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 307 308 qdev_prop_set_uint64(dev, "sector-length", SBSA_FLASH_SECTOR_SIZE); 309 qdev_prop_set_uint8(dev, "width", 4); 310 qdev_prop_set_uint8(dev, "device-width", 2); 311 qdev_prop_set_bit(dev, "big-endian", false); 312 qdev_prop_set_uint16(dev, "id0", 0x89); 313 qdev_prop_set_uint16(dev, "id1", 0x18); 314 qdev_prop_set_uint16(dev, "id2", 0x00); 315 qdev_prop_set_uint16(dev, "id3", 0x00); 316 qdev_prop_set_string(dev, "name", name); 317 object_property_add_child(OBJECT(sms), name, OBJECT(dev)); 318 object_property_add_alias(OBJECT(sms), alias_prop_name, 319 OBJECT(dev), "drive"); 320 return PFLASH_CFI01(dev); 321 } 322 323 static void sbsa_flash_create(SBSAMachineState *sms) 324 { 325 sms->flash[0] = sbsa_flash_create1(sms, "sbsa.flash0", "pflash0"); 326 sms->flash[1] = sbsa_flash_create1(sms, "sbsa.flash1", "pflash1"); 327 } 328 329 static void sbsa_flash_map1(PFlashCFI01 *flash, 330 hwaddr base, hwaddr size, 331 MemoryRegion *sysmem) 332 { 333 DeviceState *dev = DEVICE(flash); 334 335 assert(QEMU_IS_ALIGNED(size, SBSA_FLASH_SECTOR_SIZE)); 336 assert(size / SBSA_FLASH_SECTOR_SIZE <= UINT32_MAX); 337 qdev_prop_set_uint32(dev, "num-blocks", size / SBSA_FLASH_SECTOR_SIZE); 338 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 339 340 memory_region_add_subregion(sysmem, base, 341 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 342 0)); 343 } 344 345 static void sbsa_flash_map(SBSAMachineState *sms, 346 MemoryRegion *sysmem, 347 MemoryRegion *secure_sysmem) 348 { 349 /* 350 * Map two flash devices to fill the SBSA_FLASH space in the memmap. 351 * sysmem is the system memory space. secure_sysmem is the secure view 352 * of the system, and the first flash device should be made visible only 353 * there. The second flash device is visible to both secure and nonsecure. 354 */ 355 hwaddr flashsize = sbsa_ref_memmap[SBSA_FLASH].size / 2; 356 hwaddr flashbase = sbsa_ref_memmap[SBSA_FLASH].base; 357 358 sbsa_flash_map1(sms->flash[0], flashbase, flashsize, 359 secure_sysmem); 360 sbsa_flash_map1(sms->flash[1], flashbase + flashsize, flashsize, 361 sysmem); 362 } 363 364 static bool sbsa_firmware_init(SBSAMachineState *sms, 365 MemoryRegion *sysmem, 366 MemoryRegion *secure_sysmem) 367 { 368 const char *bios_name; 369 int i; 370 BlockBackend *pflash_blk0; 371 372 /* Map legacy -drive if=pflash to machine properties */ 373 for (i = 0; i < ARRAY_SIZE(sms->flash); i++) { 374 pflash_cfi01_legacy_drive(sms->flash[i], 375 drive_get(IF_PFLASH, 0, i)); 376 } 377 378 sbsa_flash_map(sms, sysmem, secure_sysmem); 379 380 pflash_blk0 = pflash_cfi01_get_blk(sms->flash[0]); 381 382 bios_name = MACHINE(sms)->firmware; 383 if (bios_name) { 384 char *fname; 385 MemoryRegion *mr; 386 int image_size; 387 388 if (pflash_blk0) { 389 error_report("The contents of the first flash device may be " 390 "specified with -bios or with -drive if=pflash... " 391 "but you cannot use both options at once"); 392 exit(1); 393 } 394 395 /* Fall back to -bios */ 396 397 fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 398 if (!fname) { 399 error_report("Could not find ROM image '%s'", bios_name); 400 exit(1); 401 } 402 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(sms->flash[0]), 0); 403 image_size = load_image_mr(fname, mr); 404 g_free(fname); 405 if (image_size < 0) { 406 error_report("Could not load ROM image '%s'", bios_name); 407 exit(1); 408 } 409 } 410 411 return pflash_blk0 || bios_name; 412 } 413 414 static void create_secure_ram(SBSAMachineState *sms, 415 MemoryRegion *secure_sysmem) 416 { 417 MemoryRegion *secram = g_new(MemoryRegion, 1); 418 hwaddr base = sbsa_ref_memmap[SBSA_SECURE_MEM].base; 419 hwaddr size = sbsa_ref_memmap[SBSA_SECURE_MEM].size; 420 421 memory_region_init_ram(secram, NULL, "sbsa-ref.secure-ram", size, 422 &error_fatal); 423 memory_region_add_subregion(secure_sysmem, base, secram); 424 } 425 426 static void create_its(SBSAMachineState *sms) 427 { 428 const char *itsclass = its_class_name(); 429 DeviceState *dev; 430 431 dev = qdev_new(itsclass); 432 433 object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(sms->gic), 434 &error_abort); 435 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 436 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, sbsa_ref_memmap[SBSA_GIC_ITS].base); 437 } 438 439 static void create_gic(SBSAMachineState *sms, MemoryRegion *mem) 440 { 441 unsigned int smp_cpus = MACHINE(sms)->smp.cpus; 442 SysBusDevice *gicbusdev; 443 const char *gictype; 444 uint32_t redist0_capacity, redist0_count; 445 int i; 446 447 gictype = gicv3_class_name(); 448 449 sms->gic = qdev_new(gictype); 450 qdev_prop_set_uint32(sms->gic, "revision", 3); 451 qdev_prop_set_uint32(sms->gic, "num-cpu", smp_cpus); 452 /* 453 * Note that the num-irq property counts both internal and external 454 * interrupts; there are always 32 of the former (mandated by GIC spec). 455 */ 456 qdev_prop_set_uint32(sms->gic, "num-irq", NUM_IRQS + 32); 457 qdev_prop_set_bit(sms->gic, "has-security-extensions", true); 458 459 redist0_capacity = 460 sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE; 461 redist0_count = MIN(smp_cpus, redist0_capacity); 462 463 qdev_prop_set_uint32(sms->gic, "len-redist-region-count", 1); 464 qdev_prop_set_uint32(sms->gic, "redist-region-count[0]", redist0_count); 465 466 object_property_set_link(OBJECT(sms->gic), "sysmem", 467 OBJECT(mem), &error_fatal); 468 qdev_prop_set_bit(sms->gic, "has-lpi", true); 469 470 gicbusdev = SYS_BUS_DEVICE(sms->gic); 471 sysbus_realize_and_unref(gicbusdev, &error_fatal); 472 sysbus_mmio_map(gicbusdev, 0, sbsa_ref_memmap[SBSA_GIC_DIST].base); 473 sysbus_mmio_map(gicbusdev, 1, sbsa_ref_memmap[SBSA_GIC_REDIST].base); 474 475 /* 476 * Wire the outputs from each CPU's generic timer and the GICv3 477 * maintenance interrupt signal to the appropriate GIC PPI inputs, 478 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. 479 */ 480 for (i = 0; i < smp_cpus; i++) { 481 DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); 482 int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; 483 int irq; 484 /* 485 * Mapping from the output timer irq lines from the CPU to the 486 * GIC PPI inputs used for this board. 487 */ 488 const int timer_irq[] = { 489 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 490 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 491 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 492 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 493 [GTIMER_HYPVIRT] = ARCH_TIMER_NS_EL2_VIRT_IRQ, 494 }; 495 496 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 497 qdev_connect_gpio_out(cpudev, irq, 498 qdev_get_gpio_in(sms->gic, 499 ppibase + timer_irq[irq])); 500 } 501 502 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0, 503 qdev_get_gpio_in(sms->gic, ppibase 504 + ARCH_GIC_MAINT_IRQ)); 505 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 506 qdev_get_gpio_in(sms->gic, ppibase 507 + VIRTUAL_PMU_IRQ)); 508 509 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 510 sysbus_connect_irq(gicbusdev, i + smp_cpus, 511 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 512 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, 513 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 514 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, 515 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 516 } 517 create_its(sms); 518 } 519 520 static void create_uart(const SBSAMachineState *sms, int uart, 521 MemoryRegion *mem, Chardev *chr) 522 { 523 hwaddr base = sbsa_ref_memmap[uart].base; 524 int irq = sbsa_ref_irqmap[uart]; 525 DeviceState *dev = qdev_new(TYPE_PL011); 526 SysBusDevice *s = SYS_BUS_DEVICE(dev); 527 528 qdev_prop_set_chr(dev, "chardev", chr); 529 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 530 memory_region_add_subregion(mem, base, 531 sysbus_mmio_get_region(s, 0)); 532 sysbus_connect_irq(s, 0, qdev_get_gpio_in(sms->gic, irq)); 533 } 534 535 static void create_rtc(const SBSAMachineState *sms) 536 { 537 hwaddr base = sbsa_ref_memmap[SBSA_RTC].base; 538 int irq = sbsa_ref_irqmap[SBSA_RTC]; 539 540 sysbus_create_simple("pl031", base, qdev_get_gpio_in(sms->gic, irq)); 541 } 542 543 static void create_wdt(const SBSAMachineState *sms) 544 { 545 hwaddr rbase = sbsa_ref_memmap[SBSA_GWDT_REFRESH].base; 546 hwaddr cbase = sbsa_ref_memmap[SBSA_GWDT_CONTROL].base; 547 DeviceState *dev = qdev_new(TYPE_WDT_SBSA); 548 SysBusDevice *s = SYS_BUS_DEVICE(dev); 549 int irq = sbsa_ref_irqmap[SBSA_GWDT_WS0]; 550 551 sysbus_realize_and_unref(s, &error_fatal); 552 sysbus_mmio_map(s, 0, rbase); 553 sysbus_mmio_map(s, 1, cbase); 554 sysbus_connect_irq(s, 0, qdev_get_gpio_in(sms->gic, irq)); 555 } 556 557 static DeviceState *gpio_key_dev; 558 static void sbsa_ref_powerdown_req(Notifier *n, void *opaque) 559 { 560 /* use gpio Pin 3 for power button event */ 561 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); 562 } 563 564 static Notifier sbsa_ref_powerdown_notifier = { 565 .notify = sbsa_ref_powerdown_req 566 }; 567 568 static void create_gpio(const SBSAMachineState *sms) 569 { 570 DeviceState *pl061_dev; 571 hwaddr base = sbsa_ref_memmap[SBSA_GPIO].base; 572 int irq = sbsa_ref_irqmap[SBSA_GPIO]; 573 574 pl061_dev = sysbus_create_simple("pl061", base, 575 qdev_get_gpio_in(sms->gic, irq)); 576 577 gpio_key_dev = sysbus_create_simple("gpio-key", -1, 578 qdev_get_gpio_in(pl061_dev, 3)); 579 580 /* connect powerdown request */ 581 qemu_register_powerdown_notifier(&sbsa_ref_powerdown_notifier); 582 } 583 584 static void create_ahci(const SBSAMachineState *sms) 585 { 586 hwaddr base = sbsa_ref_memmap[SBSA_AHCI].base; 587 int irq = sbsa_ref_irqmap[SBSA_AHCI]; 588 DeviceState *dev; 589 DriveInfo *hd[NUM_SATA_PORTS]; 590 SysbusAHCIState *sysahci; 591 AHCIState *ahci; 592 int i; 593 594 dev = qdev_new("sysbus-ahci"); 595 qdev_prop_set_uint32(dev, "num-ports", NUM_SATA_PORTS); 596 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 597 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 598 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(sms->gic, irq)); 599 600 sysahci = SYSBUS_AHCI(dev); 601 ahci = &sysahci->ahci; 602 ide_drive_get(hd, ARRAY_SIZE(hd)); 603 for (i = 0; i < ahci->ports; i++) { 604 if (hd[i] == NULL) { 605 continue; 606 } 607 ide_bus_create_drive(&ahci->dev[i].port, 0, hd[i]); 608 } 609 } 610 611 static void create_xhci(const SBSAMachineState *sms) 612 { 613 hwaddr base = sbsa_ref_memmap[SBSA_XHCI].base; 614 int irq = sbsa_ref_irqmap[SBSA_XHCI]; 615 DeviceState *dev = qdev_new(TYPE_XHCI_SYSBUS); 616 qdev_prop_set_uint32(dev, "slots", XHCI_MAXSLOTS); 617 618 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 619 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 620 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(sms->gic, irq)); 621 } 622 623 static void create_smmu(const SBSAMachineState *sms, PCIBus *bus) 624 { 625 hwaddr base = sbsa_ref_memmap[SBSA_SMMU].base; 626 int irq = sbsa_ref_irqmap[SBSA_SMMU]; 627 DeviceState *dev; 628 int i; 629 630 dev = qdev_new(TYPE_ARM_SMMUV3); 631 632 object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus), 633 &error_abort); 634 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 635 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 636 for (i = 0; i < NUM_SMMU_IRQS; i++) { 637 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 638 qdev_get_gpio_in(sms->gic, irq + i)); 639 } 640 } 641 642 static void create_pcie(SBSAMachineState *sms) 643 { 644 hwaddr base_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].base; 645 hwaddr size_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].size; 646 hwaddr base_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].base; 647 hwaddr size_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].size; 648 hwaddr base_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].base; 649 hwaddr size_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].size; 650 hwaddr base_pio = sbsa_ref_memmap[SBSA_PCIE_PIO].base; 651 int irq = sbsa_ref_irqmap[SBSA_PCIE]; 652 MachineClass *mc = MACHINE_GET_CLASS(sms); 653 MemoryRegion *mmio_alias, *mmio_alias_high, *mmio_reg; 654 MemoryRegion *ecam_alias, *ecam_reg; 655 DeviceState *dev; 656 PCIHostState *pci; 657 int i; 658 659 dev = qdev_new(TYPE_GPEX_HOST); 660 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 661 662 /* Map ECAM space */ 663 ecam_alias = g_new0(MemoryRegion, 1); 664 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 665 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 666 ecam_reg, 0, size_ecam); 667 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); 668 669 /* Map the MMIO space */ 670 mmio_alias = g_new0(MemoryRegion, 1); 671 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 672 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 673 mmio_reg, base_mmio, size_mmio); 674 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); 675 676 /* Map the MMIO_HIGH space */ 677 mmio_alias_high = g_new0(MemoryRegion, 1); 678 memory_region_init_alias(mmio_alias_high, OBJECT(dev), "pcie-mmio-high", 679 mmio_reg, base_mmio_high, size_mmio_high); 680 memory_region_add_subregion(get_system_memory(), base_mmio_high, 681 mmio_alias_high); 682 683 /* Map IO port space */ 684 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); 685 686 for (i = 0; i < GPEX_NUM_IRQS; i++) { 687 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 688 qdev_get_gpio_in(sms->gic, irq + i)); 689 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); 690 } 691 692 pci = PCI_HOST_BRIDGE(dev); 693 if (pci->bus) { 694 for (i = 0; i < nb_nics; i++) { 695 pci_nic_init_nofail(&nd_table[i], pci->bus, mc->default_nic, NULL); 696 } 697 } 698 699 pci_create_simple(pci->bus, -1, "bochs-display"); 700 701 create_smmu(sms, pci->bus); 702 } 703 704 static void *sbsa_ref_dtb(const struct arm_boot_info *binfo, int *fdt_size) 705 { 706 const SBSAMachineState *board = container_of(binfo, SBSAMachineState, 707 bootinfo); 708 709 *fdt_size = board->fdt_size; 710 return board->fdt; 711 } 712 713 static void create_secure_ec(MemoryRegion *mem) 714 { 715 hwaddr base = sbsa_ref_memmap[SBSA_SECURE_EC].base; 716 DeviceState *dev = qdev_new("sbsa-ec"); 717 SysBusDevice *s = SYS_BUS_DEVICE(dev); 718 719 memory_region_add_subregion(mem, base, 720 sysbus_mmio_get_region(s, 0)); 721 } 722 723 static void sbsa_ref_init(MachineState *machine) 724 { 725 unsigned int smp_cpus = machine->smp.cpus; 726 unsigned int max_cpus = machine->smp.max_cpus; 727 SBSAMachineState *sms = SBSA_MACHINE(machine); 728 MachineClass *mc = MACHINE_GET_CLASS(machine); 729 MemoryRegion *sysmem = get_system_memory(); 730 MemoryRegion *secure_sysmem = g_new(MemoryRegion, 1); 731 bool firmware_loaded; 732 const CPUArchIdList *possible_cpus; 733 int n, sbsa_max_cpus; 734 735 if (!cpu_type_valid(machine->cpu_type)) { 736 error_report("sbsa-ref: CPU type %s not supported", machine->cpu_type); 737 exit(1); 738 } 739 740 if (kvm_enabled()) { 741 error_report("sbsa-ref: KVM is not supported for this machine"); 742 exit(1); 743 } 744 745 /* 746 * The Secure view of the world is the same as the NonSecure, 747 * but with a few extra devices. Create it as a container region 748 * containing the system memory at low priority; any secure-only 749 * devices go in at higher priority and take precedence. 750 */ 751 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", 752 UINT64_MAX); 753 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); 754 755 firmware_loaded = sbsa_firmware_init(sms, sysmem, secure_sysmem); 756 757 /* 758 * This machine has EL3 enabled, external firmware should supply PSCI 759 * implementation, so the QEMU's internal PSCI is disabled. 760 */ 761 sms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; 762 763 sbsa_max_cpus = sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE; 764 765 if (max_cpus > sbsa_max_cpus) { 766 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " 767 "supported by machine 'sbsa-ref' (%d)", 768 max_cpus, sbsa_max_cpus); 769 exit(1); 770 } 771 772 sms->smp_cpus = smp_cpus; 773 774 if (machine->ram_size > sbsa_ref_memmap[SBSA_MEM].size) { 775 error_report("sbsa-ref: cannot model more than %dGB RAM", RAMLIMIT_GB); 776 exit(1); 777 } 778 779 possible_cpus = mc->possible_cpu_arch_ids(machine); 780 for (n = 0; n < possible_cpus->len; n++) { 781 Object *cpuobj; 782 CPUState *cs; 783 784 if (n >= smp_cpus) { 785 break; 786 } 787 788 cpuobj = object_new(possible_cpus->cpus[n].type); 789 object_property_set_int(cpuobj, "mp-affinity", 790 possible_cpus->cpus[n].arch_id, NULL); 791 792 cs = CPU(cpuobj); 793 cs->cpu_index = n; 794 795 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj), 796 &error_fatal); 797 798 if (object_property_find(cpuobj, "reset-cbar")) { 799 object_property_set_int(cpuobj, "reset-cbar", 800 sbsa_ref_memmap[SBSA_CPUPERIPHS].base, 801 &error_abort); 802 } 803 804 object_property_set_link(cpuobj, "memory", OBJECT(sysmem), 805 &error_abort); 806 807 object_property_set_link(cpuobj, "secure-memory", 808 OBJECT(secure_sysmem), &error_abort); 809 810 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); 811 object_unref(cpuobj); 812 } 813 814 memory_region_add_subregion(sysmem, sbsa_ref_memmap[SBSA_MEM].base, 815 machine->ram); 816 817 create_fdt(sms); 818 819 create_secure_ram(sms, secure_sysmem); 820 821 create_gic(sms, sysmem); 822 823 create_uart(sms, SBSA_UART, sysmem, serial_hd(0)); 824 create_uart(sms, SBSA_SECURE_UART, secure_sysmem, serial_hd(1)); 825 /* Second secure UART for RAS and MM from EL0 */ 826 create_uart(sms, SBSA_SECURE_UART_MM, secure_sysmem, serial_hd(2)); 827 828 create_rtc(sms); 829 830 create_wdt(sms); 831 832 create_gpio(sms); 833 834 create_ahci(sms); 835 836 create_xhci(sms); 837 838 create_pcie(sms); 839 840 create_secure_ec(secure_sysmem); 841 842 sms->bootinfo.ram_size = machine->ram_size; 843 sms->bootinfo.board_id = -1; 844 sms->bootinfo.loader_start = sbsa_ref_memmap[SBSA_MEM].base; 845 sms->bootinfo.get_dtb = sbsa_ref_dtb; 846 sms->bootinfo.firmware_loaded = firmware_loaded; 847 arm_load_kernel(ARM_CPU(first_cpu), machine, &sms->bootinfo); 848 } 849 850 static const CPUArchIdList *sbsa_ref_possible_cpu_arch_ids(MachineState *ms) 851 { 852 unsigned int max_cpus = ms->smp.max_cpus; 853 SBSAMachineState *sms = SBSA_MACHINE(ms); 854 int n; 855 856 if (ms->possible_cpus) { 857 assert(ms->possible_cpus->len == max_cpus); 858 return ms->possible_cpus; 859 } 860 861 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 862 sizeof(CPUArchId) * max_cpus); 863 ms->possible_cpus->len = max_cpus; 864 for (n = 0; n < ms->possible_cpus->len; n++) { 865 ms->possible_cpus->cpus[n].type = ms->cpu_type; 866 ms->possible_cpus->cpus[n].arch_id = 867 sbsa_ref_cpu_mp_affinity(sms, n); 868 ms->possible_cpus->cpus[n].props.has_thread_id = true; 869 ms->possible_cpus->cpus[n].props.thread_id = n; 870 } 871 return ms->possible_cpus; 872 } 873 874 static CpuInstanceProperties 875 sbsa_ref_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 876 { 877 MachineClass *mc = MACHINE_GET_CLASS(ms); 878 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 879 880 assert(cpu_index < possible_cpus->len); 881 return possible_cpus->cpus[cpu_index].props; 882 } 883 884 static int64_t 885 sbsa_ref_get_default_cpu_node_id(const MachineState *ms, int idx) 886 { 887 return idx % ms->numa_state->num_nodes; 888 } 889 890 static void sbsa_ref_instance_init(Object *obj) 891 { 892 SBSAMachineState *sms = SBSA_MACHINE(obj); 893 894 sbsa_flash_create(sms); 895 } 896 897 static void sbsa_ref_class_init(ObjectClass *oc, void *data) 898 { 899 MachineClass *mc = MACHINE_CLASS(oc); 900 901 mc->init = sbsa_ref_init; 902 mc->desc = "QEMU 'SBSA Reference' ARM Virtual Machine"; 903 mc->default_cpu_type = ARM_CPU_TYPE_NAME("neoverse-n1"); 904 mc->max_cpus = 512; 905 mc->pci_allow_0_address = true; 906 mc->minimum_page_bits = 12; 907 mc->block_default_type = IF_IDE; 908 mc->no_cdrom = 1; 909 mc->default_nic = "e1000e"; 910 mc->default_ram_size = 1 * GiB; 911 mc->default_ram_id = "sbsa-ref.ram"; 912 mc->default_cpus = 4; 913 mc->possible_cpu_arch_ids = sbsa_ref_possible_cpu_arch_ids; 914 mc->cpu_index_to_instance_props = sbsa_ref_cpu_index_to_props; 915 mc->get_default_cpu_node_id = sbsa_ref_get_default_cpu_node_id; 916 /* platform instead of architectural choice */ 917 mc->cpu_cluster_has_numa_boundary = true; 918 } 919 920 static const TypeInfo sbsa_ref_info = { 921 .name = TYPE_SBSA_MACHINE, 922 .parent = TYPE_MACHINE, 923 .instance_init = sbsa_ref_instance_init, 924 .class_init = sbsa_ref_class_init, 925 .instance_size = sizeof(SBSAMachineState), 926 }; 927 928 static void sbsa_ref_machine_init(void) 929 { 930 type_register_static(&sbsa_ref_info); 931 } 932 933 type_init(sbsa_ref_machine_init); 934