1 /* 2 * ARM SBSA Reference Platform emulation 3 * 4 * Copyright (c) 2018 Linaro Limited 5 * Written by Hongbo Zhang <hongbo.zhang@linaro.org> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/datadir.h" 22 #include "qapi/error.h" 23 #include "qemu/error-report.h" 24 #include "qemu/units.h" 25 #include "sysemu/device_tree.h" 26 #include "sysemu/kvm.h" 27 #include "sysemu/numa.h" 28 #include "sysemu/runstate.h" 29 #include "sysemu/sysemu.h" 30 #include "exec/hwaddr.h" 31 #include "kvm_arm.h" 32 #include "hw/arm/boot.h" 33 #include "hw/arm/fdt.h" 34 #include "hw/arm/smmuv3.h" 35 #include "hw/block/flash.h" 36 #include "hw/boards.h" 37 #include "hw/ide/internal.h" 38 #include "hw/ide/ahci_internal.h" 39 #include "hw/intc/arm_gicv3_common.h" 40 #include "hw/intc/arm_gicv3_its_common.h" 41 #include "hw/loader.h" 42 #include "hw/pci-host/gpex.h" 43 #include "hw/qdev-properties.h" 44 #include "hw/usb.h" 45 #include "hw/char/pl011.h" 46 #include "hw/watchdog/sbsa_gwdt.h" 47 #include "net/net.h" 48 #include "qom/object.h" 49 50 #define RAMLIMIT_GB 8192 51 #define RAMLIMIT_BYTES (RAMLIMIT_GB * GiB) 52 53 #define NUM_IRQS 256 54 #define NUM_SMMU_IRQS 4 55 #define NUM_SATA_PORTS 6 56 57 #define VIRTUAL_PMU_IRQ 7 58 #define ARCH_GIC_MAINT_IRQ 9 59 #define ARCH_TIMER_VIRT_IRQ 11 60 #define ARCH_TIMER_S_EL1_IRQ 13 61 #define ARCH_TIMER_NS_EL1_IRQ 14 62 #define ARCH_TIMER_NS_EL2_IRQ 10 63 64 enum { 65 SBSA_FLASH, 66 SBSA_MEM, 67 SBSA_CPUPERIPHS, 68 SBSA_GIC_DIST, 69 SBSA_GIC_REDIST, 70 SBSA_GIC_ITS, 71 SBSA_SECURE_EC, 72 SBSA_GWDT_WS0, 73 SBSA_GWDT_REFRESH, 74 SBSA_GWDT_CONTROL, 75 SBSA_SMMU, 76 SBSA_UART, 77 SBSA_RTC, 78 SBSA_PCIE, 79 SBSA_PCIE_MMIO, 80 SBSA_PCIE_MMIO_HIGH, 81 SBSA_PCIE_PIO, 82 SBSA_PCIE_ECAM, 83 SBSA_GPIO, 84 SBSA_SECURE_UART, 85 SBSA_SECURE_UART_MM, 86 SBSA_SECURE_MEM, 87 SBSA_AHCI, 88 SBSA_EHCI, 89 }; 90 91 struct SBSAMachineState { 92 MachineState parent; 93 struct arm_boot_info bootinfo; 94 int smp_cpus; 95 void *fdt; 96 int fdt_size; 97 int psci_conduit; 98 DeviceState *gic; 99 PFlashCFI01 *flash[2]; 100 }; 101 102 #define TYPE_SBSA_MACHINE MACHINE_TYPE_NAME("sbsa-ref") 103 OBJECT_DECLARE_SIMPLE_TYPE(SBSAMachineState, SBSA_MACHINE) 104 105 static const MemMapEntry sbsa_ref_memmap[] = { 106 /* 512M boot ROM */ 107 [SBSA_FLASH] = { 0, 0x20000000 }, 108 /* 512M secure memory */ 109 [SBSA_SECURE_MEM] = { 0x20000000, 0x20000000 }, 110 /* Space reserved for CPU peripheral devices */ 111 [SBSA_CPUPERIPHS] = { 0x40000000, 0x00040000 }, 112 [SBSA_GIC_DIST] = { 0x40060000, 0x00010000 }, 113 [SBSA_GIC_REDIST] = { 0x40080000, 0x04000000 }, 114 [SBSA_GIC_ITS] = { 0x44081000, 0x00020000 }, 115 [SBSA_SECURE_EC] = { 0x50000000, 0x00001000 }, 116 [SBSA_GWDT_REFRESH] = { 0x50010000, 0x00001000 }, 117 [SBSA_GWDT_CONTROL] = { 0x50011000, 0x00001000 }, 118 [SBSA_UART] = { 0x60000000, 0x00001000 }, 119 [SBSA_RTC] = { 0x60010000, 0x00001000 }, 120 [SBSA_GPIO] = { 0x60020000, 0x00001000 }, 121 [SBSA_SECURE_UART] = { 0x60030000, 0x00001000 }, 122 [SBSA_SECURE_UART_MM] = { 0x60040000, 0x00001000 }, 123 [SBSA_SMMU] = { 0x60050000, 0x00020000 }, 124 /* Space here reserved for more SMMUs */ 125 [SBSA_AHCI] = { 0x60100000, 0x00010000 }, 126 [SBSA_EHCI] = { 0x60110000, 0x00010000 }, 127 /* Space here reserved for other devices */ 128 [SBSA_PCIE_PIO] = { 0x7fff0000, 0x00010000 }, 129 /* 32-bit address PCIE MMIO space */ 130 [SBSA_PCIE_MMIO] = { 0x80000000, 0x70000000 }, 131 /* 256M PCIE ECAM space */ 132 [SBSA_PCIE_ECAM] = { 0xf0000000, 0x10000000 }, 133 /* ~1TB PCIE MMIO space (4GB to 1024GB boundary) */ 134 [SBSA_PCIE_MMIO_HIGH] = { 0x100000000ULL, 0xFF00000000ULL }, 135 [SBSA_MEM] = { 0x10000000000ULL, RAMLIMIT_BYTES }, 136 }; 137 138 static const int sbsa_ref_irqmap[] = { 139 [SBSA_UART] = 1, 140 [SBSA_RTC] = 2, 141 [SBSA_PCIE] = 3, /* ... to 6 */ 142 [SBSA_GPIO] = 7, 143 [SBSA_SECURE_UART] = 8, 144 [SBSA_SECURE_UART_MM] = 9, 145 [SBSA_AHCI] = 10, 146 [SBSA_EHCI] = 11, 147 [SBSA_SMMU] = 12, /* ... to 15 */ 148 [SBSA_GWDT_WS0] = 16, 149 }; 150 151 static const char * const valid_cpus[] = { 152 ARM_CPU_TYPE_NAME("cortex-a57"), 153 ARM_CPU_TYPE_NAME("cortex-a72"), 154 ARM_CPU_TYPE_NAME("neoverse-n1"), 155 ARM_CPU_TYPE_NAME("max"), 156 }; 157 158 static bool cpu_type_valid(const char *cpu) 159 { 160 int i; 161 162 for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) { 163 if (strcmp(cpu, valid_cpus[i]) == 0) { 164 return true; 165 } 166 } 167 return false; 168 } 169 170 static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx) 171 { 172 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER; 173 return arm_cpu_mp_affinity(idx, clustersz); 174 } 175 176 static void sbsa_fdt_add_gic_node(SBSAMachineState *sms) 177 { 178 char *nodename; 179 180 nodename = g_strdup_printf("/intc"); 181 qemu_fdt_add_subnode(sms->fdt, nodename); 182 qemu_fdt_setprop_sized_cells(sms->fdt, nodename, "reg", 183 2, sbsa_ref_memmap[SBSA_GIC_DIST].base, 184 2, sbsa_ref_memmap[SBSA_GIC_DIST].size, 185 2, sbsa_ref_memmap[SBSA_GIC_REDIST].base, 186 2, sbsa_ref_memmap[SBSA_GIC_REDIST].size); 187 188 nodename = g_strdup_printf("/intc/its"); 189 qemu_fdt_add_subnode(sms->fdt, nodename); 190 qemu_fdt_setprop_sized_cells(sms->fdt, nodename, "reg", 191 2, sbsa_ref_memmap[SBSA_GIC_ITS].base, 192 2, sbsa_ref_memmap[SBSA_GIC_ITS].size); 193 194 g_free(nodename); 195 } 196 197 /* 198 * Firmware on this machine only uses ACPI table to load OS, these limited 199 * device tree nodes are just to let firmware know the info which varies from 200 * command line parameters, so it is not necessary to be fully compatible 201 * with the kernel CPU and NUMA binding rules. 202 */ 203 static void create_fdt(SBSAMachineState *sms) 204 { 205 void *fdt = create_device_tree(&sms->fdt_size); 206 const MachineState *ms = MACHINE(sms); 207 int nb_numa_nodes = ms->numa_state->num_nodes; 208 int cpu; 209 210 if (!fdt) { 211 error_report("create_device_tree() failed"); 212 exit(1); 213 } 214 215 sms->fdt = fdt; 216 217 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,sbsa-ref"); 218 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 219 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 220 221 /* 222 * This versioning scheme is for informing platform fw only. It is neither: 223 * - A QEMU versioned machine type; a given version of QEMU will emulate 224 * a given version of the platform. 225 * - A reflection of level of SBSA (now SystemReady SR) support provided. 226 * 227 * machine-version-major: updated when changes breaking fw compatibility 228 * are introduced. 229 * machine-version-minor: updated when features are added that don't break 230 * fw compatibility. 231 */ 232 qemu_fdt_setprop_cell(fdt, "/", "machine-version-major", 0); 233 qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 2); 234 235 if (ms->numa_state->have_numa_distance) { 236 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); 237 uint32_t *matrix = g_malloc0(size); 238 int idx, i, j; 239 240 for (i = 0; i < nb_numa_nodes; i++) { 241 for (j = 0; j < nb_numa_nodes; j++) { 242 idx = (i * nb_numa_nodes + j) * 3; 243 matrix[idx + 0] = cpu_to_be32(i); 244 matrix[idx + 1] = cpu_to_be32(j); 245 matrix[idx + 2] = 246 cpu_to_be32(ms->numa_state->nodes[i].distance[j]); 247 } 248 } 249 250 qemu_fdt_add_subnode(fdt, "/distance-map"); 251 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", 252 matrix, size); 253 g_free(matrix); 254 } 255 256 /* 257 * From Documentation/devicetree/bindings/arm/cpus.yaml 258 * On ARM v8 64-bit systems this property is required 259 * and matches the MPIDR_EL1 register affinity bits. 260 * 261 * * If cpus node's #address-cells property is set to 2 262 * 263 * The first reg cell bits [7:0] must be set to 264 * bits [39:32] of MPIDR_EL1. 265 * 266 * The second reg cell bits [23:0] must be set to 267 * bits [23:0] of MPIDR_EL1. 268 */ 269 qemu_fdt_add_subnode(sms->fdt, "/cpus"); 270 qemu_fdt_setprop_cell(sms->fdt, "/cpus", "#address-cells", 2); 271 qemu_fdt_setprop_cell(sms->fdt, "/cpus", "#size-cells", 0x0); 272 273 for (cpu = sms->smp_cpus - 1; cpu >= 0; cpu--) { 274 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 275 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 276 CPUState *cs = CPU(armcpu); 277 uint64_t mpidr = sbsa_ref_cpu_mp_affinity(sms, cpu); 278 279 qemu_fdt_add_subnode(sms->fdt, nodename); 280 qemu_fdt_setprop_u64(sms->fdt, nodename, "reg", mpidr); 281 282 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 283 qemu_fdt_setprop_cell(sms->fdt, nodename, "numa-node-id", 284 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 285 } 286 287 g_free(nodename); 288 } 289 290 sbsa_fdt_add_gic_node(sms); 291 } 292 293 #define SBSA_FLASH_SECTOR_SIZE (256 * KiB) 294 295 static PFlashCFI01 *sbsa_flash_create1(SBSAMachineState *sms, 296 const char *name, 297 const char *alias_prop_name) 298 { 299 /* 300 * Create a single flash device. We use the same parameters as 301 * the flash devices on the Versatile Express board. 302 */ 303 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 304 305 qdev_prop_set_uint64(dev, "sector-length", SBSA_FLASH_SECTOR_SIZE); 306 qdev_prop_set_uint8(dev, "width", 4); 307 qdev_prop_set_uint8(dev, "device-width", 2); 308 qdev_prop_set_bit(dev, "big-endian", false); 309 qdev_prop_set_uint16(dev, "id0", 0x89); 310 qdev_prop_set_uint16(dev, "id1", 0x18); 311 qdev_prop_set_uint16(dev, "id2", 0x00); 312 qdev_prop_set_uint16(dev, "id3", 0x00); 313 qdev_prop_set_string(dev, "name", name); 314 object_property_add_child(OBJECT(sms), name, OBJECT(dev)); 315 object_property_add_alias(OBJECT(sms), alias_prop_name, 316 OBJECT(dev), "drive"); 317 return PFLASH_CFI01(dev); 318 } 319 320 static void sbsa_flash_create(SBSAMachineState *sms) 321 { 322 sms->flash[0] = sbsa_flash_create1(sms, "sbsa.flash0", "pflash0"); 323 sms->flash[1] = sbsa_flash_create1(sms, "sbsa.flash1", "pflash1"); 324 } 325 326 static void sbsa_flash_map1(PFlashCFI01 *flash, 327 hwaddr base, hwaddr size, 328 MemoryRegion *sysmem) 329 { 330 DeviceState *dev = DEVICE(flash); 331 332 assert(QEMU_IS_ALIGNED(size, SBSA_FLASH_SECTOR_SIZE)); 333 assert(size / SBSA_FLASH_SECTOR_SIZE <= UINT32_MAX); 334 qdev_prop_set_uint32(dev, "num-blocks", size / SBSA_FLASH_SECTOR_SIZE); 335 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 336 337 memory_region_add_subregion(sysmem, base, 338 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 339 0)); 340 } 341 342 static void sbsa_flash_map(SBSAMachineState *sms, 343 MemoryRegion *sysmem, 344 MemoryRegion *secure_sysmem) 345 { 346 /* 347 * Map two flash devices to fill the SBSA_FLASH space in the memmap. 348 * sysmem is the system memory space. secure_sysmem is the secure view 349 * of the system, and the first flash device should be made visible only 350 * there. The second flash device is visible to both secure and nonsecure. 351 */ 352 hwaddr flashsize = sbsa_ref_memmap[SBSA_FLASH].size / 2; 353 hwaddr flashbase = sbsa_ref_memmap[SBSA_FLASH].base; 354 355 sbsa_flash_map1(sms->flash[0], flashbase, flashsize, 356 secure_sysmem); 357 sbsa_flash_map1(sms->flash[1], flashbase + flashsize, flashsize, 358 sysmem); 359 } 360 361 static bool sbsa_firmware_init(SBSAMachineState *sms, 362 MemoryRegion *sysmem, 363 MemoryRegion *secure_sysmem) 364 { 365 const char *bios_name; 366 int i; 367 BlockBackend *pflash_blk0; 368 369 /* Map legacy -drive if=pflash to machine properties */ 370 for (i = 0; i < ARRAY_SIZE(sms->flash); i++) { 371 pflash_cfi01_legacy_drive(sms->flash[i], 372 drive_get(IF_PFLASH, 0, i)); 373 } 374 375 sbsa_flash_map(sms, sysmem, secure_sysmem); 376 377 pflash_blk0 = pflash_cfi01_get_blk(sms->flash[0]); 378 379 bios_name = MACHINE(sms)->firmware; 380 if (bios_name) { 381 char *fname; 382 MemoryRegion *mr; 383 int image_size; 384 385 if (pflash_blk0) { 386 error_report("The contents of the first flash device may be " 387 "specified with -bios or with -drive if=pflash... " 388 "but you cannot use both options at once"); 389 exit(1); 390 } 391 392 /* Fall back to -bios */ 393 394 fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 395 if (!fname) { 396 error_report("Could not find ROM image '%s'", bios_name); 397 exit(1); 398 } 399 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(sms->flash[0]), 0); 400 image_size = load_image_mr(fname, mr); 401 g_free(fname); 402 if (image_size < 0) { 403 error_report("Could not load ROM image '%s'", bios_name); 404 exit(1); 405 } 406 } 407 408 return pflash_blk0 || bios_name; 409 } 410 411 static void create_secure_ram(SBSAMachineState *sms, 412 MemoryRegion *secure_sysmem) 413 { 414 MemoryRegion *secram = g_new(MemoryRegion, 1); 415 hwaddr base = sbsa_ref_memmap[SBSA_SECURE_MEM].base; 416 hwaddr size = sbsa_ref_memmap[SBSA_SECURE_MEM].size; 417 418 memory_region_init_ram(secram, NULL, "sbsa-ref.secure-ram", size, 419 &error_fatal); 420 memory_region_add_subregion(secure_sysmem, base, secram); 421 } 422 423 static void create_its(SBSAMachineState *sms) 424 { 425 const char *itsclass = its_class_name(); 426 DeviceState *dev; 427 428 dev = qdev_new(itsclass); 429 430 object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(sms->gic), 431 &error_abort); 432 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 433 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, sbsa_ref_memmap[SBSA_GIC_ITS].base); 434 } 435 436 static void create_gic(SBSAMachineState *sms, MemoryRegion *mem) 437 { 438 unsigned int smp_cpus = MACHINE(sms)->smp.cpus; 439 SysBusDevice *gicbusdev; 440 const char *gictype; 441 uint32_t redist0_capacity, redist0_count; 442 int i; 443 444 gictype = gicv3_class_name(); 445 446 sms->gic = qdev_new(gictype); 447 qdev_prop_set_uint32(sms->gic, "revision", 3); 448 qdev_prop_set_uint32(sms->gic, "num-cpu", smp_cpus); 449 /* 450 * Note that the num-irq property counts both internal and external 451 * interrupts; there are always 32 of the former (mandated by GIC spec). 452 */ 453 qdev_prop_set_uint32(sms->gic, "num-irq", NUM_IRQS + 32); 454 qdev_prop_set_bit(sms->gic, "has-security-extensions", true); 455 456 redist0_capacity = 457 sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE; 458 redist0_count = MIN(smp_cpus, redist0_capacity); 459 460 qdev_prop_set_uint32(sms->gic, "len-redist-region-count", 1); 461 qdev_prop_set_uint32(sms->gic, "redist-region-count[0]", redist0_count); 462 463 object_property_set_link(OBJECT(sms->gic), "sysmem", 464 OBJECT(mem), &error_fatal); 465 qdev_prop_set_bit(sms->gic, "has-lpi", true); 466 467 gicbusdev = SYS_BUS_DEVICE(sms->gic); 468 sysbus_realize_and_unref(gicbusdev, &error_fatal); 469 sysbus_mmio_map(gicbusdev, 0, sbsa_ref_memmap[SBSA_GIC_DIST].base); 470 sysbus_mmio_map(gicbusdev, 1, sbsa_ref_memmap[SBSA_GIC_REDIST].base); 471 472 /* 473 * Wire the outputs from each CPU's generic timer and the GICv3 474 * maintenance interrupt signal to the appropriate GIC PPI inputs, 475 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. 476 */ 477 for (i = 0; i < smp_cpus; i++) { 478 DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); 479 int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; 480 int irq; 481 /* 482 * Mapping from the output timer irq lines from the CPU to the 483 * GIC PPI inputs used for this board. 484 */ 485 const int timer_irq[] = { 486 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 487 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 488 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 489 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 490 }; 491 492 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 493 qdev_connect_gpio_out(cpudev, irq, 494 qdev_get_gpio_in(sms->gic, 495 ppibase + timer_irq[irq])); 496 } 497 498 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0, 499 qdev_get_gpio_in(sms->gic, ppibase 500 + ARCH_GIC_MAINT_IRQ)); 501 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 502 qdev_get_gpio_in(sms->gic, ppibase 503 + VIRTUAL_PMU_IRQ)); 504 505 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 506 sysbus_connect_irq(gicbusdev, i + smp_cpus, 507 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 508 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, 509 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 510 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, 511 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 512 } 513 create_its(sms); 514 } 515 516 static void create_uart(const SBSAMachineState *sms, int uart, 517 MemoryRegion *mem, Chardev *chr) 518 { 519 hwaddr base = sbsa_ref_memmap[uart].base; 520 int irq = sbsa_ref_irqmap[uart]; 521 DeviceState *dev = qdev_new(TYPE_PL011); 522 SysBusDevice *s = SYS_BUS_DEVICE(dev); 523 524 qdev_prop_set_chr(dev, "chardev", chr); 525 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 526 memory_region_add_subregion(mem, base, 527 sysbus_mmio_get_region(s, 0)); 528 sysbus_connect_irq(s, 0, qdev_get_gpio_in(sms->gic, irq)); 529 } 530 531 static void create_rtc(const SBSAMachineState *sms) 532 { 533 hwaddr base = sbsa_ref_memmap[SBSA_RTC].base; 534 int irq = sbsa_ref_irqmap[SBSA_RTC]; 535 536 sysbus_create_simple("pl031", base, qdev_get_gpio_in(sms->gic, irq)); 537 } 538 539 static void create_wdt(const SBSAMachineState *sms) 540 { 541 hwaddr rbase = sbsa_ref_memmap[SBSA_GWDT_REFRESH].base; 542 hwaddr cbase = sbsa_ref_memmap[SBSA_GWDT_CONTROL].base; 543 DeviceState *dev = qdev_new(TYPE_WDT_SBSA); 544 SysBusDevice *s = SYS_BUS_DEVICE(dev); 545 int irq = sbsa_ref_irqmap[SBSA_GWDT_WS0]; 546 547 sysbus_realize_and_unref(s, &error_fatal); 548 sysbus_mmio_map(s, 0, rbase); 549 sysbus_mmio_map(s, 1, cbase); 550 sysbus_connect_irq(s, 0, qdev_get_gpio_in(sms->gic, irq)); 551 } 552 553 static DeviceState *gpio_key_dev; 554 static void sbsa_ref_powerdown_req(Notifier *n, void *opaque) 555 { 556 /* use gpio Pin 3 for power button event */ 557 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); 558 } 559 560 static Notifier sbsa_ref_powerdown_notifier = { 561 .notify = sbsa_ref_powerdown_req 562 }; 563 564 static void create_gpio(const SBSAMachineState *sms) 565 { 566 DeviceState *pl061_dev; 567 hwaddr base = sbsa_ref_memmap[SBSA_GPIO].base; 568 int irq = sbsa_ref_irqmap[SBSA_GPIO]; 569 570 pl061_dev = sysbus_create_simple("pl061", base, 571 qdev_get_gpio_in(sms->gic, irq)); 572 573 gpio_key_dev = sysbus_create_simple("gpio-key", -1, 574 qdev_get_gpio_in(pl061_dev, 3)); 575 576 /* connect powerdown request */ 577 qemu_register_powerdown_notifier(&sbsa_ref_powerdown_notifier); 578 } 579 580 static void create_ahci(const SBSAMachineState *sms) 581 { 582 hwaddr base = sbsa_ref_memmap[SBSA_AHCI].base; 583 int irq = sbsa_ref_irqmap[SBSA_AHCI]; 584 DeviceState *dev; 585 DriveInfo *hd[NUM_SATA_PORTS]; 586 SysbusAHCIState *sysahci; 587 AHCIState *ahci; 588 int i; 589 590 dev = qdev_new("sysbus-ahci"); 591 qdev_prop_set_uint32(dev, "num-ports", NUM_SATA_PORTS); 592 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 593 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 594 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(sms->gic, irq)); 595 596 sysahci = SYSBUS_AHCI(dev); 597 ahci = &sysahci->ahci; 598 ide_drive_get(hd, ARRAY_SIZE(hd)); 599 for (i = 0; i < ahci->ports; i++) { 600 if (hd[i] == NULL) { 601 continue; 602 } 603 ide_bus_create_drive(&ahci->dev[i].port, 0, hd[i]); 604 } 605 } 606 607 static void create_ehci(const SBSAMachineState *sms) 608 { 609 hwaddr base = sbsa_ref_memmap[SBSA_EHCI].base; 610 int irq = sbsa_ref_irqmap[SBSA_EHCI]; 611 612 sysbus_create_simple("platform-ehci-usb", base, 613 qdev_get_gpio_in(sms->gic, irq)); 614 } 615 616 static void create_smmu(const SBSAMachineState *sms, PCIBus *bus) 617 { 618 hwaddr base = sbsa_ref_memmap[SBSA_SMMU].base; 619 int irq = sbsa_ref_irqmap[SBSA_SMMU]; 620 DeviceState *dev; 621 int i; 622 623 dev = qdev_new(TYPE_ARM_SMMUV3); 624 625 object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus), 626 &error_abort); 627 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 628 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 629 for (i = 0; i < NUM_SMMU_IRQS; i++) { 630 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 631 qdev_get_gpio_in(sms->gic, irq + i)); 632 } 633 } 634 635 static void create_pcie(SBSAMachineState *sms) 636 { 637 hwaddr base_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].base; 638 hwaddr size_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].size; 639 hwaddr base_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].base; 640 hwaddr size_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].size; 641 hwaddr base_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].base; 642 hwaddr size_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].size; 643 hwaddr base_pio = sbsa_ref_memmap[SBSA_PCIE_PIO].base; 644 int irq = sbsa_ref_irqmap[SBSA_PCIE]; 645 MachineClass *mc = MACHINE_GET_CLASS(sms); 646 MemoryRegion *mmio_alias, *mmio_alias_high, *mmio_reg; 647 MemoryRegion *ecam_alias, *ecam_reg; 648 DeviceState *dev; 649 PCIHostState *pci; 650 int i; 651 652 dev = qdev_new(TYPE_GPEX_HOST); 653 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 654 655 /* Map ECAM space */ 656 ecam_alias = g_new0(MemoryRegion, 1); 657 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 658 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 659 ecam_reg, 0, size_ecam); 660 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); 661 662 /* Map the MMIO space */ 663 mmio_alias = g_new0(MemoryRegion, 1); 664 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 665 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 666 mmio_reg, base_mmio, size_mmio); 667 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); 668 669 /* Map the MMIO_HIGH space */ 670 mmio_alias_high = g_new0(MemoryRegion, 1); 671 memory_region_init_alias(mmio_alias_high, OBJECT(dev), "pcie-mmio-high", 672 mmio_reg, base_mmio_high, size_mmio_high); 673 memory_region_add_subregion(get_system_memory(), base_mmio_high, 674 mmio_alias_high); 675 676 /* Map IO port space */ 677 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); 678 679 for (i = 0; i < GPEX_NUM_IRQS; i++) { 680 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 681 qdev_get_gpio_in(sms->gic, irq + i)); 682 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); 683 } 684 685 pci = PCI_HOST_BRIDGE(dev); 686 if (pci->bus) { 687 for (i = 0; i < nb_nics; i++) { 688 NICInfo *nd = &nd_table[i]; 689 690 if (!nd->model) { 691 nd->model = g_strdup(mc->default_nic); 692 } 693 694 pci_nic_init_nofail(nd, pci->bus, nd->model, NULL); 695 } 696 } 697 698 pci_create_simple(pci->bus, -1, "bochs-display"); 699 700 create_smmu(sms, pci->bus); 701 } 702 703 static void *sbsa_ref_dtb(const struct arm_boot_info *binfo, int *fdt_size) 704 { 705 const SBSAMachineState *board = container_of(binfo, SBSAMachineState, 706 bootinfo); 707 708 *fdt_size = board->fdt_size; 709 return board->fdt; 710 } 711 712 static void create_secure_ec(MemoryRegion *mem) 713 { 714 hwaddr base = sbsa_ref_memmap[SBSA_SECURE_EC].base; 715 DeviceState *dev = qdev_new("sbsa-ec"); 716 SysBusDevice *s = SYS_BUS_DEVICE(dev); 717 718 memory_region_add_subregion(mem, base, 719 sysbus_mmio_get_region(s, 0)); 720 } 721 722 static void sbsa_ref_init(MachineState *machine) 723 { 724 unsigned int smp_cpus = machine->smp.cpus; 725 unsigned int max_cpus = machine->smp.max_cpus; 726 SBSAMachineState *sms = SBSA_MACHINE(machine); 727 MachineClass *mc = MACHINE_GET_CLASS(machine); 728 MemoryRegion *sysmem = get_system_memory(); 729 MemoryRegion *secure_sysmem = g_new(MemoryRegion, 1); 730 bool firmware_loaded; 731 const CPUArchIdList *possible_cpus; 732 int n, sbsa_max_cpus; 733 734 if (!cpu_type_valid(machine->cpu_type)) { 735 error_report("sbsa-ref: CPU type %s not supported", machine->cpu_type); 736 exit(1); 737 } 738 739 if (kvm_enabled()) { 740 error_report("sbsa-ref: KVM is not supported for this machine"); 741 exit(1); 742 } 743 744 /* 745 * The Secure view of the world is the same as the NonSecure, 746 * but with a few extra devices. Create it as a container region 747 * containing the system memory at low priority; any secure-only 748 * devices go in at higher priority and take precedence. 749 */ 750 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", 751 UINT64_MAX); 752 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); 753 754 firmware_loaded = sbsa_firmware_init(sms, sysmem, secure_sysmem); 755 756 /* 757 * This machine has EL3 enabled, external firmware should supply PSCI 758 * implementation, so the QEMU's internal PSCI is disabled. 759 */ 760 sms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; 761 762 sbsa_max_cpus = sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE; 763 764 if (max_cpus > sbsa_max_cpus) { 765 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " 766 "supported by machine 'sbsa-ref' (%d)", 767 max_cpus, sbsa_max_cpus); 768 exit(1); 769 } 770 771 sms->smp_cpus = smp_cpus; 772 773 if (machine->ram_size > sbsa_ref_memmap[SBSA_MEM].size) { 774 error_report("sbsa-ref: cannot model more than %dGB RAM", RAMLIMIT_GB); 775 exit(1); 776 } 777 778 possible_cpus = mc->possible_cpu_arch_ids(machine); 779 for (n = 0; n < possible_cpus->len; n++) { 780 Object *cpuobj; 781 CPUState *cs; 782 783 if (n >= smp_cpus) { 784 break; 785 } 786 787 cpuobj = object_new(possible_cpus->cpus[n].type); 788 object_property_set_int(cpuobj, "mp-affinity", 789 possible_cpus->cpus[n].arch_id, NULL); 790 791 cs = CPU(cpuobj); 792 cs->cpu_index = n; 793 794 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj), 795 &error_fatal); 796 797 if (object_property_find(cpuobj, "reset-cbar")) { 798 object_property_set_int(cpuobj, "reset-cbar", 799 sbsa_ref_memmap[SBSA_CPUPERIPHS].base, 800 &error_abort); 801 } 802 803 object_property_set_link(cpuobj, "memory", OBJECT(sysmem), 804 &error_abort); 805 806 object_property_set_link(cpuobj, "secure-memory", 807 OBJECT(secure_sysmem), &error_abort); 808 809 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); 810 object_unref(cpuobj); 811 } 812 813 memory_region_add_subregion(sysmem, sbsa_ref_memmap[SBSA_MEM].base, 814 machine->ram); 815 816 create_fdt(sms); 817 818 create_secure_ram(sms, secure_sysmem); 819 820 create_gic(sms, sysmem); 821 822 create_uart(sms, SBSA_UART, sysmem, serial_hd(0)); 823 create_uart(sms, SBSA_SECURE_UART, secure_sysmem, serial_hd(1)); 824 /* Second secure UART for RAS and MM from EL0 */ 825 create_uart(sms, SBSA_SECURE_UART_MM, secure_sysmem, serial_hd(2)); 826 827 create_rtc(sms); 828 829 create_wdt(sms); 830 831 create_gpio(sms); 832 833 create_ahci(sms); 834 835 create_ehci(sms); 836 837 create_pcie(sms); 838 839 create_secure_ec(secure_sysmem); 840 841 sms->bootinfo.ram_size = machine->ram_size; 842 sms->bootinfo.board_id = -1; 843 sms->bootinfo.loader_start = sbsa_ref_memmap[SBSA_MEM].base; 844 sms->bootinfo.get_dtb = sbsa_ref_dtb; 845 sms->bootinfo.firmware_loaded = firmware_loaded; 846 arm_load_kernel(ARM_CPU(first_cpu), machine, &sms->bootinfo); 847 } 848 849 static const CPUArchIdList *sbsa_ref_possible_cpu_arch_ids(MachineState *ms) 850 { 851 unsigned int max_cpus = ms->smp.max_cpus; 852 SBSAMachineState *sms = SBSA_MACHINE(ms); 853 int n; 854 855 if (ms->possible_cpus) { 856 assert(ms->possible_cpus->len == max_cpus); 857 return ms->possible_cpus; 858 } 859 860 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 861 sizeof(CPUArchId) * max_cpus); 862 ms->possible_cpus->len = max_cpus; 863 for (n = 0; n < ms->possible_cpus->len; n++) { 864 ms->possible_cpus->cpus[n].type = ms->cpu_type; 865 ms->possible_cpus->cpus[n].arch_id = 866 sbsa_ref_cpu_mp_affinity(sms, n); 867 ms->possible_cpus->cpus[n].props.has_thread_id = true; 868 ms->possible_cpus->cpus[n].props.thread_id = n; 869 } 870 return ms->possible_cpus; 871 } 872 873 static CpuInstanceProperties 874 sbsa_ref_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 875 { 876 MachineClass *mc = MACHINE_GET_CLASS(ms); 877 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 878 879 assert(cpu_index < possible_cpus->len); 880 return possible_cpus->cpus[cpu_index].props; 881 } 882 883 static int64_t 884 sbsa_ref_get_default_cpu_node_id(const MachineState *ms, int idx) 885 { 886 return idx % ms->numa_state->num_nodes; 887 } 888 889 static void sbsa_ref_instance_init(Object *obj) 890 { 891 SBSAMachineState *sms = SBSA_MACHINE(obj); 892 893 sbsa_flash_create(sms); 894 } 895 896 static void sbsa_ref_class_init(ObjectClass *oc, void *data) 897 { 898 MachineClass *mc = MACHINE_CLASS(oc); 899 900 mc->init = sbsa_ref_init; 901 mc->desc = "QEMU 'SBSA Reference' ARM Virtual Machine"; 902 mc->default_cpu_type = ARM_CPU_TYPE_NAME("neoverse-n1"); 903 mc->max_cpus = 512; 904 mc->pci_allow_0_address = true; 905 mc->minimum_page_bits = 12; 906 mc->block_default_type = IF_IDE; 907 mc->no_cdrom = 1; 908 mc->default_nic = "e1000e"; 909 mc->default_ram_size = 1 * GiB; 910 mc->default_ram_id = "sbsa-ref.ram"; 911 mc->default_cpus = 4; 912 mc->possible_cpu_arch_ids = sbsa_ref_possible_cpu_arch_ids; 913 mc->cpu_index_to_instance_props = sbsa_ref_cpu_index_to_props; 914 mc->get_default_cpu_node_id = sbsa_ref_get_default_cpu_node_id; 915 /* platform instead of architectural choice */ 916 mc->cpu_cluster_has_numa_boundary = true; 917 } 918 919 static const TypeInfo sbsa_ref_info = { 920 .name = TYPE_SBSA_MACHINE, 921 .parent = TYPE_MACHINE, 922 .instance_init = sbsa_ref_instance_init, 923 .class_init = sbsa_ref_class_init, 924 .instance_size = sizeof(SBSAMachineState), 925 }; 926 927 static void sbsa_ref_machine_init(void) 928 { 929 type_register_static(&sbsa_ref_info); 930 } 931 932 type_init(sbsa_ref_machine_init); 933