1 /* 2 * ARM SBSA Reference Platform emulation 3 * 4 * Copyright (c) 2018 Linaro Limited 5 * Written by Hongbo Zhang <hongbo.zhang@linaro.org> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu-common.h" 22 #include "qapi/error.h" 23 #include "qemu/error-report.h" 24 #include "qemu/units.h" 25 #include "sysemu/device_tree.h" 26 #include "sysemu/numa.h" 27 #include "sysemu/runstate.h" 28 #include "sysemu/sysemu.h" 29 #include "exec/address-spaces.h" 30 #include "exec/hwaddr.h" 31 #include "kvm_arm.h" 32 #include "hw/arm/boot.h" 33 #include "hw/block/flash.h" 34 #include "hw/boards.h" 35 #include "hw/ide/internal.h" 36 #include "hw/ide/ahci_internal.h" 37 #include "hw/intc/arm_gicv3_common.h" 38 #include "hw/loader.h" 39 #include "hw/pci-host/gpex.h" 40 #include "hw/qdev-properties.h" 41 #include "hw/usb.h" 42 #include "hw/char/pl011.h" 43 #include "net/net.h" 44 #include "qom/object.h" 45 46 #define RAMLIMIT_GB 8192 47 #define RAMLIMIT_BYTES (RAMLIMIT_GB * GiB) 48 49 #define NUM_IRQS 256 50 #define NUM_SMMU_IRQS 4 51 #define NUM_SATA_PORTS 6 52 53 #define VIRTUAL_PMU_IRQ 7 54 #define ARCH_GIC_MAINT_IRQ 9 55 #define ARCH_TIMER_VIRT_IRQ 11 56 #define ARCH_TIMER_S_EL1_IRQ 13 57 #define ARCH_TIMER_NS_EL1_IRQ 14 58 #define ARCH_TIMER_NS_EL2_IRQ 10 59 60 enum { 61 SBSA_FLASH, 62 SBSA_MEM, 63 SBSA_CPUPERIPHS, 64 SBSA_GIC_DIST, 65 SBSA_GIC_REDIST, 66 SBSA_SECURE_EC, 67 SBSA_SMMU, 68 SBSA_UART, 69 SBSA_RTC, 70 SBSA_PCIE, 71 SBSA_PCIE_MMIO, 72 SBSA_PCIE_MMIO_HIGH, 73 SBSA_PCIE_PIO, 74 SBSA_PCIE_ECAM, 75 SBSA_GPIO, 76 SBSA_SECURE_UART, 77 SBSA_SECURE_UART_MM, 78 SBSA_SECURE_MEM, 79 SBSA_AHCI, 80 SBSA_EHCI, 81 }; 82 83 typedef struct MemMapEntry { 84 hwaddr base; 85 hwaddr size; 86 } MemMapEntry; 87 88 struct SBSAMachineState { 89 MachineState parent; 90 struct arm_boot_info bootinfo; 91 int smp_cpus; 92 void *fdt; 93 int fdt_size; 94 int psci_conduit; 95 DeviceState *gic; 96 PFlashCFI01 *flash[2]; 97 }; 98 typedef struct SBSAMachineState SBSAMachineState; 99 100 #define TYPE_SBSA_MACHINE MACHINE_TYPE_NAME("sbsa-ref") 101 DECLARE_INSTANCE_CHECKER(SBSAMachineState, SBSA_MACHINE, 102 TYPE_SBSA_MACHINE) 103 104 static const MemMapEntry sbsa_ref_memmap[] = { 105 /* 512M boot ROM */ 106 [SBSA_FLASH] = { 0, 0x20000000 }, 107 /* 512M secure memory */ 108 [SBSA_SECURE_MEM] = { 0x20000000, 0x20000000 }, 109 /* Space reserved for CPU peripheral devices */ 110 [SBSA_CPUPERIPHS] = { 0x40000000, 0x00040000 }, 111 [SBSA_GIC_DIST] = { 0x40060000, 0x00010000 }, 112 [SBSA_GIC_REDIST] = { 0x40080000, 0x04000000 }, 113 [SBSA_SECURE_EC] = { 0x50000000, 0x00001000 }, 114 [SBSA_UART] = { 0x60000000, 0x00001000 }, 115 [SBSA_RTC] = { 0x60010000, 0x00001000 }, 116 [SBSA_GPIO] = { 0x60020000, 0x00001000 }, 117 [SBSA_SECURE_UART] = { 0x60030000, 0x00001000 }, 118 [SBSA_SECURE_UART_MM] = { 0x60040000, 0x00001000 }, 119 [SBSA_SMMU] = { 0x60050000, 0x00020000 }, 120 /* Space here reserved for more SMMUs */ 121 [SBSA_AHCI] = { 0x60100000, 0x00010000 }, 122 [SBSA_EHCI] = { 0x60110000, 0x00010000 }, 123 /* Space here reserved for other devices */ 124 [SBSA_PCIE_PIO] = { 0x7fff0000, 0x00010000 }, 125 /* 32-bit address PCIE MMIO space */ 126 [SBSA_PCIE_MMIO] = { 0x80000000, 0x70000000 }, 127 /* 256M PCIE ECAM space */ 128 [SBSA_PCIE_ECAM] = { 0xf0000000, 0x10000000 }, 129 /* ~1TB PCIE MMIO space (4GB to 1024GB boundary) */ 130 [SBSA_PCIE_MMIO_HIGH] = { 0x100000000ULL, 0xFF00000000ULL }, 131 [SBSA_MEM] = { 0x10000000000ULL, RAMLIMIT_BYTES }, 132 }; 133 134 static const int sbsa_ref_irqmap[] = { 135 [SBSA_UART] = 1, 136 [SBSA_RTC] = 2, 137 [SBSA_PCIE] = 3, /* ... to 6 */ 138 [SBSA_GPIO] = 7, 139 [SBSA_SECURE_UART] = 8, 140 [SBSA_SECURE_UART_MM] = 9, 141 [SBSA_AHCI] = 10, 142 [SBSA_EHCI] = 11, 143 }; 144 145 static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx) 146 { 147 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER; 148 return arm_cpu_mp_affinity(idx, clustersz); 149 } 150 151 /* 152 * Firmware on this machine only uses ACPI table to load OS, these limited 153 * device tree nodes are just to let firmware know the info which varies from 154 * command line parameters, so it is not necessary to be fully compatible 155 * with the kernel CPU and NUMA binding rules. 156 */ 157 static void create_fdt(SBSAMachineState *sms) 158 { 159 void *fdt = create_device_tree(&sms->fdt_size); 160 const MachineState *ms = MACHINE(sms); 161 int nb_numa_nodes = ms->numa_state->num_nodes; 162 int cpu; 163 164 if (!fdt) { 165 error_report("create_device_tree() failed"); 166 exit(1); 167 } 168 169 sms->fdt = fdt; 170 171 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,sbsa-ref"); 172 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 173 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 174 175 if (ms->numa_state->have_numa_distance) { 176 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); 177 uint32_t *matrix = g_malloc0(size); 178 int idx, i, j; 179 180 for (i = 0; i < nb_numa_nodes; i++) { 181 for (j = 0; j < nb_numa_nodes; j++) { 182 idx = (i * nb_numa_nodes + j) * 3; 183 matrix[idx + 0] = cpu_to_be32(i); 184 matrix[idx + 1] = cpu_to_be32(j); 185 matrix[idx + 2] = 186 cpu_to_be32(ms->numa_state->nodes[i].distance[j]); 187 } 188 } 189 190 qemu_fdt_add_subnode(fdt, "/distance-map"); 191 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", 192 matrix, size); 193 g_free(matrix); 194 } 195 196 /* 197 * From Documentation/devicetree/bindings/arm/cpus.yaml 198 * On ARM v8 64-bit systems this property is required 199 * and matches the MPIDR_EL1 register affinity bits. 200 * 201 * * If cpus node's #address-cells property is set to 2 202 * 203 * The first reg cell bits [7:0] must be set to 204 * bits [39:32] of MPIDR_EL1. 205 * 206 * The second reg cell bits [23:0] must be set to 207 * bits [23:0] of MPIDR_EL1. 208 */ 209 qemu_fdt_add_subnode(sms->fdt, "/cpus"); 210 qemu_fdt_setprop_cell(sms->fdt, "/cpus", "#address-cells", 2); 211 qemu_fdt_setprop_cell(sms->fdt, "/cpus", "#size-cells", 0x0); 212 213 for (cpu = sms->smp_cpus - 1; cpu >= 0; cpu--) { 214 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 215 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 216 CPUState *cs = CPU(armcpu); 217 uint64_t mpidr = sbsa_ref_cpu_mp_affinity(sms, cpu); 218 219 qemu_fdt_add_subnode(sms->fdt, nodename); 220 qemu_fdt_setprop_u64(sms->fdt, nodename, "reg", mpidr); 221 222 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 223 qemu_fdt_setprop_cell(sms->fdt, nodename, "numa-node-id", 224 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 225 } 226 227 g_free(nodename); 228 } 229 } 230 231 #define SBSA_FLASH_SECTOR_SIZE (256 * KiB) 232 233 static PFlashCFI01 *sbsa_flash_create1(SBSAMachineState *sms, 234 const char *name, 235 const char *alias_prop_name) 236 { 237 /* 238 * Create a single flash device. We use the same parameters as 239 * the flash devices on the Versatile Express board. 240 */ 241 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 242 243 qdev_prop_set_uint64(dev, "sector-length", SBSA_FLASH_SECTOR_SIZE); 244 qdev_prop_set_uint8(dev, "width", 4); 245 qdev_prop_set_uint8(dev, "device-width", 2); 246 qdev_prop_set_bit(dev, "big-endian", false); 247 qdev_prop_set_uint16(dev, "id0", 0x89); 248 qdev_prop_set_uint16(dev, "id1", 0x18); 249 qdev_prop_set_uint16(dev, "id2", 0x00); 250 qdev_prop_set_uint16(dev, "id3", 0x00); 251 qdev_prop_set_string(dev, "name", name); 252 object_property_add_child(OBJECT(sms), name, OBJECT(dev)); 253 object_property_add_alias(OBJECT(sms), alias_prop_name, 254 OBJECT(dev), "drive"); 255 return PFLASH_CFI01(dev); 256 } 257 258 static void sbsa_flash_create(SBSAMachineState *sms) 259 { 260 sms->flash[0] = sbsa_flash_create1(sms, "sbsa.flash0", "pflash0"); 261 sms->flash[1] = sbsa_flash_create1(sms, "sbsa.flash1", "pflash1"); 262 } 263 264 static void sbsa_flash_map1(PFlashCFI01 *flash, 265 hwaddr base, hwaddr size, 266 MemoryRegion *sysmem) 267 { 268 DeviceState *dev = DEVICE(flash); 269 270 assert(QEMU_IS_ALIGNED(size, SBSA_FLASH_SECTOR_SIZE)); 271 assert(size / SBSA_FLASH_SECTOR_SIZE <= UINT32_MAX); 272 qdev_prop_set_uint32(dev, "num-blocks", size / SBSA_FLASH_SECTOR_SIZE); 273 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 274 275 memory_region_add_subregion(sysmem, base, 276 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 277 0)); 278 } 279 280 static void sbsa_flash_map(SBSAMachineState *sms, 281 MemoryRegion *sysmem, 282 MemoryRegion *secure_sysmem) 283 { 284 /* 285 * Map two flash devices to fill the SBSA_FLASH space in the memmap. 286 * sysmem is the system memory space. secure_sysmem is the secure view 287 * of the system, and the first flash device should be made visible only 288 * there. The second flash device is visible to both secure and nonsecure. 289 */ 290 hwaddr flashsize = sbsa_ref_memmap[SBSA_FLASH].size / 2; 291 hwaddr flashbase = sbsa_ref_memmap[SBSA_FLASH].base; 292 293 sbsa_flash_map1(sms->flash[0], flashbase, flashsize, 294 secure_sysmem); 295 sbsa_flash_map1(sms->flash[1], flashbase + flashsize, flashsize, 296 sysmem); 297 } 298 299 static bool sbsa_firmware_init(SBSAMachineState *sms, 300 MemoryRegion *sysmem, 301 MemoryRegion *secure_sysmem) 302 { 303 int i; 304 BlockBackend *pflash_blk0; 305 306 /* Map legacy -drive if=pflash to machine properties */ 307 for (i = 0; i < ARRAY_SIZE(sms->flash); i++) { 308 pflash_cfi01_legacy_drive(sms->flash[i], 309 drive_get(IF_PFLASH, 0, i)); 310 } 311 312 sbsa_flash_map(sms, sysmem, secure_sysmem); 313 314 pflash_blk0 = pflash_cfi01_get_blk(sms->flash[0]); 315 316 if (bios_name) { 317 char *fname; 318 MemoryRegion *mr; 319 int image_size; 320 321 if (pflash_blk0) { 322 error_report("The contents of the first flash device may be " 323 "specified with -bios or with -drive if=pflash... " 324 "but you cannot use both options at once"); 325 exit(1); 326 } 327 328 /* Fall back to -bios */ 329 330 fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 331 if (!fname) { 332 error_report("Could not find ROM image '%s'", bios_name); 333 exit(1); 334 } 335 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(sms->flash[0]), 0); 336 image_size = load_image_mr(fname, mr); 337 g_free(fname); 338 if (image_size < 0) { 339 error_report("Could not load ROM image '%s'", bios_name); 340 exit(1); 341 } 342 } 343 344 return pflash_blk0 || bios_name; 345 } 346 347 static void create_secure_ram(SBSAMachineState *sms, 348 MemoryRegion *secure_sysmem) 349 { 350 MemoryRegion *secram = g_new(MemoryRegion, 1); 351 hwaddr base = sbsa_ref_memmap[SBSA_SECURE_MEM].base; 352 hwaddr size = sbsa_ref_memmap[SBSA_SECURE_MEM].size; 353 354 memory_region_init_ram(secram, NULL, "sbsa-ref.secure-ram", size, 355 &error_fatal); 356 memory_region_add_subregion(secure_sysmem, base, secram); 357 } 358 359 static void create_gic(SBSAMachineState *sms) 360 { 361 unsigned int smp_cpus = MACHINE(sms)->smp.cpus; 362 SysBusDevice *gicbusdev; 363 const char *gictype; 364 uint32_t redist0_capacity, redist0_count; 365 int i; 366 367 gictype = gicv3_class_name(); 368 369 sms->gic = qdev_new(gictype); 370 qdev_prop_set_uint32(sms->gic, "revision", 3); 371 qdev_prop_set_uint32(sms->gic, "num-cpu", smp_cpus); 372 /* 373 * Note that the num-irq property counts both internal and external 374 * interrupts; there are always 32 of the former (mandated by GIC spec). 375 */ 376 qdev_prop_set_uint32(sms->gic, "num-irq", NUM_IRQS + 32); 377 qdev_prop_set_bit(sms->gic, "has-security-extensions", true); 378 379 redist0_capacity = 380 sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE; 381 redist0_count = MIN(smp_cpus, redist0_capacity); 382 383 qdev_prop_set_uint32(sms->gic, "len-redist-region-count", 1); 384 qdev_prop_set_uint32(sms->gic, "redist-region-count[0]", redist0_count); 385 386 gicbusdev = SYS_BUS_DEVICE(sms->gic); 387 sysbus_realize_and_unref(gicbusdev, &error_fatal); 388 sysbus_mmio_map(gicbusdev, 0, sbsa_ref_memmap[SBSA_GIC_DIST].base); 389 sysbus_mmio_map(gicbusdev, 1, sbsa_ref_memmap[SBSA_GIC_REDIST].base); 390 391 /* 392 * Wire the outputs from each CPU's generic timer and the GICv3 393 * maintenance interrupt signal to the appropriate GIC PPI inputs, 394 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. 395 */ 396 for (i = 0; i < smp_cpus; i++) { 397 DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); 398 int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; 399 int irq; 400 /* 401 * Mapping from the output timer irq lines from the CPU to the 402 * GIC PPI inputs used for this board. 403 */ 404 const int timer_irq[] = { 405 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 406 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 407 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 408 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 409 }; 410 411 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 412 qdev_connect_gpio_out(cpudev, irq, 413 qdev_get_gpio_in(sms->gic, 414 ppibase + timer_irq[irq])); 415 } 416 417 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0, 418 qdev_get_gpio_in(sms->gic, ppibase 419 + ARCH_GIC_MAINT_IRQ)); 420 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 421 qdev_get_gpio_in(sms->gic, ppibase 422 + VIRTUAL_PMU_IRQ)); 423 424 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 425 sysbus_connect_irq(gicbusdev, i + smp_cpus, 426 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 427 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, 428 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 429 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, 430 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 431 } 432 } 433 434 static void create_uart(const SBSAMachineState *sms, int uart, 435 MemoryRegion *mem, Chardev *chr) 436 { 437 hwaddr base = sbsa_ref_memmap[uart].base; 438 int irq = sbsa_ref_irqmap[uart]; 439 DeviceState *dev = qdev_new(TYPE_PL011); 440 SysBusDevice *s = SYS_BUS_DEVICE(dev); 441 442 qdev_prop_set_chr(dev, "chardev", chr); 443 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 444 memory_region_add_subregion(mem, base, 445 sysbus_mmio_get_region(s, 0)); 446 sysbus_connect_irq(s, 0, qdev_get_gpio_in(sms->gic, irq)); 447 } 448 449 static void create_rtc(const SBSAMachineState *sms) 450 { 451 hwaddr base = sbsa_ref_memmap[SBSA_RTC].base; 452 int irq = sbsa_ref_irqmap[SBSA_RTC]; 453 454 sysbus_create_simple("pl031", base, qdev_get_gpio_in(sms->gic, irq)); 455 } 456 457 static DeviceState *gpio_key_dev; 458 static void sbsa_ref_powerdown_req(Notifier *n, void *opaque) 459 { 460 /* use gpio Pin 3 for power button event */ 461 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); 462 } 463 464 static Notifier sbsa_ref_powerdown_notifier = { 465 .notify = sbsa_ref_powerdown_req 466 }; 467 468 static void create_gpio(const SBSAMachineState *sms) 469 { 470 DeviceState *pl061_dev; 471 hwaddr base = sbsa_ref_memmap[SBSA_GPIO].base; 472 int irq = sbsa_ref_irqmap[SBSA_GPIO]; 473 474 pl061_dev = sysbus_create_simple("pl061", base, 475 qdev_get_gpio_in(sms->gic, irq)); 476 477 gpio_key_dev = sysbus_create_simple("gpio-key", -1, 478 qdev_get_gpio_in(pl061_dev, 3)); 479 480 /* connect powerdown request */ 481 qemu_register_powerdown_notifier(&sbsa_ref_powerdown_notifier); 482 } 483 484 static void create_ahci(const SBSAMachineState *sms) 485 { 486 hwaddr base = sbsa_ref_memmap[SBSA_AHCI].base; 487 int irq = sbsa_ref_irqmap[SBSA_AHCI]; 488 DeviceState *dev; 489 DriveInfo *hd[NUM_SATA_PORTS]; 490 SysbusAHCIState *sysahci; 491 AHCIState *ahci; 492 int i; 493 494 dev = qdev_new("sysbus-ahci"); 495 qdev_prop_set_uint32(dev, "num-ports", NUM_SATA_PORTS); 496 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 497 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 498 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(sms->gic, irq)); 499 500 sysahci = SYSBUS_AHCI(dev); 501 ahci = &sysahci->ahci; 502 ide_drive_get(hd, ARRAY_SIZE(hd)); 503 for (i = 0; i < ahci->ports; i++) { 504 if (hd[i] == NULL) { 505 continue; 506 } 507 ide_create_drive(&ahci->dev[i].port, 0, hd[i]); 508 } 509 } 510 511 static void create_ehci(const SBSAMachineState *sms) 512 { 513 hwaddr base = sbsa_ref_memmap[SBSA_EHCI].base; 514 int irq = sbsa_ref_irqmap[SBSA_EHCI]; 515 516 sysbus_create_simple("platform-ehci-usb", base, 517 qdev_get_gpio_in(sms->gic, irq)); 518 } 519 520 static void create_smmu(const SBSAMachineState *sms, PCIBus *bus) 521 { 522 hwaddr base = sbsa_ref_memmap[SBSA_SMMU].base; 523 int irq = sbsa_ref_irqmap[SBSA_SMMU]; 524 DeviceState *dev; 525 int i; 526 527 dev = qdev_new("arm-smmuv3"); 528 529 object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus), 530 &error_abort); 531 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 532 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 533 for (i = 0; i < NUM_SMMU_IRQS; i++) { 534 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 535 qdev_get_gpio_in(sms->gic, irq + 1)); 536 } 537 } 538 539 static void create_pcie(SBSAMachineState *sms) 540 { 541 hwaddr base_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].base; 542 hwaddr size_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].size; 543 hwaddr base_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].base; 544 hwaddr size_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].size; 545 hwaddr base_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].base; 546 hwaddr size_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].size; 547 hwaddr base_pio = sbsa_ref_memmap[SBSA_PCIE_PIO].base; 548 int irq = sbsa_ref_irqmap[SBSA_PCIE]; 549 MemoryRegion *mmio_alias, *mmio_alias_high, *mmio_reg; 550 MemoryRegion *ecam_alias, *ecam_reg; 551 DeviceState *dev; 552 PCIHostState *pci; 553 int i; 554 555 dev = qdev_new(TYPE_GPEX_HOST); 556 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 557 558 /* Map ECAM space */ 559 ecam_alias = g_new0(MemoryRegion, 1); 560 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 561 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 562 ecam_reg, 0, size_ecam); 563 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); 564 565 /* Map the MMIO space */ 566 mmio_alias = g_new0(MemoryRegion, 1); 567 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 568 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 569 mmio_reg, base_mmio, size_mmio); 570 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); 571 572 /* Map the MMIO_HIGH space */ 573 mmio_alias_high = g_new0(MemoryRegion, 1); 574 memory_region_init_alias(mmio_alias_high, OBJECT(dev), "pcie-mmio-high", 575 mmio_reg, base_mmio_high, size_mmio_high); 576 memory_region_add_subregion(get_system_memory(), base_mmio_high, 577 mmio_alias_high); 578 579 /* Map IO port space */ 580 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); 581 582 for (i = 0; i < GPEX_NUM_IRQS; i++) { 583 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 584 qdev_get_gpio_in(sms->gic, irq + i)); 585 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); 586 } 587 588 pci = PCI_HOST_BRIDGE(dev); 589 if (pci->bus) { 590 for (i = 0; i < nb_nics; i++) { 591 NICInfo *nd = &nd_table[i]; 592 593 if (!nd->model) { 594 nd->model = g_strdup("e1000e"); 595 } 596 597 pci_nic_init_nofail(nd, pci->bus, nd->model, NULL); 598 } 599 } 600 601 pci_create_simple(pci->bus, -1, "VGA"); 602 603 create_smmu(sms, pci->bus); 604 } 605 606 static void *sbsa_ref_dtb(const struct arm_boot_info *binfo, int *fdt_size) 607 { 608 const SBSAMachineState *board = container_of(binfo, SBSAMachineState, 609 bootinfo); 610 611 *fdt_size = board->fdt_size; 612 return board->fdt; 613 } 614 615 static void create_secure_ec(MemoryRegion *mem) 616 { 617 hwaddr base = sbsa_ref_memmap[SBSA_SECURE_EC].base; 618 DeviceState *dev = qdev_new("sbsa-ec"); 619 SysBusDevice *s = SYS_BUS_DEVICE(dev); 620 621 memory_region_add_subregion(mem, base, 622 sysbus_mmio_get_region(s, 0)); 623 } 624 625 static void sbsa_ref_init(MachineState *machine) 626 { 627 unsigned int smp_cpus = machine->smp.cpus; 628 unsigned int max_cpus = machine->smp.max_cpus; 629 SBSAMachineState *sms = SBSA_MACHINE(machine); 630 MachineClass *mc = MACHINE_GET_CLASS(machine); 631 MemoryRegion *sysmem = get_system_memory(); 632 MemoryRegion *secure_sysmem = g_new(MemoryRegion, 1); 633 bool firmware_loaded; 634 const CPUArchIdList *possible_cpus; 635 int n, sbsa_max_cpus; 636 637 if (strcmp(machine->cpu_type, ARM_CPU_TYPE_NAME("cortex-a57"))) { 638 error_report("sbsa-ref: CPU type other than the built-in " 639 "cortex-a57 not supported"); 640 exit(1); 641 } 642 643 if (kvm_enabled()) { 644 error_report("sbsa-ref: KVM is not supported for this machine"); 645 exit(1); 646 } 647 648 /* 649 * The Secure view of the world is the same as the NonSecure, 650 * but with a few extra devices. Create it as a container region 651 * containing the system memory at low priority; any secure-only 652 * devices go in at higher priority and take precedence. 653 */ 654 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", 655 UINT64_MAX); 656 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); 657 658 firmware_loaded = sbsa_firmware_init(sms, sysmem, secure_sysmem); 659 660 if (machine->kernel_filename && firmware_loaded) { 661 error_report("sbsa-ref: No fw_cfg device on this machine, " 662 "so -kernel option is not supported when firmware loaded, " 663 "please load OS from hard disk instead"); 664 exit(1); 665 } 666 667 /* 668 * This machine has EL3 enabled, external firmware should supply PSCI 669 * implementation, so the QEMU's internal PSCI is disabled. 670 */ 671 sms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; 672 673 sbsa_max_cpus = sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE; 674 675 if (max_cpus > sbsa_max_cpus) { 676 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " 677 "supported by machine 'sbsa-ref' (%d)", 678 max_cpus, sbsa_max_cpus); 679 exit(1); 680 } 681 682 sms->smp_cpus = smp_cpus; 683 684 if (machine->ram_size > sbsa_ref_memmap[SBSA_MEM].size) { 685 error_report("sbsa-ref: cannot model more than %dGB RAM", RAMLIMIT_GB); 686 exit(1); 687 } 688 689 possible_cpus = mc->possible_cpu_arch_ids(machine); 690 for (n = 0; n < possible_cpus->len; n++) { 691 Object *cpuobj; 692 CPUState *cs; 693 694 if (n >= smp_cpus) { 695 break; 696 } 697 698 cpuobj = object_new(possible_cpus->cpus[n].type); 699 object_property_set_int(cpuobj, "mp-affinity", 700 possible_cpus->cpus[n].arch_id, NULL); 701 702 cs = CPU(cpuobj); 703 cs->cpu_index = n; 704 705 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj), 706 &error_fatal); 707 708 if (object_property_find(cpuobj, "reset-cbar", NULL)) { 709 object_property_set_int(cpuobj, "reset-cbar", 710 sbsa_ref_memmap[SBSA_CPUPERIPHS].base, 711 &error_abort); 712 } 713 714 object_property_set_link(cpuobj, "memory", OBJECT(sysmem), 715 &error_abort); 716 717 object_property_set_link(cpuobj, "secure-memory", 718 OBJECT(secure_sysmem), &error_abort); 719 720 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); 721 object_unref(cpuobj); 722 } 723 724 memory_region_add_subregion(sysmem, sbsa_ref_memmap[SBSA_MEM].base, 725 machine->ram); 726 727 create_fdt(sms); 728 729 create_secure_ram(sms, secure_sysmem); 730 731 create_gic(sms); 732 733 create_uart(sms, SBSA_UART, sysmem, serial_hd(0)); 734 create_uart(sms, SBSA_SECURE_UART, secure_sysmem, serial_hd(1)); 735 /* Second secure UART for RAS and MM from EL0 */ 736 create_uart(sms, SBSA_SECURE_UART_MM, secure_sysmem, serial_hd(2)); 737 738 create_rtc(sms); 739 740 create_gpio(sms); 741 742 create_ahci(sms); 743 744 create_ehci(sms); 745 746 create_pcie(sms); 747 748 create_secure_ec(secure_sysmem); 749 750 sms->bootinfo.ram_size = machine->ram_size; 751 sms->bootinfo.nb_cpus = smp_cpus; 752 sms->bootinfo.board_id = -1; 753 sms->bootinfo.loader_start = sbsa_ref_memmap[SBSA_MEM].base; 754 sms->bootinfo.get_dtb = sbsa_ref_dtb; 755 sms->bootinfo.firmware_loaded = firmware_loaded; 756 arm_load_kernel(ARM_CPU(first_cpu), machine, &sms->bootinfo); 757 } 758 759 static const CPUArchIdList *sbsa_ref_possible_cpu_arch_ids(MachineState *ms) 760 { 761 unsigned int max_cpus = ms->smp.max_cpus; 762 SBSAMachineState *sms = SBSA_MACHINE(ms); 763 int n; 764 765 if (ms->possible_cpus) { 766 assert(ms->possible_cpus->len == max_cpus); 767 return ms->possible_cpus; 768 } 769 770 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 771 sizeof(CPUArchId) * max_cpus); 772 ms->possible_cpus->len = max_cpus; 773 for (n = 0; n < ms->possible_cpus->len; n++) { 774 ms->possible_cpus->cpus[n].type = ms->cpu_type; 775 ms->possible_cpus->cpus[n].arch_id = 776 sbsa_ref_cpu_mp_affinity(sms, n); 777 ms->possible_cpus->cpus[n].props.has_thread_id = true; 778 ms->possible_cpus->cpus[n].props.thread_id = n; 779 } 780 return ms->possible_cpus; 781 } 782 783 static CpuInstanceProperties 784 sbsa_ref_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 785 { 786 MachineClass *mc = MACHINE_GET_CLASS(ms); 787 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 788 789 assert(cpu_index < possible_cpus->len); 790 return possible_cpus->cpus[cpu_index].props; 791 } 792 793 static int64_t 794 sbsa_ref_get_default_cpu_node_id(const MachineState *ms, int idx) 795 { 796 return idx % ms->numa_state->num_nodes; 797 } 798 799 static void sbsa_ref_instance_init(Object *obj) 800 { 801 SBSAMachineState *sms = SBSA_MACHINE(obj); 802 803 sbsa_flash_create(sms); 804 } 805 806 static void sbsa_ref_class_init(ObjectClass *oc, void *data) 807 { 808 MachineClass *mc = MACHINE_CLASS(oc); 809 810 mc->init = sbsa_ref_init; 811 mc->desc = "QEMU 'SBSA Reference' ARM Virtual Machine"; 812 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a57"); 813 mc->max_cpus = 512; 814 mc->pci_allow_0_address = true; 815 mc->minimum_page_bits = 12; 816 mc->block_default_type = IF_IDE; 817 mc->no_cdrom = 1; 818 mc->default_ram_size = 1 * GiB; 819 mc->default_ram_id = "sbsa-ref.ram"; 820 mc->default_cpus = 4; 821 mc->possible_cpu_arch_ids = sbsa_ref_possible_cpu_arch_ids; 822 mc->cpu_index_to_instance_props = sbsa_ref_cpu_index_to_props; 823 mc->get_default_cpu_node_id = sbsa_ref_get_default_cpu_node_id; 824 } 825 826 static const TypeInfo sbsa_ref_info = { 827 .name = TYPE_SBSA_MACHINE, 828 .parent = TYPE_MACHINE, 829 .instance_init = sbsa_ref_instance_init, 830 .class_init = sbsa_ref_class_init, 831 .instance_size = sizeof(SBSAMachineState), 832 }; 833 834 static void sbsa_ref_machine_init(void) 835 { 836 type_register_static(&sbsa_ref_info); 837 } 838 839 type_init(sbsa_ref_machine_init); 840