1 /* 2 * ARM SBSA Reference Platform emulation 3 * 4 * Copyright (c) 2018 Linaro Limited 5 * Written by Hongbo Zhang <hongbo.zhang@linaro.org> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu-common.h" 22 #include "qapi/error.h" 23 #include "qemu/error-report.h" 24 #include "qemu/units.h" 25 #include "sysemu/device_tree.h" 26 #include "sysemu/numa.h" 27 #include "sysemu/runstate.h" 28 #include "sysemu/sysemu.h" 29 #include "exec/address-spaces.h" 30 #include "exec/hwaddr.h" 31 #include "kvm_arm.h" 32 #include "hw/arm/boot.h" 33 #include "hw/block/flash.h" 34 #include "hw/boards.h" 35 #include "hw/ide/internal.h" 36 #include "hw/ide/ahci_internal.h" 37 #include "hw/intc/arm_gicv3_common.h" 38 #include "hw/loader.h" 39 #include "hw/pci-host/gpex.h" 40 #include "hw/qdev-properties.h" 41 #include "hw/usb.h" 42 #include "hw/char/pl011.h" 43 #include "net/net.h" 44 #include "qom/object.h" 45 46 #define RAMLIMIT_GB 8192 47 #define RAMLIMIT_BYTES (RAMLIMIT_GB * GiB) 48 49 #define NUM_IRQS 256 50 #define NUM_SMMU_IRQS 4 51 #define NUM_SATA_PORTS 6 52 53 #define VIRTUAL_PMU_IRQ 7 54 #define ARCH_GIC_MAINT_IRQ 9 55 #define ARCH_TIMER_VIRT_IRQ 11 56 #define ARCH_TIMER_S_EL1_IRQ 13 57 #define ARCH_TIMER_NS_EL1_IRQ 14 58 #define ARCH_TIMER_NS_EL2_IRQ 10 59 60 enum { 61 SBSA_FLASH, 62 SBSA_MEM, 63 SBSA_CPUPERIPHS, 64 SBSA_GIC_DIST, 65 SBSA_GIC_REDIST, 66 SBSA_SECURE_EC, 67 SBSA_SMMU, 68 SBSA_UART, 69 SBSA_RTC, 70 SBSA_PCIE, 71 SBSA_PCIE_MMIO, 72 SBSA_PCIE_MMIO_HIGH, 73 SBSA_PCIE_PIO, 74 SBSA_PCIE_ECAM, 75 SBSA_GPIO, 76 SBSA_SECURE_UART, 77 SBSA_SECURE_UART_MM, 78 SBSA_SECURE_MEM, 79 SBSA_AHCI, 80 SBSA_EHCI, 81 }; 82 83 struct SBSAMachineState { 84 MachineState parent; 85 struct arm_boot_info bootinfo; 86 int smp_cpus; 87 void *fdt; 88 int fdt_size; 89 int psci_conduit; 90 DeviceState *gic; 91 PFlashCFI01 *flash[2]; 92 }; 93 94 #define TYPE_SBSA_MACHINE MACHINE_TYPE_NAME("sbsa-ref") 95 OBJECT_DECLARE_SIMPLE_TYPE(SBSAMachineState, SBSA_MACHINE) 96 97 static const MemMapEntry sbsa_ref_memmap[] = { 98 /* 512M boot ROM */ 99 [SBSA_FLASH] = { 0, 0x20000000 }, 100 /* 512M secure memory */ 101 [SBSA_SECURE_MEM] = { 0x20000000, 0x20000000 }, 102 /* Space reserved for CPU peripheral devices */ 103 [SBSA_CPUPERIPHS] = { 0x40000000, 0x00040000 }, 104 [SBSA_GIC_DIST] = { 0x40060000, 0x00010000 }, 105 [SBSA_GIC_REDIST] = { 0x40080000, 0x04000000 }, 106 [SBSA_SECURE_EC] = { 0x50000000, 0x00001000 }, 107 [SBSA_UART] = { 0x60000000, 0x00001000 }, 108 [SBSA_RTC] = { 0x60010000, 0x00001000 }, 109 [SBSA_GPIO] = { 0x60020000, 0x00001000 }, 110 [SBSA_SECURE_UART] = { 0x60030000, 0x00001000 }, 111 [SBSA_SECURE_UART_MM] = { 0x60040000, 0x00001000 }, 112 [SBSA_SMMU] = { 0x60050000, 0x00020000 }, 113 /* Space here reserved for more SMMUs */ 114 [SBSA_AHCI] = { 0x60100000, 0x00010000 }, 115 [SBSA_EHCI] = { 0x60110000, 0x00010000 }, 116 /* Space here reserved for other devices */ 117 [SBSA_PCIE_PIO] = { 0x7fff0000, 0x00010000 }, 118 /* 32-bit address PCIE MMIO space */ 119 [SBSA_PCIE_MMIO] = { 0x80000000, 0x70000000 }, 120 /* 256M PCIE ECAM space */ 121 [SBSA_PCIE_ECAM] = { 0xf0000000, 0x10000000 }, 122 /* ~1TB PCIE MMIO space (4GB to 1024GB boundary) */ 123 [SBSA_PCIE_MMIO_HIGH] = { 0x100000000ULL, 0xFF00000000ULL }, 124 [SBSA_MEM] = { 0x10000000000ULL, RAMLIMIT_BYTES }, 125 }; 126 127 static const int sbsa_ref_irqmap[] = { 128 [SBSA_UART] = 1, 129 [SBSA_RTC] = 2, 130 [SBSA_PCIE] = 3, /* ... to 6 */ 131 [SBSA_GPIO] = 7, 132 [SBSA_SECURE_UART] = 8, 133 [SBSA_SECURE_UART_MM] = 9, 134 [SBSA_AHCI] = 10, 135 [SBSA_EHCI] = 11, 136 }; 137 138 static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx) 139 { 140 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER; 141 return arm_cpu_mp_affinity(idx, clustersz); 142 } 143 144 /* 145 * Firmware on this machine only uses ACPI table to load OS, these limited 146 * device tree nodes are just to let firmware know the info which varies from 147 * command line parameters, so it is not necessary to be fully compatible 148 * with the kernel CPU and NUMA binding rules. 149 */ 150 static void create_fdt(SBSAMachineState *sms) 151 { 152 void *fdt = create_device_tree(&sms->fdt_size); 153 const MachineState *ms = MACHINE(sms); 154 int nb_numa_nodes = ms->numa_state->num_nodes; 155 int cpu; 156 157 if (!fdt) { 158 error_report("create_device_tree() failed"); 159 exit(1); 160 } 161 162 sms->fdt = fdt; 163 164 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,sbsa-ref"); 165 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 166 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 167 168 if (ms->numa_state->have_numa_distance) { 169 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); 170 uint32_t *matrix = g_malloc0(size); 171 int idx, i, j; 172 173 for (i = 0; i < nb_numa_nodes; i++) { 174 for (j = 0; j < nb_numa_nodes; j++) { 175 idx = (i * nb_numa_nodes + j) * 3; 176 matrix[idx + 0] = cpu_to_be32(i); 177 matrix[idx + 1] = cpu_to_be32(j); 178 matrix[idx + 2] = 179 cpu_to_be32(ms->numa_state->nodes[i].distance[j]); 180 } 181 } 182 183 qemu_fdt_add_subnode(fdt, "/distance-map"); 184 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", 185 matrix, size); 186 g_free(matrix); 187 } 188 189 /* 190 * From Documentation/devicetree/bindings/arm/cpus.yaml 191 * On ARM v8 64-bit systems this property is required 192 * and matches the MPIDR_EL1 register affinity bits. 193 * 194 * * If cpus node's #address-cells property is set to 2 195 * 196 * The first reg cell bits [7:0] must be set to 197 * bits [39:32] of MPIDR_EL1. 198 * 199 * The second reg cell bits [23:0] must be set to 200 * bits [23:0] of MPIDR_EL1. 201 */ 202 qemu_fdt_add_subnode(sms->fdt, "/cpus"); 203 qemu_fdt_setprop_cell(sms->fdt, "/cpus", "#address-cells", 2); 204 qemu_fdt_setprop_cell(sms->fdt, "/cpus", "#size-cells", 0x0); 205 206 for (cpu = sms->smp_cpus - 1; cpu >= 0; cpu--) { 207 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 208 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 209 CPUState *cs = CPU(armcpu); 210 uint64_t mpidr = sbsa_ref_cpu_mp_affinity(sms, cpu); 211 212 qemu_fdt_add_subnode(sms->fdt, nodename); 213 qemu_fdt_setprop_u64(sms->fdt, nodename, "reg", mpidr); 214 215 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 216 qemu_fdt_setprop_cell(sms->fdt, nodename, "numa-node-id", 217 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 218 } 219 220 g_free(nodename); 221 } 222 } 223 224 #define SBSA_FLASH_SECTOR_SIZE (256 * KiB) 225 226 static PFlashCFI01 *sbsa_flash_create1(SBSAMachineState *sms, 227 const char *name, 228 const char *alias_prop_name) 229 { 230 /* 231 * Create a single flash device. We use the same parameters as 232 * the flash devices on the Versatile Express board. 233 */ 234 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 235 236 qdev_prop_set_uint64(dev, "sector-length", SBSA_FLASH_SECTOR_SIZE); 237 qdev_prop_set_uint8(dev, "width", 4); 238 qdev_prop_set_uint8(dev, "device-width", 2); 239 qdev_prop_set_bit(dev, "big-endian", false); 240 qdev_prop_set_uint16(dev, "id0", 0x89); 241 qdev_prop_set_uint16(dev, "id1", 0x18); 242 qdev_prop_set_uint16(dev, "id2", 0x00); 243 qdev_prop_set_uint16(dev, "id3", 0x00); 244 qdev_prop_set_string(dev, "name", name); 245 object_property_add_child(OBJECT(sms), name, OBJECT(dev)); 246 object_property_add_alias(OBJECT(sms), alias_prop_name, 247 OBJECT(dev), "drive"); 248 return PFLASH_CFI01(dev); 249 } 250 251 static void sbsa_flash_create(SBSAMachineState *sms) 252 { 253 sms->flash[0] = sbsa_flash_create1(sms, "sbsa.flash0", "pflash0"); 254 sms->flash[1] = sbsa_flash_create1(sms, "sbsa.flash1", "pflash1"); 255 } 256 257 static void sbsa_flash_map1(PFlashCFI01 *flash, 258 hwaddr base, hwaddr size, 259 MemoryRegion *sysmem) 260 { 261 DeviceState *dev = DEVICE(flash); 262 263 assert(QEMU_IS_ALIGNED(size, SBSA_FLASH_SECTOR_SIZE)); 264 assert(size / SBSA_FLASH_SECTOR_SIZE <= UINT32_MAX); 265 qdev_prop_set_uint32(dev, "num-blocks", size / SBSA_FLASH_SECTOR_SIZE); 266 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 267 268 memory_region_add_subregion(sysmem, base, 269 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 270 0)); 271 } 272 273 static void sbsa_flash_map(SBSAMachineState *sms, 274 MemoryRegion *sysmem, 275 MemoryRegion *secure_sysmem) 276 { 277 /* 278 * Map two flash devices to fill the SBSA_FLASH space in the memmap. 279 * sysmem is the system memory space. secure_sysmem is the secure view 280 * of the system, and the first flash device should be made visible only 281 * there. The second flash device is visible to both secure and nonsecure. 282 */ 283 hwaddr flashsize = sbsa_ref_memmap[SBSA_FLASH].size / 2; 284 hwaddr flashbase = sbsa_ref_memmap[SBSA_FLASH].base; 285 286 sbsa_flash_map1(sms->flash[0], flashbase, flashsize, 287 secure_sysmem); 288 sbsa_flash_map1(sms->flash[1], flashbase + flashsize, flashsize, 289 sysmem); 290 } 291 292 static bool sbsa_firmware_init(SBSAMachineState *sms, 293 MemoryRegion *sysmem, 294 MemoryRegion *secure_sysmem) 295 { 296 int i; 297 BlockBackend *pflash_blk0; 298 299 /* Map legacy -drive if=pflash to machine properties */ 300 for (i = 0; i < ARRAY_SIZE(sms->flash); i++) { 301 pflash_cfi01_legacy_drive(sms->flash[i], 302 drive_get(IF_PFLASH, 0, i)); 303 } 304 305 sbsa_flash_map(sms, sysmem, secure_sysmem); 306 307 pflash_blk0 = pflash_cfi01_get_blk(sms->flash[0]); 308 309 if (bios_name) { 310 char *fname; 311 MemoryRegion *mr; 312 int image_size; 313 314 if (pflash_blk0) { 315 error_report("The contents of the first flash device may be " 316 "specified with -bios or with -drive if=pflash... " 317 "but you cannot use both options at once"); 318 exit(1); 319 } 320 321 /* Fall back to -bios */ 322 323 fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 324 if (!fname) { 325 error_report("Could not find ROM image '%s'", bios_name); 326 exit(1); 327 } 328 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(sms->flash[0]), 0); 329 image_size = load_image_mr(fname, mr); 330 g_free(fname); 331 if (image_size < 0) { 332 error_report("Could not load ROM image '%s'", bios_name); 333 exit(1); 334 } 335 } 336 337 return pflash_blk0 || bios_name; 338 } 339 340 static void create_secure_ram(SBSAMachineState *sms, 341 MemoryRegion *secure_sysmem) 342 { 343 MemoryRegion *secram = g_new(MemoryRegion, 1); 344 hwaddr base = sbsa_ref_memmap[SBSA_SECURE_MEM].base; 345 hwaddr size = sbsa_ref_memmap[SBSA_SECURE_MEM].size; 346 347 memory_region_init_ram(secram, NULL, "sbsa-ref.secure-ram", size, 348 &error_fatal); 349 memory_region_add_subregion(secure_sysmem, base, secram); 350 } 351 352 static void create_gic(SBSAMachineState *sms) 353 { 354 unsigned int smp_cpus = MACHINE(sms)->smp.cpus; 355 SysBusDevice *gicbusdev; 356 const char *gictype; 357 uint32_t redist0_capacity, redist0_count; 358 int i; 359 360 gictype = gicv3_class_name(); 361 362 sms->gic = qdev_new(gictype); 363 qdev_prop_set_uint32(sms->gic, "revision", 3); 364 qdev_prop_set_uint32(sms->gic, "num-cpu", smp_cpus); 365 /* 366 * Note that the num-irq property counts both internal and external 367 * interrupts; there are always 32 of the former (mandated by GIC spec). 368 */ 369 qdev_prop_set_uint32(sms->gic, "num-irq", NUM_IRQS + 32); 370 qdev_prop_set_bit(sms->gic, "has-security-extensions", true); 371 372 redist0_capacity = 373 sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE; 374 redist0_count = MIN(smp_cpus, redist0_capacity); 375 376 qdev_prop_set_uint32(sms->gic, "len-redist-region-count", 1); 377 qdev_prop_set_uint32(sms->gic, "redist-region-count[0]", redist0_count); 378 379 gicbusdev = SYS_BUS_DEVICE(sms->gic); 380 sysbus_realize_and_unref(gicbusdev, &error_fatal); 381 sysbus_mmio_map(gicbusdev, 0, sbsa_ref_memmap[SBSA_GIC_DIST].base); 382 sysbus_mmio_map(gicbusdev, 1, sbsa_ref_memmap[SBSA_GIC_REDIST].base); 383 384 /* 385 * Wire the outputs from each CPU's generic timer and the GICv3 386 * maintenance interrupt signal to the appropriate GIC PPI inputs, 387 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. 388 */ 389 for (i = 0; i < smp_cpus; i++) { 390 DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); 391 int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; 392 int irq; 393 /* 394 * Mapping from the output timer irq lines from the CPU to the 395 * GIC PPI inputs used for this board. 396 */ 397 const int timer_irq[] = { 398 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 399 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 400 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 401 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 402 }; 403 404 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 405 qdev_connect_gpio_out(cpudev, irq, 406 qdev_get_gpio_in(sms->gic, 407 ppibase + timer_irq[irq])); 408 } 409 410 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0, 411 qdev_get_gpio_in(sms->gic, ppibase 412 + ARCH_GIC_MAINT_IRQ)); 413 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 414 qdev_get_gpio_in(sms->gic, ppibase 415 + VIRTUAL_PMU_IRQ)); 416 417 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 418 sysbus_connect_irq(gicbusdev, i + smp_cpus, 419 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 420 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, 421 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 422 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, 423 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 424 } 425 } 426 427 static void create_uart(const SBSAMachineState *sms, int uart, 428 MemoryRegion *mem, Chardev *chr) 429 { 430 hwaddr base = sbsa_ref_memmap[uart].base; 431 int irq = sbsa_ref_irqmap[uart]; 432 DeviceState *dev = qdev_new(TYPE_PL011); 433 SysBusDevice *s = SYS_BUS_DEVICE(dev); 434 435 qdev_prop_set_chr(dev, "chardev", chr); 436 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 437 memory_region_add_subregion(mem, base, 438 sysbus_mmio_get_region(s, 0)); 439 sysbus_connect_irq(s, 0, qdev_get_gpio_in(sms->gic, irq)); 440 } 441 442 static void create_rtc(const SBSAMachineState *sms) 443 { 444 hwaddr base = sbsa_ref_memmap[SBSA_RTC].base; 445 int irq = sbsa_ref_irqmap[SBSA_RTC]; 446 447 sysbus_create_simple("pl031", base, qdev_get_gpio_in(sms->gic, irq)); 448 } 449 450 static DeviceState *gpio_key_dev; 451 static void sbsa_ref_powerdown_req(Notifier *n, void *opaque) 452 { 453 /* use gpio Pin 3 for power button event */ 454 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); 455 } 456 457 static Notifier sbsa_ref_powerdown_notifier = { 458 .notify = sbsa_ref_powerdown_req 459 }; 460 461 static void create_gpio(const SBSAMachineState *sms) 462 { 463 DeviceState *pl061_dev; 464 hwaddr base = sbsa_ref_memmap[SBSA_GPIO].base; 465 int irq = sbsa_ref_irqmap[SBSA_GPIO]; 466 467 pl061_dev = sysbus_create_simple("pl061", base, 468 qdev_get_gpio_in(sms->gic, irq)); 469 470 gpio_key_dev = sysbus_create_simple("gpio-key", -1, 471 qdev_get_gpio_in(pl061_dev, 3)); 472 473 /* connect powerdown request */ 474 qemu_register_powerdown_notifier(&sbsa_ref_powerdown_notifier); 475 } 476 477 static void create_ahci(const SBSAMachineState *sms) 478 { 479 hwaddr base = sbsa_ref_memmap[SBSA_AHCI].base; 480 int irq = sbsa_ref_irqmap[SBSA_AHCI]; 481 DeviceState *dev; 482 DriveInfo *hd[NUM_SATA_PORTS]; 483 SysbusAHCIState *sysahci; 484 AHCIState *ahci; 485 int i; 486 487 dev = qdev_new("sysbus-ahci"); 488 qdev_prop_set_uint32(dev, "num-ports", NUM_SATA_PORTS); 489 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 490 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 491 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(sms->gic, irq)); 492 493 sysahci = SYSBUS_AHCI(dev); 494 ahci = &sysahci->ahci; 495 ide_drive_get(hd, ARRAY_SIZE(hd)); 496 for (i = 0; i < ahci->ports; i++) { 497 if (hd[i] == NULL) { 498 continue; 499 } 500 ide_create_drive(&ahci->dev[i].port, 0, hd[i]); 501 } 502 } 503 504 static void create_ehci(const SBSAMachineState *sms) 505 { 506 hwaddr base = sbsa_ref_memmap[SBSA_EHCI].base; 507 int irq = sbsa_ref_irqmap[SBSA_EHCI]; 508 509 sysbus_create_simple("platform-ehci-usb", base, 510 qdev_get_gpio_in(sms->gic, irq)); 511 } 512 513 static void create_smmu(const SBSAMachineState *sms, PCIBus *bus) 514 { 515 hwaddr base = sbsa_ref_memmap[SBSA_SMMU].base; 516 int irq = sbsa_ref_irqmap[SBSA_SMMU]; 517 DeviceState *dev; 518 int i; 519 520 dev = qdev_new("arm-smmuv3"); 521 522 object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus), 523 &error_abort); 524 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 525 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 526 for (i = 0; i < NUM_SMMU_IRQS; i++) { 527 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 528 qdev_get_gpio_in(sms->gic, irq + 1)); 529 } 530 } 531 532 static void create_pcie(SBSAMachineState *sms) 533 { 534 hwaddr base_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].base; 535 hwaddr size_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].size; 536 hwaddr base_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].base; 537 hwaddr size_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].size; 538 hwaddr base_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].base; 539 hwaddr size_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].size; 540 hwaddr base_pio = sbsa_ref_memmap[SBSA_PCIE_PIO].base; 541 int irq = sbsa_ref_irqmap[SBSA_PCIE]; 542 MemoryRegion *mmio_alias, *mmio_alias_high, *mmio_reg; 543 MemoryRegion *ecam_alias, *ecam_reg; 544 DeviceState *dev; 545 PCIHostState *pci; 546 int i; 547 548 dev = qdev_new(TYPE_GPEX_HOST); 549 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 550 551 /* Map ECAM space */ 552 ecam_alias = g_new0(MemoryRegion, 1); 553 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 554 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 555 ecam_reg, 0, size_ecam); 556 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); 557 558 /* Map the MMIO space */ 559 mmio_alias = g_new0(MemoryRegion, 1); 560 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 561 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 562 mmio_reg, base_mmio, size_mmio); 563 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); 564 565 /* Map the MMIO_HIGH space */ 566 mmio_alias_high = g_new0(MemoryRegion, 1); 567 memory_region_init_alias(mmio_alias_high, OBJECT(dev), "pcie-mmio-high", 568 mmio_reg, base_mmio_high, size_mmio_high); 569 memory_region_add_subregion(get_system_memory(), base_mmio_high, 570 mmio_alias_high); 571 572 /* Map IO port space */ 573 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); 574 575 for (i = 0; i < GPEX_NUM_IRQS; i++) { 576 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 577 qdev_get_gpio_in(sms->gic, irq + i)); 578 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); 579 } 580 581 pci = PCI_HOST_BRIDGE(dev); 582 if (pci->bus) { 583 for (i = 0; i < nb_nics; i++) { 584 NICInfo *nd = &nd_table[i]; 585 586 if (!nd->model) { 587 nd->model = g_strdup("e1000e"); 588 } 589 590 pci_nic_init_nofail(nd, pci->bus, nd->model, NULL); 591 } 592 } 593 594 pci_create_simple(pci->bus, -1, "VGA"); 595 596 create_smmu(sms, pci->bus); 597 } 598 599 static void *sbsa_ref_dtb(const struct arm_boot_info *binfo, int *fdt_size) 600 { 601 const SBSAMachineState *board = container_of(binfo, SBSAMachineState, 602 bootinfo); 603 604 *fdt_size = board->fdt_size; 605 return board->fdt; 606 } 607 608 static void create_secure_ec(MemoryRegion *mem) 609 { 610 hwaddr base = sbsa_ref_memmap[SBSA_SECURE_EC].base; 611 DeviceState *dev = qdev_new("sbsa-ec"); 612 SysBusDevice *s = SYS_BUS_DEVICE(dev); 613 614 memory_region_add_subregion(mem, base, 615 sysbus_mmio_get_region(s, 0)); 616 } 617 618 static void sbsa_ref_init(MachineState *machine) 619 { 620 unsigned int smp_cpus = machine->smp.cpus; 621 unsigned int max_cpus = machine->smp.max_cpus; 622 SBSAMachineState *sms = SBSA_MACHINE(machine); 623 MachineClass *mc = MACHINE_GET_CLASS(machine); 624 MemoryRegion *sysmem = get_system_memory(); 625 MemoryRegion *secure_sysmem = g_new(MemoryRegion, 1); 626 bool firmware_loaded; 627 const CPUArchIdList *possible_cpus; 628 int n, sbsa_max_cpus; 629 630 if (strcmp(machine->cpu_type, ARM_CPU_TYPE_NAME("cortex-a57"))) { 631 error_report("sbsa-ref: CPU type other than the built-in " 632 "cortex-a57 not supported"); 633 exit(1); 634 } 635 636 if (kvm_enabled()) { 637 error_report("sbsa-ref: KVM is not supported for this machine"); 638 exit(1); 639 } 640 641 /* 642 * The Secure view of the world is the same as the NonSecure, 643 * but with a few extra devices. Create it as a container region 644 * containing the system memory at low priority; any secure-only 645 * devices go in at higher priority and take precedence. 646 */ 647 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", 648 UINT64_MAX); 649 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); 650 651 firmware_loaded = sbsa_firmware_init(sms, sysmem, secure_sysmem); 652 653 if (machine->kernel_filename && firmware_loaded) { 654 error_report("sbsa-ref: No fw_cfg device on this machine, " 655 "so -kernel option is not supported when firmware loaded, " 656 "please load OS from hard disk instead"); 657 exit(1); 658 } 659 660 /* 661 * This machine has EL3 enabled, external firmware should supply PSCI 662 * implementation, so the QEMU's internal PSCI is disabled. 663 */ 664 sms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; 665 666 sbsa_max_cpus = sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE; 667 668 if (max_cpus > sbsa_max_cpus) { 669 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " 670 "supported by machine 'sbsa-ref' (%d)", 671 max_cpus, sbsa_max_cpus); 672 exit(1); 673 } 674 675 sms->smp_cpus = smp_cpus; 676 677 if (machine->ram_size > sbsa_ref_memmap[SBSA_MEM].size) { 678 error_report("sbsa-ref: cannot model more than %dGB RAM", RAMLIMIT_GB); 679 exit(1); 680 } 681 682 possible_cpus = mc->possible_cpu_arch_ids(machine); 683 for (n = 0; n < possible_cpus->len; n++) { 684 Object *cpuobj; 685 CPUState *cs; 686 687 if (n >= smp_cpus) { 688 break; 689 } 690 691 cpuobj = object_new(possible_cpus->cpus[n].type); 692 object_property_set_int(cpuobj, "mp-affinity", 693 possible_cpus->cpus[n].arch_id, NULL); 694 695 cs = CPU(cpuobj); 696 cs->cpu_index = n; 697 698 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj), 699 &error_fatal); 700 701 if (object_property_find(cpuobj, "reset-cbar")) { 702 object_property_set_int(cpuobj, "reset-cbar", 703 sbsa_ref_memmap[SBSA_CPUPERIPHS].base, 704 &error_abort); 705 } 706 707 object_property_set_link(cpuobj, "memory", OBJECT(sysmem), 708 &error_abort); 709 710 object_property_set_link(cpuobj, "secure-memory", 711 OBJECT(secure_sysmem), &error_abort); 712 713 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); 714 object_unref(cpuobj); 715 } 716 717 memory_region_add_subregion(sysmem, sbsa_ref_memmap[SBSA_MEM].base, 718 machine->ram); 719 720 create_fdt(sms); 721 722 create_secure_ram(sms, secure_sysmem); 723 724 create_gic(sms); 725 726 create_uart(sms, SBSA_UART, sysmem, serial_hd(0)); 727 create_uart(sms, SBSA_SECURE_UART, secure_sysmem, serial_hd(1)); 728 /* Second secure UART for RAS and MM from EL0 */ 729 create_uart(sms, SBSA_SECURE_UART_MM, secure_sysmem, serial_hd(2)); 730 731 create_rtc(sms); 732 733 create_gpio(sms); 734 735 create_ahci(sms); 736 737 create_ehci(sms); 738 739 create_pcie(sms); 740 741 create_secure_ec(secure_sysmem); 742 743 sms->bootinfo.ram_size = machine->ram_size; 744 sms->bootinfo.nb_cpus = smp_cpus; 745 sms->bootinfo.board_id = -1; 746 sms->bootinfo.loader_start = sbsa_ref_memmap[SBSA_MEM].base; 747 sms->bootinfo.get_dtb = sbsa_ref_dtb; 748 sms->bootinfo.firmware_loaded = firmware_loaded; 749 arm_load_kernel(ARM_CPU(first_cpu), machine, &sms->bootinfo); 750 } 751 752 static const CPUArchIdList *sbsa_ref_possible_cpu_arch_ids(MachineState *ms) 753 { 754 unsigned int max_cpus = ms->smp.max_cpus; 755 SBSAMachineState *sms = SBSA_MACHINE(ms); 756 int n; 757 758 if (ms->possible_cpus) { 759 assert(ms->possible_cpus->len == max_cpus); 760 return ms->possible_cpus; 761 } 762 763 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 764 sizeof(CPUArchId) * max_cpus); 765 ms->possible_cpus->len = max_cpus; 766 for (n = 0; n < ms->possible_cpus->len; n++) { 767 ms->possible_cpus->cpus[n].type = ms->cpu_type; 768 ms->possible_cpus->cpus[n].arch_id = 769 sbsa_ref_cpu_mp_affinity(sms, n); 770 ms->possible_cpus->cpus[n].props.has_thread_id = true; 771 ms->possible_cpus->cpus[n].props.thread_id = n; 772 } 773 return ms->possible_cpus; 774 } 775 776 static CpuInstanceProperties 777 sbsa_ref_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 778 { 779 MachineClass *mc = MACHINE_GET_CLASS(ms); 780 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 781 782 assert(cpu_index < possible_cpus->len); 783 return possible_cpus->cpus[cpu_index].props; 784 } 785 786 static int64_t 787 sbsa_ref_get_default_cpu_node_id(const MachineState *ms, int idx) 788 { 789 return idx % ms->numa_state->num_nodes; 790 } 791 792 static void sbsa_ref_instance_init(Object *obj) 793 { 794 SBSAMachineState *sms = SBSA_MACHINE(obj); 795 796 sbsa_flash_create(sms); 797 } 798 799 static void sbsa_ref_class_init(ObjectClass *oc, void *data) 800 { 801 MachineClass *mc = MACHINE_CLASS(oc); 802 803 mc->init = sbsa_ref_init; 804 mc->desc = "QEMU 'SBSA Reference' ARM Virtual Machine"; 805 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a57"); 806 mc->max_cpus = 512; 807 mc->pci_allow_0_address = true; 808 mc->minimum_page_bits = 12; 809 mc->block_default_type = IF_IDE; 810 mc->no_cdrom = 1; 811 mc->default_ram_size = 1 * GiB; 812 mc->default_ram_id = "sbsa-ref.ram"; 813 mc->default_cpus = 4; 814 mc->possible_cpu_arch_ids = sbsa_ref_possible_cpu_arch_ids; 815 mc->cpu_index_to_instance_props = sbsa_ref_cpu_index_to_props; 816 mc->get_default_cpu_node_id = sbsa_ref_get_default_cpu_node_id; 817 } 818 819 static const TypeInfo sbsa_ref_info = { 820 .name = TYPE_SBSA_MACHINE, 821 .parent = TYPE_MACHINE, 822 .instance_init = sbsa_ref_instance_init, 823 .class_init = sbsa_ref_class_init, 824 .instance_size = sizeof(SBSAMachineState), 825 }; 826 827 static void sbsa_ref_machine_init(void) 828 { 829 type_register_static(&sbsa_ref_info); 830 } 831 832 type_init(sbsa_ref_machine_init); 833