1 /* 2 * ARM SBSA Reference Platform emulation 3 * 4 * Copyright (c) 2018 Linaro Limited 5 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 6 * Written by Hongbo Zhang <hongbo.zhang@linaro.org> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2 or later, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/datadir.h" 23 #include "qapi/error.h" 24 #include "qemu/error-report.h" 25 #include "qemu/units.h" 26 #include "sysemu/device_tree.h" 27 #include "sysemu/kvm.h" 28 #include "sysemu/numa.h" 29 #include "sysemu/runstate.h" 30 #include "sysemu/sysemu.h" 31 #include "exec/hwaddr.h" 32 #include "kvm_arm.h" 33 #include "hw/arm/boot.h" 34 #include "hw/arm/bsa.h" 35 #include "hw/arm/fdt.h" 36 #include "hw/arm/smmuv3.h" 37 #include "hw/block/flash.h" 38 #include "hw/boards.h" 39 #include "hw/ide/ide-bus.h" 40 #include "hw/ide/ahci-sysbus.h" 41 #include "hw/intc/arm_gicv3_common.h" 42 #include "hw/intc/arm_gicv3_its_common.h" 43 #include "hw/loader.h" 44 #include "hw/pci-host/gpex.h" 45 #include "hw/qdev-properties.h" 46 #include "hw/usb.h" 47 #include "hw/usb/xhci.h" 48 #include "hw/char/pl011.h" 49 #include "hw/watchdog/sbsa_gwdt.h" 50 #include "net/net.h" 51 #include "qapi/qmp/qlist.h" 52 #include "qom/object.h" 53 #include "target/arm/cpu-qom.h" 54 #include "target/arm/gtimer.h" 55 56 #define RAMLIMIT_GB 8192 57 #define RAMLIMIT_BYTES (RAMLIMIT_GB * GiB) 58 59 #define NUM_IRQS 256 60 #define NUM_SMMU_IRQS 4 61 #define NUM_SATA_PORTS 6 62 63 /* 64 * Generic timer frequency in Hz (which drives both the CPU generic timers 65 * and the SBSA watchdog-timer). Older (<2.11) versions of the TF-A firmware 66 * assumed 62.5MHz here. 67 * 68 * Starting with Armv8.6 CPU 1GHz timer frequency is mandated. 69 */ 70 #define SBSA_GTIMER_HZ 1000000000 71 72 enum { 73 SBSA_FLASH, 74 SBSA_MEM, 75 SBSA_CPUPERIPHS, 76 SBSA_GIC_DIST, 77 SBSA_GIC_REDIST, 78 SBSA_GIC_ITS, 79 SBSA_SECURE_EC, 80 SBSA_GWDT_WS0, 81 SBSA_GWDT_REFRESH, 82 SBSA_GWDT_CONTROL, 83 SBSA_SMMU, 84 SBSA_UART, 85 SBSA_RTC, 86 SBSA_PCIE, 87 SBSA_PCIE_MMIO, 88 SBSA_PCIE_MMIO_HIGH, 89 SBSA_PCIE_PIO, 90 SBSA_PCIE_ECAM, 91 SBSA_GPIO, 92 SBSA_SECURE_UART, 93 SBSA_SECURE_UART_MM, 94 SBSA_SECURE_MEM, 95 SBSA_AHCI, 96 SBSA_XHCI, 97 }; 98 99 struct SBSAMachineState { 100 MachineState parent; 101 struct arm_boot_info bootinfo; 102 int smp_cpus; 103 void *fdt; 104 int fdt_size; 105 int psci_conduit; 106 DeviceState *gic; 107 PFlashCFI01 *flash[2]; 108 }; 109 110 #define TYPE_SBSA_MACHINE MACHINE_TYPE_NAME("sbsa-ref") 111 OBJECT_DECLARE_SIMPLE_TYPE(SBSAMachineState, SBSA_MACHINE) 112 113 static const MemMapEntry sbsa_ref_memmap[] = { 114 /* 512M boot ROM */ 115 [SBSA_FLASH] = { 0, 0x20000000 }, 116 /* 512M secure memory */ 117 [SBSA_SECURE_MEM] = { 0x20000000, 0x20000000 }, 118 /* Space reserved for CPU peripheral devices */ 119 [SBSA_CPUPERIPHS] = { 0x40000000, 0x00040000 }, 120 [SBSA_GIC_DIST] = { 0x40060000, 0x00010000 }, 121 [SBSA_GIC_REDIST] = { 0x40080000, 0x04000000 }, 122 [SBSA_GIC_ITS] = { 0x44081000, 0x00020000 }, 123 [SBSA_SECURE_EC] = { 0x50000000, 0x00001000 }, 124 [SBSA_GWDT_REFRESH] = { 0x50010000, 0x00001000 }, 125 [SBSA_GWDT_CONTROL] = { 0x50011000, 0x00001000 }, 126 [SBSA_UART] = { 0x60000000, 0x00001000 }, 127 [SBSA_RTC] = { 0x60010000, 0x00001000 }, 128 [SBSA_GPIO] = { 0x60020000, 0x00001000 }, 129 [SBSA_SECURE_UART] = { 0x60030000, 0x00001000 }, 130 [SBSA_SECURE_UART_MM] = { 0x60040000, 0x00001000 }, 131 [SBSA_SMMU] = { 0x60050000, 0x00020000 }, 132 /* Space here reserved for more SMMUs */ 133 [SBSA_AHCI] = { 0x60100000, 0x00010000 }, 134 [SBSA_XHCI] = { 0x60110000, 0x00010000 }, 135 /* Space here reserved for other devices */ 136 [SBSA_PCIE_PIO] = { 0x7fff0000, 0x00010000 }, 137 /* 32-bit address PCIE MMIO space */ 138 [SBSA_PCIE_MMIO] = { 0x80000000, 0x70000000 }, 139 /* 256M PCIE ECAM space */ 140 [SBSA_PCIE_ECAM] = { 0xf0000000, 0x10000000 }, 141 /* ~1TB PCIE MMIO space (4GB to 1024GB boundary) */ 142 [SBSA_PCIE_MMIO_HIGH] = { 0x100000000ULL, 0xFF00000000ULL }, 143 [SBSA_MEM] = { 0x10000000000ULL, RAMLIMIT_BYTES }, 144 }; 145 146 static const int sbsa_ref_irqmap[] = { 147 [SBSA_UART] = 1, 148 [SBSA_RTC] = 2, 149 [SBSA_PCIE] = 3, /* ... to 6 */ 150 [SBSA_GPIO] = 7, 151 [SBSA_SECURE_UART] = 8, 152 [SBSA_SECURE_UART_MM] = 9, 153 [SBSA_AHCI] = 10, 154 [SBSA_XHCI] = 11, 155 [SBSA_SMMU] = 12, /* ... to 15 */ 156 [SBSA_GWDT_WS0] = 16, 157 }; 158 159 static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx) 160 { 161 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER; 162 return arm_build_mp_affinity(idx, clustersz); 163 } 164 165 static void sbsa_fdt_add_gic_node(SBSAMachineState *sms) 166 { 167 const char *intc_nodename = "/intc"; 168 const char *its_nodename = "/intc/its"; 169 170 qemu_fdt_add_subnode(sms->fdt, intc_nodename); 171 qemu_fdt_setprop_sized_cells(sms->fdt, intc_nodename, "reg", 172 2, sbsa_ref_memmap[SBSA_GIC_DIST].base, 173 2, sbsa_ref_memmap[SBSA_GIC_DIST].size, 174 2, sbsa_ref_memmap[SBSA_GIC_REDIST].base, 175 2, sbsa_ref_memmap[SBSA_GIC_REDIST].size); 176 177 qemu_fdt_add_subnode(sms->fdt, its_nodename); 178 qemu_fdt_setprop_sized_cells(sms->fdt, its_nodename, "reg", 179 2, sbsa_ref_memmap[SBSA_GIC_ITS].base, 180 2, sbsa_ref_memmap[SBSA_GIC_ITS].size); 181 } 182 183 /* 184 * Firmware on this machine only uses ACPI table to load OS, these limited 185 * device tree nodes are just to let firmware know the info which varies from 186 * command line parameters, so it is not necessary to be fully compatible 187 * with the kernel CPU and NUMA binding rules. 188 */ 189 static void create_fdt(SBSAMachineState *sms) 190 { 191 void *fdt = create_device_tree(&sms->fdt_size); 192 const MachineState *ms = MACHINE(sms); 193 int nb_numa_nodes = ms->numa_state->num_nodes; 194 int cpu; 195 196 if (!fdt) { 197 error_report("create_device_tree() failed"); 198 exit(1); 199 } 200 201 sms->fdt = fdt; 202 203 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,sbsa-ref"); 204 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 205 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 206 207 /* 208 * This versioning scheme is for informing platform fw only. It is neither: 209 * - A QEMU versioned machine type; a given version of QEMU will emulate 210 * a given version of the platform. 211 * - A reflection of level of SBSA (now SystemReady SR) support provided. 212 * 213 * machine-version-major: updated when changes breaking fw compatibility 214 * are introduced. 215 * machine-version-minor: updated when features are added that don't break 216 * fw compatibility. 217 */ 218 qemu_fdt_setprop_cell(fdt, "/", "machine-version-major", 0); 219 qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 4); 220 221 if (ms->numa_state->have_numa_distance) { 222 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); 223 uint32_t *matrix = g_malloc0(size); 224 int idx, i, j; 225 226 for (i = 0; i < nb_numa_nodes; i++) { 227 for (j = 0; j < nb_numa_nodes; j++) { 228 idx = (i * nb_numa_nodes + j) * 3; 229 matrix[idx + 0] = cpu_to_be32(i); 230 matrix[idx + 1] = cpu_to_be32(j); 231 matrix[idx + 2] = 232 cpu_to_be32(ms->numa_state->nodes[i].distance[j]); 233 } 234 } 235 236 qemu_fdt_add_subnode(fdt, "/distance-map"); 237 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", 238 matrix, size); 239 g_free(matrix); 240 } 241 242 /* 243 * From Documentation/devicetree/bindings/arm/cpus.yaml 244 * On ARM v8 64-bit systems this property is required 245 * and matches the MPIDR_EL1 register affinity bits. 246 * 247 * * If cpus node's #address-cells property is set to 2 248 * 249 * The first reg cell bits [7:0] must be set to 250 * bits [39:32] of MPIDR_EL1. 251 * 252 * The second reg cell bits [23:0] must be set to 253 * bits [23:0] of MPIDR_EL1. 254 */ 255 qemu_fdt_add_subnode(sms->fdt, "/cpus"); 256 qemu_fdt_setprop_cell(sms->fdt, "/cpus", "#address-cells", 2); 257 qemu_fdt_setprop_cell(sms->fdt, "/cpus", "#size-cells", 0x0); 258 259 for (cpu = sms->smp_cpus - 1; cpu >= 0; cpu--) { 260 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 261 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 262 CPUState *cs = CPU(armcpu); 263 uint64_t mpidr = sbsa_ref_cpu_mp_affinity(sms, cpu); 264 265 qemu_fdt_add_subnode(sms->fdt, nodename); 266 qemu_fdt_setprop_u64(sms->fdt, nodename, "reg", mpidr); 267 268 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 269 qemu_fdt_setprop_cell(sms->fdt, nodename, "numa-node-id", 270 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 271 } 272 273 g_free(nodename); 274 } 275 276 /* Add CPU topology description through fdt node topology. */ 277 qemu_fdt_add_subnode(sms->fdt, "/cpus/topology"); 278 279 qemu_fdt_setprop_cell(sms->fdt, "/cpus/topology", "sockets", ms->smp.sockets); 280 qemu_fdt_setprop_cell(sms->fdt, "/cpus/topology", "clusters", ms->smp.clusters); 281 qemu_fdt_setprop_cell(sms->fdt, "/cpus/topology", "cores", ms->smp.cores); 282 qemu_fdt_setprop_cell(sms->fdt, "/cpus/topology", "threads", ms->smp.threads); 283 284 sbsa_fdt_add_gic_node(sms); 285 } 286 287 #define SBSA_FLASH_SECTOR_SIZE (256 * KiB) 288 289 static PFlashCFI01 *sbsa_flash_create1(SBSAMachineState *sms, 290 const char *name, 291 const char *alias_prop_name) 292 { 293 /* 294 * Create a single flash device. We use the same parameters as 295 * the flash devices on the Versatile Express board. 296 */ 297 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 298 299 qdev_prop_set_uint64(dev, "sector-length", SBSA_FLASH_SECTOR_SIZE); 300 qdev_prop_set_uint8(dev, "width", 4); 301 qdev_prop_set_uint8(dev, "device-width", 2); 302 qdev_prop_set_bit(dev, "big-endian", false); 303 qdev_prop_set_uint16(dev, "id0", 0x89); 304 qdev_prop_set_uint16(dev, "id1", 0x18); 305 qdev_prop_set_uint16(dev, "id2", 0x00); 306 qdev_prop_set_uint16(dev, "id3", 0x00); 307 qdev_prop_set_string(dev, "name", name); 308 object_property_add_child(OBJECT(sms), name, OBJECT(dev)); 309 object_property_add_alias(OBJECT(sms), alias_prop_name, 310 OBJECT(dev), "drive"); 311 return PFLASH_CFI01(dev); 312 } 313 314 static void sbsa_flash_create(SBSAMachineState *sms) 315 { 316 sms->flash[0] = sbsa_flash_create1(sms, "sbsa.flash0", "pflash0"); 317 sms->flash[1] = sbsa_flash_create1(sms, "sbsa.flash1", "pflash1"); 318 } 319 320 static void sbsa_flash_map1(PFlashCFI01 *flash, 321 hwaddr base, hwaddr size, 322 MemoryRegion *sysmem) 323 { 324 DeviceState *dev = DEVICE(flash); 325 326 assert(QEMU_IS_ALIGNED(size, SBSA_FLASH_SECTOR_SIZE)); 327 assert(size / SBSA_FLASH_SECTOR_SIZE <= UINT32_MAX); 328 qdev_prop_set_uint32(dev, "num-blocks", size / SBSA_FLASH_SECTOR_SIZE); 329 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 330 331 memory_region_add_subregion(sysmem, base, 332 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 333 0)); 334 } 335 336 static void sbsa_flash_map(SBSAMachineState *sms, 337 MemoryRegion *sysmem, 338 MemoryRegion *secure_sysmem) 339 { 340 /* 341 * Map two flash devices to fill the SBSA_FLASH space in the memmap. 342 * sysmem is the system memory space. secure_sysmem is the secure view 343 * of the system, and the first flash device should be made visible only 344 * there. The second flash device is visible to both secure and nonsecure. 345 */ 346 hwaddr flashsize = sbsa_ref_memmap[SBSA_FLASH].size / 2; 347 hwaddr flashbase = sbsa_ref_memmap[SBSA_FLASH].base; 348 349 sbsa_flash_map1(sms->flash[0], flashbase, flashsize, 350 secure_sysmem); 351 sbsa_flash_map1(sms->flash[1], flashbase + flashsize, flashsize, 352 sysmem); 353 } 354 355 static bool sbsa_firmware_init(SBSAMachineState *sms, 356 MemoryRegion *sysmem, 357 MemoryRegion *secure_sysmem) 358 { 359 const char *bios_name; 360 int i; 361 BlockBackend *pflash_blk0; 362 363 /* Map legacy -drive if=pflash to machine properties */ 364 for (i = 0; i < ARRAY_SIZE(sms->flash); i++) { 365 pflash_cfi01_legacy_drive(sms->flash[i], 366 drive_get(IF_PFLASH, 0, i)); 367 } 368 369 sbsa_flash_map(sms, sysmem, secure_sysmem); 370 371 pflash_blk0 = pflash_cfi01_get_blk(sms->flash[0]); 372 373 bios_name = MACHINE(sms)->firmware; 374 if (bios_name) { 375 char *fname; 376 MemoryRegion *mr; 377 int image_size; 378 379 if (pflash_blk0) { 380 error_report("The contents of the first flash device may be " 381 "specified with -bios or with -drive if=pflash... " 382 "but you cannot use both options at once"); 383 exit(1); 384 } 385 386 /* Fall back to -bios */ 387 388 fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 389 if (!fname) { 390 error_report("Could not find ROM image '%s'", bios_name); 391 exit(1); 392 } 393 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(sms->flash[0]), 0); 394 image_size = load_image_mr(fname, mr); 395 g_free(fname); 396 if (image_size < 0) { 397 error_report("Could not load ROM image '%s'", bios_name); 398 exit(1); 399 } 400 } 401 402 return pflash_blk0 || bios_name; 403 } 404 405 static void create_secure_ram(SBSAMachineState *sms, 406 MemoryRegion *secure_sysmem) 407 { 408 MemoryRegion *secram = g_new(MemoryRegion, 1); 409 hwaddr base = sbsa_ref_memmap[SBSA_SECURE_MEM].base; 410 hwaddr size = sbsa_ref_memmap[SBSA_SECURE_MEM].size; 411 412 memory_region_init_ram(secram, NULL, "sbsa-ref.secure-ram", size, 413 &error_fatal); 414 memory_region_add_subregion(secure_sysmem, base, secram); 415 } 416 417 static void create_its(SBSAMachineState *sms) 418 { 419 const char *itsclass = its_class_name(); 420 DeviceState *dev; 421 422 dev = qdev_new(itsclass); 423 424 object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(sms->gic), 425 &error_abort); 426 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 427 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, sbsa_ref_memmap[SBSA_GIC_ITS].base); 428 } 429 430 static void create_gic(SBSAMachineState *sms, MemoryRegion *mem) 431 { 432 unsigned int smp_cpus = MACHINE(sms)->smp.cpus; 433 SysBusDevice *gicbusdev; 434 const char *gictype; 435 uint32_t redist0_capacity, redist0_count; 436 QList *redist_region_count; 437 int i; 438 439 gictype = gicv3_class_name(); 440 441 sms->gic = qdev_new(gictype); 442 qdev_prop_set_uint32(sms->gic, "revision", 3); 443 qdev_prop_set_uint32(sms->gic, "num-cpu", smp_cpus); 444 /* 445 * Note that the num-irq property counts both internal and external 446 * interrupts; there are always 32 of the former (mandated by GIC spec). 447 */ 448 qdev_prop_set_uint32(sms->gic, "num-irq", NUM_IRQS + 32); 449 qdev_prop_set_bit(sms->gic, "has-security-extensions", true); 450 451 redist0_capacity = 452 sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE; 453 redist0_count = MIN(smp_cpus, redist0_capacity); 454 455 redist_region_count = qlist_new(); 456 qlist_append_int(redist_region_count, redist0_count); 457 qdev_prop_set_array(sms->gic, "redist-region-count", redist_region_count); 458 459 object_property_set_link(OBJECT(sms->gic), "sysmem", 460 OBJECT(mem), &error_fatal); 461 qdev_prop_set_bit(sms->gic, "has-lpi", true); 462 463 gicbusdev = SYS_BUS_DEVICE(sms->gic); 464 sysbus_realize_and_unref(gicbusdev, &error_fatal); 465 sysbus_mmio_map(gicbusdev, 0, sbsa_ref_memmap[SBSA_GIC_DIST].base); 466 sysbus_mmio_map(gicbusdev, 1, sbsa_ref_memmap[SBSA_GIC_REDIST].base); 467 468 /* 469 * Wire the outputs from each CPU's generic timer and the GICv3 470 * maintenance interrupt signal to the appropriate GIC PPI inputs, 471 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. 472 */ 473 for (i = 0; i < smp_cpus; i++) { 474 DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); 475 int intidbase = NUM_IRQS + i * GIC_INTERNAL; 476 int irq; 477 /* 478 * Mapping from the output timer irq lines from the CPU to the 479 * GIC PPI inputs used for this board. 480 */ 481 const int timer_irq[] = { 482 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 483 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 484 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 485 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 486 [GTIMER_HYPVIRT] = ARCH_TIMER_NS_EL2_VIRT_IRQ, 487 }; 488 489 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 490 qdev_connect_gpio_out(cpudev, irq, 491 qdev_get_gpio_in(sms->gic, 492 intidbase + timer_irq[irq])); 493 } 494 495 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0, 496 qdev_get_gpio_in(sms->gic, 497 intidbase 498 + ARCH_GIC_MAINT_IRQ)); 499 500 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 501 qdev_get_gpio_in(sms->gic, 502 intidbase 503 + VIRTUAL_PMU_IRQ)); 504 505 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 506 sysbus_connect_irq(gicbusdev, i + smp_cpus, 507 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 508 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, 509 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 510 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, 511 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 512 } 513 create_its(sms); 514 } 515 516 static void create_uart(const SBSAMachineState *sms, int uart, 517 MemoryRegion *mem, Chardev *chr) 518 { 519 hwaddr base = sbsa_ref_memmap[uart].base; 520 int irq = sbsa_ref_irqmap[uart]; 521 DeviceState *dev = qdev_new(TYPE_PL011); 522 SysBusDevice *s = SYS_BUS_DEVICE(dev); 523 524 qdev_prop_set_chr(dev, "chardev", chr); 525 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 526 memory_region_add_subregion(mem, base, 527 sysbus_mmio_get_region(s, 0)); 528 sysbus_connect_irq(s, 0, qdev_get_gpio_in(sms->gic, irq)); 529 } 530 531 static void create_rtc(const SBSAMachineState *sms) 532 { 533 hwaddr base = sbsa_ref_memmap[SBSA_RTC].base; 534 int irq = sbsa_ref_irqmap[SBSA_RTC]; 535 536 sysbus_create_simple("pl031", base, qdev_get_gpio_in(sms->gic, irq)); 537 } 538 539 static void create_wdt(const SBSAMachineState *sms) 540 { 541 hwaddr rbase = sbsa_ref_memmap[SBSA_GWDT_REFRESH].base; 542 hwaddr cbase = sbsa_ref_memmap[SBSA_GWDT_CONTROL].base; 543 DeviceState *dev = qdev_new(TYPE_WDT_SBSA); 544 SysBusDevice *s = SYS_BUS_DEVICE(dev); 545 int irq = sbsa_ref_irqmap[SBSA_GWDT_WS0]; 546 547 qdev_prop_set_uint64(dev, "clock-frequency", SBSA_GTIMER_HZ); 548 sysbus_realize_and_unref(s, &error_fatal); 549 sysbus_mmio_map(s, 0, rbase); 550 sysbus_mmio_map(s, 1, cbase); 551 sysbus_connect_irq(s, 0, qdev_get_gpio_in(sms->gic, irq)); 552 } 553 554 static DeviceState *gpio_key_dev; 555 static void sbsa_ref_powerdown_req(Notifier *n, void *opaque) 556 { 557 /* use gpio Pin 3 for power button event */ 558 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); 559 } 560 561 static Notifier sbsa_ref_powerdown_notifier = { 562 .notify = sbsa_ref_powerdown_req 563 }; 564 565 static void create_gpio(const SBSAMachineState *sms) 566 { 567 DeviceState *pl061_dev; 568 hwaddr base = sbsa_ref_memmap[SBSA_GPIO].base; 569 int irq = sbsa_ref_irqmap[SBSA_GPIO]; 570 571 pl061_dev = sysbus_create_simple("pl061", base, 572 qdev_get_gpio_in(sms->gic, irq)); 573 574 gpio_key_dev = sysbus_create_simple("gpio-key", -1, 575 qdev_get_gpio_in(pl061_dev, 3)); 576 577 /* connect powerdown request */ 578 qemu_register_powerdown_notifier(&sbsa_ref_powerdown_notifier); 579 } 580 581 static void create_ahci(const SBSAMachineState *sms) 582 { 583 hwaddr base = sbsa_ref_memmap[SBSA_AHCI].base; 584 int irq = sbsa_ref_irqmap[SBSA_AHCI]; 585 DeviceState *dev; 586 DriveInfo *hd[NUM_SATA_PORTS]; 587 SysbusAHCIState *sysahci; 588 589 dev = qdev_new("sysbus-ahci"); 590 qdev_prop_set_uint32(dev, "num-ports", NUM_SATA_PORTS); 591 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 592 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 593 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(sms->gic, irq)); 594 595 sysahci = SYSBUS_AHCI(dev); 596 ide_drive_get(hd, ARRAY_SIZE(hd)); 597 ahci_ide_create_devs(&sysahci->ahci, hd); 598 } 599 600 static void create_xhci(const SBSAMachineState *sms) 601 { 602 hwaddr base = sbsa_ref_memmap[SBSA_XHCI].base; 603 int irq = sbsa_ref_irqmap[SBSA_XHCI]; 604 DeviceState *dev = qdev_new(TYPE_XHCI_SYSBUS); 605 qdev_prop_set_uint32(dev, "slots", XHCI_MAXSLOTS); 606 607 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 608 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 609 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(sms->gic, irq)); 610 } 611 612 static void create_smmu(const SBSAMachineState *sms, PCIBus *bus) 613 { 614 hwaddr base = sbsa_ref_memmap[SBSA_SMMU].base; 615 int irq = sbsa_ref_irqmap[SBSA_SMMU]; 616 DeviceState *dev; 617 int i; 618 619 dev = qdev_new(TYPE_ARM_SMMUV3); 620 621 object_property_set_str(OBJECT(dev), "stage", "nested", &error_abort); 622 object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus), 623 &error_abort); 624 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 625 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 626 for (i = 0; i < NUM_SMMU_IRQS; i++) { 627 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 628 qdev_get_gpio_in(sms->gic, irq + i)); 629 } 630 } 631 632 static void create_pcie(SBSAMachineState *sms) 633 { 634 hwaddr base_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].base; 635 hwaddr size_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].size; 636 hwaddr base_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].base; 637 hwaddr size_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].size; 638 hwaddr base_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].base; 639 hwaddr size_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].size; 640 hwaddr base_pio = sbsa_ref_memmap[SBSA_PCIE_PIO].base; 641 int irq = sbsa_ref_irqmap[SBSA_PCIE]; 642 MachineClass *mc = MACHINE_GET_CLASS(sms); 643 MemoryRegion *mmio_alias, *mmio_alias_high, *mmio_reg; 644 MemoryRegion *ecam_alias, *ecam_reg; 645 DeviceState *dev; 646 PCIHostState *pci; 647 int i; 648 649 dev = qdev_new(TYPE_GPEX_HOST); 650 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 651 652 /* Map ECAM space */ 653 ecam_alias = g_new0(MemoryRegion, 1); 654 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 655 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 656 ecam_reg, 0, size_ecam); 657 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); 658 659 /* Map the MMIO space */ 660 mmio_alias = g_new0(MemoryRegion, 1); 661 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 662 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 663 mmio_reg, base_mmio, size_mmio); 664 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); 665 666 /* Map the MMIO_HIGH space */ 667 mmio_alias_high = g_new0(MemoryRegion, 1); 668 memory_region_init_alias(mmio_alias_high, OBJECT(dev), "pcie-mmio-high", 669 mmio_reg, base_mmio_high, size_mmio_high); 670 memory_region_add_subregion(get_system_memory(), base_mmio_high, 671 mmio_alias_high); 672 673 /* Map IO port space */ 674 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); 675 676 for (i = 0; i < GPEX_NUM_IRQS; i++) { 677 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 678 qdev_get_gpio_in(sms->gic, irq + i)); 679 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); 680 } 681 682 pci = PCI_HOST_BRIDGE(dev); 683 684 pci_init_nic_devices(pci->bus, mc->default_nic); 685 686 pci_create_simple(pci->bus, -1, "bochs-display"); 687 688 create_smmu(sms, pci->bus); 689 } 690 691 static void *sbsa_ref_dtb(const struct arm_boot_info *binfo, int *fdt_size) 692 { 693 const SBSAMachineState *board = container_of(binfo, SBSAMachineState, 694 bootinfo); 695 696 *fdt_size = board->fdt_size; 697 return board->fdt; 698 } 699 700 static void create_secure_ec(MemoryRegion *mem) 701 { 702 hwaddr base = sbsa_ref_memmap[SBSA_SECURE_EC].base; 703 DeviceState *dev = qdev_new("sbsa-ec"); 704 SysBusDevice *s = SYS_BUS_DEVICE(dev); 705 706 memory_region_add_subregion(mem, base, 707 sysbus_mmio_get_region(s, 0)); 708 } 709 710 static void sbsa_ref_init(MachineState *machine) 711 { 712 unsigned int smp_cpus = machine->smp.cpus; 713 unsigned int max_cpus = machine->smp.max_cpus; 714 SBSAMachineState *sms = SBSA_MACHINE(machine); 715 MachineClass *mc = MACHINE_GET_CLASS(machine); 716 MemoryRegion *sysmem = get_system_memory(); 717 MemoryRegion *secure_sysmem = g_new(MemoryRegion, 1); 718 bool firmware_loaded; 719 const CPUArchIdList *possible_cpus; 720 int n, sbsa_max_cpus; 721 722 if (kvm_enabled()) { 723 error_report("sbsa-ref: KVM is not supported for this machine"); 724 exit(1); 725 } 726 727 /* 728 * The Secure view of the world is the same as the NonSecure, 729 * but with a few extra devices. Create it as a container region 730 * containing the system memory at low priority; any secure-only 731 * devices go in at higher priority and take precedence. 732 */ 733 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", 734 UINT64_MAX); 735 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); 736 737 firmware_loaded = sbsa_firmware_init(sms, sysmem, secure_sysmem); 738 739 /* 740 * This machine has EL3 enabled, external firmware should supply PSCI 741 * implementation, so the QEMU's internal PSCI is disabled. 742 */ 743 sms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; 744 745 sbsa_max_cpus = sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE; 746 747 if (max_cpus > sbsa_max_cpus) { 748 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " 749 "supported by machine 'sbsa-ref' (%d)", 750 max_cpus, sbsa_max_cpus); 751 exit(1); 752 } 753 754 sms->smp_cpus = smp_cpus; 755 756 if (machine->ram_size > sbsa_ref_memmap[SBSA_MEM].size) { 757 error_report("sbsa-ref: cannot model more than %dGB RAM", RAMLIMIT_GB); 758 exit(1); 759 } 760 761 possible_cpus = mc->possible_cpu_arch_ids(machine); 762 for (n = 0; n < possible_cpus->len; n++) { 763 Object *cpuobj; 764 CPUState *cs; 765 766 if (n >= smp_cpus) { 767 break; 768 } 769 770 cpuobj = object_new(possible_cpus->cpus[n].type); 771 object_property_set_int(cpuobj, "mp-affinity", 772 possible_cpus->cpus[n].arch_id, NULL); 773 774 cs = CPU(cpuobj); 775 cs->cpu_index = n; 776 777 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj), 778 &error_fatal); 779 780 if (object_property_find(cpuobj, "reset-cbar")) { 781 object_property_set_int(cpuobj, "reset-cbar", 782 sbsa_ref_memmap[SBSA_CPUPERIPHS].base, 783 &error_abort); 784 } 785 786 object_property_set_int(cpuobj, "cntfrq", SBSA_GTIMER_HZ, &error_abort); 787 788 object_property_set_link(cpuobj, "memory", OBJECT(sysmem), 789 &error_abort); 790 791 object_property_set_link(cpuobj, "secure-memory", 792 OBJECT(secure_sysmem), &error_abort); 793 794 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); 795 object_unref(cpuobj); 796 } 797 798 memory_region_add_subregion(sysmem, sbsa_ref_memmap[SBSA_MEM].base, 799 machine->ram); 800 801 create_fdt(sms); 802 803 create_secure_ram(sms, secure_sysmem); 804 805 create_gic(sms, sysmem); 806 807 create_uart(sms, SBSA_UART, sysmem, serial_hd(0)); 808 create_uart(sms, SBSA_SECURE_UART, secure_sysmem, serial_hd(1)); 809 /* Second secure UART for RAS and MM from EL0 */ 810 create_uart(sms, SBSA_SECURE_UART_MM, secure_sysmem, serial_hd(2)); 811 812 create_rtc(sms); 813 814 create_wdt(sms); 815 816 create_gpio(sms); 817 818 create_ahci(sms); 819 820 create_xhci(sms); 821 822 create_pcie(sms); 823 824 create_secure_ec(secure_sysmem); 825 826 sms->bootinfo.ram_size = machine->ram_size; 827 sms->bootinfo.board_id = -1; 828 sms->bootinfo.loader_start = sbsa_ref_memmap[SBSA_MEM].base; 829 sms->bootinfo.get_dtb = sbsa_ref_dtb; 830 sms->bootinfo.firmware_loaded = firmware_loaded; 831 arm_load_kernel(ARM_CPU(first_cpu), machine, &sms->bootinfo); 832 } 833 834 static const CPUArchIdList *sbsa_ref_possible_cpu_arch_ids(MachineState *ms) 835 { 836 unsigned int max_cpus = ms->smp.max_cpus; 837 SBSAMachineState *sms = SBSA_MACHINE(ms); 838 int n; 839 840 if (ms->possible_cpus) { 841 assert(ms->possible_cpus->len == max_cpus); 842 return ms->possible_cpus; 843 } 844 845 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 846 sizeof(CPUArchId) * max_cpus); 847 ms->possible_cpus->len = max_cpus; 848 for (n = 0; n < ms->possible_cpus->len; n++) { 849 ms->possible_cpus->cpus[n].type = ms->cpu_type; 850 ms->possible_cpus->cpus[n].arch_id = 851 sbsa_ref_cpu_mp_affinity(sms, n); 852 ms->possible_cpus->cpus[n].props.has_thread_id = true; 853 ms->possible_cpus->cpus[n].props.thread_id = n; 854 } 855 return ms->possible_cpus; 856 } 857 858 static CpuInstanceProperties 859 sbsa_ref_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 860 { 861 MachineClass *mc = MACHINE_GET_CLASS(ms); 862 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 863 864 assert(cpu_index < possible_cpus->len); 865 return possible_cpus->cpus[cpu_index].props; 866 } 867 868 static int64_t 869 sbsa_ref_get_default_cpu_node_id(const MachineState *ms, int idx) 870 { 871 return idx % ms->numa_state->num_nodes; 872 } 873 874 static void sbsa_ref_instance_init(Object *obj) 875 { 876 SBSAMachineState *sms = SBSA_MACHINE(obj); 877 878 sbsa_flash_create(sms); 879 } 880 881 static void sbsa_ref_class_init(ObjectClass *oc, void *data) 882 { 883 MachineClass *mc = MACHINE_CLASS(oc); 884 static const char * const valid_cpu_types[] = { 885 ARM_CPU_TYPE_NAME("cortex-a57"), 886 ARM_CPU_TYPE_NAME("cortex-a72"), 887 ARM_CPU_TYPE_NAME("neoverse-n1"), 888 ARM_CPU_TYPE_NAME("neoverse-v1"), 889 ARM_CPU_TYPE_NAME("neoverse-n2"), 890 ARM_CPU_TYPE_NAME("max"), 891 NULL, 892 }; 893 894 mc->init = sbsa_ref_init; 895 mc->desc = "QEMU 'SBSA Reference' ARM Virtual Machine"; 896 mc->default_cpu_type = ARM_CPU_TYPE_NAME("neoverse-n2"); 897 mc->valid_cpu_types = valid_cpu_types; 898 mc->max_cpus = 512; 899 mc->pci_allow_0_address = true; 900 mc->minimum_page_bits = 12; 901 mc->block_default_type = IF_IDE; 902 mc->no_cdrom = 1; 903 mc->default_nic = "e1000e"; 904 mc->default_ram_size = 1 * GiB; 905 mc->default_ram_id = "sbsa-ref.ram"; 906 mc->default_cpus = 4; 907 mc->smp_props.clusters_supported = true; 908 mc->possible_cpu_arch_ids = sbsa_ref_possible_cpu_arch_ids; 909 mc->cpu_index_to_instance_props = sbsa_ref_cpu_index_to_props; 910 mc->get_default_cpu_node_id = sbsa_ref_get_default_cpu_node_id; 911 /* platform instead of architectural choice */ 912 mc->cpu_cluster_has_numa_boundary = true; 913 } 914 915 static const TypeInfo sbsa_ref_info = { 916 .name = TYPE_SBSA_MACHINE, 917 .parent = TYPE_MACHINE, 918 .instance_init = sbsa_ref_instance_init, 919 .class_init = sbsa_ref_class_init, 920 .instance_size = sizeof(SBSAMachineState), 921 }; 922 923 static void sbsa_ref_machine_init(void) 924 { 925 type_register_static(&sbsa_ref_info); 926 } 927 928 type_init(sbsa_ref_machine_init); 929