1 /* 2 * ARM SBSA Reference Platform emulation 3 * 4 * Copyright (c) 2018 Linaro Limited 5 * Written by Hongbo Zhang <hongbo.zhang@linaro.org> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu-common.h" 22 #include "qapi/error.h" 23 #include "qemu/error-report.h" 24 #include "qemu/units.h" 25 #include "sysemu/device_tree.h" 26 #include "sysemu/numa.h" 27 #include "sysemu/runstate.h" 28 #include "sysemu/sysemu.h" 29 #include "exec/address-spaces.h" 30 #include "exec/hwaddr.h" 31 #include "kvm_arm.h" 32 #include "hw/arm/boot.h" 33 #include "hw/block/flash.h" 34 #include "hw/boards.h" 35 #include "hw/ide/internal.h" 36 #include "hw/ide/ahci_internal.h" 37 #include "hw/intc/arm_gicv3_common.h" 38 #include "hw/loader.h" 39 #include "hw/pci-host/gpex.h" 40 #include "hw/qdev-properties.h" 41 #include "hw/usb.h" 42 #include "hw/char/pl011.h" 43 #include "net/net.h" 44 #include "qom/object.h" 45 46 #define RAMLIMIT_GB 8192 47 #define RAMLIMIT_BYTES (RAMLIMIT_GB * GiB) 48 49 #define NUM_IRQS 256 50 #define NUM_SMMU_IRQS 4 51 #define NUM_SATA_PORTS 6 52 53 #define VIRTUAL_PMU_IRQ 7 54 #define ARCH_GIC_MAINT_IRQ 9 55 #define ARCH_TIMER_VIRT_IRQ 11 56 #define ARCH_TIMER_S_EL1_IRQ 13 57 #define ARCH_TIMER_NS_EL1_IRQ 14 58 #define ARCH_TIMER_NS_EL2_IRQ 10 59 60 enum { 61 SBSA_FLASH, 62 SBSA_MEM, 63 SBSA_CPUPERIPHS, 64 SBSA_GIC_DIST, 65 SBSA_GIC_REDIST, 66 SBSA_SECURE_EC, 67 SBSA_SMMU, 68 SBSA_UART, 69 SBSA_RTC, 70 SBSA_PCIE, 71 SBSA_PCIE_MMIO, 72 SBSA_PCIE_MMIO_HIGH, 73 SBSA_PCIE_PIO, 74 SBSA_PCIE_ECAM, 75 SBSA_GPIO, 76 SBSA_SECURE_UART, 77 SBSA_SECURE_UART_MM, 78 SBSA_SECURE_MEM, 79 SBSA_AHCI, 80 SBSA_EHCI, 81 }; 82 83 struct SBSAMachineState { 84 MachineState parent; 85 struct arm_boot_info bootinfo; 86 int smp_cpus; 87 void *fdt; 88 int fdt_size; 89 int psci_conduit; 90 DeviceState *gic; 91 PFlashCFI01 *flash[2]; 92 }; 93 94 #define TYPE_SBSA_MACHINE MACHINE_TYPE_NAME("sbsa-ref") 95 OBJECT_DECLARE_SIMPLE_TYPE(SBSAMachineState, SBSA_MACHINE) 96 97 static const MemMapEntry sbsa_ref_memmap[] = { 98 /* 512M boot ROM */ 99 [SBSA_FLASH] = { 0, 0x20000000 }, 100 /* 512M secure memory */ 101 [SBSA_SECURE_MEM] = { 0x20000000, 0x20000000 }, 102 /* Space reserved for CPU peripheral devices */ 103 [SBSA_CPUPERIPHS] = { 0x40000000, 0x00040000 }, 104 [SBSA_GIC_DIST] = { 0x40060000, 0x00010000 }, 105 [SBSA_GIC_REDIST] = { 0x40080000, 0x04000000 }, 106 [SBSA_SECURE_EC] = { 0x50000000, 0x00001000 }, 107 [SBSA_UART] = { 0x60000000, 0x00001000 }, 108 [SBSA_RTC] = { 0x60010000, 0x00001000 }, 109 [SBSA_GPIO] = { 0x60020000, 0x00001000 }, 110 [SBSA_SECURE_UART] = { 0x60030000, 0x00001000 }, 111 [SBSA_SECURE_UART_MM] = { 0x60040000, 0x00001000 }, 112 [SBSA_SMMU] = { 0x60050000, 0x00020000 }, 113 /* Space here reserved for more SMMUs */ 114 [SBSA_AHCI] = { 0x60100000, 0x00010000 }, 115 [SBSA_EHCI] = { 0x60110000, 0x00010000 }, 116 /* Space here reserved for other devices */ 117 [SBSA_PCIE_PIO] = { 0x7fff0000, 0x00010000 }, 118 /* 32-bit address PCIE MMIO space */ 119 [SBSA_PCIE_MMIO] = { 0x80000000, 0x70000000 }, 120 /* 256M PCIE ECAM space */ 121 [SBSA_PCIE_ECAM] = { 0xf0000000, 0x10000000 }, 122 /* ~1TB PCIE MMIO space (4GB to 1024GB boundary) */ 123 [SBSA_PCIE_MMIO_HIGH] = { 0x100000000ULL, 0xFF00000000ULL }, 124 [SBSA_MEM] = { 0x10000000000ULL, RAMLIMIT_BYTES }, 125 }; 126 127 static const int sbsa_ref_irqmap[] = { 128 [SBSA_UART] = 1, 129 [SBSA_RTC] = 2, 130 [SBSA_PCIE] = 3, /* ... to 6 */ 131 [SBSA_GPIO] = 7, 132 [SBSA_SECURE_UART] = 8, 133 [SBSA_SECURE_UART_MM] = 9, 134 [SBSA_AHCI] = 10, 135 [SBSA_EHCI] = 11, 136 [SBSA_SMMU] = 12, /* ... to 15 */ 137 }; 138 139 static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx) 140 { 141 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER; 142 return arm_cpu_mp_affinity(idx, clustersz); 143 } 144 145 /* 146 * Firmware on this machine only uses ACPI table to load OS, these limited 147 * device tree nodes are just to let firmware know the info which varies from 148 * command line parameters, so it is not necessary to be fully compatible 149 * with the kernel CPU and NUMA binding rules. 150 */ 151 static void create_fdt(SBSAMachineState *sms) 152 { 153 void *fdt = create_device_tree(&sms->fdt_size); 154 const MachineState *ms = MACHINE(sms); 155 int nb_numa_nodes = ms->numa_state->num_nodes; 156 int cpu; 157 158 if (!fdt) { 159 error_report("create_device_tree() failed"); 160 exit(1); 161 } 162 163 sms->fdt = fdt; 164 165 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,sbsa-ref"); 166 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 167 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 168 169 if (ms->numa_state->have_numa_distance) { 170 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); 171 uint32_t *matrix = g_malloc0(size); 172 int idx, i, j; 173 174 for (i = 0; i < nb_numa_nodes; i++) { 175 for (j = 0; j < nb_numa_nodes; j++) { 176 idx = (i * nb_numa_nodes + j) * 3; 177 matrix[idx + 0] = cpu_to_be32(i); 178 matrix[idx + 1] = cpu_to_be32(j); 179 matrix[idx + 2] = 180 cpu_to_be32(ms->numa_state->nodes[i].distance[j]); 181 } 182 } 183 184 qemu_fdt_add_subnode(fdt, "/distance-map"); 185 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", 186 matrix, size); 187 g_free(matrix); 188 } 189 190 /* 191 * From Documentation/devicetree/bindings/arm/cpus.yaml 192 * On ARM v8 64-bit systems this property is required 193 * and matches the MPIDR_EL1 register affinity bits. 194 * 195 * * If cpus node's #address-cells property is set to 2 196 * 197 * The first reg cell bits [7:0] must be set to 198 * bits [39:32] of MPIDR_EL1. 199 * 200 * The second reg cell bits [23:0] must be set to 201 * bits [23:0] of MPIDR_EL1. 202 */ 203 qemu_fdt_add_subnode(sms->fdt, "/cpus"); 204 qemu_fdt_setprop_cell(sms->fdt, "/cpus", "#address-cells", 2); 205 qemu_fdt_setprop_cell(sms->fdt, "/cpus", "#size-cells", 0x0); 206 207 for (cpu = sms->smp_cpus - 1; cpu >= 0; cpu--) { 208 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 209 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 210 CPUState *cs = CPU(armcpu); 211 uint64_t mpidr = sbsa_ref_cpu_mp_affinity(sms, cpu); 212 213 qemu_fdt_add_subnode(sms->fdt, nodename); 214 qemu_fdt_setprop_u64(sms->fdt, nodename, "reg", mpidr); 215 216 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 217 qemu_fdt_setprop_cell(sms->fdt, nodename, "numa-node-id", 218 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 219 } 220 221 g_free(nodename); 222 } 223 } 224 225 #define SBSA_FLASH_SECTOR_SIZE (256 * KiB) 226 227 static PFlashCFI01 *sbsa_flash_create1(SBSAMachineState *sms, 228 const char *name, 229 const char *alias_prop_name) 230 { 231 /* 232 * Create a single flash device. We use the same parameters as 233 * the flash devices on the Versatile Express board. 234 */ 235 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 236 237 qdev_prop_set_uint64(dev, "sector-length", SBSA_FLASH_SECTOR_SIZE); 238 qdev_prop_set_uint8(dev, "width", 4); 239 qdev_prop_set_uint8(dev, "device-width", 2); 240 qdev_prop_set_bit(dev, "big-endian", false); 241 qdev_prop_set_uint16(dev, "id0", 0x89); 242 qdev_prop_set_uint16(dev, "id1", 0x18); 243 qdev_prop_set_uint16(dev, "id2", 0x00); 244 qdev_prop_set_uint16(dev, "id3", 0x00); 245 qdev_prop_set_string(dev, "name", name); 246 object_property_add_child(OBJECT(sms), name, OBJECT(dev)); 247 object_property_add_alias(OBJECT(sms), alias_prop_name, 248 OBJECT(dev), "drive"); 249 return PFLASH_CFI01(dev); 250 } 251 252 static void sbsa_flash_create(SBSAMachineState *sms) 253 { 254 sms->flash[0] = sbsa_flash_create1(sms, "sbsa.flash0", "pflash0"); 255 sms->flash[1] = sbsa_flash_create1(sms, "sbsa.flash1", "pflash1"); 256 } 257 258 static void sbsa_flash_map1(PFlashCFI01 *flash, 259 hwaddr base, hwaddr size, 260 MemoryRegion *sysmem) 261 { 262 DeviceState *dev = DEVICE(flash); 263 264 assert(QEMU_IS_ALIGNED(size, SBSA_FLASH_SECTOR_SIZE)); 265 assert(size / SBSA_FLASH_SECTOR_SIZE <= UINT32_MAX); 266 qdev_prop_set_uint32(dev, "num-blocks", size / SBSA_FLASH_SECTOR_SIZE); 267 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 268 269 memory_region_add_subregion(sysmem, base, 270 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 271 0)); 272 } 273 274 static void sbsa_flash_map(SBSAMachineState *sms, 275 MemoryRegion *sysmem, 276 MemoryRegion *secure_sysmem) 277 { 278 /* 279 * Map two flash devices to fill the SBSA_FLASH space in the memmap. 280 * sysmem is the system memory space. secure_sysmem is the secure view 281 * of the system, and the first flash device should be made visible only 282 * there. The second flash device is visible to both secure and nonsecure. 283 */ 284 hwaddr flashsize = sbsa_ref_memmap[SBSA_FLASH].size / 2; 285 hwaddr flashbase = sbsa_ref_memmap[SBSA_FLASH].base; 286 287 sbsa_flash_map1(sms->flash[0], flashbase, flashsize, 288 secure_sysmem); 289 sbsa_flash_map1(sms->flash[1], flashbase + flashsize, flashsize, 290 sysmem); 291 } 292 293 static bool sbsa_firmware_init(SBSAMachineState *sms, 294 MemoryRegion *sysmem, 295 MemoryRegion *secure_sysmem) 296 { 297 int i; 298 BlockBackend *pflash_blk0; 299 300 /* Map legacy -drive if=pflash to machine properties */ 301 for (i = 0; i < ARRAY_SIZE(sms->flash); i++) { 302 pflash_cfi01_legacy_drive(sms->flash[i], 303 drive_get(IF_PFLASH, 0, i)); 304 } 305 306 sbsa_flash_map(sms, sysmem, secure_sysmem); 307 308 pflash_blk0 = pflash_cfi01_get_blk(sms->flash[0]); 309 310 if (bios_name) { 311 char *fname; 312 MemoryRegion *mr; 313 int image_size; 314 315 if (pflash_blk0) { 316 error_report("The contents of the first flash device may be " 317 "specified with -bios or with -drive if=pflash... " 318 "but you cannot use both options at once"); 319 exit(1); 320 } 321 322 /* Fall back to -bios */ 323 324 fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 325 if (!fname) { 326 error_report("Could not find ROM image '%s'", bios_name); 327 exit(1); 328 } 329 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(sms->flash[0]), 0); 330 image_size = load_image_mr(fname, mr); 331 g_free(fname); 332 if (image_size < 0) { 333 error_report("Could not load ROM image '%s'", bios_name); 334 exit(1); 335 } 336 } 337 338 return pflash_blk0 || bios_name; 339 } 340 341 static void create_secure_ram(SBSAMachineState *sms, 342 MemoryRegion *secure_sysmem) 343 { 344 MemoryRegion *secram = g_new(MemoryRegion, 1); 345 hwaddr base = sbsa_ref_memmap[SBSA_SECURE_MEM].base; 346 hwaddr size = sbsa_ref_memmap[SBSA_SECURE_MEM].size; 347 348 memory_region_init_ram(secram, NULL, "sbsa-ref.secure-ram", size, 349 &error_fatal); 350 memory_region_add_subregion(secure_sysmem, base, secram); 351 } 352 353 static void create_gic(SBSAMachineState *sms) 354 { 355 unsigned int smp_cpus = MACHINE(sms)->smp.cpus; 356 SysBusDevice *gicbusdev; 357 const char *gictype; 358 uint32_t redist0_capacity, redist0_count; 359 int i; 360 361 gictype = gicv3_class_name(); 362 363 sms->gic = qdev_new(gictype); 364 qdev_prop_set_uint32(sms->gic, "revision", 3); 365 qdev_prop_set_uint32(sms->gic, "num-cpu", smp_cpus); 366 /* 367 * Note that the num-irq property counts both internal and external 368 * interrupts; there are always 32 of the former (mandated by GIC spec). 369 */ 370 qdev_prop_set_uint32(sms->gic, "num-irq", NUM_IRQS + 32); 371 qdev_prop_set_bit(sms->gic, "has-security-extensions", true); 372 373 redist0_capacity = 374 sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE; 375 redist0_count = MIN(smp_cpus, redist0_capacity); 376 377 qdev_prop_set_uint32(sms->gic, "len-redist-region-count", 1); 378 qdev_prop_set_uint32(sms->gic, "redist-region-count[0]", redist0_count); 379 380 gicbusdev = SYS_BUS_DEVICE(sms->gic); 381 sysbus_realize_and_unref(gicbusdev, &error_fatal); 382 sysbus_mmio_map(gicbusdev, 0, sbsa_ref_memmap[SBSA_GIC_DIST].base); 383 sysbus_mmio_map(gicbusdev, 1, sbsa_ref_memmap[SBSA_GIC_REDIST].base); 384 385 /* 386 * Wire the outputs from each CPU's generic timer and the GICv3 387 * maintenance interrupt signal to the appropriate GIC PPI inputs, 388 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. 389 */ 390 for (i = 0; i < smp_cpus; i++) { 391 DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); 392 int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; 393 int irq; 394 /* 395 * Mapping from the output timer irq lines from the CPU to the 396 * GIC PPI inputs used for this board. 397 */ 398 const int timer_irq[] = { 399 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 400 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 401 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 402 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 403 }; 404 405 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 406 qdev_connect_gpio_out(cpudev, irq, 407 qdev_get_gpio_in(sms->gic, 408 ppibase + timer_irq[irq])); 409 } 410 411 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0, 412 qdev_get_gpio_in(sms->gic, ppibase 413 + ARCH_GIC_MAINT_IRQ)); 414 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 415 qdev_get_gpio_in(sms->gic, ppibase 416 + VIRTUAL_PMU_IRQ)); 417 418 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 419 sysbus_connect_irq(gicbusdev, i + smp_cpus, 420 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 421 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, 422 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 423 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, 424 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 425 } 426 } 427 428 static void create_uart(const SBSAMachineState *sms, int uart, 429 MemoryRegion *mem, Chardev *chr) 430 { 431 hwaddr base = sbsa_ref_memmap[uart].base; 432 int irq = sbsa_ref_irqmap[uart]; 433 DeviceState *dev = qdev_new(TYPE_PL011); 434 SysBusDevice *s = SYS_BUS_DEVICE(dev); 435 436 qdev_prop_set_chr(dev, "chardev", chr); 437 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 438 memory_region_add_subregion(mem, base, 439 sysbus_mmio_get_region(s, 0)); 440 sysbus_connect_irq(s, 0, qdev_get_gpio_in(sms->gic, irq)); 441 } 442 443 static void create_rtc(const SBSAMachineState *sms) 444 { 445 hwaddr base = sbsa_ref_memmap[SBSA_RTC].base; 446 int irq = sbsa_ref_irqmap[SBSA_RTC]; 447 448 sysbus_create_simple("pl031", base, qdev_get_gpio_in(sms->gic, irq)); 449 } 450 451 static DeviceState *gpio_key_dev; 452 static void sbsa_ref_powerdown_req(Notifier *n, void *opaque) 453 { 454 /* use gpio Pin 3 for power button event */ 455 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); 456 } 457 458 static Notifier sbsa_ref_powerdown_notifier = { 459 .notify = sbsa_ref_powerdown_req 460 }; 461 462 static void create_gpio(const SBSAMachineState *sms) 463 { 464 DeviceState *pl061_dev; 465 hwaddr base = sbsa_ref_memmap[SBSA_GPIO].base; 466 int irq = sbsa_ref_irqmap[SBSA_GPIO]; 467 468 pl061_dev = sysbus_create_simple("pl061", base, 469 qdev_get_gpio_in(sms->gic, irq)); 470 471 gpio_key_dev = sysbus_create_simple("gpio-key", -1, 472 qdev_get_gpio_in(pl061_dev, 3)); 473 474 /* connect powerdown request */ 475 qemu_register_powerdown_notifier(&sbsa_ref_powerdown_notifier); 476 } 477 478 static void create_ahci(const SBSAMachineState *sms) 479 { 480 hwaddr base = sbsa_ref_memmap[SBSA_AHCI].base; 481 int irq = sbsa_ref_irqmap[SBSA_AHCI]; 482 DeviceState *dev; 483 DriveInfo *hd[NUM_SATA_PORTS]; 484 SysbusAHCIState *sysahci; 485 AHCIState *ahci; 486 int i; 487 488 dev = qdev_new("sysbus-ahci"); 489 qdev_prop_set_uint32(dev, "num-ports", NUM_SATA_PORTS); 490 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 491 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 492 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(sms->gic, irq)); 493 494 sysahci = SYSBUS_AHCI(dev); 495 ahci = &sysahci->ahci; 496 ide_drive_get(hd, ARRAY_SIZE(hd)); 497 for (i = 0; i < ahci->ports; i++) { 498 if (hd[i] == NULL) { 499 continue; 500 } 501 ide_create_drive(&ahci->dev[i].port, 0, hd[i]); 502 } 503 } 504 505 static void create_ehci(const SBSAMachineState *sms) 506 { 507 hwaddr base = sbsa_ref_memmap[SBSA_EHCI].base; 508 int irq = sbsa_ref_irqmap[SBSA_EHCI]; 509 510 sysbus_create_simple("platform-ehci-usb", base, 511 qdev_get_gpio_in(sms->gic, irq)); 512 } 513 514 static void create_smmu(const SBSAMachineState *sms, PCIBus *bus) 515 { 516 hwaddr base = sbsa_ref_memmap[SBSA_SMMU].base; 517 int irq = sbsa_ref_irqmap[SBSA_SMMU]; 518 DeviceState *dev; 519 int i; 520 521 dev = qdev_new("arm-smmuv3"); 522 523 object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus), 524 &error_abort); 525 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 526 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 527 for (i = 0; i < NUM_SMMU_IRQS; i++) { 528 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 529 qdev_get_gpio_in(sms->gic, irq + i)); 530 } 531 } 532 533 static void create_pcie(SBSAMachineState *sms) 534 { 535 hwaddr base_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].base; 536 hwaddr size_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].size; 537 hwaddr base_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].base; 538 hwaddr size_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].size; 539 hwaddr base_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].base; 540 hwaddr size_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].size; 541 hwaddr base_pio = sbsa_ref_memmap[SBSA_PCIE_PIO].base; 542 int irq = sbsa_ref_irqmap[SBSA_PCIE]; 543 MemoryRegion *mmio_alias, *mmio_alias_high, *mmio_reg; 544 MemoryRegion *ecam_alias, *ecam_reg; 545 DeviceState *dev; 546 PCIHostState *pci; 547 int i; 548 549 dev = qdev_new(TYPE_GPEX_HOST); 550 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 551 552 /* Map ECAM space */ 553 ecam_alias = g_new0(MemoryRegion, 1); 554 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 555 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 556 ecam_reg, 0, size_ecam); 557 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); 558 559 /* Map the MMIO space */ 560 mmio_alias = g_new0(MemoryRegion, 1); 561 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 562 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 563 mmio_reg, base_mmio, size_mmio); 564 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); 565 566 /* Map the MMIO_HIGH space */ 567 mmio_alias_high = g_new0(MemoryRegion, 1); 568 memory_region_init_alias(mmio_alias_high, OBJECT(dev), "pcie-mmio-high", 569 mmio_reg, base_mmio_high, size_mmio_high); 570 memory_region_add_subregion(get_system_memory(), base_mmio_high, 571 mmio_alias_high); 572 573 /* Map IO port space */ 574 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); 575 576 for (i = 0; i < GPEX_NUM_IRQS; i++) { 577 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 578 qdev_get_gpio_in(sms->gic, irq + i)); 579 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); 580 } 581 582 pci = PCI_HOST_BRIDGE(dev); 583 if (pci->bus) { 584 for (i = 0; i < nb_nics; i++) { 585 NICInfo *nd = &nd_table[i]; 586 587 if (!nd->model) { 588 nd->model = g_strdup("e1000e"); 589 } 590 591 pci_nic_init_nofail(nd, pci->bus, nd->model, NULL); 592 } 593 } 594 595 pci_create_simple(pci->bus, -1, "VGA"); 596 597 create_smmu(sms, pci->bus); 598 } 599 600 static void *sbsa_ref_dtb(const struct arm_boot_info *binfo, int *fdt_size) 601 { 602 const SBSAMachineState *board = container_of(binfo, SBSAMachineState, 603 bootinfo); 604 605 *fdt_size = board->fdt_size; 606 return board->fdt; 607 } 608 609 static void create_secure_ec(MemoryRegion *mem) 610 { 611 hwaddr base = sbsa_ref_memmap[SBSA_SECURE_EC].base; 612 DeviceState *dev = qdev_new("sbsa-ec"); 613 SysBusDevice *s = SYS_BUS_DEVICE(dev); 614 615 memory_region_add_subregion(mem, base, 616 sysbus_mmio_get_region(s, 0)); 617 } 618 619 static void sbsa_ref_init(MachineState *machine) 620 { 621 unsigned int smp_cpus = machine->smp.cpus; 622 unsigned int max_cpus = machine->smp.max_cpus; 623 SBSAMachineState *sms = SBSA_MACHINE(machine); 624 MachineClass *mc = MACHINE_GET_CLASS(machine); 625 MemoryRegion *sysmem = get_system_memory(); 626 MemoryRegion *secure_sysmem = g_new(MemoryRegion, 1); 627 bool firmware_loaded; 628 const CPUArchIdList *possible_cpus; 629 int n, sbsa_max_cpus; 630 631 if (strcmp(machine->cpu_type, ARM_CPU_TYPE_NAME("cortex-a57"))) { 632 error_report("sbsa-ref: CPU type other than the built-in " 633 "cortex-a57 not supported"); 634 exit(1); 635 } 636 637 if (kvm_enabled()) { 638 error_report("sbsa-ref: KVM is not supported for this machine"); 639 exit(1); 640 } 641 642 /* 643 * The Secure view of the world is the same as the NonSecure, 644 * but with a few extra devices. Create it as a container region 645 * containing the system memory at low priority; any secure-only 646 * devices go in at higher priority and take precedence. 647 */ 648 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", 649 UINT64_MAX); 650 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); 651 652 firmware_loaded = sbsa_firmware_init(sms, sysmem, secure_sysmem); 653 654 if (machine->kernel_filename && firmware_loaded) { 655 error_report("sbsa-ref: No fw_cfg device on this machine, " 656 "so -kernel option is not supported when firmware loaded, " 657 "please load OS from hard disk instead"); 658 exit(1); 659 } 660 661 /* 662 * This machine has EL3 enabled, external firmware should supply PSCI 663 * implementation, so the QEMU's internal PSCI is disabled. 664 */ 665 sms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; 666 667 sbsa_max_cpus = sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE; 668 669 if (max_cpus > sbsa_max_cpus) { 670 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " 671 "supported by machine 'sbsa-ref' (%d)", 672 max_cpus, sbsa_max_cpus); 673 exit(1); 674 } 675 676 sms->smp_cpus = smp_cpus; 677 678 if (machine->ram_size > sbsa_ref_memmap[SBSA_MEM].size) { 679 error_report("sbsa-ref: cannot model more than %dGB RAM", RAMLIMIT_GB); 680 exit(1); 681 } 682 683 possible_cpus = mc->possible_cpu_arch_ids(machine); 684 for (n = 0; n < possible_cpus->len; n++) { 685 Object *cpuobj; 686 CPUState *cs; 687 688 if (n >= smp_cpus) { 689 break; 690 } 691 692 cpuobj = object_new(possible_cpus->cpus[n].type); 693 object_property_set_int(cpuobj, "mp-affinity", 694 possible_cpus->cpus[n].arch_id, NULL); 695 696 cs = CPU(cpuobj); 697 cs->cpu_index = n; 698 699 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj), 700 &error_fatal); 701 702 if (object_property_find(cpuobj, "reset-cbar")) { 703 object_property_set_int(cpuobj, "reset-cbar", 704 sbsa_ref_memmap[SBSA_CPUPERIPHS].base, 705 &error_abort); 706 } 707 708 object_property_set_link(cpuobj, "memory", OBJECT(sysmem), 709 &error_abort); 710 711 object_property_set_link(cpuobj, "secure-memory", 712 OBJECT(secure_sysmem), &error_abort); 713 714 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); 715 object_unref(cpuobj); 716 } 717 718 memory_region_add_subregion(sysmem, sbsa_ref_memmap[SBSA_MEM].base, 719 machine->ram); 720 721 create_fdt(sms); 722 723 create_secure_ram(sms, secure_sysmem); 724 725 create_gic(sms); 726 727 create_uart(sms, SBSA_UART, sysmem, serial_hd(0)); 728 create_uart(sms, SBSA_SECURE_UART, secure_sysmem, serial_hd(1)); 729 /* Second secure UART for RAS and MM from EL0 */ 730 create_uart(sms, SBSA_SECURE_UART_MM, secure_sysmem, serial_hd(2)); 731 732 create_rtc(sms); 733 734 create_gpio(sms); 735 736 create_ahci(sms); 737 738 create_ehci(sms); 739 740 create_pcie(sms); 741 742 create_secure_ec(secure_sysmem); 743 744 sms->bootinfo.ram_size = machine->ram_size; 745 sms->bootinfo.nb_cpus = smp_cpus; 746 sms->bootinfo.board_id = -1; 747 sms->bootinfo.loader_start = sbsa_ref_memmap[SBSA_MEM].base; 748 sms->bootinfo.get_dtb = sbsa_ref_dtb; 749 sms->bootinfo.firmware_loaded = firmware_loaded; 750 arm_load_kernel(ARM_CPU(first_cpu), machine, &sms->bootinfo); 751 } 752 753 static const CPUArchIdList *sbsa_ref_possible_cpu_arch_ids(MachineState *ms) 754 { 755 unsigned int max_cpus = ms->smp.max_cpus; 756 SBSAMachineState *sms = SBSA_MACHINE(ms); 757 int n; 758 759 if (ms->possible_cpus) { 760 assert(ms->possible_cpus->len == max_cpus); 761 return ms->possible_cpus; 762 } 763 764 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 765 sizeof(CPUArchId) * max_cpus); 766 ms->possible_cpus->len = max_cpus; 767 for (n = 0; n < ms->possible_cpus->len; n++) { 768 ms->possible_cpus->cpus[n].type = ms->cpu_type; 769 ms->possible_cpus->cpus[n].arch_id = 770 sbsa_ref_cpu_mp_affinity(sms, n); 771 ms->possible_cpus->cpus[n].props.has_thread_id = true; 772 ms->possible_cpus->cpus[n].props.thread_id = n; 773 } 774 return ms->possible_cpus; 775 } 776 777 static CpuInstanceProperties 778 sbsa_ref_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 779 { 780 MachineClass *mc = MACHINE_GET_CLASS(ms); 781 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 782 783 assert(cpu_index < possible_cpus->len); 784 return possible_cpus->cpus[cpu_index].props; 785 } 786 787 static int64_t 788 sbsa_ref_get_default_cpu_node_id(const MachineState *ms, int idx) 789 { 790 return idx % ms->numa_state->num_nodes; 791 } 792 793 static void sbsa_ref_instance_init(Object *obj) 794 { 795 SBSAMachineState *sms = SBSA_MACHINE(obj); 796 797 sbsa_flash_create(sms); 798 } 799 800 static void sbsa_ref_class_init(ObjectClass *oc, void *data) 801 { 802 MachineClass *mc = MACHINE_CLASS(oc); 803 804 mc->init = sbsa_ref_init; 805 mc->desc = "QEMU 'SBSA Reference' ARM Virtual Machine"; 806 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a57"); 807 mc->max_cpus = 512; 808 mc->pci_allow_0_address = true; 809 mc->minimum_page_bits = 12; 810 mc->block_default_type = IF_IDE; 811 mc->no_cdrom = 1; 812 mc->default_ram_size = 1 * GiB; 813 mc->default_ram_id = "sbsa-ref.ram"; 814 mc->default_cpus = 4; 815 mc->possible_cpu_arch_ids = sbsa_ref_possible_cpu_arch_ids; 816 mc->cpu_index_to_instance_props = sbsa_ref_cpu_index_to_props; 817 mc->get_default_cpu_node_id = sbsa_ref_get_default_cpu_node_id; 818 } 819 820 static const TypeInfo sbsa_ref_info = { 821 .name = TYPE_SBSA_MACHINE, 822 .parent = TYPE_MACHINE, 823 .instance_init = sbsa_ref_instance_init, 824 .class_init = sbsa_ref_class_init, 825 .instance_size = sizeof(SBSAMachineState), 826 }; 827 828 static void sbsa_ref_machine_init(void) 829 { 830 type_register_static(&sbsa_ref_info); 831 } 832 833 type_init(sbsa_ref_machine_init); 834