1 /* 2 * ARM SBSA Reference Platform emulation 3 * 4 * Copyright (c) 2018 Linaro Limited 5 * Written by Hongbo Zhang <hongbo.zhang@linaro.org> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu-common.h" 22 #include "qapi/error.h" 23 #include "qemu/error-report.h" 24 #include "qemu/units.h" 25 #include "sysemu/device_tree.h" 26 #include "sysemu/numa.h" 27 #include "sysemu/runstate.h" 28 #include "sysemu/sysemu.h" 29 #include "exec/address-spaces.h" 30 #include "exec/hwaddr.h" 31 #include "kvm_arm.h" 32 #include "hw/arm/boot.h" 33 #include "hw/block/flash.h" 34 #include "hw/boards.h" 35 #include "hw/ide/internal.h" 36 #include "hw/ide/ahci_internal.h" 37 #include "hw/intc/arm_gicv3_common.h" 38 #include "hw/loader.h" 39 #include "hw/pci-host/gpex.h" 40 #include "hw/qdev-properties.h" 41 #include "hw/usb.h" 42 #include "hw/char/pl011.h" 43 #include "hw/watchdog/sbsa_gwdt.h" 44 #include "net/net.h" 45 #include "qom/object.h" 46 47 #define RAMLIMIT_GB 8192 48 #define RAMLIMIT_BYTES (RAMLIMIT_GB * GiB) 49 50 #define NUM_IRQS 256 51 #define NUM_SMMU_IRQS 4 52 #define NUM_SATA_PORTS 6 53 54 #define VIRTUAL_PMU_IRQ 7 55 #define ARCH_GIC_MAINT_IRQ 9 56 #define ARCH_TIMER_VIRT_IRQ 11 57 #define ARCH_TIMER_S_EL1_IRQ 13 58 #define ARCH_TIMER_NS_EL1_IRQ 14 59 #define ARCH_TIMER_NS_EL2_IRQ 10 60 61 enum { 62 SBSA_FLASH, 63 SBSA_MEM, 64 SBSA_CPUPERIPHS, 65 SBSA_GIC_DIST, 66 SBSA_GIC_REDIST, 67 SBSA_SECURE_EC, 68 SBSA_GWDT, 69 SBSA_GWDT_REFRESH, 70 SBSA_GWDT_CONTROL, 71 SBSA_SMMU, 72 SBSA_UART, 73 SBSA_RTC, 74 SBSA_PCIE, 75 SBSA_PCIE_MMIO, 76 SBSA_PCIE_MMIO_HIGH, 77 SBSA_PCIE_PIO, 78 SBSA_PCIE_ECAM, 79 SBSA_GPIO, 80 SBSA_SECURE_UART, 81 SBSA_SECURE_UART_MM, 82 SBSA_SECURE_MEM, 83 SBSA_AHCI, 84 SBSA_EHCI, 85 }; 86 87 struct SBSAMachineState { 88 MachineState parent; 89 struct arm_boot_info bootinfo; 90 int smp_cpus; 91 void *fdt; 92 int fdt_size; 93 int psci_conduit; 94 DeviceState *gic; 95 PFlashCFI01 *flash[2]; 96 }; 97 98 #define TYPE_SBSA_MACHINE MACHINE_TYPE_NAME("sbsa-ref") 99 OBJECT_DECLARE_SIMPLE_TYPE(SBSAMachineState, SBSA_MACHINE) 100 101 static const MemMapEntry sbsa_ref_memmap[] = { 102 /* 512M boot ROM */ 103 [SBSA_FLASH] = { 0, 0x20000000 }, 104 /* 512M secure memory */ 105 [SBSA_SECURE_MEM] = { 0x20000000, 0x20000000 }, 106 /* Space reserved for CPU peripheral devices */ 107 [SBSA_CPUPERIPHS] = { 0x40000000, 0x00040000 }, 108 [SBSA_GIC_DIST] = { 0x40060000, 0x00010000 }, 109 [SBSA_GIC_REDIST] = { 0x40080000, 0x04000000 }, 110 [SBSA_SECURE_EC] = { 0x50000000, 0x00001000 }, 111 [SBSA_GWDT_REFRESH] = { 0x50010000, 0x00001000 }, 112 [SBSA_GWDT_CONTROL] = { 0x50011000, 0x00001000 }, 113 [SBSA_UART] = { 0x60000000, 0x00001000 }, 114 [SBSA_RTC] = { 0x60010000, 0x00001000 }, 115 [SBSA_GPIO] = { 0x60020000, 0x00001000 }, 116 [SBSA_SECURE_UART] = { 0x60030000, 0x00001000 }, 117 [SBSA_SECURE_UART_MM] = { 0x60040000, 0x00001000 }, 118 [SBSA_SMMU] = { 0x60050000, 0x00020000 }, 119 /* Space here reserved for more SMMUs */ 120 [SBSA_AHCI] = { 0x60100000, 0x00010000 }, 121 [SBSA_EHCI] = { 0x60110000, 0x00010000 }, 122 /* Space here reserved for other devices */ 123 [SBSA_PCIE_PIO] = { 0x7fff0000, 0x00010000 }, 124 /* 32-bit address PCIE MMIO space */ 125 [SBSA_PCIE_MMIO] = { 0x80000000, 0x70000000 }, 126 /* 256M PCIE ECAM space */ 127 [SBSA_PCIE_ECAM] = { 0xf0000000, 0x10000000 }, 128 /* ~1TB PCIE MMIO space (4GB to 1024GB boundary) */ 129 [SBSA_PCIE_MMIO_HIGH] = { 0x100000000ULL, 0xFF00000000ULL }, 130 [SBSA_MEM] = { 0x10000000000ULL, RAMLIMIT_BYTES }, 131 }; 132 133 static const int sbsa_ref_irqmap[] = { 134 [SBSA_UART] = 1, 135 [SBSA_RTC] = 2, 136 [SBSA_PCIE] = 3, /* ... to 6 */ 137 [SBSA_GPIO] = 7, 138 [SBSA_SECURE_UART] = 8, 139 [SBSA_SECURE_UART_MM] = 9, 140 [SBSA_AHCI] = 10, 141 [SBSA_EHCI] = 11, 142 [SBSA_SMMU] = 12, /* ... to 15 */ 143 [SBSA_GWDT] = 16, 144 }; 145 146 static const char * const valid_cpus[] = { 147 ARM_CPU_TYPE_NAME("cortex-a53"), 148 ARM_CPU_TYPE_NAME("cortex-a57"), 149 ARM_CPU_TYPE_NAME("cortex-a72"), 150 }; 151 152 static bool cpu_type_valid(const char *cpu) 153 { 154 int i; 155 156 for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) { 157 if (strcmp(cpu, valid_cpus[i]) == 0) { 158 return true; 159 } 160 } 161 return false; 162 } 163 164 static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx) 165 { 166 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER; 167 return arm_cpu_mp_affinity(idx, clustersz); 168 } 169 170 /* 171 * Firmware on this machine only uses ACPI table to load OS, these limited 172 * device tree nodes are just to let firmware know the info which varies from 173 * command line parameters, so it is not necessary to be fully compatible 174 * with the kernel CPU and NUMA binding rules. 175 */ 176 static void create_fdt(SBSAMachineState *sms) 177 { 178 void *fdt = create_device_tree(&sms->fdt_size); 179 const MachineState *ms = MACHINE(sms); 180 int nb_numa_nodes = ms->numa_state->num_nodes; 181 int cpu; 182 183 if (!fdt) { 184 error_report("create_device_tree() failed"); 185 exit(1); 186 } 187 188 sms->fdt = fdt; 189 190 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,sbsa-ref"); 191 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 192 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 193 194 if (ms->numa_state->have_numa_distance) { 195 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); 196 uint32_t *matrix = g_malloc0(size); 197 int idx, i, j; 198 199 for (i = 0; i < nb_numa_nodes; i++) { 200 for (j = 0; j < nb_numa_nodes; j++) { 201 idx = (i * nb_numa_nodes + j) * 3; 202 matrix[idx + 0] = cpu_to_be32(i); 203 matrix[idx + 1] = cpu_to_be32(j); 204 matrix[idx + 2] = 205 cpu_to_be32(ms->numa_state->nodes[i].distance[j]); 206 } 207 } 208 209 qemu_fdt_add_subnode(fdt, "/distance-map"); 210 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", 211 matrix, size); 212 g_free(matrix); 213 } 214 215 /* 216 * From Documentation/devicetree/bindings/arm/cpus.yaml 217 * On ARM v8 64-bit systems this property is required 218 * and matches the MPIDR_EL1 register affinity bits. 219 * 220 * * If cpus node's #address-cells property is set to 2 221 * 222 * The first reg cell bits [7:0] must be set to 223 * bits [39:32] of MPIDR_EL1. 224 * 225 * The second reg cell bits [23:0] must be set to 226 * bits [23:0] of MPIDR_EL1. 227 */ 228 qemu_fdt_add_subnode(sms->fdt, "/cpus"); 229 qemu_fdt_setprop_cell(sms->fdt, "/cpus", "#address-cells", 2); 230 qemu_fdt_setprop_cell(sms->fdt, "/cpus", "#size-cells", 0x0); 231 232 for (cpu = sms->smp_cpus - 1; cpu >= 0; cpu--) { 233 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 234 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 235 CPUState *cs = CPU(armcpu); 236 uint64_t mpidr = sbsa_ref_cpu_mp_affinity(sms, cpu); 237 238 qemu_fdt_add_subnode(sms->fdt, nodename); 239 qemu_fdt_setprop_u64(sms->fdt, nodename, "reg", mpidr); 240 241 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 242 qemu_fdt_setprop_cell(sms->fdt, nodename, "numa-node-id", 243 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 244 } 245 246 g_free(nodename); 247 } 248 } 249 250 #define SBSA_FLASH_SECTOR_SIZE (256 * KiB) 251 252 static PFlashCFI01 *sbsa_flash_create1(SBSAMachineState *sms, 253 const char *name, 254 const char *alias_prop_name) 255 { 256 /* 257 * Create a single flash device. We use the same parameters as 258 * the flash devices on the Versatile Express board. 259 */ 260 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 261 262 qdev_prop_set_uint64(dev, "sector-length", SBSA_FLASH_SECTOR_SIZE); 263 qdev_prop_set_uint8(dev, "width", 4); 264 qdev_prop_set_uint8(dev, "device-width", 2); 265 qdev_prop_set_bit(dev, "big-endian", false); 266 qdev_prop_set_uint16(dev, "id0", 0x89); 267 qdev_prop_set_uint16(dev, "id1", 0x18); 268 qdev_prop_set_uint16(dev, "id2", 0x00); 269 qdev_prop_set_uint16(dev, "id3", 0x00); 270 qdev_prop_set_string(dev, "name", name); 271 object_property_add_child(OBJECT(sms), name, OBJECT(dev)); 272 object_property_add_alias(OBJECT(sms), alias_prop_name, 273 OBJECT(dev), "drive"); 274 return PFLASH_CFI01(dev); 275 } 276 277 static void sbsa_flash_create(SBSAMachineState *sms) 278 { 279 sms->flash[0] = sbsa_flash_create1(sms, "sbsa.flash0", "pflash0"); 280 sms->flash[1] = sbsa_flash_create1(sms, "sbsa.flash1", "pflash1"); 281 } 282 283 static void sbsa_flash_map1(PFlashCFI01 *flash, 284 hwaddr base, hwaddr size, 285 MemoryRegion *sysmem) 286 { 287 DeviceState *dev = DEVICE(flash); 288 289 assert(QEMU_IS_ALIGNED(size, SBSA_FLASH_SECTOR_SIZE)); 290 assert(size / SBSA_FLASH_SECTOR_SIZE <= UINT32_MAX); 291 qdev_prop_set_uint32(dev, "num-blocks", size / SBSA_FLASH_SECTOR_SIZE); 292 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 293 294 memory_region_add_subregion(sysmem, base, 295 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 296 0)); 297 } 298 299 static void sbsa_flash_map(SBSAMachineState *sms, 300 MemoryRegion *sysmem, 301 MemoryRegion *secure_sysmem) 302 { 303 /* 304 * Map two flash devices to fill the SBSA_FLASH space in the memmap. 305 * sysmem is the system memory space. secure_sysmem is the secure view 306 * of the system, and the first flash device should be made visible only 307 * there. The second flash device is visible to both secure and nonsecure. 308 */ 309 hwaddr flashsize = sbsa_ref_memmap[SBSA_FLASH].size / 2; 310 hwaddr flashbase = sbsa_ref_memmap[SBSA_FLASH].base; 311 312 sbsa_flash_map1(sms->flash[0], flashbase, flashsize, 313 secure_sysmem); 314 sbsa_flash_map1(sms->flash[1], flashbase + flashsize, flashsize, 315 sysmem); 316 } 317 318 static bool sbsa_firmware_init(SBSAMachineState *sms, 319 MemoryRegion *sysmem, 320 MemoryRegion *secure_sysmem) 321 { 322 int i; 323 BlockBackend *pflash_blk0; 324 325 /* Map legacy -drive if=pflash to machine properties */ 326 for (i = 0; i < ARRAY_SIZE(sms->flash); i++) { 327 pflash_cfi01_legacy_drive(sms->flash[i], 328 drive_get(IF_PFLASH, 0, i)); 329 } 330 331 sbsa_flash_map(sms, sysmem, secure_sysmem); 332 333 pflash_blk0 = pflash_cfi01_get_blk(sms->flash[0]); 334 335 if (bios_name) { 336 char *fname; 337 MemoryRegion *mr; 338 int image_size; 339 340 if (pflash_blk0) { 341 error_report("The contents of the first flash device may be " 342 "specified with -bios or with -drive if=pflash... " 343 "but you cannot use both options at once"); 344 exit(1); 345 } 346 347 /* Fall back to -bios */ 348 349 fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 350 if (!fname) { 351 error_report("Could not find ROM image '%s'", bios_name); 352 exit(1); 353 } 354 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(sms->flash[0]), 0); 355 image_size = load_image_mr(fname, mr); 356 g_free(fname); 357 if (image_size < 0) { 358 error_report("Could not load ROM image '%s'", bios_name); 359 exit(1); 360 } 361 } 362 363 return pflash_blk0 || bios_name; 364 } 365 366 static void create_secure_ram(SBSAMachineState *sms, 367 MemoryRegion *secure_sysmem) 368 { 369 MemoryRegion *secram = g_new(MemoryRegion, 1); 370 hwaddr base = sbsa_ref_memmap[SBSA_SECURE_MEM].base; 371 hwaddr size = sbsa_ref_memmap[SBSA_SECURE_MEM].size; 372 373 memory_region_init_ram(secram, NULL, "sbsa-ref.secure-ram", size, 374 &error_fatal); 375 memory_region_add_subregion(secure_sysmem, base, secram); 376 } 377 378 static void create_gic(SBSAMachineState *sms) 379 { 380 unsigned int smp_cpus = MACHINE(sms)->smp.cpus; 381 SysBusDevice *gicbusdev; 382 const char *gictype; 383 uint32_t redist0_capacity, redist0_count; 384 int i; 385 386 gictype = gicv3_class_name(); 387 388 sms->gic = qdev_new(gictype); 389 qdev_prop_set_uint32(sms->gic, "revision", 3); 390 qdev_prop_set_uint32(sms->gic, "num-cpu", smp_cpus); 391 /* 392 * Note that the num-irq property counts both internal and external 393 * interrupts; there are always 32 of the former (mandated by GIC spec). 394 */ 395 qdev_prop_set_uint32(sms->gic, "num-irq", NUM_IRQS + 32); 396 qdev_prop_set_bit(sms->gic, "has-security-extensions", true); 397 398 redist0_capacity = 399 sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE; 400 redist0_count = MIN(smp_cpus, redist0_capacity); 401 402 qdev_prop_set_uint32(sms->gic, "len-redist-region-count", 1); 403 qdev_prop_set_uint32(sms->gic, "redist-region-count[0]", redist0_count); 404 405 gicbusdev = SYS_BUS_DEVICE(sms->gic); 406 sysbus_realize_and_unref(gicbusdev, &error_fatal); 407 sysbus_mmio_map(gicbusdev, 0, sbsa_ref_memmap[SBSA_GIC_DIST].base); 408 sysbus_mmio_map(gicbusdev, 1, sbsa_ref_memmap[SBSA_GIC_REDIST].base); 409 410 /* 411 * Wire the outputs from each CPU's generic timer and the GICv3 412 * maintenance interrupt signal to the appropriate GIC PPI inputs, 413 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. 414 */ 415 for (i = 0; i < smp_cpus; i++) { 416 DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); 417 int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; 418 int irq; 419 /* 420 * Mapping from the output timer irq lines from the CPU to the 421 * GIC PPI inputs used for this board. 422 */ 423 const int timer_irq[] = { 424 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 425 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 426 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 427 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 428 }; 429 430 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 431 qdev_connect_gpio_out(cpudev, irq, 432 qdev_get_gpio_in(sms->gic, 433 ppibase + timer_irq[irq])); 434 } 435 436 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0, 437 qdev_get_gpio_in(sms->gic, ppibase 438 + ARCH_GIC_MAINT_IRQ)); 439 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 440 qdev_get_gpio_in(sms->gic, ppibase 441 + VIRTUAL_PMU_IRQ)); 442 443 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 444 sysbus_connect_irq(gicbusdev, i + smp_cpus, 445 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 446 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, 447 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 448 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, 449 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 450 } 451 } 452 453 static void create_uart(const SBSAMachineState *sms, int uart, 454 MemoryRegion *mem, Chardev *chr) 455 { 456 hwaddr base = sbsa_ref_memmap[uart].base; 457 int irq = sbsa_ref_irqmap[uart]; 458 DeviceState *dev = qdev_new(TYPE_PL011); 459 SysBusDevice *s = SYS_BUS_DEVICE(dev); 460 461 qdev_prop_set_chr(dev, "chardev", chr); 462 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 463 memory_region_add_subregion(mem, base, 464 sysbus_mmio_get_region(s, 0)); 465 sysbus_connect_irq(s, 0, qdev_get_gpio_in(sms->gic, irq)); 466 } 467 468 static void create_rtc(const SBSAMachineState *sms) 469 { 470 hwaddr base = sbsa_ref_memmap[SBSA_RTC].base; 471 int irq = sbsa_ref_irqmap[SBSA_RTC]; 472 473 sysbus_create_simple("pl031", base, qdev_get_gpio_in(sms->gic, irq)); 474 } 475 476 static void create_wdt(const SBSAMachineState *sms) 477 { 478 hwaddr rbase = sbsa_ref_memmap[SBSA_GWDT_REFRESH].base; 479 hwaddr cbase = sbsa_ref_memmap[SBSA_GWDT_CONTROL].base; 480 DeviceState *dev = qdev_new(TYPE_WDT_SBSA); 481 SysBusDevice *s = SYS_BUS_DEVICE(dev); 482 int irq = sbsa_ref_irqmap[SBSA_GWDT]; 483 484 sysbus_realize_and_unref(s, &error_fatal); 485 sysbus_mmio_map(s, 0, rbase); 486 sysbus_mmio_map(s, 1, cbase); 487 sysbus_connect_irq(s, 0, qdev_get_gpio_in(sms->gic, irq)); 488 } 489 490 static DeviceState *gpio_key_dev; 491 static void sbsa_ref_powerdown_req(Notifier *n, void *opaque) 492 { 493 /* use gpio Pin 3 for power button event */ 494 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); 495 } 496 497 static Notifier sbsa_ref_powerdown_notifier = { 498 .notify = sbsa_ref_powerdown_req 499 }; 500 501 static void create_gpio(const SBSAMachineState *sms) 502 { 503 DeviceState *pl061_dev; 504 hwaddr base = sbsa_ref_memmap[SBSA_GPIO].base; 505 int irq = sbsa_ref_irqmap[SBSA_GPIO]; 506 507 pl061_dev = sysbus_create_simple("pl061", base, 508 qdev_get_gpio_in(sms->gic, irq)); 509 510 gpio_key_dev = sysbus_create_simple("gpio-key", -1, 511 qdev_get_gpio_in(pl061_dev, 3)); 512 513 /* connect powerdown request */ 514 qemu_register_powerdown_notifier(&sbsa_ref_powerdown_notifier); 515 } 516 517 static void create_ahci(const SBSAMachineState *sms) 518 { 519 hwaddr base = sbsa_ref_memmap[SBSA_AHCI].base; 520 int irq = sbsa_ref_irqmap[SBSA_AHCI]; 521 DeviceState *dev; 522 DriveInfo *hd[NUM_SATA_PORTS]; 523 SysbusAHCIState *sysahci; 524 AHCIState *ahci; 525 int i; 526 527 dev = qdev_new("sysbus-ahci"); 528 qdev_prop_set_uint32(dev, "num-ports", NUM_SATA_PORTS); 529 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 530 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 531 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(sms->gic, irq)); 532 533 sysahci = SYSBUS_AHCI(dev); 534 ahci = &sysahci->ahci; 535 ide_drive_get(hd, ARRAY_SIZE(hd)); 536 for (i = 0; i < ahci->ports; i++) { 537 if (hd[i] == NULL) { 538 continue; 539 } 540 ide_create_drive(&ahci->dev[i].port, 0, hd[i]); 541 } 542 } 543 544 static void create_ehci(const SBSAMachineState *sms) 545 { 546 hwaddr base = sbsa_ref_memmap[SBSA_EHCI].base; 547 int irq = sbsa_ref_irqmap[SBSA_EHCI]; 548 549 sysbus_create_simple("platform-ehci-usb", base, 550 qdev_get_gpio_in(sms->gic, irq)); 551 } 552 553 static void create_smmu(const SBSAMachineState *sms, PCIBus *bus) 554 { 555 hwaddr base = sbsa_ref_memmap[SBSA_SMMU].base; 556 int irq = sbsa_ref_irqmap[SBSA_SMMU]; 557 DeviceState *dev; 558 int i; 559 560 dev = qdev_new("arm-smmuv3"); 561 562 object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus), 563 &error_abort); 564 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 565 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 566 for (i = 0; i < NUM_SMMU_IRQS; i++) { 567 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 568 qdev_get_gpio_in(sms->gic, irq + i)); 569 } 570 } 571 572 static void create_pcie(SBSAMachineState *sms) 573 { 574 hwaddr base_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].base; 575 hwaddr size_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].size; 576 hwaddr base_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].base; 577 hwaddr size_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].size; 578 hwaddr base_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].base; 579 hwaddr size_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].size; 580 hwaddr base_pio = sbsa_ref_memmap[SBSA_PCIE_PIO].base; 581 int irq = sbsa_ref_irqmap[SBSA_PCIE]; 582 MemoryRegion *mmio_alias, *mmio_alias_high, *mmio_reg; 583 MemoryRegion *ecam_alias, *ecam_reg; 584 DeviceState *dev; 585 PCIHostState *pci; 586 int i; 587 588 dev = qdev_new(TYPE_GPEX_HOST); 589 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 590 591 /* Map ECAM space */ 592 ecam_alias = g_new0(MemoryRegion, 1); 593 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 594 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 595 ecam_reg, 0, size_ecam); 596 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); 597 598 /* Map the MMIO space */ 599 mmio_alias = g_new0(MemoryRegion, 1); 600 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 601 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 602 mmio_reg, base_mmio, size_mmio); 603 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); 604 605 /* Map the MMIO_HIGH space */ 606 mmio_alias_high = g_new0(MemoryRegion, 1); 607 memory_region_init_alias(mmio_alias_high, OBJECT(dev), "pcie-mmio-high", 608 mmio_reg, base_mmio_high, size_mmio_high); 609 memory_region_add_subregion(get_system_memory(), base_mmio_high, 610 mmio_alias_high); 611 612 /* Map IO port space */ 613 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); 614 615 for (i = 0; i < GPEX_NUM_IRQS; i++) { 616 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 617 qdev_get_gpio_in(sms->gic, irq + i)); 618 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); 619 } 620 621 pci = PCI_HOST_BRIDGE(dev); 622 if (pci->bus) { 623 for (i = 0; i < nb_nics; i++) { 624 NICInfo *nd = &nd_table[i]; 625 626 if (!nd->model) { 627 nd->model = g_strdup("e1000e"); 628 } 629 630 pci_nic_init_nofail(nd, pci->bus, nd->model, NULL); 631 } 632 } 633 634 pci_create_simple(pci->bus, -1, "VGA"); 635 636 create_smmu(sms, pci->bus); 637 } 638 639 static void *sbsa_ref_dtb(const struct arm_boot_info *binfo, int *fdt_size) 640 { 641 const SBSAMachineState *board = container_of(binfo, SBSAMachineState, 642 bootinfo); 643 644 *fdt_size = board->fdt_size; 645 return board->fdt; 646 } 647 648 static void create_secure_ec(MemoryRegion *mem) 649 { 650 hwaddr base = sbsa_ref_memmap[SBSA_SECURE_EC].base; 651 DeviceState *dev = qdev_new("sbsa-ec"); 652 SysBusDevice *s = SYS_BUS_DEVICE(dev); 653 654 memory_region_add_subregion(mem, base, 655 sysbus_mmio_get_region(s, 0)); 656 } 657 658 static void sbsa_ref_init(MachineState *machine) 659 { 660 unsigned int smp_cpus = machine->smp.cpus; 661 unsigned int max_cpus = machine->smp.max_cpus; 662 SBSAMachineState *sms = SBSA_MACHINE(machine); 663 MachineClass *mc = MACHINE_GET_CLASS(machine); 664 MemoryRegion *sysmem = get_system_memory(); 665 MemoryRegion *secure_sysmem = g_new(MemoryRegion, 1); 666 bool firmware_loaded; 667 const CPUArchIdList *possible_cpus; 668 int n, sbsa_max_cpus; 669 670 if (!cpu_type_valid(machine->cpu_type)) { 671 error_report("mach-virt: CPU type %s not supported", machine->cpu_type); 672 exit(1); 673 } 674 675 if (kvm_enabled()) { 676 error_report("sbsa-ref: KVM is not supported for this machine"); 677 exit(1); 678 } 679 680 /* 681 * The Secure view of the world is the same as the NonSecure, 682 * but with a few extra devices. Create it as a container region 683 * containing the system memory at low priority; any secure-only 684 * devices go in at higher priority and take precedence. 685 */ 686 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", 687 UINT64_MAX); 688 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); 689 690 firmware_loaded = sbsa_firmware_init(sms, sysmem, secure_sysmem); 691 692 if (machine->kernel_filename && firmware_loaded) { 693 error_report("sbsa-ref: No fw_cfg device on this machine, " 694 "so -kernel option is not supported when firmware loaded, " 695 "please load OS from hard disk instead"); 696 exit(1); 697 } 698 699 /* 700 * This machine has EL3 enabled, external firmware should supply PSCI 701 * implementation, so the QEMU's internal PSCI is disabled. 702 */ 703 sms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; 704 705 sbsa_max_cpus = sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE; 706 707 if (max_cpus > sbsa_max_cpus) { 708 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " 709 "supported by machine 'sbsa-ref' (%d)", 710 max_cpus, sbsa_max_cpus); 711 exit(1); 712 } 713 714 sms->smp_cpus = smp_cpus; 715 716 if (machine->ram_size > sbsa_ref_memmap[SBSA_MEM].size) { 717 error_report("sbsa-ref: cannot model more than %dGB RAM", RAMLIMIT_GB); 718 exit(1); 719 } 720 721 possible_cpus = mc->possible_cpu_arch_ids(machine); 722 for (n = 0; n < possible_cpus->len; n++) { 723 Object *cpuobj; 724 CPUState *cs; 725 726 if (n >= smp_cpus) { 727 break; 728 } 729 730 cpuobj = object_new(possible_cpus->cpus[n].type); 731 object_property_set_int(cpuobj, "mp-affinity", 732 possible_cpus->cpus[n].arch_id, NULL); 733 734 cs = CPU(cpuobj); 735 cs->cpu_index = n; 736 737 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj), 738 &error_fatal); 739 740 if (object_property_find(cpuobj, "reset-cbar")) { 741 object_property_set_int(cpuobj, "reset-cbar", 742 sbsa_ref_memmap[SBSA_CPUPERIPHS].base, 743 &error_abort); 744 } 745 746 object_property_set_link(cpuobj, "memory", OBJECT(sysmem), 747 &error_abort); 748 749 object_property_set_link(cpuobj, "secure-memory", 750 OBJECT(secure_sysmem), &error_abort); 751 752 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); 753 object_unref(cpuobj); 754 } 755 756 memory_region_add_subregion(sysmem, sbsa_ref_memmap[SBSA_MEM].base, 757 machine->ram); 758 759 create_fdt(sms); 760 761 create_secure_ram(sms, secure_sysmem); 762 763 create_gic(sms); 764 765 create_uart(sms, SBSA_UART, sysmem, serial_hd(0)); 766 create_uart(sms, SBSA_SECURE_UART, secure_sysmem, serial_hd(1)); 767 /* Second secure UART for RAS and MM from EL0 */ 768 create_uart(sms, SBSA_SECURE_UART_MM, secure_sysmem, serial_hd(2)); 769 770 create_rtc(sms); 771 772 create_wdt(sms); 773 774 create_gpio(sms); 775 776 create_ahci(sms); 777 778 create_ehci(sms); 779 780 create_pcie(sms); 781 782 create_secure_ec(secure_sysmem); 783 784 sms->bootinfo.ram_size = machine->ram_size; 785 sms->bootinfo.nb_cpus = smp_cpus; 786 sms->bootinfo.board_id = -1; 787 sms->bootinfo.loader_start = sbsa_ref_memmap[SBSA_MEM].base; 788 sms->bootinfo.get_dtb = sbsa_ref_dtb; 789 sms->bootinfo.firmware_loaded = firmware_loaded; 790 arm_load_kernel(ARM_CPU(first_cpu), machine, &sms->bootinfo); 791 } 792 793 static const CPUArchIdList *sbsa_ref_possible_cpu_arch_ids(MachineState *ms) 794 { 795 unsigned int max_cpus = ms->smp.max_cpus; 796 SBSAMachineState *sms = SBSA_MACHINE(ms); 797 int n; 798 799 if (ms->possible_cpus) { 800 assert(ms->possible_cpus->len == max_cpus); 801 return ms->possible_cpus; 802 } 803 804 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 805 sizeof(CPUArchId) * max_cpus); 806 ms->possible_cpus->len = max_cpus; 807 for (n = 0; n < ms->possible_cpus->len; n++) { 808 ms->possible_cpus->cpus[n].type = ms->cpu_type; 809 ms->possible_cpus->cpus[n].arch_id = 810 sbsa_ref_cpu_mp_affinity(sms, n); 811 ms->possible_cpus->cpus[n].props.has_thread_id = true; 812 ms->possible_cpus->cpus[n].props.thread_id = n; 813 } 814 return ms->possible_cpus; 815 } 816 817 static CpuInstanceProperties 818 sbsa_ref_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 819 { 820 MachineClass *mc = MACHINE_GET_CLASS(ms); 821 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 822 823 assert(cpu_index < possible_cpus->len); 824 return possible_cpus->cpus[cpu_index].props; 825 } 826 827 static int64_t 828 sbsa_ref_get_default_cpu_node_id(const MachineState *ms, int idx) 829 { 830 return idx % ms->numa_state->num_nodes; 831 } 832 833 static void sbsa_ref_instance_init(Object *obj) 834 { 835 SBSAMachineState *sms = SBSA_MACHINE(obj); 836 837 sbsa_flash_create(sms); 838 } 839 840 static void sbsa_ref_class_init(ObjectClass *oc, void *data) 841 { 842 MachineClass *mc = MACHINE_CLASS(oc); 843 844 mc->init = sbsa_ref_init; 845 mc->desc = "QEMU 'SBSA Reference' ARM Virtual Machine"; 846 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a57"); 847 mc->max_cpus = 512; 848 mc->pci_allow_0_address = true; 849 mc->minimum_page_bits = 12; 850 mc->block_default_type = IF_IDE; 851 mc->no_cdrom = 1; 852 mc->default_ram_size = 1 * GiB; 853 mc->default_ram_id = "sbsa-ref.ram"; 854 mc->default_cpus = 4; 855 mc->possible_cpu_arch_ids = sbsa_ref_possible_cpu_arch_ids; 856 mc->cpu_index_to_instance_props = sbsa_ref_cpu_index_to_props; 857 mc->get_default_cpu_node_id = sbsa_ref_get_default_cpu_node_id; 858 } 859 860 static const TypeInfo sbsa_ref_info = { 861 .name = TYPE_SBSA_MACHINE, 862 .parent = TYPE_MACHINE, 863 .instance_init = sbsa_ref_instance_init, 864 .class_init = sbsa_ref_class_init, 865 .instance_size = sizeof(SBSAMachineState), 866 }; 867 868 static void sbsa_ref_machine_init(void) 869 { 870 type_register_static(&sbsa_ref_info); 871 } 872 873 type_init(sbsa_ref_machine_init); 874