1 /* 2 * ARM SBSA Reference Platform emulation 3 * 4 * Copyright (c) 2018 Linaro Limited 5 * Written by Hongbo Zhang <hongbo.zhang@linaro.org> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu-common.h" 22 #include "qapi/error.h" 23 #include "qemu/error-report.h" 24 #include "qemu/units.h" 25 #include "sysemu/device_tree.h" 26 #include "sysemu/numa.h" 27 #include "sysemu/runstate.h" 28 #include "sysemu/sysemu.h" 29 #include "exec/address-spaces.h" 30 #include "exec/hwaddr.h" 31 #include "kvm_arm.h" 32 #include "hw/arm/boot.h" 33 #include "hw/block/flash.h" 34 #include "hw/boards.h" 35 #include "hw/ide/internal.h" 36 #include "hw/ide/ahci_internal.h" 37 #include "hw/intc/arm_gicv3_common.h" 38 #include "hw/loader.h" 39 #include "hw/pci-host/gpex.h" 40 #include "hw/qdev-properties.h" 41 #include "hw/usb.h" 42 #include "net/net.h" 43 44 #define RAMLIMIT_GB 8192 45 #define RAMLIMIT_BYTES (RAMLIMIT_GB * GiB) 46 47 #define NUM_IRQS 256 48 #define NUM_SMMU_IRQS 4 49 #define NUM_SATA_PORTS 6 50 51 #define VIRTUAL_PMU_IRQ 7 52 #define ARCH_GIC_MAINT_IRQ 9 53 #define ARCH_TIMER_VIRT_IRQ 11 54 #define ARCH_TIMER_S_EL1_IRQ 13 55 #define ARCH_TIMER_NS_EL1_IRQ 14 56 #define ARCH_TIMER_NS_EL2_IRQ 10 57 58 enum { 59 SBSA_FLASH, 60 SBSA_MEM, 61 SBSA_CPUPERIPHS, 62 SBSA_GIC_DIST, 63 SBSA_GIC_REDIST, 64 SBSA_SMMU, 65 SBSA_UART, 66 SBSA_RTC, 67 SBSA_PCIE, 68 SBSA_PCIE_MMIO, 69 SBSA_PCIE_MMIO_HIGH, 70 SBSA_PCIE_PIO, 71 SBSA_PCIE_ECAM, 72 SBSA_GPIO, 73 SBSA_SECURE_UART, 74 SBSA_SECURE_UART_MM, 75 SBSA_SECURE_MEM, 76 SBSA_AHCI, 77 SBSA_EHCI, 78 }; 79 80 typedef struct MemMapEntry { 81 hwaddr base; 82 hwaddr size; 83 } MemMapEntry; 84 85 typedef struct { 86 MachineState parent; 87 struct arm_boot_info bootinfo; 88 int smp_cpus; 89 void *fdt; 90 int fdt_size; 91 int psci_conduit; 92 PFlashCFI01 *flash[2]; 93 } SBSAMachineState; 94 95 #define TYPE_SBSA_MACHINE MACHINE_TYPE_NAME("sbsa-ref") 96 #define SBSA_MACHINE(obj) \ 97 OBJECT_CHECK(SBSAMachineState, (obj), TYPE_SBSA_MACHINE) 98 99 static const MemMapEntry sbsa_ref_memmap[] = { 100 /* 512M boot ROM */ 101 [SBSA_FLASH] = { 0, 0x20000000 }, 102 /* 512M secure memory */ 103 [SBSA_SECURE_MEM] = { 0x20000000, 0x20000000 }, 104 /* Space reserved for CPU peripheral devices */ 105 [SBSA_CPUPERIPHS] = { 0x40000000, 0x00040000 }, 106 [SBSA_GIC_DIST] = { 0x40060000, 0x00010000 }, 107 [SBSA_GIC_REDIST] = { 0x40080000, 0x04000000 }, 108 [SBSA_UART] = { 0x60000000, 0x00001000 }, 109 [SBSA_RTC] = { 0x60010000, 0x00001000 }, 110 [SBSA_GPIO] = { 0x60020000, 0x00001000 }, 111 [SBSA_SECURE_UART] = { 0x60030000, 0x00001000 }, 112 [SBSA_SECURE_UART_MM] = { 0x60040000, 0x00001000 }, 113 [SBSA_SMMU] = { 0x60050000, 0x00020000 }, 114 /* Space here reserved for more SMMUs */ 115 [SBSA_AHCI] = { 0x60100000, 0x00010000 }, 116 [SBSA_EHCI] = { 0x60110000, 0x00010000 }, 117 /* Space here reserved for other devices */ 118 [SBSA_PCIE_PIO] = { 0x7fff0000, 0x00010000 }, 119 /* 32-bit address PCIE MMIO space */ 120 [SBSA_PCIE_MMIO] = { 0x80000000, 0x70000000 }, 121 /* 256M PCIE ECAM space */ 122 [SBSA_PCIE_ECAM] = { 0xf0000000, 0x10000000 }, 123 /* ~1TB PCIE MMIO space (4GB to 1024GB boundary) */ 124 [SBSA_PCIE_MMIO_HIGH] = { 0x100000000ULL, 0xFF00000000ULL }, 125 [SBSA_MEM] = { 0x10000000000ULL, RAMLIMIT_BYTES }, 126 }; 127 128 static const int sbsa_ref_irqmap[] = { 129 [SBSA_UART] = 1, 130 [SBSA_RTC] = 2, 131 [SBSA_PCIE] = 3, /* ... to 6 */ 132 [SBSA_GPIO] = 7, 133 [SBSA_SECURE_UART] = 8, 134 [SBSA_SECURE_UART_MM] = 9, 135 [SBSA_AHCI] = 10, 136 [SBSA_EHCI] = 11, 137 }; 138 139 /* 140 * Firmware on this machine only uses ACPI table to load OS, these limited 141 * device tree nodes are just to let firmware know the info which varies from 142 * command line parameters, so it is not necessary to be fully compatible 143 * with the kernel CPU and NUMA binding rules. 144 */ 145 static void create_fdt(SBSAMachineState *sms) 146 { 147 void *fdt = create_device_tree(&sms->fdt_size); 148 const MachineState *ms = MACHINE(sms); 149 int cpu; 150 151 if (!fdt) { 152 error_report("create_device_tree() failed"); 153 exit(1); 154 } 155 156 sms->fdt = fdt; 157 158 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,sbsa-ref"); 159 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 160 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 161 162 if (have_numa_distance) { 163 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); 164 uint32_t *matrix = g_malloc0(size); 165 int idx, i, j; 166 167 for (i = 0; i < nb_numa_nodes; i++) { 168 for (j = 0; j < nb_numa_nodes; j++) { 169 idx = (i * nb_numa_nodes + j) * 3; 170 matrix[idx + 0] = cpu_to_be32(i); 171 matrix[idx + 1] = cpu_to_be32(j); 172 matrix[idx + 2] = cpu_to_be32(numa_info[i].distance[j]); 173 } 174 } 175 176 qemu_fdt_add_subnode(fdt, "/distance-map"); 177 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", 178 matrix, size); 179 g_free(matrix); 180 } 181 182 qemu_fdt_add_subnode(sms->fdt, "/cpus"); 183 184 for (cpu = sms->smp_cpus - 1; cpu >= 0; cpu--) { 185 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 186 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 187 CPUState *cs = CPU(armcpu); 188 189 qemu_fdt_add_subnode(sms->fdt, nodename); 190 191 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 192 qemu_fdt_setprop_cell(sms->fdt, nodename, "numa-node-id", 193 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 194 } 195 196 g_free(nodename); 197 } 198 } 199 200 #define SBSA_FLASH_SECTOR_SIZE (256 * KiB) 201 202 static PFlashCFI01 *sbsa_flash_create1(SBSAMachineState *sms, 203 const char *name, 204 const char *alias_prop_name) 205 { 206 /* 207 * Create a single flash device. We use the same parameters as 208 * the flash devices on the Versatile Express board. 209 */ 210 DeviceState *dev = qdev_create(NULL, TYPE_PFLASH_CFI01); 211 212 qdev_prop_set_uint64(dev, "sector-length", SBSA_FLASH_SECTOR_SIZE); 213 qdev_prop_set_uint8(dev, "width", 4); 214 qdev_prop_set_uint8(dev, "device-width", 2); 215 qdev_prop_set_bit(dev, "big-endian", false); 216 qdev_prop_set_uint16(dev, "id0", 0x89); 217 qdev_prop_set_uint16(dev, "id1", 0x18); 218 qdev_prop_set_uint16(dev, "id2", 0x00); 219 qdev_prop_set_uint16(dev, "id3", 0x00); 220 qdev_prop_set_string(dev, "name", name); 221 object_property_add_child(OBJECT(sms), name, OBJECT(dev), 222 &error_abort); 223 object_property_add_alias(OBJECT(sms), alias_prop_name, 224 OBJECT(dev), "drive", &error_abort); 225 return PFLASH_CFI01(dev); 226 } 227 228 static void sbsa_flash_create(SBSAMachineState *sms) 229 { 230 sms->flash[0] = sbsa_flash_create1(sms, "sbsa.flash0", "pflash0"); 231 sms->flash[1] = sbsa_flash_create1(sms, "sbsa.flash1", "pflash1"); 232 } 233 234 static void sbsa_flash_map1(PFlashCFI01 *flash, 235 hwaddr base, hwaddr size, 236 MemoryRegion *sysmem) 237 { 238 DeviceState *dev = DEVICE(flash); 239 240 assert(size % SBSA_FLASH_SECTOR_SIZE == 0); 241 assert(size / SBSA_FLASH_SECTOR_SIZE <= UINT32_MAX); 242 qdev_prop_set_uint32(dev, "num-blocks", size / SBSA_FLASH_SECTOR_SIZE); 243 qdev_init_nofail(dev); 244 245 memory_region_add_subregion(sysmem, base, 246 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 247 0)); 248 } 249 250 static void sbsa_flash_map(SBSAMachineState *sms, 251 MemoryRegion *sysmem, 252 MemoryRegion *secure_sysmem) 253 { 254 /* 255 * Map two flash devices to fill the SBSA_FLASH space in the memmap. 256 * sysmem is the system memory space. secure_sysmem is the secure view 257 * of the system, and the first flash device should be made visible only 258 * there. The second flash device is visible to both secure and nonsecure. 259 */ 260 hwaddr flashsize = sbsa_ref_memmap[SBSA_FLASH].size / 2; 261 hwaddr flashbase = sbsa_ref_memmap[SBSA_FLASH].base; 262 263 sbsa_flash_map1(sms->flash[0], flashbase, flashsize, 264 secure_sysmem); 265 sbsa_flash_map1(sms->flash[1], flashbase + flashsize, flashsize, 266 sysmem); 267 } 268 269 static bool sbsa_firmware_init(SBSAMachineState *sms, 270 MemoryRegion *sysmem, 271 MemoryRegion *secure_sysmem) 272 { 273 int i; 274 BlockBackend *pflash_blk0; 275 276 /* Map legacy -drive if=pflash to machine properties */ 277 for (i = 0; i < ARRAY_SIZE(sms->flash); i++) { 278 pflash_cfi01_legacy_drive(sms->flash[i], 279 drive_get(IF_PFLASH, 0, i)); 280 } 281 282 sbsa_flash_map(sms, sysmem, secure_sysmem); 283 284 pflash_blk0 = pflash_cfi01_get_blk(sms->flash[0]); 285 286 if (bios_name) { 287 char *fname; 288 MemoryRegion *mr; 289 int image_size; 290 291 if (pflash_blk0) { 292 error_report("The contents of the first flash device may be " 293 "specified with -bios or with -drive if=pflash... " 294 "but you cannot use both options at once"); 295 exit(1); 296 } 297 298 /* Fall back to -bios */ 299 300 fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 301 if (!fname) { 302 error_report("Could not find ROM image '%s'", bios_name); 303 exit(1); 304 } 305 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(sms->flash[0]), 0); 306 image_size = load_image_mr(fname, mr); 307 g_free(fname); 308 if (image_size < 0) { 309 error_report("Could not load ROM image '%s'", bios_name); 310 exit(1); 311 } 312 } 313 314 return pflash_blk0 || bios_name; 315 } 316 317 static void create_secure_ram(SBSAMachineState *sms, 318 MemoryRegion *secure_sysmem) 319 { 320 MemoryRegion *secram = g_new(MemoryRegion, 1); 321 hwaddr base = sbsa_ref_memmap[SBSA_SECURE_MEM].base; 322 hwaddr size = sbsa_ref_memmap[SBSA_SECURE_MEM].size; 323 324 memory_region_init_ram(secram, NULL, "sbsa-ref.secure-ram", size, 325 &error_fatal); 326 memory_region_add_subregion(secure_sysmem, base, secram); 327 } 328 329 static void create_gic(SBSAMachineState *sms, qemu_irq *pic) 330 { 331 unsigned int smp_cpus = MACHINE(sms)->smp.cpus; 332 DeviceState *gicdev; 333 SysBusDevice *gicbusdev; 334 const char *gictype; 335 uint32_t redist0_capacity, redist0_count; 336 int i; 337 338 gictype = gicv3_class_name(); 339 340 gicdev = qdev_create(NULL, gictype); 341 qdev_prop_set_uint32(gicdev, "revision", 3); 342 qdev_prop_set_uint32(gicdev, "num-cpu", smp_cpus); 343 /* 344 * Note that the num-irq property counts both internal and external 345 * interrupts; there are always 32 of the former (mandated by GIC spec). 346 */ 347 qdev_prop_set_uint32(gicdev, "num-irq", NUM_IRQS + 32); 348 qdev_prop_set_bit(gicdev, "has-security-extensions", true); 349 350 redist0_capacity = 351 sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE; 352 redist0_count = MIN(smp_cpus, redist0_capacity); 353 354 qdev_prop_set_uint32(gicdev, "len-redist-region-count", 1); 355 qdev_prop_set_uint32(gicdev, "redist-region-count[0]", redist0_count); 356 357 qdev_init_nofail(gicdev); 358 gicbusdev = SYS_BUS_DEVICE(gicdev); 359 sysbus_mmio_map(gicbusdev, 0, sbsa_ref_memmap[SBSA_GIC_DIST].base); 360 sysbus_mmio_map(gicbusdev, 1, sbsa_ref_memmap[SBSA_GIC_REDIST].base); 361 362 /* 363 * Wire the outputs from each CPU's generic timer and the GICv3 364 * maintenance interrupt signal to the appropriate GIC PPI inputs, 365 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. 366 */ 367 for (i = 0; i < smp_cpus; i++) { 368 DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); 369 int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; 370 int irq; 371 /* 372 * Mapping from the output timer irq lines from the CPU to the 373 * GIC PPI inputs used for this board. 374 */ 375 const int timer_irq[] = { 376 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 377 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 378 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 379 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 380 }; 381 382 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 383 qdev_connect_gpio_out(cpudev, irq, 384 qdev_get_gpio_in(gicdev, 385 ppibase + timer_irq[irq])); 386 } 387 388 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0, 389 qdev_get_gpio_in(gicdev, ppibase 390 + ARCH_GIC_MAINT_IRQ)); 391 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 392 qdev_get_gpio_in(gicdev, ppibase 393 + VIRTUAL_PMU_IRQ)); 394 395 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 396 sysbus_connect_irq(gicbusdev, i + smp_cpus, 397 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 398 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, 399 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 400 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, 401 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 402 } 403 404 for (i = 0; i < NUM_IRQS; i++) { 405 pic[i] = qdev_get_gpio_in(gicdev, i); 406 } 407 } 408 409 static void create_uart(const SBSAMachineState *sms, qemu_irq *pic, int uart, 410 MemoryRegion *mem, Chardev *chr) 411 { 412 hwaddr base = sbsa_ref_memmap[uart].base; 413 int irq = sbsa_ref_irqmap[uart]; 414 DeviceState *dev = qdev_create(NULL, "pl011"); 415 SysBusDevice *s = SYS_BUS_DEVICE(dev); 416 417 qdev_prop_set_chr(dev, "chardev", chr); 418 qdev_init_nofail(dev); 419 memory_region_add_subregion(mem, base, 420 sysbus_mmio_get_region(s, 0)); 421 sysbus_connect_irq(s, 0, pic[irq]); 422 } 423 424 static void create_rtc(const SBSAMachineState *sms, qemu_irq *pic) 425 { 426 hwaddr base = sbsa_ref_memmap[SBSA_RTC].base; 427 int irq = sbsa_ref_irqmap[SBSA_RTC]; 428 429 sysbus_create_simple("pl031", base, pic[irq]); 430 } 431 432 static DeviceState *gpio_key_dev; 433 static void sbsa_ref_powerdown_req(Notifier *n, void *opaque) 434 { 435 /* use gpio Pin 3 for power button event */ 436 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); 437 } 438 439 static Notifier sbsa_ref_powerdown_notifier = { 440 .notify = sbsa_ref_powerdown_req 441 }; 442 443 static void create_gpio(const SBSAMachineState *sms, qemu_irq *pic) 444 { 445 DeviceState *pl061_dev; 446 hwaddr base = sbsa_ref_memmap[SBSA_GPIO].base; 447 int irq = sbsa_ref_irqmap[SBSA_GPIO]; 448 449 pl061_dev = sysbus_create_simple("pl061", base, pic[irq]); 450 451 gpio_key_dev = sysbus_create_simple("gpio-key", -1, 452 qdev_get_gpio_in(pl061_dev, 3)); 453 454 /* connect powerdown request */ 455 qemu_register_powerdown_notifier(&sbsa_ref_powerdown_notifier); 456 } 457 458 static void create_ahci(const SBSAMachineState *sms, qemu_irq *pic) 459 { 460 hwaddr base = sbsa_ref_memmap[SBSA_AHCI].base; 461 int irq = sbsa_ref_irqmap[SBSA_AHCI]; 462 DeviceState *dev; 463 DriveInfo *hd[NUM_SATA_PORTS]; 464 SysbusAHCIState *sysahci; 465 AHCIState *ahci; 466 int i; 467 468 dev = qdev_create(NULL, "sysbus-ahci"); 469 qdev_prop_set_uint32(dev, "num-ports", NUM_SATA_PORTS); 470 qdev_init_nofail(dev); 471 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 472 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[irq]); 473 474 sysahci = SYSBUS_AHCI(dev); 475 ahci = &sysahci->ahci; 476 ide_drive_get(hd, ARRAY_SIZE(hd)); 477 for (i = 0; i < ahci->ports; i++) { 478 if (hd[i] == NULL) { 479 continue; 480 } 481 ide_create_drive(&ahci->dev[i].port, 0, hd[i]); 482 } 483 } 484 485 static void create_ehci(const SBSAMachineState *sms, qemu_irq *pic) 486 { 487 hwaddr base = sbsa_ref_memmap[SBSA_EHCI].base; 488 int irq = sbsa_ref_irqmap[SBSA_EHCI]; 489 490 sysbus_create_simple("platform-ehci-usb", base, pic[irq]); 491 } 492 493 static void create_smmu(const SBSAMachineState *sms, qemu_irq *pic, 494 PCIBus *bus) 495 { 496 hwaddr base = sbsa_ref_memmap[SBSA_SMMU].base; 497 int irq = sbsa_ref_irqmap[SBSA_SMMU]; 498 DeviceState *dev; 499 int i; 500 501 dev = qdev_create(NULL, "arm-smmuv3"); 502 503 object_property_set_link(OBJECT(dev), OBJECT(bus), "primary-bus", 504 &error_abort); 505 qdev_init_nofail(dev); 506 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 507 for (i = 0; i < NUM_SMMU_IRQS; i++) { 508 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); 509 } 510 } 511 512 static void create_pcie(SBSAMachineState *sms, qemu_irq *pic) 513 { 514 hwaddr base_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].base; 515 hwaddr size_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].size; 516 hwaddr base_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].base; 517 hwaddr size_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].size; 518 hwaddr base_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].base; 519 hwaddr size_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].size; 520 hwaddr base_pio = sbsa_ref_memmap[SBSA_PCIE_PIO].base; 521 int irq = sbsa_ref_irqmap[SBSA_PCIE]; 522 MemoryRegion *mmio_alias, *mmio_alias_high, *mmio_reg; 523 MemoryRegion *ecam_alias, *ecam_reg; 524 DeviceState *dev; 525 PCIHostState *pci; 526 int i; 527 528 dev = qdev_create(NULL, TYPE_GPEX_HOST); 529 qdev_init_nofail(dev); 530 531 /* Map ECAM space */ 532 ecam_alias = g_new0(MemoryRegion, 1); 533 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 534 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 535 ecam_reg, 0, size_ecam); 536 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); 537 538 /* Map the MMIO space */ 539 mmio_alias = g_new0(MemoryRegion, 1); 540 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 541 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 542 mmio_reg, base_mmio, size_mmio); 543 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); 544 545 /* Map the MMIO_HIGH space */ 546 mmio_alias_high = g_new0(MemoryRegion, 1); 547 memory_region_init_alias(mmio_alias_high, OBJECT(dev), "pcie-mmio-high", 548 mmio_reg, base_mmio_high, size_mmio_high); 549 memory_region_add_subregion(get_system_memory(), base_mmio_high, 550 mmio_alias_high); 551 552 /* Map IO port space */ 553 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); 554 555 for (i = 0; i < GPEX_NUM_IRQS; i++) { 556 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); 557 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); 558 } 559 560 pci = PCI_HOST_BRIDGE(dev); 561 if (pci->bus) { 562 for (i = 0; i < nb_nics; i++) { 563 NICInfo *nd = &nd_table[i]; 564 565 if (!nd->model) { 566 nd->model = g_strdup("e1000e"); 567 } 568 569 pci_nic_init_nofail(nd, pci->bus, nd->model, NULL); 570 } 571 } 572 573 pci_create_simple(pci->bus, -1, "VGA"); 574 575 create_smmu(sms, pic, pci->bus); 576 } 577 578 static void *sbsa_ref_dtb(const struct arm_boot_info *binfo, int *fdt_size) 579 { 580 const SBSAMachineState *board = container_of(binfo, SBSAMachineState, 581 bootinfo); 582 583 *fdt_size = board->fdt_size; 584 return board->fdt; 585 } 586 587 static void sbsa_ref_init(MachineState *machine) 588 { 589 unsigned int smp_cpus = machine->smp.cpus; 590 unsigned int max_cpus = machine->smp.max_cpus; 591 SBSAMachineState *sms = SBSA_MACHINE(machine); 592 MachineClass *mc = MACHINE_GET_CLASS(machine); 593 MemoryRegion *sysmem = get_system_memory(); 594 MemoryRegion *secure_sysmem = g_new(MemoryRegion, 1); 595 MemoryRegion *ram = g_new(MemoryRegion, 1); 596 bool firmware_loaded; 597 const CPUArchIdList *possible_cpus; 598 int n, sbsa_max_cpus; 599 qemu_irq pic[NUM_IRQS]; 600 601 if (strcmp(machine->cpu_type, ARM_CPU_TYPE_NAME("cortex-a57"))) { 602 error_report("sbsa-ref: CPU type other than the built-in " 603 "cortex-a57 not supported"); 604 exit(1); 605 } 606 607 if (kvm_enabled()) { 608 error_report("sbsa-ref: KVM is not supported for this machine"); 609 exit(1); 610 } 611 612 /* 613 * The Secure view of the world is the same as the NonSecure, 614 * but with a few extra devices. Create it as a container region 615 * containing the system memory at low priority; any secure-only 616 * devices go in at higher priority and take precedence. 617 */ 618 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", 619 UINT64_MAX); 620 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); 621 622 firmware_loaded = sbsa_firmware_init(sms, sysmem, secure_sysmem); 623 624 if (machine->kernel_filename && firmware_loaded) { 625 error_report("sbsa-ref: No fw_cfg device on this machine, " 626 "so -kernel option is not supported when firmware loaded, " 627 "please load OS from hard disk instead"); 628 exit(1); 629 } 630 631 /* 632 * This machine has EL3 enabled, external firmware should supply PSCI 633 * implementation, so the QEMU's internal PSCI is disabled. 634 */ 635 sms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; 636 637 sbsa_max_cpus = sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE; 638 639 if (max_cpus > sbsa_max_cpus) { 640 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " 641 "supported by machine 'sbsa-ref' (%d)", 642 max_cpus, sbsa_max_cpus); 643 exit(1); 644 } 645 646 sms->smp_cpus = smp_cpus; 647 648 if (machine->ram_size > sbsa_ref_memmap[SBSA_MEM].size) { 649 error_report("sbsa-ref: cannot model more than %dGB RAM", RAMLIMIT_GB); 650 exit(1); 651 } 652 653 possible_cpus = mc->possible_cpu_arch_ids(machine); 654 for (n = 0; n < possible_cpus->len; n++) { 655 Object *cpuobj; 656 CPUState *cs; 657 658 if (n >= smp_cpus) { 659 break; 660 } 661 662 cpuobj = object_new(possible_cpus->cpus[n].type); 663 object_property_set_int(cpuobj, possible_cpus->cpus[n].arch_id, 664 "mp-affinity", NULL); 665 666 cs = CPU(cpuobj); 667 cs->cpu_index = n; 668 669 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj), 670 &error_fatal); 671 672 if (object_property_find(cpuobj, "reset-cbar", NULL)) { 673 object_property_set_int(cpuobj, 674 sbsa_ref_memmap[SBSA_CPUPERIPHS].base, 675 "reset-cbar", &error_abort); 676 } 677 678 object_property_set_link(cpuobj, OBJECT(sysmem), "memory", 679 &error_abort); 680 681 object_property_set_link(cpuobj, OBJECT(secure_sysmem), 682 "secure-memory", &error_abort); 683 684 object_property_set_bool(cpuobj, true, "realized", &error_fatal); 685 object_unref(cpuobj); 686 } 687 688 memory_region_allocate_system_memory(ram, NULL, "sbsa-ref.ram", 689 machine->ram_size); 690 memory_region_add_subregion(sysmem, sbsa_ref_memmap[SBSA_MEM].base, ram); 691 692 create_fdt(sms); 693 694 create_secure_ram(sms, secure_sysmem); 695 696 create_gic(sms, pic); 697 698 create_uart(sms, pic, SBSA_UART, sysmem, serial_hd(0)); 699 create_uart(sms, pic, SBSA_SECURE_UART, secure_sysmem, serial_hd(1)); 700 /* Second secure UART for RAS and MM from EL0 */ 701 create_uart(sms, pic, SBSA_SECURE_UART_MM, secure_sysmem, serial_hd(2)); 702 703 create_rtc(sms, pic); 704 705 create_gpio(sms, pic); 706 707 create_ahci(sms, pic); 708 709 create_ehci(sms, pic); 710 711 create_pcie(sms, pic); 712 713 sms->bootinfo.ram_size = machine->ram_size; 714 sms->bootinfo.kernel_filename = machine->kernel_filename; 715 sms->bootinfo.nb_cpus = smp_cpus; 716 sms->bootinfo.board_id = -1; 717 sms->bootinfo.loader_start = sbsa_ref_memmap[SBSA_MEM].base; 718 sms->bootinfo.get_dtb = sbsa_ref_dtb; 719 sms->bootinfo.firmware_loaded = firmware_loaded; 720 arm_load_kernel(ARM_CPU(first_cpu), &sms->bootinfo); 721 } 722 723 static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx) 724 { 725 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER; 726 return arm_cpu_mp_affinity(idx, clustersz); 727 } 728 729 static const CPUArchIdList *sbsa_ref_possible_cpu_arch_ids(MachineState *ms) 730 { 731 unsigned int max_cpus = ms->smp.max_cpus; 732 SBSAMachineState *sms = SBSA_MACHINE(ms); 733 int n; 734 735 if (ms->possible_cpus) { 736 assert(ms->possible_cpus->len == max_cpus); 737 return ms->possible_cpus; 738 } 739 740 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 741 sizeof(CPUArchId) * max_cpus); 742 ms->possible_cpus->len = max_cpus; 743 for (n = 0; n < ms->possible_cpus->len; n++) { 744 ms->possible_cpus->cpus[n].type = ms->cpu_type; 745 ms->possible_cpus->cpus[n].arch_id = 746 sbsa_ref_cpu_mp_affinity(sms, n); 747 ms->possible_cpus->cpus[n].props.has_thread_id = true; 748 ms->possible_cpus->cpus[n].props.thread_id = n; 749 } 750 return ms->possible_cpus; 751 } 752 753 static CpuInstanceProperties 754 sbsa_ref_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 755 { 756 MachineClass *mc = MACHINE_GET_CLASS(ms); 757 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 758 759 assert(cpu_index < possible_cpus->len); 760 return possible_cpus->cpus[cpu_index].props; 761 } 762 763 static int64_t 764 sbsa_ref_get_default_cpu_node_id(const MachineState *ms, int idx) 765 { 766 return idx % nb_numa_nodes; 767 } 768 769 static void sbsa_ref_instance_init(Object *obj) 770 { 771 SBSAMachineState *sms = SBSA_MACHINE(obj); 772 773 sbsa_flash_create(sms); 774 } 775 776 static void sbsa_ref_class_init(ObjectClass *oc, void *data) 777 { 778 MachineClass *mc = MACHINE_CLASS(oc); 779 780 mc->init = sbsa_ref_init; 781 mc->desc = "QEMU 'SBSA Reference' ARM Virtual Machine"; 782 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a57"); 783 mc->max_cpus = 512; 784 mc->pci_allow_0_address = true; 785 mc->minimum_page_bits = 12; 786 mc->block_default_type = IF_IDE; 787 mc->no_cdrom = 1; 788 mc->default_ram_size = 1 * GiB; 789 mc->default_cpus = 4; 790 mc->possible_cpu_arch_ids = sbsa_ref_possible_cpu_arch_ids; 791 mc->cpu_index_to_instance_props = sbsa_ref_cpu_index_to_props; 792 mc->get_default_cpu_node_id = sbsa_ref_get_default_cpu_node_id; 793 } 794 795 static const TypeInfo sbsa_ref_info = { 796 .name = TYPE_SBSA_MACHINE, 797 .parent = TYPE_MACHINE, 798 .instance_init = sbsa_ref_instance_init, 799 .class_init = sbsa_ref_class_init, 800 .instance_size = sizeof(SBSAMachineState), 801 }; 802 803 static void sbsa_ref_machine_init(void) 804 { 805 type_register_static(&sbsa_ref_info); 806 } 807 808 type_init(sbsa_ref_machine_init); 809