1 /* 2 * ARM SBSA Reference Platform emulation 3 * 4 * Copyright (c) 2018 Linaro Limited 5 * Written by Hongbo Zhang <hongbo.zhang@linaro.org> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/datadir.h" 22 #include "qapi/error.h" 23 #include "qemu/error-report.h" 24 #include "qemu/units.h" 25 #include "sysemu/device_tree.h" 26 #include "sysemu/numa.h" 27 #include "sysemu/runstate.h" 28 #include "sysemu/sysemu.h" 29 #include "exec/hwaddr.h" 30 #include "kvm_arm.h" 31 #include "hw/arm/boot.h" 32 #include "hw/arm/fdt.h" 33 #include "hw/arm/smmuv3.h" 34 #include "hw/block/flash.h" 35 #include "hw/boards.h" 36 #include "hw/ide/internal.h" 37 #include "hw/ide/ahci_internal.h" 38 #include "hw/intc/arm_gicv3_common.h" 39 #include "hw/loader.h" 40 #include "hw/pci-host/gpex.h" 41 #include "hw/qdev-properties.h" 42 #include "hw/usb.h" 43 #include "hw/char/pl011.h" 44 #include "hw/watchdog/sbsa_gwdt.h" 45 #include "net/net.h" 46 #include "qom/object.h" 47 48 #define RAMLIMIT_GB 8192 49 #define RAMLIMIT_BYTES (RAMLIMIT_GB * GiB) 50 51 #define NUM_IRQS 256 52 #define NUM_SMMU_IRQS 4 53 #define NUM_SATA_PORTS 6 54 55 #define VIRTUAL_PMU_IRQ 7 56 #define ARCH_GIC_MAINT_IRQ 9 57 #define ARCH_TIMER_VIRT_IRQ 11 58 #define ARCH_TIMER_S_EL1_IRQ 13 59 #define ARCH_TIMER_NS_EL1_IRQ 14 60 #define ARCH_TIMER_NS_EL2_IRQ 10 61 62 enum { 63 SBSA_FLASH, 64 SBSA_MEM, 65 SBSA_CPUPERIPHS, 66 SBSA_GIC_DIST, 67 SBSA_GIC_REDIST, 68 SBSA_GIC_ITS, 69 SBSA_SECURE_EC, 70 SBSA_GWDT_WS0, 71 SBSA_GWDT_REFRESH, 72 SBSA_GWDT_CONTROL, 73 SBSA_SMMU, 74 SBSA_UART, 75 SBSA_RTC, 76 SBSA_PCIE, 77 SBSA_PCIE_MMIO, 78 SBSA_PCIE_MMIO_HIGH, 79 SBSA_PCIE_PIO, 80 SBSA_PCIE_ECAM, 81 SBSA_GPIO, 82 SBSA_SECURE_UART, 83 SBSA_SECURE_UART_MM, 84 SBSA_SECURE_MEM, 85 SBSA_AHCI, 86 SBSA_EHCI, 87 }; 88 89 struct SBSAMachineState { 90 MachineState parent; 91 struct arm_boot_info bootinfo; 92 int smp_cpus; 93 void *fdt; 94 int fdt_size; 95 int psci_conduit; 96 DeviceState *gic; 97 PFlashCFI01 *flash[2]; 98 }; 99 100 #define TYPE_SBSA_MACHINE MACHINE_TYPE_NAME("sbsa-ref") 101 OBJECT_DECLARE_SIMPLE_TYPE(SBSAMachineState, SBSA_MACHINE) 102 103 static const MemMapEntry sbsa_ref_memmap[] = { 104 /* 512M boot ROM */ 105 [SBSA_FLASH] = { 0, 0x20000000 }, 106 /* 512M secure memory */ 107 [SBSA_SECURE_MEM] = { 0x20000000, 0x20000000 }, 108 /* Space reserved for CPU peripheral devices */ 109 [SBSA_CPUPERIPHS] = { 0x40000000, 0x00040000 }, 110 [SBSA_GIC_DIST] = { 0x40060000, 0x00010000 }, 111 [SBSA_GIC_REDIST] = { 0x40080000, 0x04000000 }, 112 [SBSA_GIC_ITS] = { 0x44081000, 0x00020000 }, 113 [SBSA_SECURE_EC] = { 0x50000000, 0x00001000 }, 114 [SBSA_GWDT_REFRESH] = { 0x50010000, 0x00001000 }, 115 [SBSA_GWDT_CONTROL] = { 0x50011000, 0x00001000 }, 116 [SBSA_UART] = { 0x60000000, 0x00001000 }, 117 [SBSA_RTC] = { 0x60010000, 0x00001000 }, 118 [SBSA_GPIO] = { 0x60020000, 0x00001000 }, 119 [SBSA_SECURE_UART] = { 0x60030000, 0x00001000 }, 120 [SBSA_SECURE_UART_MM] = { 0x60040000, 0x00001000 }, 121 [SBSA_SMMU] = { 0x60050000, 0x00020000 }, 122 /* Space here reserved for more SMMUs */ 123 [SBSA_AHCI] = { 0x60100000, 0x00010000 }, 124 [SBSA_EHCI] = { 0x60110000, 0x00010000 }, 125 /* Space here reserved for other devices */ 126 [SBSA_PCIE_PIO] = { 0x7fff0000, 0x00010000 }, 127 /* 32-bit address PCIE MMIO space */ 128 [SBSA_PCIE_MMIO] = { 0x80000000, 0x70000000 }, 129 /* 256M PCIE ECAM space */ 130 [SBSA_PCIE_ECAM] = { 0xf0000000, 0x10000000 }, 131 /* ~1TB PCIE MMIO space (4GB to 1024GB boundary) */ 132 [SBSA_PCIE_MMIO_HIGH] = { 0x100000000ULL, 0xFF00000000ULL }, 133 [SBSA_MEM] = { 0x10000000000ULL, RAMLIMIT_BYTES }, 134 }; 135 136 static const int sbsa_ref_irqmap[] = { 137 [SBSA_UART] = 1, 138 [SBSA_RTC] = 2, 139 [SBSA_PCIE] = 3, /* ... to 6 */ 140 [SBSA_GPIO] = 7, 141 [SBSA_SECURE_UART] = 8, 142 [SBSA_SECURE_UART_MM] = 9, 143 [SBSA_AHCI] = 10, 144 [SBSA_EHCI] = 11, 145 [SBSA_SMMU] = 12, /* ... to 15 */ 146 [SBSA_GWDT_WS0] = 16, 147 }; 148 149 static const char * const valid_cpus[] = { 150 ARM_CPU_TYPE_NAME("cortex-a57"), 151 ARM_CPU_TYPE_NAME("cortex-a72"), 152 ARM_CPU_TYPE_NAME("neoverse-n1"), 153 ARM_CPU_TYPE_NAME("max"), 154 }; 155 156 static bool cpu_type_valid(const char *cpu) 157 { 158 int i; 159 160 for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) { 161 if (strcmp(cpu, valid_cpus[i]) == 0) { 162 return true; 163 } 164 } 165 return false; 166 } 167 168 static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx) 169 { 170 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER; 171 return arm_cpu_mp_affinity(idx, clustersz); 172 } 173 174 static void sbsa_fdt_add_gic_node(SBSAMachineState *sms) 175 { 176 char *nodename; 177 178 nodename = g_strdup_printf("/intc"); 179 qemu_fdt_add_subnode(sms->fdt, nodename); 180 qemu_fdt_setprop_sized_cells(sms->fdt, nodename, "reg", 181 2, sbsa_ref_memmap[SBSA_GIC_DIST].base, 182 2, sbsa_ref_memmap[SBSA_GIC_DIST].size, 183 2, sbsa_ref_memmap[SBSA_GIC_REDIST].base, 184 2, sbsa_ref_memmap[SBSA_GIC_REDIST].size); 185 186 nodename = g_strdup_printf("/intc/its"); 187 qemu_fdt_add_subnode(sms->fdt, nodename); 188 qemu_fdt_setprop_sized_cells(sms->fdt, nodename, "reg", 189 2, sbsa_ref_memmap[SBSA_GIC_ITS].base, 190 2, sbsa_ref_memmap[SBSA_GIC_ITS].size); 191 192 g_free(nodename); 193 } 194 195 /* 196 * Firmware on this machine only uses ACPI table to load OS, these limited 197 * device tree nodes are just to let firmware know the info which varies from 198 * command line parameters, so it is not necessary to be fully compatible 199 * with the kernel CPU and NUMA binding rules. 200 */ 201 static void create_fdt(SBSAMachineState *sms) 202 { 203 void *fdt = create_device_tree(&sms->fdt_size); 204 const MachineState *ms = MACHINE(sms); 205 int nb_numa_nodes = ms->numa_state->num_nodes; 206 int cpu; 207 208 if (!fdt) { 209 error_report("create_device_tree() failed"); 210 exit(1); 211 } 212 213 sms->fdt = fdt; 214 215 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,sbsa-ref"); 216 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 217 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 218 219 /* 220 * This versioning scheme is for informing platform fw only. It is neither: 221 * - A QEMU versioned machine type; a given version of QEMU will emulate 222 * a given version of the platform. 223 * - A reflection of level of SBSA (now SystemReady SR) support provided. 224 * 225 * machine-version-major: updated when changes breaking fw compatibility 226 * are introduced. 227 * machine-version-minor: updated when features are added that don't break 228 * fw compatibility. 229 */ 230 qemu_fdt_setprop_cell(fdt, "/", "machine-version-major", 0); 231 qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 2); 232 233 if (ms->numa_state->have_numa_distance) { 234 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); 235 uint32_t *matrix = g_malloc0(size); 236 int idx, i, j; 237 238 for (i = 0; i < nb_numa_nodes; i++) { 239 for (j = 0; j < nb_numa_nodes; j++) { 240 idx = (i * nb_numa_nodes + j) * 3; 241 matrix[idx + 0] = cpu_to_be32(i); 242 matrix[idx + 1] = cpu_to_be32(j); 243 matrix[idx + 2] = 244 cpu_to_be32(ms->numa_state->nodes[i].distance[j]); 245 } 246 } 247 248 qemu_fdt_add_subnode(fdt, "/distance-map"); 249 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", 250 matrix, size); 251 g_free(matrix); 252 } 253 254 /* 255 * From Documentation/devicetree/bindings/arm/cpus.yaml 256 * On ARM v8 64-bit systems this property is required 257 * and matches the MPIDR_EL1 register affinity bits. 258 * 259 * * If cpus node's #address-cells property is set to 2 260 * 261 * The first reg cell bits [7:0] must be set to 262 * bits [39:32] of MPIDR_EL1. 263 * 264 * The second reg cell bits [23:0] must be set to 265 * bits [23:0] of MPIDR_EL1. 266 */ 267 qemu_fdt_add_subnode(sms->fdt, "/cpus"); 268 qemu_fdt_setprop_cell(sms->fdt, "/cpus", "#address-cells", 2); 269 qemu_fdt_setprop_cell(sms->fdt, "/cpus", "#size-cells", 0x0); 270 271 for (cpu = sms->smp_cpus - 1; cpu >= 0; cpu--) { 272 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 273 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 274 CPUState *cs = CPU(armcpu); 275 uint64_t mpidr = sbsa_ref_cpu_mp_affinity(sms, cpu); 276 277 qemu_fdt_add_subnode(sms->fdt, nodename); 278 qemu_fdt_setprop_u64(sms->fdt, nodename, "reg", mpidr); 279 280 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 281 qemu_fdt_setprop_cell(sms->fdt, nodename, "numa-node-id", 282 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 283 } 284 285 g_free(nodename); 286 } 287 288 sbsa_fdt_add_gic_node(sms); 289 } 290 291 #define SBSA_FLASH_SECTOR_SIZE (256 * KiB) 292 293 static PFlashCFI01 *sbsa_flash_create1(SBSAMachineState *sms, 294 const char *name, 295 const char *alias_prop_name) 296 { 297 /* 298 * Create a single flash device. We use the same parameters as 299 * the flash devices on the Versatile Express board. 300 */ 301 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 302 303 qdev_prop_set_uint64(dev, "sector-length", SBSA_FLASH_SECTOR_SIZE); 304 qdev_prop_set_uint8(dev, "width", 4); 305 qdev_prop_set_uint8(dev, "device-width", 2); 306 qdev_prop_set_bit(dev, "big-endian", false); 307 qdev_prop_set_uint16(dev, "id0", 0x89); 308 qdev_prop_set_uint16(dev, "id1", 0x18); 309 qdev_prop_set_uint16(dev, "id2", 0x00); 310 qdev_prop_set_uint16(dev, "id3", 0x00); 311 qdev_prop_set_string(dev, "name", name); 312 object_property_add_child(OBJECT(sms), name, OBJECT(dev)); 313 object_property_add_alias(OBJECT(sms), alias_prop_name, 314 OBJECT(dev), "drive"); 315 return PFLASH_CFI01(dev); 316 } 317 318 static void sbsa_flash_create(SBSAMachineState *sms) 319 { 320 sms->flash[0] = sbsa_flash_create1(sms, "sbsa.flash0", "pflash0"); 321 sms->flash[1] = sbsa_flash_create1(sms, "sbsa.flash1", "pflash1"); 322 } 323 324 static void sbsa_flash_map1(PFlashCFI01 *flash, 325 hwaddr base, hwaddr size, 326 MemoryRegion *sysmem) 327 { 328 DeviceState *dev = DEVICE(flash); 329 330 assert(QEMU_IS_ALIGNED(size, SBSA_FLASH_SECTOR_SIZE)); 331 assert(size / SBSA_FLASH_SECTOR_SIZE <= UINT32_MAX); 332 qdev_prop_set_uint32(dev, "num-blocks", size / SBSA_FLASH_SECTOR_SIZE); 333 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 334 335 memory_region_add_subregion(sysmem, base, 336 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 337 0)); 338 } 339 340 static void sbsa_flash_map(SBSAMachineState *sms, 341 MemoryRegion *sysmem, 342 MemoryRegion *secure_sysmem) 343 { 344 /* 345 * Map two flash devices to fill the SBSA_FLASH space in the memmap. 346 * sysmem is the system memory space. secure_sysmem is the secure view 347 * of the system, and the first flash device should be made visible only 348 * there. The second flash device is visible to both secure and nonsecure. 349 */ 350 hwaddr flashsize = sbsa_ref_memmap[SBSA_FLASH].size / 2; 351 hwaddr flashbase = sbsa_ref_memmap[SBSA_FLASH].base; 352 353 sbsa_flash_map1(sms->flash[0], flashbase, flashsize, 354 secure_sysmem); 355 sbsa_flash_map1(sms->flash[1], flashbase + flashsize, flashsize, 356 sysmem); 357 } 358 359 static bool sbsa_firmware_init(SBSAMachineState *sms, 360 MemoryRegion *sysmem, 361 MemoryRegion *secure_sysmem) 362 { 363 const char *bios_name; 364 int i; 365 BlockBackend *pflash_blk0; 366 367 /* Map legacy -drive if=pflash to machine properties */ 368 for (i = 0; i < ARRAY_SIZE(sms->flash); i++) { 369 pflash_cfi01_legacy_drive(sms->flash[i], 370 drive_get(IF_PFLASH, 0, i)); 371 } 372 373 sbsa_flash_map(sms, sysmem, secure_sysmem); 374 375 pflash_blk0 = pflash_cfi01_get_blk(sms->flash[0]); 376 377 bios_name = MACHINE(sms)->firmware; 378 if (bios_name) { 379 char *fname; 380 MemoryRegion *mr; 381 int image_size; 382 383 if (pflash_blk0) { 384 error_report("The contents of the first flash device may be " 385 "specified with -bios or with -drive if=pflash... " 386 "but you cannot use both options at once"); 387 exit(1); 388 } 389 390 /* Fall back to -bios */ 391 392 fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 393 if (!fname) { 394 error_report("Could not find ROM image '%s'", bios_name); 395 exit(1); 396 } 397 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(sms->flash[0]), 0); 398 image_size = load_image_mr(fname, mr); 399 g_free(fname); 400 if (image_size < 0) { 401 error_report("Could not load ROM image '%s'", bios_name); 402 exit(1); 403 } 404 } 405 406 return pflash_blk0 || bios_name; 407 } 408 409 static void create_secure_ram(SBSAMachineState *sms, 410 MemoryRegion *secure_sysmem) 411 { 412 MemoryRegion *secram = g_new(MemoryRegion, 1); 413 hwaddr base = sbsa_ref_memmap[SBSA_SECURE_MEM].base; 414 hwaddr size = sbsa_ref_memmap[SBSA_SECURE_MEM].size; 415 416 memory_region_init_ram(secram, NULL, "sbsa-ref.secure-ram", size, 417 &error_fatal); 418 memory_region_add_subregion(secure_sysmem, base, secram); 419 } 420 421 static void create_its(SBSAMachineState *sms) 422 { 423 const char *itsclass = its_class_name(); 424 DeviceState *dev; 425 426 dev = qdev_new(itsclass); 427 428 object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(sms->gic), 429 &error_abort); 430 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 431 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, sbsa_ref_memmap[SBSA_GIC_ITS].base); 432 } 433 434 static void create_gic(SBSAMachineState *sms, MemoryRegion *mem) 435 { 436 unsigned int smp_cpus = MACHINE(sms)->smp.cpus; 437 SysBusDevice *gicbusdev; 438 const char *gictype; 439 uint32_t redist0_capacity, redist0_count; 440 int i; 441 442 gictype = gicv3_class_name(); 443 444 sms->gic = qdev_new(gictype); 445 qdev_prop_set_uint32(sms->gic, "revision", 3); 446 qdev_prop_set_uint32(sms->gic, "num-cpu", smp_cpus); 447 /* 448 * Note that the num-irq property counts both internal and external 449 * interrupts; there are always 32 of the former (mandated by GIC spec). 450 */ 451 qdev_prop_set_uint32(sms->gic, "num-irq", NUM_IRQS + 32); 452 qdev_prop_set_bit(sms->gic, "has-security-extensions", true); 453 454 redist0_capacity = 455 sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE; 456 redist0_count = MIN(smp_cpus, redist0_capacity); 457 458 qdev_prop_set_uint32(sms->gic, "len-redist-region-count", 1); 459 qdev_prop_set_uint32(sms->gic, "redist-region-count[0]", redist0_count); 460 461 object_property_set_link(OBJECT(sms->gic), "sysmem", 462 OBJECT(mem), &error_fatal); 463 qdev_prop_set_bit(sms->gic, "has-lpi", true); 464 465 gicbusdev = SYS_BUS_DEVICE(sms->gic); 466 sysbus_realize_and_unref(gicbusdev, &error_fatal); 467 sysbus_mmio_map(gicbusdev, 0, sbsa_ref_memmap[SBSA_GIC_DIST].base); 468 sysbus_mmio_map(gicbusdev, 1, sbsa_ref_memmap[SBSA_GIC_REDIST].base); 469 470 /* 471 * Wire the outputs from each CPU's generic timer and the GICv3 472 * maintenance interrupt signal to the appropriate GIC PPI inputs, 473 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. 474 */ 475 for (i = 0; i < smp_cpus; i++) { 476 DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); 477 int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; 478 int irq; 479 /* 480 * Mapping from the output timer irq lines from the CPU to the 481 * GIC PPI inputs used for this board. 482 */ 483 const int timer_irq[] = { 484 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 485 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 486 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 487 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 488 }; 489 490 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 491 qdev_connect_gpio_out(cpudev, irq, 492 qdev_get_gpio_in(sms->gic, 493 ppibase + timer_irq[irq])); 494 } 495 496 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0, 497 qdev_get_gpio_in(sms->gic, ppibase 498 + ARCH_GIC_MAINT_IRQ)); 499 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 500 qdev_get_gpio_in(sms->gic, ppibase 501 + VIRTUAL_PMU_IRQ)); 502 503 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 504 sysbus_connect_irq(gicbusdev, i + smp_cpus, 505 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 506 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, 507 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 508 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, 509 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 510 } 511 create_its(sms); 512 } 513 514 static void create_uart(const SBSAMachineState *sms, int uart, 515 MemoryRegion *mem, Chardev *chr) 516 { 517 hwaddr base = sbsa_ref_memmap[uart].base; 518 int irq = sbsa_ref_irqmap[uart]; 519 DeviceState *dev = qdev_new(TYPE_PL011); 520 SysBusDevice *s = SYS_BUS_DEVICE(dev); 521 522 qdev_prop_set_chr(dev, "chardev", chr); 523 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 524 memory_region_add_subregion(mem, base, 525 sysbus_mmio_get_region(s, 0)); 526 sysbus_connect_irq(s, 0, qdev_get_gpio_in(sms->gic, irq)); 527 } 528 529 static void create_rtc(const SBSAMachineState *sms) 530 { 531 hwaddr base = sbsa_ref_memmap[SBSA_RTC].base; 532 int irq = sbsa_ref_irqmap[SBSA_RTC]; 533 534 sysbus_create_simple("pl031", base, qdev_get_gpio_in(sms->gic, irq)); 535 } 536 537 static void create_wdt(const SBSAMachineState *sms) 538 { 539 hwaddr rbase = sbsa_ref_memmap[SBSA_GWDT_REFRESH].base; 540 hwaddr cbase = sbsa_ref_memmap[SBSA_GWDT_CONTROL].base; 541 DeviceState *dev = qdev_new(TYPE_WDT_SBSA); 542 SysBusDevice *s = SYS_BUS_DEVICE(dev); 543 int irq = sbsa_ref_irqmap[SBSA_GWDT_WS0]; 544 545 sysbus_realize_and_unref(s, &error_fatal); 546 sysbus_mmio_map(s, 0, rbase); 547 sysbus_mmio_map(s, 1, cbase); 548 sysbus_connect_irq(s, 0, qdev_get_gpio_in(sms->gic, irq)); 549 } 550 551 static DeviceState *gpio_key_dev; 552 static void sbsa_ref_powerdown_req(Notifier *n, void *opaque) 553 { 554 /* use gpio Pin 3 for power button event */ 555 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); 556 } 557 558 static Notifier sbsa_ref_powerdown_notifier = { 559 .notify = sbsa_ref_powerdown_req 560 }; 561 562 static void create_gpio(const SBSAMachineState *sms) 563 { 564 DeviceState *pl061_dev; 565 hwaddr base = sbsa_ref_memmap[SBSA_GPIO].base; 566 int irq = sbsa_ref_irqmap[SBSA_GPIO]; 567 568 pl061_dev = sysbus_create_simple("pl061", base, 569 qdev_get_gpio_in(sms->gic, irq)); 570 571 gpio_key_dev = sysbus_create_simple("gpio-key", -1, 572 qdev_get_gpio_in(pl061_dev, 3)); 573 574 /* connect powerdown request */ 575 qemu_register_powerdown_notifier(&sbsa_ref_powerdown_notifier); 576 } 577 578 static void create_ahci(const SBSAMachineState *sms) 579 { 580 hwaddr base = sbsa_ref_memmap[SBSA_AHCI].base; 581 int irq = sbsa_ref_irqmap[SBSA_AHCI]; 582 DeviceState *dev; 583 DriveInfo *hd[NUM_SATA_PORTS]; 584 SysbusAHCIState *sysahci; 585 AHCIState *ahci; 586 int i; 587 588 dev = qdev_new("sysbus-ahci"); 589 qdev_prop_set_uint32(dev, "num-ports", NUM_SATA_PORTS); 590 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 591 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 592 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(sms->gic, irq)); 593 594 sysahci = SYSBUS_AHCI(dev); 595 ahci = &sysahci->ahci; 596 ide_drive_get(hd, ARRAY_SIZE(hd)); 597 for (i = 0; i < ahci->ports; i++) { 598 if (hd[i] == NULL) { 599 continue; 600 } 601 ide_bus_create_drive(&ahci->dev[i].port, 0, hd[i]); 602 } 603 } 604 605 static void create_ehci(const SBSAMachineState *sms) 606 { 607 hwaddr base = sbsa_ref_memmap[SBSA_EHCI].base; 608 int irq = sbsa_ref_irqmap[SBSA_EHCI]; 609 610 sysbus_create_simple("platform-ehci-usb", base, 611 qdev_get_gpio_in(sms->gic, irq)); 612 } 613 614 static void create_smmu(const SBSAMachineState *sms, PCIBus *bus) 615 { 616 hwaddr base = sbsa_ref_memmap[SBSA_SMMU].base; 617 int irq = sbsa_ref_irqmap[SBSA_SMMU]; 618 DeviceState *dev; 619 int i; 620 621 dev = qdev_new(TYPE_ARM_SMMUV3); 622 623 object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus), 624 &error_abort); 625 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 626 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 627 for (i = 0; i < NUM_SMMU_IRQS; i++) { 628 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 629 qdev_get_gpio_in(sms->gic, irq + i)); 630 } 631 } 632 633 static void create_pcie(SBSAMachineState *sms) 634 { 635 hwaddr base_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].base; 636 hwaddr size_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].size; 637 hwaddr base_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].base; 638 hwaddr size_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].size; 639 hwaddr base_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].base; 640 hwaddr size_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].size; 641 hwaddr base_pio = sbsa_ref_memmap[SBSA_PCIE_PIO].base; 642 int irq = sbsa_ref_irqmap[SBSA_PCIE]; 643 MachineClass *mc = MACHINE_GET_CLASS(sms); 644 MemoryRegion *mmio_alias, *mmio_alias_high, *mmio_reg; 645 MemoryRegion *ecam_alias, *ecam_reg; 646 DeviceState *dev; 647 PCIHostState *pci; 648 int i; 649 650 dev = qdev_new(TYPE_GPEX_HOST); 651 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 652 653 /* Map ECAM space */ 654 ecam_alias = g_new0(MemoryRegion, 1); 655 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 656 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 657 ecam_reg, 0, size_ecam); 658 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); 659 660 /* Map the MMIO space */ 661 mmio_alias = g_new0(MemoryRegion, 1); 662 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 663 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 664 mmio_reg, base_mmio, size_mmio); 665 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); 666 667 /* Map the MMIO_HIGH space */ 668 mmio_alias_high = g_new0(MemoryRegion, 1); 669 memory_region_init_alias(mmio_alias_high, OBJECT(dev), "pcie-mmio-high", 670 mmio_reg, base_mmio_high, size_mmio_high); 671 memory_region_add_subregion(get_system_memory(), base_mmio_high, 672 mmio_alias_high); 673 674 /* Map IO port space */ 675 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); 676 677 for (i = 0; i < GPEX_NUM_IRQS; i++) { 678 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 679 qdev_get_gpio_in(sms->gic, irq + i)); 680 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); 681 } 682 683 pci = PCI_HOST_BRIDGE(dev); 684 if (pci->bus) { 685 for (i = 0; i < nb_nics; i++) { 686 NICInfo *nd = &nd_table[i]; 687 688 if (!nd->model) { 689 nd->model = g_strdup(mc->default_nic); 690 } 691 692 pci_nic_init_nofail(nd, pci->bus, nd->model, NULL); 693 } 694 } 695 696 pci_create_simple(pci->bus, -1, "bochs-display"); 697 698 create_smmu(sms, pci->bus); 699 } 700 701 static void *sbsa_ref_dtb(const struct arm_boot_info *binfo, int *fdt_size) 702 { 703 const SBSAMachineState *board = container_of(binfo, SBSAMachineState, 704 bootinfo); 705 706 *fdt_size = board->fdt_size; 707 return board->fdt; 708 } 709 710 static void create_secure_ec(MemoryRegion *mem) 711 { 712 hwaddr base = sbsa_ref_memmap[SBSA_SECURE_EC].base; 713 DeviceState *dev = qdev_new("sbsa-ec"); 714 SysBusDevice *s = SYS_BUS_DEVICE(dev); 715 716 memory_region_add_subregion(mem, base, 717 sysbus_mmio_get_region(s, 0)); 718 } 719 720 static void sbsa_ref_init(MachineState *machine) 721 { 722 unsigned int smp_cpus = machine->smp.cpus; 723 unsigned int max_cpus = machine->smp.max_cpus; 724 SBSAMachineState *sms = SBSA_MACHINE(machine); 725 MachineClass *mc = MACHINE_GET_CLASS(machine); 726 MemoryRegion *sysmem = get_system_memory(); 727 MemoryRegion *secure_sysmem = g_new(MemoryRegion, 1); 728 bool firmware_loaded; 729 const CPUArchIdList *possible_cpus; 730 int n, sbsa_max_cpus; 731 732 if (!cpu_type_valid(machine->cpu_type)) { 733 error_report("sbsa-ref: CPU type %s not supported", machine->cpu_type); 734 exit(1); 735 } 736 737 if (kvm_enabled()) { 738 error_report("sbsa-ref: KVM is not supported for this machine"); 739 exit(1); 740 } 741 742 /* 743 * The Secure view of the world is the same as the NonSecure, 744 * but with a few extra devices. Create it as a container region 745 * containing the system memory at low priority; any secure-only 746 * devices go in at higher priority and take precedence. 747 */ 748 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", 749 UINT64_MAX); 750 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); 751 752 firmware_loaded = sbsa_firmware_init(sms, sysmem, secure_sysmem); 753 754 /* 755 * This machine has EL3 enabled, external firmware should supply PSCI 756 * implementation, so the QEMU's internal PSCI is disabled. 757 */ 758 sms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; 759 760 sbsa_max_cpus = sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE; 761 762 if (max_cpus > sbsa_max_cpus) { 763 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " 764 "supported by machine 'sbsa-ref' (%d)", 765 max_cpus, sbsa_max_cpus); 766 exit(1); 767 } 768 769 sms->smp_cpus = smp_cpus; 770 771 if (machine->ram_size > sbsa_ref_memmap[SBSA_MEM].size) { 772 error_report("sbsa-ref: cannot model more than %dGB RAM", RAMLIMIT_GB); 773 exit(1); 774 } 775 776 possible_cpus = mc->possible_cpu_arch_ids(machine); 777 for (n = 0; n < possible_cpus->len; n++) { 778 Object *cpuobj; 779 CPUState *cs; 780 781 if (n >= smp_cpus) { 782 break; 783 } 784 785 cpuobj = object_new(possible_cpus->cpus[n].type); 786 object_property_set_int(cpuobj, "mp-affinity", 787 possible_cpus->cpus[n].arch_id, NULL); 788 789 cs = CPU(cpuobj); 790 cs->cpu_index = n; 791 792 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj), 793 &error_fatal); 794 795 if (object_property_find(cpuobj, "reset-cbar")) { 796 object_property_set_int(cpuobj, "reset-cbar", 797 sbsa_ref_memmap[SBSA_CPUPERIPHS].base, 798 &error_abort); 799 } 800 801 object_property_set_link(cpuobj, "memory", OBJECT(sysmem), 802 &error_abort); 803 804 object_property_set_link(cpuobj, "secure-memory", 805 OBJECT(secure_sysmem), &error_abort); 806 807 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); 808 object_unref(cpuobj); 809 } 810 811 memory_region_add_subregion(sysmem, sbsa_ref_memmap[SBSA_MEM].base, 812 machine->ram); 813 814 create_fdt(sms); 815 816 create_secure_ram(sms, secure_sysmem); 817 818 create_gic(sms, sysmem); 819 820 create_uart(sms, SBSA_UART, sysmem, serial_hd(0)); 821 create_uart(sms, SBSA_SECURE_UART, secure_sysmem, serial_hd(1)); 822 /* Second secure UART for RAS and MM from EL0 */ 823 create_uart(sms, SBSA_SECURE_UART_MM, secure_sysmem, serial_hd(2)); 824 825 create_rtc(sms); 826 827 create_wdt(sms); 828 829 create_gpio(sms); 830 831 create_ahci(sms); 832 833 create_ehci(sms); 834 835 create_pcie(sms); 836 837 create_secure_ec(secure_sysmem); 838 839 sms->bootinfo.ram_size = machine->ram_size; 840 sms->bootinfo.board_id = -1; 841 sms->bootinfo.loader_start = sbsa_ref_memmap[SBSA_MEM].base; 842 sms->bootinfo.get_dtb = sbsa_ref_dtb; 843 sms->bootinfo.firmware_loaded = firmware_loaded; 844 arm_load_kernel(ARM_CPU(first_cpu), machine, &sms->bootinfo); 845 } 846 847 static const CPUArchIdList *sbsa_ref_possible_cpu_arch_ids(MachineState *ms) 848 { 849 unsigned int max_cpus = ms->smp.max_cpus; 850 SBSAMachineState *sms = SBSA_MACHINE(ms); 851 int n; 852 853 if (ms->possible_cpus) { 854 assert(ms->possible_cpus->len == max_cpus); 855 return ms->possible_cpus; 856 } 857 858 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 859 sizeof(CPUArchId) * max_cpus); 860 ms->possible_cpus->len = max_cpus; 861 for (n = 0; n < ms->possible_cpus->len; n++) { 862 ms->possible_cpus->cpus[n].type = ms->cpu_type; 863 ms->possible_cpus->cpus[n].arch_id = 864 sbsa_ref_cpu_mp_affinity(sms, n); 865 ms->possible_cpus->cpus[n].props.has_thread_id = true; 866 ms->possible_cpus->cpus[n].props.thread_id = n; 867 } 868 return ms->possible_cpus; 869 } 870 871 static CpuInstanceProperties 872 sbsa_ref_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 873 { 874 MachineClass *mc = MACHINE_GET_CLASS(ms); 875 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 876 877 assert(cpu_index < possible_cpus->len); 878 return possible_cpus->cpus[cpu_index].props; 879 } 880 881 static int64_t 882 sbsa_ref_get_default_cpu_node_id(const MachineState *ms, int idx) 883 { 884 return idx % ms->numa_state->num_nodes; 885 } 886 887 static void sbsa_ref_instance_init(Object *obj) 888 { 889 SBSAMachineState *sms = SBSA_MACHINE(obj); 890 891 sbsa_flash_create(sms); 892 } 893 894 static void sbsa_ref_class_init(ObjectClass *oc, void *data) 895 { 896 MachineClass *mc = MACHINE_CLASS(oc); 897 898 mc->init = sbsa_ref_init; 899 mc->desc = "QEMU 'SBSA Reference' ARM Virtual Machine"; 900 mc->default_cpu_type = ARM_CPU_TYPE_NAME("neoverse-n1"); 901 mc->max_cpus = 512; 902 mc->pci_allow_0_address = true; 903 mc->minimum_page_bits = 12; 904 mc->block_default_type = IF_IDE; 905 mc->no_cdrom = 1; 906 mc->default_nic = "e1000e"; 907 mc->default_ram_size = 1 * GiB; 908 mc->default_ram_id = "sbsa-ref.ram"; 909 mc->default_cpus = 4; 910 mc->possible_cpu_arch_ids = sbsa_ref_possible_cpu_arch_ids; 911 mc->cpu_index_to_instance_props = sbsa_ref_cpu_index_to_props; 912 mc->get_default_cpu_node_id = sbsa_ref_get_default_cpu_node_id; 913 /* platform instead of architectural choice */ 914 mc->cpu_cluster_has_numa_boundary = true; 915 } 916 917 static const TypeInfo sbsa_ref_info = { 918 .name = TYPE_SBSA_MACHINE, 919 .parent = TYPE_MACHINE, 920 .instance_init = sbsa_ref_instance_init, 921 .class_init = sbsa_ref_class_init, 922 .instance_size = sizeof(SBSAMachineState), 923 }; 924 925 static void sbsa_ref_machine_init(void) 926 { 927 type_register_static(&sbsa_ref_info); 928 } 929 930 type_init(sbsa_ref_machine_init); 931