1 /* 2 * ARM SBSA Reference Platform emulation 3 * 4 * Copyright (c) 2018 Linaro Limited 5 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 6 * Written by Hongbo Zhang <hongbo.zhang@linaro.org> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2 or later, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/datadir.h" 23 #include "qapi/error.h" 24 #include "qemu/error-report.h" 25 #include "qemu/units.h" 26 #include "sysemu/device_tree.h" 27 #include "sysemu/kvm.h" 28 #include "sysemu/numa.h" 29 #include "sysemu/runstate.h" 30 #include "sysemu/sysemu.h" 31 #include "exec/hwaddr.h" 32 #include "kvm_arm.h" 33 #include "hw/arm/boot.h" 34 #include "hw/arm/bsa.h" 35 #include "hw/arm/fdt.h" 36 #include "hw/arm/smmuv3.h" 37 #include "hw/block/flash.h" 38 #include "hw/boards.h" 39 #include "hw/ide/ide-bus.h" 40 #include "hw/ide/ahci-sysbus.h" 41 #include "hw/intc/arm_gicv3_common.h" 42 #include "hw/intc/arm_gicv3_its_common.h" 43 #include "hw/loader.h" 44 #include "hw/pci-host/gpex.h" 45 #include "hw/qdev-properties.h" 46 #include "hw/usb.h" 47 #include "hw/usb/xhci.h" 48 #include "hw/char/pl011.h" 49 #include "hw/watchdog/sbsa_gwdt.h" 50 #include "net/net.h" 51 #include "qapi/qmp/qlist.h" 52 #include "qom/object.h" 53 #include "target/arm/cpu-qom.h" 54 #include "target/arm/gtimer.h" 55 56 #define RAMLIMIT_GB 8192 57 #define RAMLIMIT_BYTES (RAMLIMIT_GB * GiB) 58 59 #define NUM_IRQS 256 60 #define NUM_SMMU_IRQS 4 61 #define NUM_SATA_PORTS 6 62 63 /* 64 * Generic timer frequency in Hz (which drives both the CPU generic timers 65 * and the SBSA watchdog-timer). Older (<2.11) versions of the TF-A firmware 66 * assumed 62.5MHz here. 67 * 68 * Starting with Armv8.6 CPU 1GHz timer frequency is mandated. 69 */ 70 #define SBSA_GTIMER_HZ 1000000000 71 72 enum { 73 SBSA_FLASH, 74 SBSA_MEM, 75 SBSA_CPUPERIPHS, 76 SBSA_GIC_DIST, 77 SBSA_GIC_REDIST, 78 SBSA_GIC_ITS, 79 SBSA_SECURE_EC, 80 SBSA_GWDT_WS0, 81 SBSA_GWDT_REFRESH, 82 SBSA_GWDT_CONTROL, 83 SBSA_SMMU, 84 SBSA_UART, 85 SBSA_RTC, 86 SBSA_PCIE, 87 SBSA_PCIE_MMIO, 88 SBSA_PCIE_MMIO_HIGH, 89 SBSA_PCIE_PIO, 90 SBSA_PCIE_ECAM, 91 SBSA_GPIO, 92 SBSA_SECURE_UART, 93 SBSA_SECURE_UART_MM, 94 SBSA_SECURE_MEM, 95 SBSA_AHCI, 96 SBSA_XHCI, 97 }; 98 99 struct SBSAMachineState { 100 MachineState parent; 101 struct arm_boot_info bootinfo; 102 int smp_cpus; 103 void *fdt; 104 int fdt_size; 105 int psci_conduit; 106 DeviceState *gic; 107 PFlashCFI01 *flash[2]; 108 }; 109 110 #define TYPE_SBSA_MACHINE MACHINE_TYPE_NAME("sbsa-ref") 111 OBJECT_DECLARE_SIMPLE_TYPE(SBSAMachineState, SBSA_MACHINE) 112 113 static const MemMapEntry sbsa_ref_memmap[] = { 114 /* 512M boot ROM */ 115 [SBSA_FLASH] = { 0, 0x20000000 }, 116 /* 512M secure memory */ 117 [SBSA_SECURE_MEM] = { 0x20000000, 0x20000000 }, 118 /* Space reserved for CPU peripheral devices */ 119 [SBSA_CPUPERIPHS] = { 0x40000000, 0x00040000 }, 120 [SBSA_GIC_DIST] = { 0x40060000, 0x00010000 }, 121 [SBSA_GIC_REDIST] = { 0x40080000, 0x04000000 }, 122 [SBSA_GIC_ITS] = { 0x44081000, 0x00020000 }, 123 [SBSA_SECURE_EC] = { 0x50000000, 0x00001000 }, 124 [SBSA_GWDT_REFRESH] = { 0x50010000, 0x00001000 }, 125 [SBSA_GWDT_CONTROL] = { 0x50011000, 0x00001000 }, 126 [SBSA_UART] = { 0x60000000, 0x00001000 }, 127 [SBSA_RTC] = { 0x60010000, 0x00001000 }, 128 [SBSA_GPIO] = { 0x60020000, 0x00001000 }, 129 [SBSA_SECURE_UART] = { 0x60030000, 0x00001000 }, 130 [SBSA_SECURE_UART_MM] = { 0x60040000, 0x00001000 }, 131 [SBSA_SMMU] = { 0x60050000, 0x00020000 }, 132 /* Space here reserved for more SMMUs */ 133 [SBSA_AHCI] = { 0x60100000, 0x00010000 }, 134 [SBSA_XHCI] = { 0x60110000, 0x00010000 }, 135 /* Space here reserved for other devices */ 136 [SBSA_PCIE_PIO] = { 0x7fff0000, 0x00010000 }, 137 /* 32-bit address PCIE MMIO space */ 138 [SBSA_PCIE_MMIO] = { 0x80000000, 0x70000000 }, 139 /* 256M PCIE ECAM space */ 140 [SBSA_PCIE_ECAM] = { 0xf0000000, 0x10000000 }, 141 /* ~1TB PCIE MMIO space (4GB to 1024GB boundary) */ 142 [SBSA_PCIE_MMIO_HIGH] = { 0x100000000ULL, 0xFF00000000ULL }, 143 [SBSA_MEM] = { 0x10000000000ULL, RAMLIMIT_BYTES }, 144 }; 145 146 static const int sbsa_ref_irqmap[] = { 147 [SBSA_UART] = 1, 148 [SBSA_RTC] = 2, 149 [SBSA_PCIE] = 3, /* ... to 6 */ 150 [SBSA_GPIO] = 7, 151 [SBSA_SECURE_UART] = 8, 152 [SBSA_SECURE_UART_MM] = 9, 153 [SBSA_AHCI] = 10, 154 [SBSA_XHCI] = 11, 155 [SBSA_SMMU] = 12, /* ... to 15 */ 156 [SBSA_GWDT_WS0] = 16, 157 }; 158 159 static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx) 160 { 161 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER; 162 return arm_build_mp_affinity(idx, clustersz); 163 } 164 165 static void sbsa_fdt_add_gic_node(SBSAMachineState *sms) 166 { 167 char *nodename; 168 169 nodename = g_strdup_printf("/intc"); 170 qemu_fdt_add_subnode(sms->fdt, nodename); 171 qemu_fdt_setprop_sized_cells(sms->fdt, nodename, "reg", 172 2, sbsa_ref_memmap[SBSA_GIC_DIST].base, 173 2, sbsa_ref_memmap[SBSA_GIC_DIST].size, 174 2, sbsa_ref_memmap[SBSA_GIC_REDIST].base, 175 2, sbsa_ref_memmap[SBSA_GIC_REDIST].size); 176 177 nodename = g_strdup_printf("/intc/its"); 178 qemu_fdt_add_subnode(sms->fdt, nodename); 179 qemu_fdt_setprop_sized_cells(sms->fdt, nodename, "reg", 180 2, sbsa_ref_memmap[SBSA_GIC_ITS].base, 181 2, sbsa_ref_memmap[SBSA_GIC_ITS].size); 182 183 g_free(nodename); 184 } 185 186 /* 187 * Firmware on this machine only uses ACPI table to load OS, these limited 188 * device tree nodes are just to let firmware know the info which varies from 189 * command line parameters, so it is not necessary to be fully compatible 190 * with the kernel CPU and NUMA binding rules. 191 */ 192 static void create_fdt(SBSAMachineState *sms) 193 { 194 void *fdt = create_device_tree(&sms->fdt_size); 195 const MachineState *ms = MACHINE(sms); 196 int nb_numa_nodes = ms->numa_state->num_nodes; 197 int cpu; 198 199 if (!fdt) { 200 error_report("create_device_tree() failed"); 201 exit(1); 202 } 203 204 sms->fdt = fdt; 205 206 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,sbsa-ref"); 207 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 208 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 209 210 /* 211 * This versioning scheme is for informing platform fw only. It is neither: 212 * - A QEMU versioned machine type; a given version of QEMU will emulate 213 * a given version of the platform. 214 * - A reflection of level of SBSA (now SystemReady SR) support provided. 215 * 216 * machine-version-major: updated when changes breaking fw compatibility 217 * are introduced. 218 * machine-version-minor: updated when features are added that don't break 219 * fw compatibility. 220 */ 221 qemu_fdt_setprop_cell(fdt, "/", "machine-version-major", 0); 222 qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 3); 223 224 if (ms->numa_state->have_numa_distance) { 225 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); 226 uint32_t *matrix = g_malloc0(size); 227 int idx, i, j; 228 229 for (i = 0; i < nb_numa_nodes; i++) { 230 for (j = 0; j < nb_numa_nodes; j++) { 231 idx = (i * nb_numa_nodes + j) * 3; 232 matrix[idx + 0] = cpu_to_be32(i); 233 matrix[idx + 1] = cpu_to_be32(j); 234 matrix[idx + 2] = 235 cpu_to_be32(ms->numa_state->nodes[i].distance[j]); 236 } 237 } 238 239 qemu_fdt_add_subnode(fdt, "/distance-map"); 240 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", 241 matrix, size); 242 g_free(matrix); 243 } 244 245 /* 246 * From Documentation/devicetree/bindings/arm/cpus.yaml 247 * On ARM v8 64-bit systems this property is required 248 * and matches the MPIDR_EL1 register affinity bits. 249 * 250 * * If cpus node's #address-cells property is set to 2 251 * 252 * The first reg cell bits [7:0] must be set to 253 * bits [39:32] of MPIDR_EL1. 254 * 255 * The second reg cell bits [23:0] must be set to 256 * bits [23:0] of MPIDR_EL1. 257 */ 258 qemu_fdt_add_subnode(sms->fdt, "/cpus"); 259 qemu_fdt_setprop_cell(sms->fdt, "/cpus", "#address-cells", 2); 260 qemu_fdt_setprop_cell(sms->fdt, "/cpus", "#size-cells", 0x0); 261 262 for (cpu = sms->smp_cpus - 1; cpu >= 0; cpu--) { 263 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 264 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 265 CPUState *cs = CPU(armcpu); 266 uint64_t mpidr = sbsa_ref_cpu_mp_affinity(sms, cpu); 267 268 qemu_fdt_add_subnode(sms->fdt, nodename); 269 qemu_fdt_setprop_u64(sms->fdt, nodename, "reg", mpidr); 270 271 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 272 qemu_fdt_setprop_cell(sms->fdt, nodename, "numa-node-id", 273 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 274 } 275 276 g_free(nodename); 277 } 278 279 sbsa_fdt_add_gic_node(sms); 280 } 281 282 #define SBSA_FLASH_SECTOR_SIZE (256 * KiB) 283 284 static PFlashCFI01 *sbsa_flash_create1(SBSAMachineState *sms, 285 const char *name, 286 const char *alias_prop_name) 287 { 288 /* 289 * Create a single flash device. We use the same parameters as 290 * the flash devices on the Versatile Express board. 291 */ 292 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 293 294 qdev_prop_set_uint64(dev, "sector-length", SBSA_FLASH_SECTOR_SIZE); 295 qdev_prop_set_uint8(dev, "width", 4); 296 qdev_prop_set_uint8(dev, "device-width", 2); 297 qdev_prop_set_bit(dev, "big-endian", false); 298 qdev_prop_set_uint16(dev, "id0", 0x89); 299 qdev_prop_set_uint16(dev, "id1", 0x18); 300 qdev_prop_set_uint16(dev, "id2", 0x00); 301 qdev_prop_set_uint16(dev, "id3", 0x00); 302 qdev_prop_set_string(dev, "name", name); 303 object_property_add_child(OBJECT(sms), name, OBJECT(dev)); 304 object_property_add_alias(OBJECT(sms), alias_prop_name, 305 OBJECT(dev), "drive"); 306 return PFLASH_CFI01(dev); 307 } 308 309 static void sbsa_flash_create(SBSAMachineState *sms) 310 { 311 sms->flash[0] = sbsa_flash_create1(sms, "sbsa.flash0", "pflash0"); 312 sms->flash[1] = sbsa_flash_create1(sms, "sbsa.flash1", "pflash1"); 313 } 314 315 static void sbsa_flash_map1(PFlashCFI01 *flash, 316 hwaddr base, hwaddr size, 317 MemoryRegion *sysmem) 318 { 319 DeviceState *dev = DEVICE(flash); 320 321 assert(QEMU_IS_ALIGNED(size, SBSA_FLASH_SECTOR_SIZE)); 322 assert(size / SBSA_FLASH_SECTOR_SIZE <= UINT32_MAX); 323 qdev_prop_set_uint32(dev, "num-blocks", size / SBSA_FLASH_SECTOR_SIZE); 324 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 325 326 memory_region_add_subregion(sysmem, base, 327 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 328 0)); 329 } 330 331 static void sbsa_flash_map(SBSAMachineState *sms, 332 MemoryRegion *sysmem, 333 MemoryRegion *secure_sysmem) 334 { 335 /* 336 * Map two flash devices to fill the SBSA_FLASH space in the memmap. 337 * sysmem is the system memory space. secure_sysmem is the secure view 338 * of the system, and the first flash device should be made visible only 339 * there. The second flash device is visible to both secure and nonsecure. 340 */ 341 hwaddr flashsize = sbsa_ref_memmap[SBSA_FLASH].size / 2; 342 hwaddr flashbase = sbsa_ref_memmap[SBSA_FLASH].base; 343 344 sbsa_flash_map1(sms->flash[0], flashbase, flashsize, 345 secure_sysmem); 346 sbsa_flash_map1(sms->flash[1], flashbase + flashsize, flashsize, 347 sysmem); 348 } 349 350 static bool sbsa_firmware_init(SBSAMachineState *sms, 351 MemoryRegion *sysmem, 352 MemoryRegion *secure_sysmem) 353 { 354 const char *bios_name; 355 int i; 356 BlockBackend *pflash_blk0; 357 358 /* Map legacy -drive if=pflash to machine properties */ 359 for (i = 0; i < ARRAY_SIZE(sms->flash); i++) { 360 pflash_cfi01_legacy_drive(sms->flash[i], 361 drive_get(IF_PFLASH, 0, i)); 362 } 363 364 sbsa_flash_map(sms, sysmem, secure_sysmem); 365 366 pflash_blk0 = pflash_cfi01_get_blk(sms->flash[0]); 367 368 bios_name = MACHINE(sms)->firmware; 369 if (bios_name) { 370 char *fname; 371 MemoryRegion *mr; 372 int image_size; 373 374 if (pflash_blk0) { 375 error_report("The contents of the first flash device may be " 376 "specified with -bios or with -drive if=pflash... " 377 "but you cannot use both options at once"); 378 exit(1); 379 } 380 381 /* Fall back to -bios */ 382 383 fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 384 if (!fname) { 385 error_report("Could not find ROM image '%s'", bios_name); 386 exit(1); 387 } 388 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(sms->flash[0]), 0); 389 image_size = load_image_mr(fname, mr); 390 g_free(fname); 391 if (image_size < 0) { 392 error_report("Could not load ROM image '%s'", bios_name); 393 exit(1); 394 } 395 } 396 397 return pflash_blk0 || bios_name; 398 } 399 400 static void create_secure_ram(SBSAMachineState *sms, 401 MemoryRegion *secure_sysmem) 402 { 403 MemoryRegion *secram = g_new(MemoryRegion, 1); 404 hwaddr base = sbsa_ref_memmap[SBSA_SECURE_MEM].base; 405 hwaddr size = sbsa_ref_memmap[SBSA_SECURE_MEM].size; 406 407 memory_region_init_ram(secram, NULL, "sbsa-ref.secure-ram", size, 408 &error_fatal); 409 memory_region_add_subregion(secure_sysmem, base, secram); 410 } 411 412 static void create_its(SBSAMachineState *sms) 413 { 414 const char *itsclass = its_class_name(); 415 DeviceState *dev; 416 417 dev = qdev_new(itsclass); 418 419 object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(sms->gic), 420 &error_abort); 421 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 422 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, sbsa_ref_memmap[SBSA_GIC_ITS].base); 423 } 424 425 static void create_gic(SBSAMachineState *sms, MemoryRegion *mem) 426 { 427 unsigned int smp_cpus = MACHINE(sms)->smp.cpus; 428 SysBusDevice *gicbusdev; 429 const char *gictype; 430 uint32_t redist0_capacity, redist0_count; 431 QList *redist_region_count; 432 int i; 433 434 gictype = gicv3_class_name(); 435 436 sms->gic = qdev_new(gictype); 437 qdev_prop_set_uint32(sms->gic, "revision", 3); 438 qdev_prop_set_uint32(sms->gic, "num-cpu", smp_cpus); 439 /* 440 * Note that the num-irq property counts both internal and external 441 * interrupts; there are always 32 of the former (mandated by GIC spec). 442 */ 443 qdev_prop_set_uint32(sms->gic, "num-irq", NUM_IRQS + 32); 444 qdev_prop_set_bit(sms->gic, "has-security-extensions", true); 445 446 redist0_capacity = 447 sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE; 448 redist0_count = MIN(smp_cpus, redist0_capacity); 449 450 redist_region_count = qlist_new(); 451 qlist_append_int(redist_region_count, redist0_count); 452 qdev_prop_set_array(sms->gic, "redist-region-count", redist_region_count); 453 454 object_property_set_link(OBJECT(sms->gic), "sysmem", 455 OBJECT(mem), &error_fatal); 456 qdev_prop_set_bit(sms->gic, "has-lpi", true); 457 458 gicbusdev = SYS_BUS_DEVICE(sms->gic); 459 sysbus_realize_and_unref(gicbusdev, &error_fatal); 460 sysbus_mmio_map(gicbusdev, 0, sbsa_ref_memmap[SBSA_GIC_DIST].base); 461 sysbus_mmio_map(gicbusdev, 1, sbsa_ref_memmap[SBSA_GIC_REDIST].base); 462 463 /* 464 * Wire the outputs from each CPU's generic timer and the GICv3 465 * maintenance interrupt signal to the appropriate GIC PPI inputs, 466 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. 467 */ 468 for (i = 0; i < smp_cpus; i++) { 469 DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); 470 int intidbase = NUM_IRQS + i * GIC_INTERNAL; 471 int irq; 472 /* 473 * Mapping from the output timer irq lines from the CPU to the 474 * GIC PPI inputs used for this board. 475 */ 476 const int timer_irq[] = { 477 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 478 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 479 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 480 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 481 [GTIMER_HYPVIRT] = ARCH_TIMER_NS_EL2_VIRT_IRQ, 482 }; 483 484 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 485 qdev_connect_gpio_out(cpudev, irq, 486 qdev_get_gpio_in(sms->gic, 487 intidbase + timer_irq[irq])); 488 } 489 490 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0, 491 qdev_get_gpio_in(sms->gic, 492 intidbase 493 + ARCH_GIC_MAINT_IRQ)); 494 495 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 496 qdev_get_gpio_in(sms->gic, 497 intidbase 498 + VIRTUAL_PMU_IRQ)); 499 500 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 501 sysbus_connect_irq(gicbusdev, i + smp_cpus, 502 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 503 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, 504 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 505 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, 506 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 507 } 508 create_its(sms); 509 } 510 511 static void create_uart(const SBSAMachineState *sms, int uart, 512 MemoryRegion *mem, Chardev *chr) 513 { 514 hwaddr base = sbsa_ref_memmap[uart].base; 515 int irq = sbsa_ref_irqmap[uart]; 516 DeviceState *dev = qdev_new(TYPE_PL011); 517 SysBusDevice *s = SYS_BUS_DEVICE(dev); 518 519 qdev_prop_set_chr(dev, "chardev", chr); 520 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 521 memory_region_add_subregion(mem, base, 522 sysbus_mmio_get_region(s, 0)); 523 sysbus_connect_irq(s, 0, qdev_get_gpio_in(sms->gic, irq)); 524 } 525 526 static void create_rtc(const SBSAMachineState *sms) 527 { 528 hwaddr base = sbsa_ref_memmap[SBSA_RTC].base; 529 int irq = sbsa_ref_irqmap[SBSA_RTC]; 530 531 sysbus_create_simple("pl031", base, qdev_get_gpio_in(sms->gic, irq)); 532 } 533 534 static void create_wdt(const SBSAMachineState *sms) 535 { 536 hwaddr rbase = sbsa_ref_memmap[SBSA_GWDT_REFRESH].base; 537 hwaddr cbase = sbsa_ref_memmap[SBSA_GWDT_CONTROL].base; 538 DeviceState *dev = qdev_new(TYPE_WDT_SBSA); 539 SysBusDevice *s = SYS_BUS_DEVICE(dev); 540 int irq = sbsa_ref_irqmap[SBSA_GWDT_WS0]; 541 542 qdev_prop_set_uint64(dev, "clock-frequency", SBSA_GTIMER_HZ); 543 sysbus_realize_and_unref(s, &error_fatal); 544 sysbus_mmio_map(s, 0, rbase); 545 sysbus_mmio_map(s, 1, cbase); 546 sysbus_connect_irq(s, 0, qdev_get_gpio_in(sms->gic, irq)); 547 } 548 549 static DeviceState *gpio_key_dev; 550 static void sbsa_ref_powerdown_req(Notifier *n, void *opaque) 551 { 552 /* use gpio Pin 3 for power button event */ 553 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); 554 } 555 556 static Notifier sbsa_ref_powerdown_notifier = { 557 .notify = sbsa_ref_powerdown_req 558 }; 559 560 static void create_gpio(const SBSAMachineState *sms) 561 { 562 DeviceState *pl061_dev; 563 hwaddr base = sbsa_ref_memmap[SBSA_GPIO].base; 564 int irq = sbsa_ref_irqmap[SBSA_GPIO]; 565 566 pl061_dev = sysbus_create_simple("pl061", base, 567 qdev_get_gpio_in(sms->gic, irq)); 568 569 gpio_key_dev = sysbus_create_simple("gpio-key", -1, 570 qdev_get_gpio_in(pl061_dev, 3)); 571 572 /* connect powerdown request */ 573 qemu_register_powerdown_notifier(&sbsa_ref_powerdown_notifier); 574 } 575 576 static void create_ahci(const SBSAMachineState *sms) 577 { 578 hwaddr base = sbsa_ref_memmap[SBSA_AHCI].base; 579 int irq = sbsa_ref_irqmap[SBSA_AHCI]; 580 DeviceState *dev; 581 DriveInfo *hd[NUM_SATA_PORTS]; 582 SysbusAHCIState *sysahci; 583 584 dev = qdev_new("sysbus-ahci"); 585 qdev_prop_set_uint32(dev, "num-ports", NUM_SATA_PORTS); 586 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 587 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 588 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(sms->gic, irq)); 589 590 sysahci = SYSBUS_AHCI(dev); 591 ide_drive_get(hd, ARRAY_SIZE(hd)); 592 ahci_ide_create_devs(&sysahci->ahci, hd); 593 } 594 595 static void create_xhci(const SBSAMachineState *sms) 596 { 597 hwaddr base = sbsa_ref_memmap[SBSA_XHCI].base; 598 int irq = sbsa_ref_irqmap[SBSA_XHCI]; 599 DeviceState *dev = qdev_new(TYPE_XHCI_SYSBUS); 600 qdev_prop_set_uint32(dev, "slots", XHCI_MAXSLOTS); 601 602 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 603 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 604 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(sms->gic, irq)); 605 } 606 607 static void create_smmu(const SBSAMachineState *sms, PCIBus *bus) 608 { 609 hwaddr base = sbsa_ref_memmap[SBSA_SMMU].base; 610 int irq = sbsa_ref_irqmap[SBSA_SMMU]; 611 DeviceState *dev; 612 int i; 613 614 dev = qdev_new(TYPE_ARM_SMMUV3); 615 616 object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus), 617 &error_abort); 618 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 619 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 620 for (i = 0; i < NUM_SMMU_IRQS; i++) { 621 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 622 qdev_get_gpio_in(sms->gic, irq + i)); 623 } 624 } 625 626 static void create_pcie(SBSAMachineState *sms) 627 { 628 hwaddr base_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].base; 629 hwaddr size_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].size; 630 hwaddr base_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].base; 631 hwaddr size_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].size; 632 hwaddr base_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].base; 633 hwaddr size_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].size; 634 hwaddr base_pio = sbsa_ref_memmap[SBSA_PCIE_PIO].base; 635 int irq = sbsa_ref_irqmap[SBSA_PCIE]; 636 MachineClass *mc = MACHINE_GET_CLASS(sms); 637 MemoryRegion *mmio_alias, *mmio_alias_high, *mmio_reg; 638 MemoryRegion *ecam_alias, *ecam_reg; 639 DeviceState *dev; 640 PCIHostState *pci; 641 int i; 642 643 dev = qdev_new(TYPE_GPEX_HOST); 644 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 645 646 /* Map ECAM space */ 647 ecam_alias = g_new0(MemoryRegion, 1); 648 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 649 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 650 ecam_reg, 0, size_ecam); 651 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); 652 653 /* Map the MMIO space */ 654 mmio_alias = g_new0(MemoryRegion, 1); 655 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 656 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 657 mmio_reg, base_mmio, size_mmio); 658 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); 659 660 /* Map the MMIO_HIGH space */ 661 mmio_alias_high = g_new0(MemoryRegion, 1); 662 memory_region_init_alias(mmio_alias_high, OBJECT(dev), "pcie-mmio-high", 663 mmio_reg, base_mmio_high, size_mmio_high); 664 memory_region_add_subregion(get_system_memory(), base_mmio_high, 665 mmio_alias_high); 666 667 /* Map IO port space */ 668 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); 669 670 for (i = 0; i < GPEX_NUM_IRQS; i++) { 671 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 672 qdev_get_gpio_in(sms->gic, irq + i)); 673 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); 674 } 675 676 pci = PCI_HOST_BRIDGE(dev); 677 678 pci_init_nic_devices(pci->bus, mc->default_nic); 679 680 pci_create_simple(pci->bus, -1, "bochs-display"); 681 682 create_smmu(sms, pci->bus); 683 } 684 685 static void *sbsa_ref_dtb(const struct arm_boot_info *binfo, int *fdt_size) 686 { 687 const SBSAMachineState *board = container_of(binfo, SBSAMachineState, 688 bootinfo); 689 690 *fdt_size = board->fdt_size; 691 return board->fdt; 692 } 693 694 static void create_secure_ec(MemoryRegion *mem) 695 { 696 hwaddr base = sbsa_ref_memmap[SBSA_SECURE_EC].base; 697 DeviceState *dev = qdev_new("sbsa-ec"); 698 SysBusDevice *s = SYS_BUS_DEVICE(dev); 699 700 memory_region_add_subregion(mem, base, 701 sysbus_mmio_get_region(s, 0)); 702 } 703 704 static void sbsa_ref_init(MachineState *machine) 705 { 706 unsigned int smp_cpus = machine->smp.cpus; 707 unsigned int max_cpus = machine->smp.max_cpus; 708 SBSAMachineState *sms = SBSA_MACHINE(machine); 709 MachineClass *mc = MACHINE_GET_CLASS(machine); 710 MemoryRegion *sysmem = get_system_memory(); 711 MemoryRegion *secure_sysmem = g_new(MemoryRegion, 1); 712 bool firmware_loaded; 713 const CPUArchIdList *possible_cpus; 714 int n, sbsa_max_cpus; 715 716 if (kvm_enabled()) { 717 error_report("sbsa-ref: KVM is not supported for this machine"); 718 exit(1); 719 } 720 721 /* 722 * The Secure view of the world is the same as the NonSecure, 723 * but with a few extra devices. Create it as a container region 724 * containing the system memory at low priority; any secure-only 725 * devices go in at higher priority and take precedence. 726 */ 727 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", 728 UINT64_MAX); 729 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); 730 731 firmware_loaded = sbsa_firmware_init(sms, sysmem, secure_sysmem); 732 733 /* 734 * This machine has EL3 enabled, external firmware should supply PSCI 735 * implementation, so the QEMU's internal PSCI is disabled. 736 */ 737 sms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; 738 739 sbsa_max_cpus = sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE; 740 741 if (max_cpus > sbsa_max_cpus) { 742 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " 743 "supported by machine 'sbsa-ref' (%d)", 744 max_cpus, sbsa_max_cpus); 745 exit(1); 746 } 747 748 sms->smp_cpus = smp_cpus; 749 750 if (machine->ram_size > sbsa_ref_memmap[SBSA_MEM].size) { 751 error_report("sbsa-ref: cannot model more than %dGB RAM", RAMLIMIT_GB); 752 exit(1); 753 } 754 755 possible_cpus = mc->possible_cpu_arch_ids(machine); 756 for (n = 0; n < possible_cpus->len; n++) { 757 Object *cpuobj; 758 CPUState *cs; 759 760 if (n >= smp_cpus) { 761 break; 762 } 763 764 cpuobj = object_new(possible_cpus->cpus[n].type); 765 object_property_set_int(cpuobj, "mp-affinity", 766 possible_cpus->cpus[n].arch_id, NULL); 767 768 cs = CPU(cpuobj); 769 cs->cpu_index = n; 770 771 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj), 772 &error_fatal); 773 774 if (object_property_find(cpuobj, "reset-cbar")) { 775 object_property_set_int(cpuobj, "reset-cbar", 776 sbsa_ref_memmap[SBSA_CPUPERIPHS].base, 777 &error_abort); 778 } 779 780 object_property_set_int(cpuobj, "cntfrq", SBSA_GTIMER_HZ, &error_abort); 781 782 object_property_set_link(cpuobj, "memory", OBJECT(sysmem), 783 &error_abort); 784 785 object_property_set_link(cpuobj, "secure-memory", 786 OBJECT(secure_sysmem), &error_abort); 787 788 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); 789 object_unref(cpuobj); 790 } 791 792 memory_region_add_subregion(sysmem, sbsa_ref_memmap[SBSA_MEM].base, 793 machine->ram); 794 795 create_fdt(sms); 796 797 create_secure_ram(sms, secure_sysmem); 798 799 create_gic(sms, sysmem); 800 801 create_uart(sms, SBSA_UART, sysmem, serial_hd(0)); 802 create_uart(sms, SBSA_SECURE_UART, secure_sysmem, serial_hd(1)); 803 /* Second secure UART for RAS and MM from EL0 */ 804 create_uart(sms, SBSA_SECURE_UART_MM, secure_sysmem, serial_hd(2)); 805 806 create_rtc(sms); 807 808 create_wdt(sms); 809 810 create_gpio(sms); 811 812 create_ahci(sms); 813 814 create_xhci(sms); 815 816 create_pcie(sms); 817 818 create_secure_ec(secure_sysmem); 819 820 sms->bootinfo.ram_size = machine->ram_size; 821 sms->bootinfo.board_id = -1; 822 sms->bootinfo.loader_start = sbsa_ref_memmap[SBSA_MEM].base; 823 sms->bootinfo.get_dtb = sbsa_ref_dtb; 824 sms->bootinfo.firmware_loaded = firmware_loaded; 825 arm_load_kernel(ARM_CPU(first_cpu), machine, &sms->bootinfo); 826 } 827 828 static const CPUArchIdList *sbsa_ref_possible_cpu_arch_ids(MachineState *ms) 829 { 830 unsigned int max_cpus = ms->smp.max_cpus; 831 SBSAMachineState *sms = SBSA_MACHINE(ms); 832 int n; 833 834 if (ms->possible_cpus) { 835 assert(ms->possible_cpus->len == max_cpus); 836 return ms->possible_cpus; 837 } 838 839 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 840 sizeof(CPUArchId) * max_cpus); 841 ms->possible_cpus->len = max_cpus; 842 for (n = 0; n < ms->possible_cpus->len; n++) { 843 ms->possible_cpus->cpus[n].type = ms->cpu_type; 844 ms->possible_cpus->cpus[n].arch_id = 845 sbsa_ref_cpu_mp_affinity(sms, n); 846 ms->possible_cpus->cpus[n].props.has_thread_id = true; 847 ms->possible_cpus->cpus[n].props.thread_id = n; 848 } 849 return ms->possible_cpus; 850 } 851 852 static CpuInstanceProperties 853 sbsa_ref_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 854 { 855 MachineClass *mc = MACHINE_GET_CLASS(ms); 856 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 857 858 assert(cpu_index < possible_cpus->len); 859 return possible_cpus->cpus[cpu_index].props; 860 } 861 862 static int64_t 863 sbsa_ref_get_default_cpu_node_id(const MachineState *ms, int idx) 864 { 865 return idx % ms->numa_state->num_nodes; 866 } 867 868 static void sbsa_ref_instance_init(Object *obj) 869 { 870 SBSAMachineState *sms = SBSA_MACHINE(obj); 871 872 sbsa_flash_create(sms); 873 } 874 875 static void sbsa_ref_class_init(ObjectClass *oc, void *data) 876 { 877 MachineClass *mc = MACHINE_CLASS(oc); 878 static const char * const valid_cpu_types[] = { 879 ARM_CPU_TYPE_NAME("cortex-a57"), 880 ARM_CPU_TYPE_NAME("cortex-a72"), 881 ARM_CPU_TYPE_NAME("neoverse-n1"), 882 ARM_CPU_TYPE_NAME("neoverse-v1"), 883 ARM_CPU_TYPE_NAME("neoverse-n2"), 884 ARM_CPU_TYPE_NAME("max"), 885 NULL, 886 }; 887 888 mc->init = sbsa_ref_init; 889 mc->desc = "QEMU 'SBSA Reference' ARM Virtual Machine"; 890 mc->default_cpu_type = ARM_CPU_TYPE_NAME("neoverse-n2"); 891 mc->valid_cpu_types = valid_cpu_types; 892 mc->max_cpus = 512; 893 mc->pci_allow_0_address = true; 894 mc->minimum_page_bits = 12; 895 mc->block_default_type = IF_IDE; 896 mc->no_cdrom = 1; 897 mc->default_nic = "e1000e"; 898 mc->default_ram_size = 1 * GiB; 899 mc->default_ram_id = "sbsa-ref.ram"; 900 mc->default_cpus = 4; 901 mc->possible_cpu_arch_ids = sbsa_ref_possible_cpu_arch_ids; 902 mc->cpu_index_to_instance_props = sbsa_ref_cpu_index_to_props; 903 mc->get_default_cpu_node_id = sbsa_ref_get_default_cpu_node_id; 904 /* platform instead of architectural choice */ 905 mc->cpu_cluster_has_numa_boundary = true; 906 } 907 908 static const TypeInfo sbsa_ref_info = { 909 .name = TYPE_SBSA_MACHINE, 910 .parent = TYPE_MACHINE, 911 .instance_init = sbsa_ref_instance_init, 912 .class_init = sbsa_ref_class_init, 913 .instance_size = sizeof(SBSAMachineState), 914 }; 915 916 static void sbsa_ref_machine_init(void) 917 { 918 type_register_static(&sbsa_ref_info); 919 } 920 921 type_init(sbsa_ref_machine_init); 922