164580903SHongbo Zhang /* 264580903SHongbo Zhang * ARM SBSA Reference Platform emulation 364580903SHongbo Zhang * 464580903SHongbo Zhang * Copyright (c) 2018 Linaro Limited 5d40ab068SLeif Lindholm * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 664580903SHongbo Zhang * Written by Hongbo Zhang <hongbo.zhang@linaro.org> 764580903SHongbo Zhang * 864580903SHongbo Zhang * This program is free software; you can redistribute it and/or modify it 964580903SHongbo Zhang * under the terms and conditions of the GNU General Public License, 1064580903SHongbo Zhang * version 2 or later, as published by the Free Software Foundation. 1164580903SHongbo Zhang * 1264580903SHongbo Zhang * This program is distributed in the hope it will be useful, but WITHOUT 1364580903SHongbo Zhang * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 1464580903SHongbo Zhang * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 1564580903SHongbo Zhang * more details. 1664580903SHongbo Zhang * 1764580903SHongbo Zhang * You should have received a copy of the GNU General Public License along with 1864580903SHongbo Zhang * this program. If not, see <http://www.gnu.org/licenses/>. 1964580903SHongbo Zhang */ 2064580903SHongbo Zhang 2164580903SHongbo Zhang #include "qemu/osdep.h" 222c65db5eSPaolo Bonzini #include "qemu/datadir.h" 2364580903SHongbo Zhang #include "qapi/error.h" 2464580903SHongbo Zhang #include "qemu/error-report.h" 2564580903SHongbo Zhang #include "qemu/units.h" 26e9fdf453SHongbo Zhang #include "sysemu/device_tree.h" 2794522562SPhilippe Mathieu-Daudé #include "sysemu/kvm.h" 2864580903SHongbo Zhang #include "sysemu/numa.h" 2954d31236SMarkus Armbruster #include "sysemu/runstate.h" 3064580903SHongbo Zhang #include "sysemu/sysemu.h" 3164580903SHongbo Zhang #include "exec/hwaddr.h" 3264580903SHongbo Zhang #include "kvm_arm.h" 3364580903SHongbo Zhang #include "hw/arm/boot.h" 34d40ab068SLeif Lindholm #include "hw/arm/bsa.h" 350c08d4f3SMarcin Juszkiewicz #include "hw/arm/fdt.h" 36a431ab0eSRichard Henderson #include "hw/arm/smmuv3.h" 37e9fdf453SHongbo Zhang #include "hw/block/flash.h" 3864580903SHongbo Zhang #include "hw/boards.h" 39e9fdf453SHongbo Zhang #include "hw/ide/internal.h" 40e9fdf453SHongbo Zhang #include "hw/ide/ahci_internal.h" 41*fbb5945eSPhilippe Mathieu-Daudé #include "hw/ide/ahci-sysbus.h" 4264580903SHongbo Zhang #include "hw/intc/arm_gicv3_common.h" 430c40daf0SPhilippe Mathieu-Daudé #include "hw/intc/arm_gicv3_its_common.h" 44e9fdf453SHongbo Zhang #include "hw/loader.h" 45e9fdf453SHongbo Zhang #include "hw/pci-host/gpex.h" 46a27bd6c7SMarkus Armbruster #include "hw/qdev-properties.h" 47e9fdf453SHongbo Zhang #include "hw/usb.h" 4862c2b876SYuquan Wang #include "hw/usb/xhci.h" 49d8f6d15fSGavin Shan #include "hw/char/pl011.h" 50baabe7d0SShashi Mallela #include "hw/watchdog/sbsa_gwdt.h" 51e9fdf453SHongbo Zhang #include "net/net.h" 52d210fa2fSKevin Wolf #include "qapi/qmp/qlist.h" 53db1015e9SEduardo Habkost #include "qom/object.h" 54d780d056SPhilippe Mathieu-Daudé #include "target/arm/cpu-qom.h" 55f4f318b4SPhilippe Mathieu-Daudé #include "target/arm/gtimer.h" 5664580903SHongbo Zhang 5764580903SHongbo Zhang #define RAMLIMIT_GB 8192 5864580903SHongbo Zhang #define RAMLIMIT_BYTES (RAMLIMIT_GB * GiB) 5964580903SHongbo Zhang 60e9fdf453SHongbo Zhang #define NUM_IRQS 256 61e9fdf453SHongbo Zhang #define NUM_SMMU_IRQS 4 62e9fdf453SHongbo Zhang #define NUM_SATA_PORTS 6 63e9fdf453SHongbo Zhang 6464580903SHongbo Zhang enum { 6564580903SHongbo Zhang SBSA_FLASH, 6664580903SHongbo Zhang SBSA_MEM, 6764580903SHongbo Zhang SBSA_CPUPERIPHS, 6864580903SHongbo Zhang SBSA_GIC_DIST, 6964580903SHongbo Zhang SBSA_GIC_REDIST, 709fe2b4a2SShashi Mallela SBSA_GIC_ITS, 713f462bf0SGraeme Gregory SBSA_SECURE_EC, 7280d60a6dSEduardo Habkost SBSA_GWDT_WS0, 73baabe7d0SShashi Mallela SBSA_GWDT_REFRESH, 74baabe7d0SShashi Mallela SBSA_GWDT_CONTROL, 7564580903SHongbo Zhang SBSA_SMMU, 7664580903SHongbo Zhang SBSA_UART, 7764580903SHongbo Zhang SBSA_RTC, 7864580903SHongbo Zhang SBSA_PCIE, 7964580903SHongbo Zhang SBSA_PCIE_MMIO, 8064580903SHongbo Zhang SBSA_PCIE_MMIO_HIGH, 8164580903SHongbo Zhang SBSA_PCIE_PIO, 8264580903SHongbo Zhang SBSA_PCIE_ECAM, 8364580903SHongbo Zhang SBSA_GPIO, 8464580903SHongbo Zhang SBSA_SECURE_UART, 8564580903SHongbo Zhang SBSA_SECURE_UART_MM, 8664580903SHongbo Zhang SBSA_SECURE_MEM, 8764580903SHongbo Zhang SBSA_AHCI, 8862c2b876SYuquan Wang SBSA_XHCI, 8964580903SHongbo Zhang }; 9064580903SHongbo Zhang 91db1015e9SEduardo Habkost struct SBSAMachineState { 9264580903SHongbo Zhang MachineState parent; 9364580903SHongbo Zhang struct arm_boot_info bootinfo; 9464580903SHongbo Zhang int smp_cpus; 9564580903SHongbo Zhang void *fdt; 9664580903SHongbo Zhang int fdt_size; 9764580903SHongbo Zhang int psci_conduit; 9848ba18e6SPhilippe Mathieu-Daudé DeviceState *gic; 99e9fdf453SHongbo Zhang PFlashCFI01 *flash[2]; 100db1015e9SEduardo Habkost }; 10164580903SHongbo Zhang 10264580903SHongbo Zhang #define TYPE_SBSA_MACHINE MACHINE_TYPE_NAME("sbsa-ref") 1038063396bSEduardo Habkost OBJECT_DECLARE_SIMPLE_TYPE(SBSAMachineState, SBSA_MACHINE) 10464580903SHongbo Zhang 10564580903SHongbo Zhang static const MemMapEntry sbsa_ref_memmap[] = { 10664580903SHongbo Zhang /* 512M boot ROM */ 10764580903SHongbo Zhang [SBSA_FLASH] = { 0, 0x20000000 }, 10864580903SHongbo Zhang /* 512M secure memory */ 10964580903SHongbo Zhang [SBSA_SECURE_MEM] = { 0x20000000, 0x20000000 }, 11064580903SHongbo Zhang /* Space reserved for CPU peripheral devices */ 11164580903SHongbo Zhang [SBSA_CPUPERIPHS] = { 0x40000000, 0x00040000 }, 11264580903SHongbo Zhang [SBSA_GIC_DIST] = { 0x40060000, 0x00010000 }, 11364580903SHongbo Zhang [SBSA_GIC_REDIST] = { 0x40080000, 0x04000000 }, 1149fe2b4a2SShashi Mallela [SBSA_GIC_ITS] = { 0x44081000, 0x00020000 }, 1153f462bf0SGraeme Gregory [SBSA_SECURE_EC] = { 0x50000000, 0x00001000 }, 116baabe7d0SShashi Mallela [SBSA_GWDT_REFRESH] = { 0x50010000, 0x00001000 }, 117baabe7d0SShashi Mallela [SBSA_GWDT_CONTROL] = { 0x50011000, 0x00001000 }, 11864580903SHongbo Zhang [SBSA_UART] = { 0x60000000, 0x00001000 }, 11964580903SHongbo Zhang [SBSA_RTC] = { 0x60010000, 0x00001000 }, 12064580903SHongbo Zhang [SBSA_GPIO] = { 0x60020000, 0x00001000 }, 12164580903SHongbo Zhang [SBSA_SECURE_UART] = { 0x60030000, 0x00001000 }, 12264580903SHongbo Zhang [SBSA_SECURE_UART_MM] = { 0x60040000, 0x00001000 }, 12364580903SHongbo Zhang [SBSA_SMMU] = { 0x60050000, 0x00020000 }, 12464580903SHongbo Zhang /* Space here reserved for more SMMUs */ 12564580903SHongbo Zhang [SBSA_AHCI] = { 0x60100000, 0x00010000 }, 12662c2b876SYuquan Wang [SBSA_XHCI] = { 0x60110000, 0x00010000 }, 12764580903SHongbo Zhang /* Space here reserved for other devices */ 12864580903SHongbo Zhang [SBSA_PCIE_PIO] = { 0x7fff0000, 0x00010000 }, 12964580903SHongbo Zhang /* 32-bit address PCIE MMIO space */ 13064580903SHongbo Zhang [SBSA_PCIE_MMIO] = { 0x80000000, 0x70000000 }, 13164580903SHongbo Zhang /* 256M PCIE ECAM space */ 13264580903SHongbo Zhang [SBSA_PCIE_ECAM] = { 0xf0000000, 0x10000000 }, 13364580903SHongbo Zhang /* ~1TB PCIE MMIO space (4GB to 1024GB boundary) */ 13464580903SHongbo Zhang [SBSA_PCIE_MMIO_HIGH] = { 0x100000000ULL, 0xFF00000000ULL }, 13564580903SHongbo Zhang [SBSA_MEM] = { 0x10000000000ULL, RAMLIMIT_BYTES }, 13664580903SHongbo Zhang }; 13764580903SHongbo Zhang 138e9fdf453SHongbo Zhang static const int sbsa_ref_irqmap[] = { 139e9fdf453SHongbo Zhang [SBSA_UART] = 1, 140e9fdf453SHongbo Zhang [SBSA_RTC] = 2, 141e9fdf453SHongbo Zhang [SBSA_PCIE] = 3, /* ... to 6 */ 142e9fdf453SHongbo Zhang [SBSA_GPIO] = 7, 143e9fdf453SHongbo Zhang [SBSA_SECURE_UART] = 8, 144e9fdf453SHongbo Zhang [SBSA_SECURE_UART_MM] = 9, 145e9fdf453SHongbo Zhang [SBSA_AHCI] = 10, 14662c2b876SYuquan Wang [SBSA_XHCI] = 11, 14704788fd5SGraeme Gregory [SBSA_SMMU] = 12, /* ... to 15 */ 14880d60a6dSEduardo Habkost [SBSA_GWDT_WS0] = 16, 149e9fdf453SHongbo Zhang }; 150e9fdf453SHongbo Zhang 151999f6ebdSLeif Lindholm static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx) 152999f6ebdSLeif Lindholm { 153999f6ebdSLeif Lindholm uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER; 154750245edSRichard Henderson return arm_build_mp_affinity(idx, clustersz); 155999f6ebdSLeif Lindholm } 156999f6ebdSLeif Lindholm 1570c08d4f3SMarcin Juszkiewicz static void sbsa_fdt_add_gic_node(SBSAMachineState *sms) 1580c08d4f3SMarcin Juszkiewicz { 1590c08d4f3SMarcin Juszkiewicz char *nodename; 1600c08d4f3SMarcin Juszkiewicz 1610c08d4f3SMarcin Juszkiewicz nodename = g_strdup_printf("/intc"); 1620c08d4f3SMarcin Juszkiewicz qemu_fdt_add_subnode(sms->fdt, nodename); 1630c08d4f3SMarcin Juszkiewicz qemu_fdt_setprop_sized_cells(sms->fdt, nodename, "reg", 1640c08d4f3SMarcin Juszkiewicz 2, sbsa_ref_memmap[SBSA_GIC_DIST].base, 1650c08d4f3SMarcin Juszkiewicz 2, sbsa_ref_memmap[SBSA_GIC_DIST].size, 1660c08d4f3SMarcin Juszkiewicz 2, sbsa_ref_memmap[SBSA_GIC_REDIST].base, 1670c08d4f3SMarcin Juszkiewicz 2, sbsa_ref_memmap[SBSA_GIC_REDIST].size); 1680c08d4f3SMarcin Juszkiewicz 1699fe2b4a2SShashi Mallela nodename = g_strdup_printf("/intc/its"); 1709fe2b4a2SShashi Mallela qemu_fdt_add_subnode(sms->fdt, nodename); 1719fe2b4a2SShashi Mallela qemu_fdt_setprop_sized_cells(sms->fdt, nodename, "reg", 1729fe2b4a2SShashi Mallela 2, sbsa_ref_memmap[SBSA_GIC_ITS].base, 1739fe2b4a2SShashi Mallela 2, sbsa_ref_memmap[SBSA_GIC_ITS].size); 1749fe2b4a2SShashi Mallela 1750c08d4f3SMarcin Juszkiewicz g_free(nodename); 1760c08d4f3SMarcin Juszkiewicz } 1779fe2b4a2SShashi Mallela 178e9fdf453SHongbo Zhang /* 179e9fdf453SHongbo Zhang * Firmware on this machine only uses ACPI table to load OS, these limited 180e9fdf453SHongbo Zhang * device tree nodes are just to let firmware know the info which varies from 181e9fdf453SHongbo Zhang * command line parameters, so it is not necessary to be fully compatible 182e9fdf453SHongbo Zhang * with the kernel CPU and NUMA binding rules. 183e9fdf453SHongbo Zhang */ 184e9fdf453SHongbo Zhang static void create_fdt(SBSAMachineState *sms) 185e9fdf453SHongbo Zhang { 186e9fdf453SHongbo Zhang void *fdt = create_device_tree(&sms->fdt_size); 187e9fdf453SHongbo Zhang const MachineState *ms = MACHINE(sms); 188aa570207STao Xu int nb_numa_nodes = ms->numa_state->num_nodes; 189e9fdf453SHongbo Zhang int cpu; 190e9fdf453SHongbo Zhang 191e9fdf453SHongbo Zhang if (!fdt) { 192e9fdf453SHongbo Zhang error_report("create_device_tree() failed"); 193e9fdf453SHongbo Zhang exit(1); 194e9fdf453SHongbo Zhang } 195e9fdf453SHongbo Zhang 196e9fdf453SHongbo Zhang sms->fdt = fdt; 197e9fdf453SHongbo Zhang 198e9fdf453SHongbo Zhang qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,sbsa-ref"); 199e9fdf453SHongbo Zhang qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 200e9fdf453SHongbo Zhang qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 201e9fdf453SHongbo Zhang 20290ea2cceSLeif Lindholm /* 20390ea2cceSLeif Lindholm * This versioning scheme is for informing platform fw only. It is neither: 20490ea2cceSLeif Lindholm * - A QEMU versioned machine type; a given version of QEMU will emulate 20590ea2cceSLeif Lindholm * a given version of the platform. 20690ea2cceSLeif Lindholm * - A reflection of level of SBSA (now SystemReady SR) support provided. 20790ea2cceSLeif Lindholm * 20890ea2cceSLeif Lindholm * machine-version-major: updated when changes breaking fw compatibility 20990ea2cceSLeif Lindholm * are introduced. 21090ea2cceSLeif Lindholm * machine-version-minor: updated when features are added that don't break 21190ea2cceSLeif Lindholm * fw compatibility. 21290ea2cceSLeif Lindholm */ 21390ea2cceSLeif Lindholm qemu_fdt_setprop_cell(fdt, "/", "machine-version-major", 0); 21462c2b876SYuquan Wang qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 3); 21590ea2cceSLeif Lindholm 216118154b7STao Xu if (ms->numa_state->have_numa_distance) { 217e9fdf453SHongbo Zhang int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); 218e9fdf453SHongbo Zhang uint32_t *matrix = g_malloc0(size); 219e9fdf453SHongbo Zhang int idx, i, j; 220e9fdf453SHongbo Zhang 221e9fdf453SHongbo Zhang for (i = 0; i < nb_numa_nodes; i++) { 222e9fdf453SHongbo Zhang for (j = 0; j < nb_numa_nodes; j++) { 223e9fdf453SHongbo Zhang idx = (i * nb_numa_nodes + j) * 3; 224e9fdf453SHongbo Zhang matrix[idx + 0] = cpu_to_be32(i); 225e9fdf453SHongbo Zhang matrix[idx + 1] = cpu_to_be32(j); 2267e721e7bSTao Xu matrix[idx + 2] = 2277e721e7bSTao Xu cpu_to_be32(ms->numa_state->nodes[i].distance[j]); 228e9fdf453SHongbo Zhang } 229e9fdf453SHongbo Zhang } 230e9fdf453SHongbo Zhang 231e9fdf453SHongbo Zhang qemu_fdt_add_subnode(fdt, "/distance-map"); 232e9fdf453SHongbo Zhang qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", 233e9fdf453SHongbo Zhang matrix, size); 234e9fdf453SHongbo Zhang g_free(matrix); 235e9fdf453SHongbo Zhang } 236e9fdf453SHongbo Zhang 237999f6ebdSLeif Lindholm /* 238999f6ebdSLeif Lindholm * From Documentation/devicetree/bindings/arm/cpus.yaml 239999f6ebdSLeif Lindholm * On ARM v8 64-bit systems this property is required 240999f6ebdSLeif Lindholm * and matches the MPIDR_EL1 register affinity bits. 241999f6ebdSLeif Lindholm * 242999f6ebdSLeif Lindholm * * If cpus node's #address-cells property is set to 2 243999f6ebdSLeif Lindholm * 244999f6ebdSLeif Lindholm * The first reg cell bits [7:0] must be set to 245999f6ebdSLeif Lindholm * bits [39:32] of MPIDR_EL1. 246999f6ebdSLeif Lindholm * 247999f6ebdSLeif Lindholm * The second reg cell bits [23:0] must be set to 248999f6ebdSLeif Lindholm * bits [23:0] of MPIDR_EL1. 249999f6ebdSLeif Lindholm */ 250e9fdf453SHongbo Zhang qemu_fdt_add_subnode(sms->fdt, "/cpus"); 251999f6ebdSLeif Lindholm qemu_fdt_setprop_cell(sms->fdt, "/cpus", "#address-cells", 2); 252999f6ebdSLeif Lindholm qemu_fdt_setprop_cell(sms->fdt, "/cpus", "#size-cells", 0x0); 253e9fdf453SHongbo Zhang 254e9fdf453SHongbo Zhang for (cpu = sms->smp_cpus - 1; cpu >= 0; cpu--) { 255e9fdf453SHongbo Zhang char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 256e9fdf453SHongbo Zhang ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 257e9fdf453SHongbo Zhang CPUState *cs = CPU(armcpu); 258999f6ebdSLeif Lindholm uint64_t mpidr = sbsa_ref_cpu_mp_affinity(sms, cpu); 259e9fdf453SHongbo Zhang 260e9fdf453SHongbo Zhang qemu_fdt_add_subnode(sms->fdt, nodename); 261999f6ebdSLeif Lindholm qemu_fdt_setprop_u64(sms->fdt, nodename, "reg", mpidr); 262e9fdf453SHongbo Zhang 263e9fdf453SHongbo Zhang if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 264e9fdf453SHongbo Zhang qemu_fdt_setprop_cell(sms->fdt, nodename, "numa-node-id", 265e9fdf453SHongbo Zhang ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 266e9fdf453SHongbo Zhang } 267e9fdf453SHongbo Zhang 268e9fdf453SHongbo Zhang g_free(nodename); 269e9fdf453SHongbo Zhang } 2700c08d4f3SMarcin Juszkiewicz 2710c08d4f3SMarcin Juszkiewicz sbsa_fdt_add_gic_node(sms); 272e9fdf453SHongbo Zhang } 273e9fdf453SHongbo Zhang 274e9fdf453SHongbo Zhang #define SBSA_FLASH_SECTOR_SIZE (256 * KiB) 275e9fdf453SHongbo Zhang 276e9fdf453SHongbo Zhang static PFlashCFI01 *sbsa_flash_create1(SBSAMachineState *sms, 277e9fdf453SHongbo Zhang const char *name, 278e9fdf453SHongbo Zhang const char *alias_prop_name) 279e9fdf453SHongbo Zhang { 280e9fdf453SHongbo Zhang /* 281e9fdf453SHongbo Zhang * Create a single flash device. We use the same parameters as 282e9fdf453SHongbo Zhang * the flash devices on the Versatile Express board. 283e9fdf453SHongbo Zhang */ 284df707969SMarkus Armbruster DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 285e9fdf453SHongbo Zhang 286e9fdf453SHongbo Zhang qdev_prop_set_uint64(dev, "sector-length", SBSA_FLASH_SECTOR_SIZE); 287e9fdf453SHongbo Zhang qdev_prop_set_uint8(dev, "width", 4); 288e9fdf453SHongbo Zhang qdev_prop_set_uint8(dev, "device-width", 2); 289e9fdf453SHongbo Zhang qdev_prop_set_bit(dev, "big-endian", false); 290e9fdf453SHongbo Zhang qdev_prop_set_uint16(dev, "id0", 0x89); 291e9fdf453SHongbo Zhang qdev_prop_set_uint16(dev, "id1", 0x18); 292e9fdf453SHongbo Zhang qdev_prop_set_uint16(dev, "id2", 0x00); 293e9fdf453SHongbo Zhang qdev_prop_set_uint16(dev, "id3", 0x00); 294e9fdf453SHongbo Zhang qdev_prop_set_string(dev, "name", name); 295d2623129SMarkus Armbruster object_property_add_child(OBJECT(sms), name, OBJECT(dev)); 296e9fdf453SHongbo Zhang object_property_add_alias(OBJECT(sms), alias_prop_name, 297d2623129SMarkus Armbruster OBJECT(dev), "drive"); 298e9fdf453SHongbo Zhang return PFLASH_CFI01(dev); 299e9fdf453SHongbo Zhang } 300e9fdf453SHongbo Zhang 301e9fdf453SHongbo Zhang static void sbsa_flash_create(SBSAMachineState *sms) 302e9fdf453SHongbo Zhang { 303e9fdf453SHongbo Zhang sms->flash[0] = sbsa_flash_create1(sms, "sbsa.flash0", "pflash0"); 304e9fdf453SHongbo Zhang sms->flash[1] = sbsa_flash_create1(sms, "sbsa.flash1", "pflash1"); 305e9fdf453SHongbo Zhang } 306e9fdf453SHongbo Zhang 307e9fdf453SHongbo Zhang static void sbsa_flash_map1(PFlashCFI01 *flash, 308e9fdf453SHongbo Zhang hwaddr base, hwaddr size, 309e9fdf453SHongbo Zhang MemoryRegion *sysmem) 310e9fdf453SHongbo Zhang { 311e9fdf453SHongbo Zhang DeviceState *dev = DEVICE(flash); 312e9fdf453SHongbo Zhang 3134cdd0a77SPhilippe Mathieu-Daudé assert(QEMU_IS_ALIGNED(size, SBSA_FLASH_SECTOR_SIZE)); 314e9fdf453SHongbo Zhang assert(size / SBSA_FLASH_SECTOR_SIZE <= UINT32_MAX); 315e9fdf453SHongbo Zhang qdev_prop_set_uint32(dev, "num-blocks", size / SBSA_FLASH_SECTOR_SIZE); 3163c6ef471SMarkus Armbruster sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 317e9fdf453SHongbo Zhang 318e9fdf453SHongbo Zhang memory_region_add_subregion(sysmem, base, 319e9fdf453SHongbo Zhang sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 320e9fdf453SHongbo Zhang 0)); 321e9fdf453SHongbo Zhang } 322e9fdf453SHongbo Zhang 323e9fdf453SHongbo Zhang static void sbsa_flash_map(SBSAMachineState *sms, 324e9fdf453SHongbo Zhang MemoryRegion *sysmem, 325e9fdf453SHongbo Zhang MemoryRegion *secure_sysmem) 326e9fdf453SHongbo Zhang { 327e9fdf453SHongbo Zhang /* 328e9fdf453SHongbo Zhang * Map two flash devices to fill the SBSA_FLASH space in the memmap. 329e9fdf453SHongbo Zhang * sysmem is the system memory space. secure_sysmem is the secure view 330e9fdf453SHongbo Zhang * of the system, and the first flash device should be made visible only 331e9fdf453SHongbo Zhang * there. The second flash device is visible to both secure and nonsecure. 332e9fdf453SHongbo Zhang */ 333e9fdf453SHongbo Zhang hwaddr flashsize = sbsa_ref_memmap[SBSA_FLASH].size / 2; 334e9fdf453SHongbo Zhang hwaddr flashbase = sbsa_ref_memmap[SBSA_FLASH].base; 335e9fdf453SHongbo Zhang 336e9fdf453SHongbo Zhang sbsa_flash_map1(sms->flash[0], flashbase, flashsize, 337e9fdf453SHongbo Zhang secure_sysmem); 338e9fdf453SHongbo Zhang sbsa_flash_map1(sms->flash[1], flashbase + flashsize, flashsize, 339e9fdf453SHongbo Zhang sysmem); 340e9fdf453SHongbo Zhang } 341e9fdf453SHongbo Zhang 342e9fdf453SHongbo Zhang static bool sbsa_firmware_init(SBSAMachineState *sms, 343e9fdf453SHongbo Zhang MemoryRegion *sysmem, 344e9fdf453SHongbo Zhang MemoryRegion *secure_sysmem) 345e9fdf453SHongbo Zhang { 3460ad3b5d3SPaolo Bonzini const char *bios_name; 347e9fdf453SHongbo Zhang int i; 348e9fdf453SHongbo Zhang BlockBackend *pflash_blk0; 349e9fdf453SHongbo Zhang 350e9fdf453SHongbo Zhang /* Map legacy -drive if=pflash to machine properties */ 351e9fdf453SHongbo Zhang for (i = 0; i < ARRAY_SIZE(sms->flash); i++) { 352e9fdf453SHongbo Zhang pflash_cfi01_legacy_drive(sms->flash[i], 353e9fdf453SHongbo Zhang drive_get(IF_PFLASH, 0, i)); 354e9fdf453SHongbo Zhang } 355e9fdf453SHongbo Zhang 356e9fdf453SHongbo Zhang sbsa_flash_map(sms, sysmem, secure_sysmem); 357e9fdf453SHongbo Zhang 358e9fdf453SHongbo Zhang pflash_blk0 = pflash_cfi01_get_blk(sms->flash[0]); 359e9fdf453SHongbo Zhang 3600ad3b5d3SPaolo Bonzini bios_name = MACHINE(sms)->firmware; 361e9fdf453SHongbo Zhang if (bios_name) { 362e9fdf453SHongbo Zhang char *fname; 363e9fdf453SHongbo Zhang MemoryRegion *mr; 364e9fdf453SHongbo Zhang int image_size; 365e9fdf453SHongbo Zhang 366e9fdf453SHongbo Zhang if (pflash_blk0) { 367e9fdf453SHongbo Zhang error_report("The contents of the first flash device may be " 368e9fdf453SHongbo Zhang "specified with -bios or with -drive if=pflash... " 369e9fdf453SHongbo Zhang "but you cannot use both options at once"); 370e9fdf453SHongbo Zhang exit(1); 371e9fdf453SHongbo Zhang } 372e9fdf453SHongbo Zhang 373e9fdf453SHongbo Zhang /* Fall back to -bios */ 374e9fdf453SHongbo Zhang 375e9fdf453SHongbo Zhang fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 376e9fdf453SHongbo Zhang if (!fname) { 377e9fdf453SHongbo Zhang error_report("Could not find ROM image '%s'", bios_name); 378e9fdf453SHongbo Zhang exit(1); 379e9fdf453SHongbo Zhang } 380e9fdf453SHongbo Zhang mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(sms->flash[0]), 0); 381e9fdf453SHongbo Zhang image_size = load_image_mr(fname, mr); 382e9fdf453SHongbo Zhang g_free(fname); 383e9fdf453SHongbo Zhang if (image_size < 0) { 384e9fdf453SHongbo Zhang error_report("Could not load ROM image '%s'", bios_name); 385e9fdf453SHongbo Zhang exit(1); 386e9fdf453SHongbo Zhang } 387e9fdf453SHongbo Zhang } 388e9fdf453SHongbo Zhang 389e9fdf453SHongbo Zhang return pflash_blk0 || bios_name; 390e9fdf453SHongbo Zhang } 391e9fdf453SHongbo Zhang 392e9fdf453SHongbo Zhang static void create_secure_ram(SBSAMachineState *sms, 393e9fdf453SHongbo Zhang MemoryRegion *secure_sysmem) 394e9fdf453SHongbo Zhang { 395e9fdf453SHongbo Zhang MemoryRegion *secram = g_new(MemoryRegion, 1); 396e9fdf453SHongbo Zhang hwaddr base = sbsa_ref_memmap[SBSA_SECURE_MEM].base; 397e9fdf453SHongbo Zhang hwaddr size = sbsa_ref_memmap[SBSA_SECURE_MEM].size; 398e9fdf453SHongbo Zhang 399e9fdf453SHongbo Zhang memory_region_init_ram(secram, NULL, "sbsa-ref.secure-ram", size, 400e9fdf453SHongbo Zhang &error_fatal); 401e9fdf453SHongbo Zhang memory_region_add_subregion(secure_sysmem, base, secram); 402e9fdf453SHongbo Zhang } 403e9fdf453SHongbo Zhang 4049fe2b4a2SShashi Mallela static void create_its(SBSAMachineState *sms) 4059fe2b4a2SShashi Mallela { 4069fe2b4a2SShashi Mallela const char *itsclass = its_class_name(); 4079fe2b4a2SShashi Mallela DeviceState *dev; 4089fe2b4a2SShashi Mallela 4099fe2b4a2SShashi Mallela dev = qdev_new(itsclass); 4109fe2b4a2SShashi Mallela 4119fe2b4a2SShashi Mallela object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(sms->gic), 4129fe2b4a2SShashi Mallela &error_abort); 4139fe2b4a2SShashi Mallela sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 4149fe2b4a2SShashi Mallela sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, sbsa_ref_memmap[SBSA_GIC_ITS].base); 4159fe2b4a2SShashi Mallela } 4169fe2b4a2SShashi Mallela 4179fe2b4a2SShashi Mallela static void create_gic(SBSAMachineState *sms, MemoryRegion *mem) 418e9fdf453SHongbo Zhang { 419cc7d44c2SLike Xu unsigned int smp_cpus = MACHINE(sms)->smp.cpus; 420e9fdf453SHongbo Zhang SysBusDevice *gicbusdev; 421e9fdf453SHongbo Zhang const char *gictype; 422e9fdf453SHongbo Zhang uint32_t redist0_capacity, redist0_count; 423d210fa2fSKevin Wolf QList *redist_region_count; 424e9fdf453SHongbo Zhang int i; 425e9fdf453SHongbo Zhang 426e9fdf453SHongbo Zhang gictype = gicv3_class_name(); 427e9fdf453SHongbo Zhang 4283e80f690SMarkus Armbruster sms->gic = qdev_new(gictype); 42948ba18e6SPhilippe Mathieu-Daudé qdev_prop_set_uint32(sms->gic, "revision", 3); 43048ba18e6SPhilippe Mathieu-Daudé qdev_prop_set_uint32(sms->gic, "num-cpu", smp_cpus); 431e9fdf453SHongbo Zhang /* 432e9fdf453SHongbo Zhang * Note that the num-irq property counts both internal and external 433e9fdf453SHongbo Zhang * interrupts; there are always 32 of the former (mandated by GIC spec). 434e9fdf453SHongbo Zhang */ 43548ba18e6SPhilippe Mathieu-Daudé qdev_prop_set_uint32(sms->gic, "num-irq", NUM_IRQS + 32); 43648ba18e6SPhilippe Mathieu-Daudé qdev_prop_set_bit(sms->gic, "has-security-extensions", true); 437e9fdf453SHongbo Zhang 438e9fdf453SHongbo Zhang redist0_capacity = 439e9fdf453SHongbo Zhang sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE; 440e9fdf453SHongbo Zhang redist0_count = MIN(smp_cpus, redist0_capacity); 441e9fdf453SHongbo Zhang 442d210fa2fSKevin Wolf redist_region_count = qlist_new(); 443d210fa2fSKevin Wolf qlist_append_int(redist_region_count, redist0_count); 444d210fa2fSKevin Wolf qdev_prop_set_array(sms->gic, "redist-region-count", redist_region_count); 445e9fdf453SHongbo Zhang 4469fe2b4a2SShashi Mallela object_property_set_link(OBJECT(sms->gic), "sysmem", 4479fe2b4a2SShashi Mallela OBJECT(mem), &error_fatal); 4489fe2b4a2SShashi Mallela qdev_prop_set_bit(sms->gic, "has-lpi", true); 4499fe2b4a2SShashi Mallela 45048ba18e6SPhilippe Mathieu-Daudé gicbusdev = SYS_BUS_DEVICE(sms->gic); 4513c6ef471SMarkus Armbruster sysbus_realize_and_unref(gicbusdev, &error_fatal); 452e9fdf453SHongbo Zhang sysbus_mmio_map(gicbusdev, 0, sbsa_ref_memmap[SBSA_GIC_DIST].base); 453e9fdf453SHongbo Zhang sysbus_mmio_map(gicbusdev, 1, sbsa_ref_memmap[SBSA_GIC_REDIST].base); 454e9fdf453SHongbo Zhang 455e9fdf453SHongbo Zhang /* 456e9fdf453SHongbo Zhang * Wire the outputs from each CPU's generic timer and the GICv3 457e9fdf453SHongbo Zhang * maintenance interrupt signal to the appropriate GIC PPI inputs, 458e9fdf453SHongbo Zhang * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. 459e9fdf453SHongbo Zhang */ 460e9fdf453SHongbo Zhang for (i = 0; i < smp_cpus; i++) { 461e9fdf453SHongbo Zhang DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); 462d40ab068SLeif Lindholm int intidbase = NUM_IRQS + i * GIC_INTERNAL; 463e9fdf453SHongbo Zhang int irq; 464e9fdf453SHongbo Zhang /* 465e9fdf453SHongbo Zhang * Mapping from the output timer irq lines from the CPU to the 466e9fdf453SHongbo Zhang * GIC PPI inputs used for this board. 467e9fdf453SHongbo Zhang */ 468e9fdf453SHongbo Zhang const int timer_irq[] = { 469e9fdf453SHongbo Zhang [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 470e9fdf453SHongbo Zhang [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 471e9fdf453SHongbo Zhang [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 472e9fdf453SHongbo Zhang [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 473058262e0SMarcin Juszkiewicz [GTIMER_HYPVIRT] = ARCH_TIMER_NS_EL2_VIRT_IRQ, 474e9fdf453SHongbo Zhang }; 475e9fdf453SHongbo Zhang 476e9fdf453SHongbo Zhang for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 477e9fdf453SHongbo Zhang qdev_connect_gpio_out(cpudev, irq, 47848ba18e6SPhilippe Mathieu-Daudé qdev_get_gpio_in(sms->gic, 479d40ab068SLeif Lindholm intidbase + timer_irq[irq])); 480e9fdf453SHongbo Zhang } 481e9fdf453SHongbo Zhang 482e9fdf453SHongbo Zhang qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0, 483d40ab068SLeif Lindholm qdev_get_gpio_in(sms->gic, 484d40ab068SLeif Lindholm intidbase 485e9fdf453SHongbo Zhang + ARCH_GIC_MAINT_IRQ)); 486d40ab068SLeif Lindholm 487e9fdf453SHongbo Zhang qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 488d40ab068SLeif Lindholm qdev_get_gpio_in(sms->gic, 489d40ab068SLeif Lindholm intidbase 490e9fdf453SHongbo Zhang + VIRTUAL_PMU_IRQ)); 491e9fdf453SHongbo Zhang 492e9fdf453SHongbo Zhang sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 493e9fdf453SHongbo Zhang sysbus_connect_irq(gicbusdev, i + smp_cpus, 494e9fdf453SHongbo Zhang qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 495e9fdf453SHongbo Zhang sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, 496e9fdf453SHongbo Zhang qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 497e9fdf453SHongbo Zhang sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, 498e9fdf453SHongbo Zhang qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 499e9fdf453SHongbo Zhang } 5009fe2b4a2SShashi Mallela create_its(sms); 501e9fdf453SHongbo Zhang } 502e9fdf453SHongbo Zhang 50348ba18e6SPhilippe Mathieu-Daudé static void create_uart(const SBSAMachineState *sms, int uart, 504e9fdf453SHongbo Zhang MemoryRegion *mem, Chardev *chr) 505e9fdf453SHongbo Zhang { 506e9fdf453SHongbo Zhang hwaddr base = sbsa_ref_memmap[uart].base; 507e9fdf453SHongbo Zhang int irq = sbsa_ref_irqmap[uart]; 5083e80f690SMarkus Armbruster DeviceState *dev = qdev_new(TYPE_PL011); 509e9fdf453SHongbo Zhang SysBusDevice *s = SYS_BUS_DEVICE(dev); 510e9fdf453SHongbo Zhang 511e9fdf453SHongbo Zhang qdev_prop_set_chr(dev, "chardev", chr); 5123c6ef471SMarkus Armbruster sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 513e9fdf453SHongbo Zhang memory_region_add_subregion(mem, base, 514e9fdf453SHongbo Zhang sysbus_mmio_get_region(s, 0)); 51548ba18e6SPhilippe Mathieu-Daudé sysbus_connect_irq(s, 0, qdev_get_gpio_in(sms->gic, irq)); 516e9fdf453SHongbo Zhang } 517e9fdf453SHongbo Zhang 51848ba18e6SPhilippe Mathieu-Daudé static void create_rtc(const SBSAMachineState *sms) 519e9fdf453SHongbo Zhang { 520e9fdf453SHongbo Zhang hwaddr base = sbsa_ref_memmap[SBSA_RTC].base; 521e9fdf453SHongbo Zhang int irq = sbsa_ref_irqmap[SBSA_RTC]; 522e9fdf453SHongbo Zhang 52348ba18e6SPhilippe Mathieu-Daudé sysbus_create_simple("pl031", base, qdev_get_gpio_in(sms->gic, irq)); 524e9fdf453SHongbo Zhang } 525e9fdf453SHongbo Zhang 526baabe7d0SShashi Mallela static void create_wdt(const SBSAMachineState *sms) 527baabe7d0SShashi Mallela { 528baabe7d0SShashi Mallela hwaddr rbase = sbsa_ref_memmap[SBSA_GWDT_REFRESH].base; 529baabe7d0SShashi Mallela hwaddr cbase = sbsa_ref_memmap[SBSA_GWDT_CONTROL].base; 530baabe7d0SShashi Mallela DeviceState *dev = qdev_new(TYPE_WDT_SBSA); 531baabe7d0SShashi Mallela SysBusDevice *s = SYS_BUS_DEVICE(dev); 53280d60a6dSEduardo Habkost int irq = sbsa_ref_irqmap[SBSA_GWDT_WS0]; 533baabe7d0SShashi Mallela 534baabe7d0SShashi Mallela sysbus_realize_and_unref(s, &error_fatal); 535baabe7d0SShashi Mallela sysbus_mmio_map(s, 0, rbase); 536baabe7d0SShashi Mallela sysbus_mmio_map(s, 1, cbase); 537baabe7d0SShashi Mallela sysbus_connect_irq(s, 0, qdev_get_gpio_in(sms->gic, irq)); 538baabe7d0SShashi Mallela } 539baabe7d0SShashi Mallela 540e9fdf453SHongbo Zhang static DeviceState *gpio_key_dev; 541e9fdf453SHongbo Zhang static void sbsa_ref_powerdown_req(Notifier *n, void *opaque) 542e9fdf453SHongbo Zhang { 543e9fdf453SHongbo Zhang /* use gpio Pin 3 for power button event */ 544e9fdf453SHongbo Zhang qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); 545e9fdf453SHongbo Zhang } 546e9fdf453SHongbo Zhang 547e9fdf453SHongbo Zhang static Notifier sbsa_ref_powerdown_notifier = { 548e9fdf453SHongbo Zhang .notify = sbsa_ref_powerdown_req 549e9fdf453SHongbo Zhang }; 550e9fdf453SHongbo Zhang 55148ba18e6SPhilippe Mathieu-Daudé static void create_gpio(const SBSAMachineState *sms) 552e9fdf453SHongbo Zhang { 553e9fdf453SHongbo Zhang DeviceState *pl061_dev; 554e9fdf453SHongbo Zhang hwaddr base = sbsa_ref_memmap[SBSA_GPIO].base; 555e9fdf453SHongbo Zhang int irq = sbsa_ref_irqmap[SBSA_GPIO]; 556e9fdf453SHongbo Zhang 55748ba18e6SPhilippe Mathieu-Daudé pl061_dev = sysbus_create_simple("pl061", base, 55848ba18e6SPhilippe Mathieu-Daudé qdev_get_gpio_in(sms->gic, irq)); 559e9fdf453SHongbo Zhang 560e9fdf453SHongbo Zhang gpio_key_dev = sysbus_create_simple("gpio-key", -1, 561e9fdf453SHongbo Zhang qdev_get_gpio_in(pl061_dev, 3)); 562e9fdf453SHongbo Zhang 563e9fdf453SHongbo Zhang /* connect powerdown request */ 564e9fdf453SHongbo Zhang qemu_register_powerdown_notifier(&sbsa_ref_powerdown_notifier); 565e9fdf453SHongbo Zhang } 566e9fdf453SHongbo Zhang 56748ba18e6SPhilippe Mathieu-Daudé static void create_ahci(const SBSAMachineState *sms) 568e9fdf453SHongbo Zhang { 569e9fdf453SHongbo Zhang hwaddr base = sbsa_ref_memmap[SBSA_AHCI].base; 570e9fdf453SHongbo Zhang int irq = sbsa_ref_irqmap[SBSA_AHCI]; 571e9fdf453SHongbo Zhang DeviceState *dev; 572e9fdf453SHongbo Zhang DriveInfo *hd[NUM_SATA_PORTS]; 573e9fdf453SHongbo Zhang SysbusAHCIState *sysahci; 574e9fdf453SHongbo Zhang AHCIState *ahci; 575e9fdf453SHongbo Zhang int i; 576e9fdf453SHongbo Zhang 5773e80f690SMarkus Armbruster dev = qdev_new("sysbus-ahci"); 578e9fdf453SHongbo Zhang qdev_prop_set_uint32(dev, "num-ports", NUM_SATA_PORTS); 5793c6ef471SMarkus Armbruster sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 580e9fdf453SHongbo Zhang sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 58148ba18e6SPhilippe Mathieu-Daudé sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(sms->gic, irq)); 582e9fdf453SHongbo Zhang 583e9fdf453SHongbo Zhang sysahci = SYSBUS_AHCI(dev); 584e9fdf453SHongbo Zhang ahci = &sysahci->ahci; 585e9fdf453SHongbo Zhang ide_drive_get(hd, ARRAY_SIZE(hd)); 586e9fdf453SHongbo Zhang for (i = 0; i < ahci->ports; i++) { 587e9fdf453SHongbo Zhang if (hd[i] == NULL) { 588e9fdf453SHongbo Zhang continue; 589e9fdf453SHongbo Zhang } 590b6a5ab27SPhilippe Mathieu-Daudé ide_bus_create_drive(&ahci->dev[i].port, 0, hd[i]); 591e9fdf453SHongbo Zhang } 592e9fdf453SHongbo Zhang } 593e9fdf453SHongbo Zhang 59462c2b876SYuquan Wang static void create_xhci(const SBSAMachineState *sms) 595e9fdf453SHongbo Zhang { 59662c2b876SYuquan Wang hwaddr base = sbsa_ref_memmap[SBSA_XHCI].base; 59762c2b876SYuquan Wang int irq = sbsa_ref_irqmap[SBSA_XHCI]; 59862c2b876SYuquan Wang DeviceState *dev = qdev_new(TYPE_XHCI_SYSBUS); 599e65ecb66SYuquan Wang qdev_prop_set_uint32(dev, "slots", XHCI_MAXSLOTS); 600e9fdf453SHongbo Zhang 60162c2b876SYuquan Wang sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 60262c2b876SYuquan Wang sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 60362c2b876SYuquan Wang sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(sms->gic, irq)); 604e9fdf453SHongbo Zhang } 605e9fdf453SHongbo Zhang 60648ba18e6SPhilippe Mathieu-Daudé static void create_smmu(const SBSAMachineState *sms, PCIBus *bus) 607e9fdf453SHongbo Zhang { 608e9fdf453SHongbo Zhang hwaddr base = sbsa_ref_memmap[SBSA_SMMU].base; 609e9fdf453SHongbo Zhang int irq = sbsa_ref_irqmap[SBSA_SMMU]; 610e9fdf453SHongbo Zhang DeviceState *dev; 611e9fdf453SHongbo Zhang int i; 612e9fdf453SHongbo Zhang 613a431ab0eSRichard Henderson dev = qdev_new(TYPE_ARM_SMMUV3); 614e9fdf453SHongbo Zhang 6155325cc34SMarkus Armbruster object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus), 616e9fdf453SHongbo Zhang &error_abort); 6173c6ef471SMarkus Armbruster sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 618e9fdf453SHongbo Zhang sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 619e9fdf453SHongbo Zhang for (i = 0; i < NUM_SMMU_IRQS; i++) { 62048ba18e6SPhilippe Mathieu-Daudé sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 621b8bf3472SGraeme Gregory qdev_get_gpio_in(sms->gic, irq + i)); 622e9fdf453SHongbo Zhang } 623e9fdf453SHongbo Zhang } 624e9fdf453SHongbo Zhang 62548ba18e6SPhilippe Mathieu-Daudé static void create_pcie(SBSAMachineState *sms) 626e9fdf453SHongbo Zhang { 627e9fdf453SHongbo Zhang hwaddr base_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].base; 628e9fdf453SHongbo Zhang hwaddr size_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].size; 629e9fdf453SHongbo Zhang hwaddr base_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].base; 630e9fdf453SHongbo Zhang hwaddr size_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].size; 631e9fdf453SHongbo Zhang hwaddr base_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].base; 632e9fdf453SHongbo Zhang hwaddr size_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].size; 633e9fdf453SHongbo Zhang hwaddr base_pio = sbsa_ref_memmap[SBSA_PCIE_PIO].base; 634e9fdf453SHongbo Zhang int irq = sbsa_ref_irqmap[SBSA_PCIE]; 635611eda59SThomas Huth MachineClass *mc = MACHINE_GET_CLASS(sms); 636e9fdf453SHongbo Zhang MemoryRegion *mmio_alias, *mmio_alias_high, *mmio_reg; 637e9fdf453SHongbo Zhang MemoryRegion *ecam_alias, *ecam_reg; 638e9fdf453SHongbo Zhang DeviceState *dev; 639e9fdf453SHongbo Zhang PCIHostState *pci; 640e9fdf453SHongbo Zhang int i; 641e9fdf453SHongbo Zhang 6423e80f690SMarkus Armbruster dev = qdev_new(TYPE_GPEX_HOST); 6433c6ef471SMarkus Armbruster sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 644e9fdf453SHongbo Zhang 645e9fdf453SHongbo Zhang /* Map ECAM space */ 646e9fdf453SHongbo Zhang ecam_alias = g_new0(MemoryRegion, 1); 647e9fdf453SHongbo Zhang ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 648e9fdf453SHongbo Zhang memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 649e9fdf453SHongbo Zhang ecam_reg, 0, size_ecam); 650e9fdf453SHongbo Zhang memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); 651e9fdf453SHongbo Zhang 652e9fdf453SHongbo Zhang /* Map the MMIO space */ 653e9fdf453SHongbo Zhang mmio_alias = g_new0(MemoryRegion, 1); 654e9fdf453SHongbo Zhang mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 655e9fdf453SHongbo Zhang memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 656e9fdf453SHongbo Zhang mmio_reg, base_mmio, size_mmio); 657e9fdf453SHongbo Zhang memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); 658e9fdf453SHongbo Zhang 659e9fdf453SHongbo Zhang /* Map the MMIO_HIGH space */ 660e9fdf453SHongbo Zhang mmio_alias_high = g_new0(MemoryRegion, 1); 661e9fdf453SHongbo Zhang memory_region_init_alias(mmio_alias_high, OBJECT(dev), "pcie-mmio-high", 662e9fdf453SHongbo Zhang mmio_reg, base_mmio_high, size_mmio_high); 663e9fdf453SHongbo Zhang memory_region_add_subregion(get_system_memory(), base_mmio_high, 664e9fdf453SHongbo Zhang mmio_alias_high); 665e9fdf453SHongbo Zhang 666e9fdf453SHongbo Zhang /* Map IO port space */ 667e9fdf453SHongbo Zhang sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); 668e9fdf453SHongbo Zhang 669e9fdf453SHongbo Zhang for (i = 0; i < GPEX_NUM_IRQS; i++) { 67048ba18e6SPhilippe Mathieu-Daudé sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 671870f0051SGraeme Gregory qdev_get_gpio_in(sms->gic, irq + i)); 672e9fdf453SHongbo Zhang gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); 673e9fdf453SHongbo Zhang } 674e9fdf453SHongbo Zhang 675e9fdf453SHongbo Zhang pci = PCI_HOST_BRIDGE(dev); 676e9fdf453SHongbo Zhang if (pci->bus) { 6770e45d0ebSDavid Woodhouse pci_init_nic_devices(pci->bus, mc->default_nic); 678e9fdf453SHongbo Zhang } 679e9fdf453SHongbo Zhang 6809162ac6bSMarcin Juszkiewicz pci_create_simple(pci->bus, -1, "bochs-display"); 681e9fdf453SHongbo Zhang 68248ba18e6SPhilippe Mathieu-Daudé create_smmu(sms, pci->bus); 683e9fdf453SHongbo Zhang } 684e9fdf453SHongbo Zhang 685e9fdf453SHongbo Zhang static void *sbsa_ref_dtb(const struct arm_boot_info *binfo, int *fdt_size) 686e9fdf453SHongbo Zhang { 687e9fdf453SHongbo Zhang const SBSAMachineState *board = container_of(binfo, SBSAMachineState, 688e9fdf453SHongbo Zhang bootinfo); 689e9fdf453SHongbo Zhang 690e9fdf453SHongbo Zhang *fdt_size = board->fdt_size; 691e9fdf453SHongbo Zhang return board->fdt; 692e9fdf453SHongbo Zhang } 693e9fdf453SHongbo Zhang 6943f462bf0SGraeme Gregory static void create_secure_ec(MemoryRegion *mem) 6953f462bf0SGraeme Gregory { 6963f462bf0SGraeme Gregory hwaddr base = sbsa_ref_memmap[SBSA_SECURE_EC].base; 6973f462bf0SGraeme Gregory DeviceState *dev = qdev_new("sbsa-ec"); 6983f462bf0SGraeme Gregory SysBusDevice *s = SYS_BUS_DEVICE(dev); 6993f462bf0SGraeme Gregory 7003f462bf0SGraeme Gregory memory_region_add_subregion(mem, base, 7013f462bf0SGraeme Gregory sysbus_mmio_get_region(s, 0)); 7023f462bf0SGraeme Gregory } 7033f462bf0SGraeme Gregory 70464580903SHongbo Zhang static void sbsa_ref_init(MachineState *machine) 70564580903SHongbo Zhang { 706cc7d44c2SLike Xu unsigned int smp_cpus = machine->smp.cpus; 707cc7d44c2SLike Xu unsigned int max_cpus = machine->smp.max_cpus; 70864580903SHongbo Zhang SBSAMachineState *sms = SBSA_MACHINE(machine); 70964580903SHongbo Zhang MachineClass *mc = MACHINE_GET_CLASS(machine); 71064580903SHongbo Zhang MemoryRegion *sysmem = get_system_memory(); 711c8ead571SPeter Maydell MemoryRegion *secure_sysmem = g_new(MemoryRegion, 1); 712e9fdf453SHongbo Zhang bool firmware_loaded; 71364580903SHongbo Zhang const CPUArchIdList *possible_cpus; 71464580903SHongbo Zhang int n, sbsa_max_cpus; 71564580903SHongbo Zhang 71664580903SHongbo Zhang if (kvm_enabled()) { 71764580903SHongbo Zhang error_report("sbsa-ref: KVM is not supported for this machine"); 71864580903SHongbo Zhang exit(1); 71964580903SHongbo Zhang } 72064580903SHongbo Zhang 72164580903SHongbo Zhang /* 722e9fdf453SHongbo Zhang * The Secure view of the world is the same as the NonSecure, 723e9fdf453SHongbo Zhang * but with a few extra devices. Create it as a container region 724e9fdf453SHongbo Zhang * containing the system memory at low priority; any secure-only 725e9fdf453SHongbo Zhang * devices go in at higher priority and take precedence. 726e9fdf453SHongbo Zhang */ 727e9fdf453SHongbo Zhang memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", 728e9fdf453SHongbo Zhang UINT64_MAX); 729e9fdf453SHongbo Zhang memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); 730e9fdf453SHongbo Zhang 731c8ead571SPeter Maydell firmware_loaded = sbsa_firmware_init(sms, sysmem, secure_sysmem); 732e9fdf453SHongbo Zhang 733e9fdf453SHongbo Zhang /* 73464580903SHongbo Zhang * This machine has EL3 enabled, external firmware should supply PSCI 73564580903SHongbo Zhang * implementation, so the QEMU's internal PSCI is disabled. 73664580903SHongbo Zhang */ 73764580903SHongbo Zhang sms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; 73864580903SHongbo Zhang 73964580903SHongbo Zhang sbsa_max_cpus = sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE; 74064580903SHongbo Zhang 74164580903SHongbo Zhang if (max_cpus > sbsa_max_cpus) { 74264580903SHongbo Zhang error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " 74364580903SHongbo Zhang "supported by machine 'sbsa-ref' (%d)", 74464580903SHongbo Zhang max_cpus, sbsa_max_cpus); 74564580903SHongbo Zhang exit(1); 74664580903SHongbo Zhang } 74764580903SHongbo Zhang 74864580903SHongbo Zhang sms->smp_cpus = smp_cpus; 74964580903SHongbo Zhang 75064580903SHongbo Zhang if (machine->ram_size > sbsa_ref_memmap[SBSA_MEM].size) { 75164580903SHongbo Zhang error_report("sbsa-ref: cannot model more than %dGB RAM", RAMLIMIT_GB); 75264580903SHongbo Zhang exit(1); 75364580903SHongbo Zhang } 75464580903SHongbo Zhang 75564580903SHongbo Zhang possible_cpus = mc->possible_cpu_arch_ids(machine); 75664580903SHongbo Zhang for (n = 0; n < possible_cpus->len; n++) { 75764580903SHongbo Zhang Object *cpuobj; 75864580903SHongbo Zhang CPUState *cs; 75964580903SHongbo Zhang 76064580903SHongbo Zhang if (n >= smp_cpus) { 76164580903SHongbo Zhang break; 76264580903SHongbo Zhang } 76364580903SHongbo Zhang 76464580903SHongbo Zhang cpuobj = object_new(possible_cpus->cpus[n].type); 7655325cc34SMarkus Armbruster object_property_set_int(cpuobj, "mp-affinity", 7665325cc34SMarkus Armbruster possible_cpus->cpus[n].arch_id, NULL); 76764580903SHongbo Zhang 76864580903SHongbo Zhang cs = CPU(cpuobj); 76964580903SHongbo Zhang cs->cpu_index = n; 77064580903SHongbo Zhang 77164580903SHongbo Zhang numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj), 77264580903SHongbo Zhang &error_fatal); 77364580903SHongbo Zhang 774efba1595SDaniel P. Berrangé if (object_property_find(cpuobj, "reset-cbar")) { 7755325cc34SMarkus Armbruster object_property_set_int(cpuobj, "reset-cbar", 77664580903SHongbo Zhang sbsa_ref_memmap[SBSA_CPUPERIPHS].base, 7775325cc34SMarkus Armbruster &error_abort); 77864580903SHongbo Zhang } 77964580903SHongbo Zhang 7805325cc34SMarkus Armbruster object_property_set_link(cpuobj, "memory", OBJECT(sysmem), 78164580903SHongbo Zhang &error_abort); 78264580903SHongbo Zhang 7835325cc34SMarkus Armbruster object_property_set_link(cpuobj, "secure-memory", 7845325cc34SMarkus Armbruster OBJECT(secure_sysmem), &error_abort); 78564580903SHongbo Zhang 786ce189ab2SMarkus Armbruster qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); 78764580903SHongbo Zhang object_unref(cpuobj); 78864580903SHongbo Zhang } 78964580903SHongbo Zhang 7903818ed92SIgor Mammedov memory_region_add_subregion(sysmem, sbsa_ref_memmap[SBSA_MEM].base, 7913818ed92SIgor Mammedov machine->ram); 79264580903SHongbo Zhang 793e9fdf453SHongbo Zhang create_fdt(sms); 794e9fdf453SHongbo Zhang 795e9fdf453SHongbo Zhang create_secure_ram(sms, secure_sysmem); 796e9fdf453SHongbo Zhang 7979fe2b4a2SShashi Mallela create_gic(sms, sysmem); 798e9fdf453SHongbo Zhang 79948ba18e6SPhilippe Mathieu-Daudé create_uart(sms, SBSA_UART, sysmem, serial_hd(0)); 80048ba18e6SPhilippe Mathieu-Daudé create_uart(sms, SBSA_SECURE_UART, secure_sysmem, serial_hd(1)); 801e9fdf453SHongbo Zhang /* Second secure UART for RAS and MM from EL0 */ 80248ba18e6SPhilippe Mathieu-Daudé create_uart(sms, SBSA_SECURE_UART_MM, secure_sysmem, serial_hd(2)); 803e9fdf453SHongbo Zhang 80448ba18e6SPhilippe Mathieu-Daudé create_rtc(sms); 805e9fdf453SHongbo Zhang 806baabe7d0SShashi Mallela create_wdt(sms); 807baabe7d0SShashi Mallela 80848ba18e6SPhilippe Mathieu-Daudé create_gpio(sms); 809e9fdf453SHongbo Zhang 81048ba18e6SPhilippe Mathieu-Daudé create_ahci(sms); 811e9fdf453SHongbo Zhang 81262c2b876SYuquan Wang create_xhci(sms); 813e9fdf453SHongbo Zhang 81448ba18e6SPhilippe Mathieu-Daudé create_pcie(sms); 815e9fdf453SHongbo Zhang 8163f462bf0SGraeme Gregory create_secure_ec(secure_sysmem); 8173f462bf0SGraeme Gregory 81864580903SHongbo Zhang sms->bootinfo.ram_size = machine->ram_size; 81964580903SHongbo Zhang sms->bootinfo.board_id = -1; 82064580903SHongbo Zhang sms->bootinfo.loader_start = sbsa_ref_memmap[SBSA_MEM].base; 821e9fdf453SHongbo Zhang sms->bootinfo.get_dtb = sbsa_ref_dtb; 822e9fdf453SHongbo Zhang sms->bootinfo.firmware_loaded = firmware_loaded; 8232744ece8STao Xu arm_load_kernel(ARM_CPU(first_cpu), machine, &sms->bootinfo); 82464580903SHongbo Zhang } 82564580903SHongbo Zhang 82664580903SHongbo Zhang static const CPUArchIdList *sbsa_ref_possible_cpu_arch_ids(MachineState *ms) 82764580903SHongbo Zhang { 828cc7d44c2SLike Xu unsigned int max_cpus = ms->smp.max_cpus; 82964580903SHongbo Zhang SBSAMachineState *sms = SBSA_MACHINE(ms); 83064580903SHongbo Zhang int n; 83164580903SHongbo Zhang 83264580903SHongbo Zhang if (ms->possible_cpus) { 83364580903SHongbo Zhang assert(ms->possible_cpus->len == max_cpus); 83464580903SHongbo Zhang return ms->possible_cpus; 83564580903SHongbo Zhang } 83664580903SHongbo Zhang 83764580903SHongbo Zhang ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 83864580903SHongbo Zhang sizeof(CPUArchId) * max_cpus); 83964580903SHongbo Zhang ms->possible_cpus->len = max_cpus; 84064580903SHongbo Zhang for (n = 0; n < ms->possible_cpus->len; n++) { 84164580903SHongbo Zhang ms->possible_cpus->cpus[n].type = ms->cpu_type; 84264580903SHongbo Zhang ms->possible_cpus->cpus[n].arch_id = 84364580903SHongbo Zhang sbsa_ref_cpu_mp_affinity(sms, n); 84464580903SHongbo Zhang ms->possible_cpus->cpus[n].props.has_thread_id = true; 84564580903SHongbo Zhang ms->possible_cpus->cpus[n].props.thread_id = n; 84664580903SHongbo Zhang } 84764580903SHongbo Zhang return ms->possible_cpus; 84864580903SHongbo Zhang } 84964580903SHongbo Zhang 85064580903SHongbo Zhang static CpuInstanceProperties 85164580903SHongbo Zhang sbsa_ref_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 85264580903SHongbo Zhang { 85364580903SHongbo Zhang MachineClass *mc = MACHINE_GET_CLASS(ms); 85464580903SHongbo Zhang const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 85564580903SHongbo Zhang 85664580903SHongbo Zhang assert(cpu_index < possible_cpus->len); 85764580903SHongbo Zhang return possible_cpus->cpus[cpu_index].props; 85864580903SHongbo Zhang } 85964580903SHongbo Zhang 86064580903SHongbo Zhang static int64_t 86164580903SHongbo Zhang sbsa_ref_get_default_cpu_node_id(const MachineState *ms, int idx) 86264580903SHongbo Zhang { 863aa570207STao Xu return idx % ms->numa_state->num_nodes; 86464580903SHongbo Zhang } 86564580903SHongbo Zhang 866e9fdf453SHongbo Zhang static void sbsa_ref_instance_init(Object *obj) 867e9fdf453SHongbo Zhang { 868e9fdf453SHongbo Zhang SBSAMachineState *sms = SBSA_MACHINE(obj); 869e9fdf453SHongbo Zhang 870e9fdf453SHongbo Zhang sbsa_flash_create(sms); 871e9fdf453SHongbo Zhang } 872e9fdf453SHongbo Zhang 87364580903SHongbo Zhang static void sbsa_ref_class_init(ObjectClass *oc, void *data) 87464580903SHongbo Zhang { 87564580903SHongbo Zhang MachineClass *mc = MACHINE_CLASS(oc); 876dbf8e8c4SGavin Shan static const char * const valid_cpu_types[] = { 877dbf8e8c4SGavin Shan ARM_CPU_TYPE_NAME("cortex-a57"), 878dbf8e8c4SGavin Shan ARM_CPU_TYPE_NAME("cortex-a72"), 879dbf8e8c4SGavin Shan ARM_CPU_TYPE_NAME("neoverse-n1"), 880dbf8e8c4SGavin Shan ARM_CPU_TYPE_NAME("neoverse-v1"), 881dbf8e8c4SGavin Shan ARM_CPU_TYPE_NAME("neoverse-n2"), 882dbf8e8c4SGavin Shan ARM_CPU_TYPE_NAME("max"), 883dbf8e8c4SGavin Shan NULL, 884dbf8e8c4SGavin Shan }; 88564580903SHongbo Zhang 88664580903SHongbo Zhang mc->init = sbsa_ref_init; 88764580903SHongbo Zhang mc->desc = "QEMU 'SBSA Reference' ARM Virtual Machine"; 8881877272bSMarcin Juszkiewicz mc->default_cpu_type = ARM_CPU_TYPE_NAME("neoverse-n1"); 889dbf8e8c4SGavin Shan mc->valid_cpu_types = valid_cpu_types; 89064580903SHongbo Zhang mc->max_cpus = 512; 89164580903SHongbo Zhang mc->pci_allow_0_address = true; 89264580903SHongbo Zhang mc->minimum_page_bits = 12; 89364580903SHongbo Zhang mc->block_default_type = IF_IDE; 89464580903SHongbo Zhang mc->no_cdrom = 1; 895611eda59SThomas Huth mc->default_nic = "e1000e"; 89664580903SHongbo Zhang mc->default_ram_size = 1 * GiB; 8973818ed92SIgor Mammedov mc->default_ram_id = "sbsa-ref.ram"; 89864580903SHongbo Zhang mc->default_cpus = 4; 89964580903SHongbo Zhang mc->possible_cpu_arch_ids = sbsa_ref_possible_cpu_arch_ids; 90064580903SHongbo Zhang mc->cpu_index_to_instance_props = sbsa_ref_cpu_index_to_props; 90164580903SHongbo Zhang mc->get_default_cpu_node_id = sbsa_ref_get_default_cpu_node_id; 902fecff672SGavin Shan /* platform instead of architectural choice */ 903fecff672SGavin Shan mc->cpu_cluster_has_numa_boundary = true; 90464580903SHongbo Zhang } 90564580903SHongbo Zhang 90664580903SHongbo Zhang static const TypeInfo sbsa_ref_info = { 90764580903SHongbo Zhang .name = TYPE_SBSA_MACHINE, 90864580903SHongbo Zhang .parent = TYPE_MACHINE, 909e9fdf453SHongbo Zhang .instance_init = sbsa_ref_instance_init, 91064580903SHongbo Zhang .class_init = sbsa_ref_class_init, 91164580903SHongbo Zhang .instance_size = sizeof(SBSAMachineState), 91264580903SHongbo Zhang }; 91364580903SHongbo Zhang 91464580903SHongbo Zhang static void sbsa_ref_machine_init(void) 91564580903SHongbo Zhang { 91664580903SHongbo Zhang type_register_static(&sbsa_ref_info); 91764580903SHongbo Zhang } 91864580903SHongbo Zhang 91964580903SHongbo Zhang type_init(sbsa_ref_machine_init); 920